hw/etraxfs_timer.c

   1 /*
   2  * QEMU ETRAX Timers
   3  *
   4  * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include <stdio.h>
  25 #include <sys/time.h>
  26 #include "hw.h"
  27 #include "sysemu.h"
  28 #include "qemu-timer.h"
  29
  30 #define D(x)
  31
  32 #define RW_TMR0_DIV   0x00
  33 #define R_TMR0_DATA   0x04
  34 #define RW_TMR0_CTRL  0x08
  35 #define RW_TMR1_DIV   0x10
  36 #define R_TMR1_DATA   0x14
  37 #define RW_TMR1_CTRL  0x18
  38 #define R_TIME        0x38
  39 #define RW_WD_CTRL    0x40
  40 #define R_WD_STAT     0x44
  41 #define RW_INTR_MASK  0x48
  42 #define RW_ACK_INTR   0x4c
  43 #define R_INTR        0x50
  44 #define R_MASKED_INTR 0x54
  45
  46 struct fs_timer_t {
  47         CPUState *env;
  48         qemu_irq *irq;
  49         qemu_irq *nmi;
  50
  51         QEMUBH *bh_t0;
  52         QEMUBH *bh_t1;
  53         QEMUBH *bh_wd;
  54         ptimer_state *ptimer_t0;
  55         ptimer_state *ptimer_t1;
  56         ptimer_state *ptimer_wd;
  57         struct timeval last;
  58
  59         int wd_hits;
  60
  61         /* Control registers.  */
  62         uint32_t rw_tmr0_div;
  63         uint32_t r_tmr0_data;
  64         uint32_t rw_tmr0_ctrl;
  65
  66         uint32_t rw_tmr1_div;
  67         uint32_t r_tmr1_data;
  68         uint32_t rw_tmr1_ctrl;
  69
  70         uint32_t rw_wd_ctrl;
  71
  72         uint32_t rw_intr_mask;
  73         uint32_t rw_ack_intr;
  74         uint32_t r_intr;
  75         uint32_t r_masked_intr;
  76 };
  77
  78 static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
  79 {
  80         struct fs_timer_t *t = opaque;
  81         uint32_t r = 0;
  82
  83         switch (addr) {
  84         case R_TMR0_DATA:
  85                 r = ptimer_get_count(t->ptimer_t0);
  86                 break;
  87         case R_TMR1_DATA:
  88                 r = ptimer_get_count(t->ptimer_t1);
  89                 break;
  90         case R_TIME:
  91                 r = qemu_get_clock(vm_clock) / 10;
  92                 break;
  93         case RW_INTR_MASK:
  94                 r = t->rw_intr_mask;
  95                 break;
  96         case R_MASKED_INTR:
  97                 r = t->r_intr & t->rw_intr_mask;
  98                 break;
  99         default:
 100                 D(printf ("%s %x\n", __func__, addr));
 101                 break;
 102         }
 103         return r;
 104 }
 105
 106 #define TIMER_SLOWDOWN 1
 107 static void update_ctrl(struct fs_timer_t *t, int tnum)
 108 {
 109         unsigned int op;
 110         unsigned int freq;
 111         unsigned int freq_hz;
 112         unsigned int div;
 113         uint32_t ctrl;
 114
 115         ptimer_state *timer;
 116
 117         if (tnum == 0) {
 118                 ctrl = t->rw_tmr0_ctrl;
 119                 div = t->rw_tmr0_div;
 120                 timer = t->ptimer_t0;
 121         } else {
 122                 ctrl = t->rw_tmr1_ctrl;
 123                 div = t->rw_tmr1_div;
 124                 timer = t->ptimer_t1;
 125         }
 126
 127
 128         op = ctrl & 3;
 129         freq = ctrl >> 2;
 130         freq_hz = 32000000;
 131
 132         switch (freq)
 133         {
 134         case 0:
 135         case 1:
 136                 D(printf ("extern or disabled timer clock?\n"));
 137                 break;
 138         case 4: freq_hz =  29493000; break;
 139         case 5: freq_hz =  32000000; break;
 140         case 6: freq_hz =  32768000; break;
 141         case 7: freq_hz = 100000000; break;
 142         default:
 143                 abort();
 144                 break;
 145         }
 146
 147         D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
 148         div = div * TIMER_SLOWDOWN;
 149         div /= 1000;
 150         freq_hz /= 1000;
 151         ptimer_set_freq(timer, freq_hz);
 152         ptimer_set_limit(timer, div, 0);
 153
 154         switch (op)
 155         {
 156                 case 0:
 157                         /* Load.  */
 158                         ptimer_set_limit(timer, div, 1);
 159                         break;
 160                 case 1:
 161                         /* Hold.  */
 162                         ptimer_stop(timer);
 163                         break;
 164                 case 2:
 165                         /* Run.  */
 166                         ptimer_run(timer, 0);
 167                         break;
 168                 default:
 169                         abort();
 170                         break;
 171         }
 172 }
 173
 174 static void timer_update_irq(struct fs_timer_t *t)
 175 {
 176         t->r_intr &= ~(t->rw_ack_intr);
 177         t->r_masked_intr = t->r_intr & t->rw_intr_mask;
 178
 179         D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
 180         if (t->r_masked_intr)
 181                 qemu_irq_raise(t->irq[0]);
 182         else
 183                 qemu_irq_lower(t->irq[0]);
 184 }
 185
 186 static void timer0_hit(void *opaque)
 187 {
 188         struct fs_timer_t *t = opaque;
 189         t->r_intr |= 1;
 190         timer_update_irq(t);
 191 }
 192
 193 static void timer1_hit(void *opaque)
 194 {
 195         struct fs_timer_t *t = opaque;
 196         t->r_intr |= 2;
 197         timer_update_irq(t);
 198 }
 199
 200 static void watchdog_hit(void *opaque)
 201 {
 202         struct fs_timer_t *t = opaque;
 203         if (t->wd_hits == 0) {
 204                 /* real hw gives a single tick before reseting but we are
 205                    a bit friendlier to compensate for our slower execution.  */
 206                 ptimer_set_count(t->ptimer_wd, 10);
 207                 ptimer_run(t->ptimer_wd, 1);
 208                 qemu_irq_raise(t->nmi[0]);
 209         }
 210         else
 211                 qemu_system_reset_request();
 212
 213         t->wd_hits++;
 214 }
 215
 216 static inline void timer_watchdog_update(struct fs_timer_t *t, uint32_t value)
 217 {
 218         unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
 219         unsigned int wd_key = t->rw_wd_ctrl >> 9;
 220         unsigned int wd_cnt = t->rw_wd_ctrl & 511;
 221         unsigned int new_key = value >> 9 & ((1 << 7) - 1);
 222         unsigned int new_cmd = (value >> 8) & 1;
 223
 224         /* If the watchdog is enabled, they written key must match the
 225            complement of the previous.  */
 226         wd_key = ~wd_key & ((1 << 7) - 1);
 227
 228         if (wd_en && wd_key != new_key)
 229                 return;
 230
 231         D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n",
 232                  wd_en, new_key, wd_key, new_cmd, wd_cnt));
 233
 234         if (t->wd_hits)
 235                 qemu_irq_lower(t->nmi[0]);
 236
 237         t->wd_hits = 0;
 238
 239         ptimer_set_freq(t->ptimer_wd, 760);
 240         if (wd_cnt == 0)
 241                 wd_cnt = 256;
 242         ptimer_set_count(t->ptimer_wd, wd_cnt);
 243         if (new_cmd)
 244                 ptimer_run(t->ptimer_wd, 1);
 245         else
 246                 ptimer_stop(t->ptimer_wd);
 247
 248         t->rw_wd_ctrl = value;
 249 }
 250
 251 static void
 252 timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
 253 {
 254         struct fs_timer_t *t = opaque;
 255
 256         switch (addr)
 257         {
 258                 case RW_TMR0_DIV:
 259                         t->rw_tmr0_div = value;
 260                         break;
 261                 case RW_TMR0_CTRL:
 262                         D(printf ("RW_TMR0_CTRL=%x\n", value));
 263                         t->rw_tmr0_ctrl = value;
 264                         update_ctrl(t, 0);
 265                         break;
 266                 case RW_TMR1_DIV:
 267                         t->rw_tmr1_div = value;
 268                         break;
 269                 case RW_TMR1_CTRL:
 270                         D(printf ("RW_TMR1_CTRL=%x\n", value));
 271                         t->rw_tmr1_ctrl = value;
 272                         update_ctrl(t, 1);
 273                         break;
 274                 case RW_INTR_MASK:
 275                         D(printf ("RW_INTR_MASK=%x\n", value));
 276                         t->rw_intr_mask = value;
 277                         timer_update_irq(t);
 278                         break;
 279                 case RW_WD_CTRL:
 280                         timer_watchdog_update(t, value);
 281                         break;
 282                 case RW_ACK_INTR:
 283                         t->rw_ack_intr = value;
 284                         timer_update_irq(t);
 285                         t->rw_ack_intr = 0;
 286                         break;
 287                 default:
 288                         printf ("%s " TARGET_FMT_plx " %x\n",
 289                                 __func__, addr, value);
 290                         break;
 291         }
 292 }
 293
 294 static CPUReadMemoryFunc *timer_read[] = {
 295         NULL, NULL,
 296         &timer_readl,
 297 };
 298
 299 static CPUWriteMemoryFunc *timer_write[] = {
 300         NULL, NULL,
 301         &timer_writel,
 302 };
 303
 304 static void etraxfs_timer_reset(void *opaque)
 305 {
 306         struct fs_timer_t *t = opaque;
 307
 308         ptimer_stop(t->ptimer_t0);
 309         ptimer_stop(t->ptimer_t1);
 310         ptimer_stop(t->ptimer_wd);
 311         t->rw_wd_ctrl = 0;
 312         t->r_intr = 0;
 313         t->rw_intr_mask = 0;
 314         qemu_irq_lower(t->irq[0]);
 315 }
 316
 317 void etraxfs_timer_init(CPUState *env, qemu_irq *irqs, qemu_irq *nmi,
 318                         target_phys_addr_t base)
 319 {
 320         static struct fs_timer_t *t;
 321         int timer_regs;
 322
 323         t = qemu_mallocz(sizeof *t);
 324         if (!t)
 325                 return;
 326
 327         t->bh_t0 = qemu_bh_new(timer0_hit, t);
 328         t->bh_t1 = qemu_bh_new(timer1_hit, t);
 329         t->bh_wd = qemu_bh_new(watchdog_hit, t);
 330         t->ptimer_t0 = ptimer_init(t->bh_t0);
 331         t->ptimer_t1 = ptimer_init(t->bh_t1);
 332         t->ptimer_wd = ptimer_init(t->bh_wd);
 333         t->irq = irqs;
 334         t->nmi = nmi;
 335         t->env = env;
 336
 337         timer_regs = cpu_register_io_memory(0, timer_read, timer_write, t);
 338         cpu_register_physical_memory (base, 0x5c, timer_regs);
 339
 340         qemu_register_reset(etraxfs_timer_reset, t);
 341 }