hw/ppc_oldworld.c

   1 /*
   2  * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
   3  *
   4  * Copyright (c) 2004-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "ppc.h"
  27 #include "ppc_mac.h"
  28 #include "mac_dbdma.h"
  29 #include "nvram.h"
  30 #include "pc.h"
  31 #include "sysemu.h"
  32 #include "net.h"
  33 #include "isa.h"
  34 #include "pci.h"
  35 #include "boards.h"
  36 #include "fw_cfg.h"
  37 #include "escc.h"
  38
  39 #define MAX_IDE_BUS 2
  40 #define VGA_BIOS_SIZE 65536
  41 #define CFG_ADDR 0xf0000510
  42
  43 /* temporary frame buffer OSI calls for the video.x driver. The right
  44    solution is to modify the driver to use VGA PCI I/Os */
  45 /* XXX: to be removed. This is no way related to emulation */
  46 static int vga_osi_call (CPUState *env)
  47 {
  48     static int vga_vbl_enabled;
  49     int linesize;
  50
  51     //    printf("osi_call R5=" REGX "\n", ppc_dump_gpr(env, 5));
  52
  53     /* same handler as PearPC, coming from the original MOL video
  54        driver. */
  55     switch(env->gpr[5]) {
  56     case 4:
  57         break;
  58     case 28: /* set_vmode */
  59         if (env->gpr[6] != 1 || env->gpr[7] != 0)
  60             env->gpr[3] = 1;
  61         else
  62             env->gpr[3] = 0;
  63         break;
  64     case 29: /* get_vmode_info */
  65         if (env->gpr[6] != 0) {
  66             if (env->gpr[6] != 1 || env->gpr[7] != 0) {
  67                 env->gpr[3] = 1;
  68                 break;
  69             }
  70         }
  71         env->gpr[3] = 0;
  72         env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
  73         env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
  74         env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
  75         env->gpr[7] = 85 << 16; /* refresh rate */
  76         env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
  77         linesize = ((graphic_depth + 7) >> 3) * graphic_width;
  78         linesize = (linesize + 3) & ~3;
  79         env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
  80         break;
  81     case 31: /* set_video power */
  82         env->gpr[3] = 0;
  83         break;
  84     case 39: /* video_ctrl */
  85         if (env->gpr[6] == 0 || env->gpr[6] == 1)
  86             vga_vbl_enabled = env->gpr[6];
  87         env->gpr[3] = 0;
  88         break;
  89     case 47:
  90         break;
  91     case 59: /* set_color */
  92         /* R6 = index, R7 = RGB */
  93         env->gpr[3] = 0;
  94         break;
  95     case 64: /* get color */
  96         /* R6 = index */
  97         env->gpr[3] = 0;
  98         break;
  99     case 116: /* set hwcursor */
 100         /* R6 = x, R7 = y, R8 = visible, R9 = data */
 101         break;
 102     default:
 103         fprintf(stderr, "unsupported OSI call R5=" REGX "\n",
 104                 ppc_dump_gpr(env, 5));
 105         break;
 106     }
 107
 108     return 1; /* osi_call handled */
 109 }
 110
 111 static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
 112                                const char *boot_device,
 113                                const char *kernel_filename,
 114                                const char *kernel_cmdline,
 115                                const char *initrd_filename,
 116                                const char *cpu_model)
 117 {
 118     CPUState *env = NULL, *envs[MAX_CPUS];
 119     char buf[1024];
 120     qemu_irq *pic, **heathrow_irqs;
 121     nvram_t nvram;
 122     m48t59_t *m48t59;
 123     int linux_boot, i;
 124     ram_addr_t ram_offset, vga_ram_offset, bios_offset, vga_bios_offset;
 125     uint32_t kernel_base, initrd_base;
 126     int32_t kernel_size, initrd_size;
 127     PCIBus *pci_bus;
 128     MacIONVRAMState *nvr;
 129     int vga_bios_size, bios_size;
 130     int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
 131     int escc_mem_index, ide_mem_index[2];
 132     int ppc_boot_device;
 133     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 134     int index;
 135     void *fw_cfg;
 136     void *dbdma;
 137
 138     linux_boot = (kernel_filename != NULL);
 139
 140     /* init CPUs */
 141     if (cpu_model == NULL)
 142         cpu_model = "G3";
 143     for (i = 0; i < smp_cpus; i++) {
 144         env = cpu_init(cpu_model);
 145         if (!env) {
 146             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 147             exit(1);
 148         }
 149         /* Set time-base frequency to 16.6 Mhz */
 150         cpu_ppc_tb_init(env,  16600000UL);
 151         env->osi_call = vga_osi_call;
 152         qemu_register_reset(&cpu_ppc_reset, env);
 153         envs[i] = env;
 154     }
 155     if (env->nip < 0xFFF80000) {
 156         /* Special test for PowerPC 601:
 157          * the boot vector is at 0xFFF00100, then we need a 1MB BIOS.
 158          * But the NVRAM is located at 0xFFF04000...
 159          */
 160         cpu_abort(env, "G3 Beige Mac hardware can not handle 1 MB BIOS\n");
 161     }
 162
 163     /* allocate RAM */
 164     if (ram_size > (2047 << 20)) {
 165         fprintf(stderr,
 166                 "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n",
 167                 ((unsigned int)ram_size / (1 << 20)));
 168         exit(1);
 169     }
 170
 171     ram_offset = qemu_ram_alloc(ram_size);
 172     cpu_register_physical_memory(0, ram_size, ram_offset);
 173
 174     /* allocate VGA RAM */
 175     vga_ram_offset = qemu_ram_alloc(vga_ram_size);
 176
 177     /* allocate and load BIOS */
 178     bios_offset = qemu_ram_alloc(BIOS_SIZE);
 179     if (bios_name == NULL)
 180         bios_name = PROM_FILENAME;
 181     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 182     cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM);
 183
 184     /* Load OpenBIOS (ELF) */
 185     bios_size = load_elf(buf, 0, NULL, NULL, NULL);
 186     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 187         cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
 188         exit(1);
 189     }
 190
 191     /* allocate and load VGA BIOS */
 192     vga_bios_offset = qemu_ram_alloc(VGA_BIOS_SIZE);
 193     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
 194     vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);
 195     if (vga_bios_size < 0) {
 196         /* if no bios is present, we can still work */
 197         fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf);
 198         vga_bios_size = 0;
 199     } else {
 200         /* set a specific header (XXX: find real Apple format for NDRV
 201            drivers) */
 202         phys_ram_base[vga_bios_offset] = 'N';
 203         phys_ram_base[vga_bios_offset + 1] = 'D';
 204         phys_ram_base[vga_bios_offset + 2] = 'R';
 205         phys_ram_base[vga_bios_offset + 3] = 'V';
 206         cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4),
 207                      vga_bios_size);
 208         vga_bios_size += 8;
 209     }
 210
 211     if (linux_boot) {
 212         uint64_t lowaddr = 0;
 213         kernel_base = KERNEL_LOAD_ADDR;
 214         /* Now we can load the kernel. The first step tries to load the kernel
 215            supposing PhysAddr = 0x00000000. If that was wrong the kernel is
 216            loaded again, the new PhysAddr being computed from lowaddr. */
 217         kernel_size = load_elf(kernel_filename, kernel_base, NULL, &lowaddr, NULL);
 218         if (kernel_size > 0 && lowaddr != KERNEL_LOAD_ADDR) {
 219             kernel_size = load_elf(kernel_filename, (2 * kernel_base) - lowaddr,
 220                                    NULL, 0, NULL);
 221         }
 222         if (kernel_size < 0)
 223             kernel_size = load_aout(kernel_filename, kernel_base,
 224                                     ram_size - kernel_base);
 225         if (kernel_size < 0)
 226             kernel_size = load_image_targphys(kernel_filename,
 227                                               kernel_base,
 228                                               ram_size - kernel_base);
 229         if (kernel_size < 0) {
 230             cpu_abort(env, "qemu: could not load kernel '%s'\n",
 231                       kernel_filename);
 232             exit(1);
 233         }
 234         /* load initrd */
 235         if (initrd_filename) {
 236             initrd_base = INITRD_LOAD_ADDR;
 237             initrd_size = load_image(initrd_filename,
 238                                      phys_ram_base + initrd_base);
 239             if (initrd_size < 0) {
 240                 cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
 241                           initrd_filename);
 242                 exit(1);
 243             }
 244         } else {
 245             initrd_base = 0;
 246             initrd_size = 0;
 247         }
 248         ppc_boot_device = 'm';
 249     } else {
 250         kernel_base = 0;
 251         kernel_size = 0;
 252         initrd_base = 0;
 253         initrd_size = 0;
 254         ppc_boot_device = '\0';
 255         for (i = 0; boot_device[i] != '\0'; i++) {
 256             /* TOFIX: for now, the second IDE channel is not properly
 257              *        used by OHW. The Mac floppy disk are not emulated.
 258              *        For now, OHW cannot boot from the network.
 259              */
 260 #if 0
 261             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 262                 ppc_boot_device = boot_device[i];
 263                 break;
 264             }
 265 #else
 266             if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
 267                 ppc_boot_device = boot_device[i];
 268                 break;
 269             }
 270 #endif
 271         }
 272         if (ppc_boot_device == '\0') {
 273             fprintf(stderr, "No valid boot device for G3 Beige machine\n");
 274             exit(1);
 275         }
 276     }
 277
 278     isa_mem_base = 0x80000000;
 279
 280     /* Register 2 MB of ISA IO space */
 281     isa_mmio_init(0xfe000000, 0x00200000);
 282
 283     /* XXX: we register only 1 output pin for heathrow PIC */
 284     heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
 285     heathrow_irqs[0] =
 286         qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1);
 287     /* Connect the heathrow PIC outputs to the 6xx bus */
 288     for (i = 0; i < smp_cpus; i++) {
 289         switch (PPC_INPUT(env)) {
 290         case PPC_FLAGS_INPUT_6xx:
 291             heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
 292             heathrow_irqs[i][0] =
 293                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
 294             break;
 295         default:
 296             cpu_abort(env, "Bus model not supported on OldWorld Mac machine\n");
 297             exit(1);
 298         }
 299     }
 300
 301     /* init basic PC hardware */
 302     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 303         cpu_abort(env, "Only 6xx bus is supported on heathrow machine\n");
 304         exit(1);
 305     }
 306     pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
 307     pci_bus = pci_grackle_init(0xfec00000, pic);
 308     pci_vga_init(pci_bus, phys_ram_base + vga_ram_offset,
 309                  vga_ram_offset, vga_ram_size,
 310                  vga_bios_offset, vga_bios_size);
 311
 312     escc_mem_index = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0],
 313                                serial_hds[1], ESCC_CLOCK, 4);
 314
 315     for(i = 0; i < nb_nics; i++)
 316         pci_nic_init(pci_bus, &nd_table[i], -1, "ne2k_pci");
 317
 318     /* First IDE channel is a CMD646 on the PCI bus */
 319
 320     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 321         fprintf(stderr, "qemu: too many IDE bus\n");
 322         exit(1);
 323     }
 324     index = drive_get_index(IF_IDE, 0, 0);
 325     if (index == -1)
 326         hd[0] = NULL;
 327     else
 328         hd[0] =  drives_table[index].bdrv;
 329     index = drive_get_index(IF_IDE, 0, 1);
 330     if (index == -1)
 331         hd[1] = NULL;
 332     else
 333         hd[1] =  drives_table[index].bdrv;
 334     hd[3] = hd[2] = NULL;
 335     pci_cmd646_ide_init(pci_bus, hd, 0);
 336
 337     /* Second IDE channel is a MAC IDE on the MacIO bus */
 338     index = drive_get_index(IF_IDE, 1, 0);
 339     if (index == -1)
 340         hd[0] = NULL;
 341     else
 342         hd[0] =  drives_table[index].bdrv;
 343     index = drive_get_index(IF_IDE, 1, 1);
 344     if (index == -1)
 345         hd[1] = NULL;
 346     else
 347         hd[1] =  drives_table[index].bdrv;
 348
 349     dbdma = DBDMA_init(&dbdma_mem_index);
 350
 351     ide_mem_index[0] = -1;
 352     ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D], dbdma, 0x16, pic[0x02]);
 353
 354     /* cuda also initialize ADB */
 355     cuda_init(&cuda_mem_index, pic[0x12]);
 356
 357     adb_kbd_init(&adb_bus);
 358     adb_mouse_init(&adb_bus);
 359
 360     nvr = macio_nvram_init(&nvram_mem_index, 0x2000);
 361     pmac_format_nvram_partition(nvr, 0x2000);
 362
 363     macio_init(pci_bus, 0x0010, 1, pic_mem_index, dbdma_mem_index,
 364                cuda_mem_index, nvr, 2, ide_mem_index, escc_mem_index);
 365
 366     if (usb_enabled) {
 367         usb_ohci_init_pci(pci_bus, 3, -1);
 368     }
 369
 370     if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
 371         graphic_depth = 15;
 372
 373     m48t59 = m48t59_init(0, 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
 374     nvram.opaque = m48t59;
 375     nvram.read_fn = &m48t59_read;
 376     nvram.write_fn = &m48t59_write;
 377     PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "HEATHROW", ram_size,
 378                          ppc_boot_device, kernel_base, kernel_size,
 379                          kernel_cmdline,
 380                          initrd_base, initrd_size,
 381                          /* XXX: need an option to load a NVRAM image */
 382                          0,
 383                          graphic_width, graphic_height, graphic_depth);
 384     /* No PCI init: the BIOS will do it */
 385
 386     fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
 387     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 388     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 389     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
 390 }
 391
 392 QEMUMachine heathrow_machine = {
 393     .name = "g3beige",
 394     .desc = "Heathrow based PowerMAC",
 395     .init = ppc_heathrow_init,
 396     .ram_require = BIOS_SIZE + VGA_BIOS_SIZE + VGA_RAM_SIZE,
 397     .max_cpus = MAX_CPUS,
 398 };