target-cris/mmu.c

   1 /*
   2  *  CRIS mmu emulation.
   3  *
   4  *  Copyright (c) 2007 AXIS Communications AB
   5  *  Written by Edgar E. Iglesias.
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #ifndef CONFIG_USER_ONLY
  23
  24 #include <stdio.h>
  25 #include <string.h>
  26 #include <stdlib.h>
  27
  28 #include "config.h"
  29 #include "cpu.h"
  30 #include "mmu.h"
  31 #include "exec-all.h"
  32
  33 #define D(x)
  34
  35 static inline int cris_mmu_enabled(uint32_t rw_gc_cfg)
  36 {
  37         return (rw_gc_cfg & 12) != 0;
  38 }
  39
  40 static inline int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg)
  41 {
  42         return (1 << seg) & rw_mm_cfg;
  43 }
  44
  45 static uint32_t cris_mmu_translate_seg(CPUState *env, int seg)
  46 {
  47         uint32_t base;
  48         int i;
  49
  50         if (seg < 8)
  51                 base = env->sregs[SFR_RW_MM_KBASE_LO];
  52         else
  53                 base = env->sregs[SFR_RW_MM_KBASE_HI];
  54
  55         i = seg & 7;
  56         base >>= i * 4;
  57         base &= 15;
  58
  59         base <<= 28;
  60         return base;
  61 }
  62 /* Used by the tlb decoder.  */
  63 #define EXTRACT_FIELD(src, start, end) \
  64             (((src) >> start) & ((1 << (end - start + 1)) - 1))
  65
  66 static inline void set_field(uint32_t *dst, unsigned int val,
  67                              unsigned int offset, unsigned int width)
  68 {
  69         uint32_t mask;
  70
  71         mask = (1 << width) - 1;
  72         mask <<= offset;
  73         val <<= offset;
  74
  75         val &= mask;
  76         *dst &= ~(mask);
  77         *dst |= val;
  78 }
  79
  80 static void dump_tlb(CPUState *env, int mmu)
  81 {
  82         int set;
  83         int idx;
  84         uint32_t hi, lo, tlb_vpn, tlb_pfn;
  85
  86         for (set = 0; set < 4; set++) {
  87                 for (idx = 0; idx < 16; idx++) {
  88                         lo = env->tlbsets[mmu][set][idx].lo;
  89                         hi = env->tlbsets[mmu][set][idx].hi;
  90                         tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
  91                         tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
  92
  93                         printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
  94                                         set, idx, hi, lo, tlb_vpn, tlb_pfn);
  95                 }
  96         }
  97 }
  98
  99 /* rw 0 = read, 1 = write, 2 = exec.  */
 100 static int cris_mmu_translate_page(struct cris_mmu_result_t *res,
 101                                    CPUState *env, uint32_t vaddr,
 102                                    int rw, int usermode)
 103 {
 104         unsigned int vpage;
 105         unsigned int idx;
 106         uint32_t lo, hi;
 107         uint32_t tlb_vpn, tlb_pfn = 0;
 108         int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x;
 109         int cfg_v, cfg_k, cfg_w, cfg_x;
 110         int set, match = 0;
 111         uint32_t r_cause;
 112         uint32_t r_cfg;
 113         int rwcause;
 114         int mmu = 1; /* Data mmu is default.  */
 115         int vect_base;
 116
 117         r_cause = env->sregs[SFR_R_MM_CAUSE];
 118         r_cfg = env->sregs[SFR_RW_MM_CFG];
 119
 120         switch (rw) {
 121                 case 2: rwcause = CRIS_MMU_ERR_EXEC; mmu = 0; break;
 122                 case 1: rwcause = CRIS_MMU_ERR_WRITE; break;
 123                 default:
 124                 case 0: rwcause = CRIS_MMU_ERR_READ; break;
 125         }
 126
 127         /* I exception vectors 4 - 7, D 8 - 11.  */
 128         vect_base = (mmu + 1) * 4;
 129
 130         vpage = vaddr >> 13;
 131
 132         /* We know the index which to check on each set.
 133            Scan both I and D.  */
 134 #if 0
 135         for (set = 0; set < 4; set++) {
 136                 for (idx = 0; idx < 16; idx++) {
 137                         lo = env->tlbsets[mmu][set][idx].lo;
 138                         hi = env->tlbsets[mmu][set][idx].hi;
 139                         tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
 140                         tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
 141
 142                         printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
 143                                         set, idx, hi, lo, tlb_vpn, tlb_pfn);
 144                 }
 145         }
 146 #endif
 147
 148         idx = vpage & 15;
 149         for (set = 0; set < 4; set++)
 150         {
 151                 lo = env->tlbsets[mmu][set][idx].lo;
 152                 hi = env->tlbsets[mmu][set][idx].hi;
 153
 154                 tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
 155                 tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
 156
 157                 D(printf("TLB[%d][%d] v=%x vpage=%x -> pfn=%x lo=%x hi=%x\n",
 158                                 i, idx, tlb_vpn, vpage, tlb_pfn, lo, hi));
 159                 if (tlb_vpn == vpage) {
 160                         match = 1;
 161                         break;
 162                 }
 163         }
 164
 165         res->bf_vec = vect_base;
 166         if (match) {
 167                 cfg_w  = EXTRACT_FIELD(r_cfg, 19, 19);
 168                 cfg_k  = EXTRACT_FIELD(r_cfg, 18, 18);
 169                 cfg_x  = EXTRACT_FIELD(r_cfg, 17, 17);
 170                 cfg_v  = EXTRACT_FIELD(r_cfg, 16, 16);
 171
 172                 tlb_pid = EXTRACT_FIELD(hi, 0, 7);
 173                 tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
 174                 tlb_g  = EXTRACT_FIELD(lo, 4, 4);
 175                 tlb_v = EXTRACT_FIELD(lo, 3, 3);
 176                 tlb_k = EXTRACT_FIELD(lo, 2, 2);
 177                 tlb_w = EXTRACT_FIELD(lo, 1, 1);
 178                 tlb_x = EXTRACT_FIELD(lo, 0, 0);
 179
 180                 /*
 181                 set_exception_vector(0x04, i_mmu_refill);
 182                 set_exception_vector(0x05, i_mmu_invalid);
 183                 set_exception_vector(0x06, i_mmu_access);
 184                 set_exception_vector(0x07, i_mmu_execute);
 185                 set_exception_vector(0x08, d_mmu_refill);
 186                 set_exception_vector(0x09, d_mmu_invalid);
 187                 set_exception_vector(0x0a, d_mmu_access);
 188                 set_exception_vector(0x0b, d_mmu_write);
 189                 */
 190                 if (!tlb_g
 191                     && tlb_pid != (env->pregs[PR_PID] & 0xff)) {
 192                         D(printf ("tlb: wrong pid %x %x pc=%x\n",
 193                                  tlb_pid, env->pregs[PR_PID], env->pc));
 194                         match = 0;
 195                         res->bf_vec = vect_base;
 196                 } else if (cfg_k && tlb_k && usermode) {
 197                         D(printf ("tlb: kernel protected %x lo=%x pc=%x\n",
 198                                   vaddr, lo, env->pc));
 199                         match = 0;
 200                         res->bf_vec = vect_base + 2;
 201                 } else if (rw == 1 && cfg_w && !tlb_w) {
 202                         D(printf ("tlb: write protected %x lo=%x pc=%x\n",
 203                                   vaddr, lo, env->pc));
 204                         match = 0;
 205                         /* write accesses never go through the I mmu.  */
 206                         res->bf_vec = vect_base + 3;
 207                 } else if (rw == 2 && cfg_x && !tlb_x) {
 208                         D(printf ("tlb: exec protected %x lo=%x pc=%x\n",
 209                                  vaddr, lo, env->pc));
 210                         match = 0;
 211                         res->bf_vec = vect_base + 3;
 212                 } else if (cfg_v && !tlb_v) {
 213                         D(printf ("tlb: invalid %x\n", vaddr));
 214                         set_field(&r_cause, rwcause, 8, 9);
 215                         match = 0;
 216                         res->bf_vec = vect_base + 1;
 217                 }
 218
 219                 res->prot = 0;
 220                 if (match) {
 221                         res->prot |= PAGE_READ;
 222                         if (tlb_w)
 223                                 res->prot |= PAGE_WRITE;
 224                         if (tlb_x)
 225                                 res->prot |= PAGE_EXEC;
 226                 }
 227                 else
 228                         D(dump_tlb(env, mmu));
 229
 230                 env->sregs[SFR_RW_MM_TLB_HI] = hi;
 231                 env->sregs[SFR_RW_MM_TLB_LO] = lo;
 232         }
 233
 234         if (!match) {
 235                 /* miss.  */
 236                 idx = vpage & 15;
 237                 set = 0;
 238
 239                 /* Update RW_MM_TLB_SEL.  */
 240                 env->sregs[SFR_RW_MM_TLB_SEL] = 0;
 241                 set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4);
 242                 set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 5);
 243
 244                 /* Update RW_MM_CAUSE.  */
 245                 set_field(&r_cause, rwcause, 8, 2);
 246                 set_field(&r_cause, vpage, 13, 19);
 247                 set_field(&r_cause, env->pregs[PR_PID], 0, 8);
 248                 env->sregs[SFR_R_MM_CAUSE] = r_cause;
 249                 D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc));
 250         }
 251
 252
 253         D(printf ("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
 254                   " %x cause=%x sel=%x sp=%x %x %x\n",
 255                   __func__, rw, match, env->pc,
 256                   vaddr, vpage,
 257                   tlb_vpn, tlb_pfn, tlb_pid,
 258                   env->pregs[PR_PID],
 259                   r_cause,
 260                   env->sregs[SFR_RW_MM_TLB_SEL],
 261                   env->regs[R_SP], env->pregs[PR_USP], env->ksp));
 262
 263         res->pfn = tlb_pfn;
 264         return !match;
 265 }
 266
 267 /* Give us the vaddr corresponding to the latest TLB update.  */
 268 target_ulong cris_mmu_tlb_latest_update(CPUState *env)
 269 {
 270         uint32_t sel = env->sregs[SFR_RW_MM_TLB_SEL];
 271         uint32_t vaddr;
 272         uint32_t hi;
 273         int set;
 274         int idx;
 275
 276         idx = EXTRACT_FIELD(sel, 0, 4);
 277         set = EXTRACT_FIELD(sel, 4, 5);
 278
 279         hi = env->tlbsets[1][set][idx].hi;
 280         vaddr = EXTRACT_FIELD(hi, 13, 31);
 281         return vaddr << TARGET_PAGE_BITS;
 282 }
 283
 284 int cris_mmu_translate(struct cris_mmu_result_t *res,
 285                        CPUState *env, uint32_t vaddr,
 286                        int rw, int mmu_idx)
 287 {
 288         uint32_t phy = vaddr;
 289         int seg;
 290         int miss = 0;
 291         int is_user = mmu_idx == MMU_USER_IDX;
 292         uint32_t old_srs;
 293
 294         old_srs= env->pregs[PR_SRS];
 295
 296         /* rw == 2 means exec, map the access to the insn mmu.  */
 297         env->pregs[PR_SRS] = rw == 2 ? 1 : 2;
 298
 299         if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
 300                 res->phy = vaddr;
 301                 res->prot = PAGE_BITS;
 302                 goto done;
 303         }
 304
 305         seg = vaddr >> 28;
 306         if (cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG]))
 307         {
 308                 uint32_t base;
 309
 310                 miss = 0;
 311                 base = cris_mmu_translate_seg(env, seg);
 312                 phy = base | (0x0fffffff & vaddr);
 313                 res->phy = phy;
 314                 res->prot = PAGE_BITS;
 315         }
 316         else
 317         {
 318                 miss = cris_mmu_translate_page(res, env, vaddr, rw, is_user);
 319                 phy = (res->pfn << 13);
 320                 res->phy = phy;
 321         }
 322   done:
 323         env->pregs[PR_SRS] = old_srs;
 324         return miss;
 325 }
 326 #endif