target-mips/exec.h

   1 #if !defined(__QEMU_MIPS_EXEC_H__)
   2 #define __QEMU_MIPS_EXEC_H__
   3
   4 //#define DEBUG_OP
   5
   6 #include "config.h"
   7 #include "mips-defs.h"
   8 #include "dyngen-exec.h"
   9 #include "cpu-defs.h"
  10
  11 register struct CPUMIPSState *env asm(AREG0);
  12
  13 #if TARGET_LONG_BITS > HOST_LONG_BITS
  14 #define T0 (env->t0)
  15 #define T1 (env->t1)
  16 #else
  17 register target_ulong T0 asm(AREG1);
  18 register target_ulong T1 asm(AREG2);
  19 #endif
  20
  21 #if defined (USE_HOST_FLOAT_REGS)
  22 #error "implement me."
  23 #else
  24 #define FDT0 (env->fpu->ft0.fd)
  25 #define FDT1 (env->fpu->ft1.fd)
  26 #define FDT2 (env->fpu->ft2.fd)
  27 #define FST0 (env->fpu->ft0.fs[FP_ENDIAN_IDX])
  28 #define FST1 (env->fpu->ft1.fs[FP_ENDIAN_IDX])
  29 #define FST2 (env->fpu->ft2.fs[FP_ENDIAN_IDX])
  30 #define FSTH0 (env->fpu->ft0.fs[!FP_ENDIAN_IDX])
  31 #define FSTH1 (env->fpu->ft1.fs[!FP_ENDIAN_IDX])
  32 #define FSTH2 (env->fpu->ft2.fs[!FP_ENDIAN_IDX])
  33 #define DT0 (env->fpu->ft0.d)
  34 #define DT1 (env->fpu->ft1.d)
  35 #define DT2 (env->fpu->ft2.d)
  36 #define WT0 (env->fpu->ft0.w[FP_ENDIAN_IDX])
  37 #define WT1 (env->fpu->ft1.w[FP_ENDIAN_IDX])
  38 #define WT2 (env->fpu->ft2.w[FP_ENDIAN_IDX])
  39 #define WTH0 (env->fpu->ft0.w[!FP_ENDIAN_IDX])
  40 #define WTH1 (env->fpu->ft1.w[!FP_ENDIAN_IDX])
  41 #define WTH2 (env->fpu->ft2.w[!FP_ENDIAN_IDX])
  42 #endif
  43
  44 #include "cpu.h"
  45 #include "exec-all.h"
  46
  47 #if !defined(CONFIG_USER_ONLY)
  48 #include "softmmu_exec.h"
  49 #endif /* !defined(CONFIG_USER_ONLY) */
  50
  51 #if defined(TARGET_MIPS64)
  52 #if TARGET_LONG_BITS > HOST_LONG_BITS
  53 void do_dsll (void);
  54 void do_dsll32 (void);
  55 void do_dsra (void);
  56 void do_dsra32 (void);
  57 void do_dsrl (void);
  58 void do_dsrl32 (void);
  59 void do_drotr (void);
  60 void do_drotr32 (void);
  61 void do_dsllv (void);
  62 void do_dsrav (void);
  63 void do_dsrlv (void);
  64 void do_drotrv (void);
  65 void do_dclo (void);
  66 void do_dclz (void);
  67 #endif
  68 #endif
  69
  70 #if HOST_LONG_BITS < 64
  71 void do_div (void);
  72 #endif
  73 #if TARGET_LONG_BITS > HOST_LONG_BITS
  74 void do_mult (void);
  75 void do_multu (void);
  76 void do_madd (void);
  77 void do_maddu (void);
  78 void do_msub (void);
  79 void do_msubu (void);
  80 void do_muls (void);
  81 void do_mulsu (void);
  82 void do_macc (void);
  83 void do_macchi (void);
  84 void do_maccu (void);
  85 void do_macchiu (void);
  86 void do_msac (void);
  87 void do_msachi (void);
  88 void do_msacu (void);
  89 void do_msachiu (void);
  90 void do_mulhi (void);
  91 void do_mulhiu (void);
  92 void do_mulshi (void);
  93 void do_mulshiu (void);
  94 #endif
  95 #if defined(TARGET_MIPS64)
  96 void do_ddiv (void);
  97 #if TARGET_LONG_BITS > HOST_LONG_BITS
  98 void do_ddivu (void);
  99 #endif
 100 #endif
 101 void do_mfc0_random(void);
 102 void do_mfc0_count(void);
 103 void do_mtc0_entryhi(uint32_t in);
 104 void do_mtc0_status_debug(uint32_t old, uint32_t val);
 105 void do_mtc0_status_irqraise_debug(void);
 106 void dump_fpu(CPUState *env);
 107 void fpu_dump_state(CPUState *env, FILE *f,
 108                     int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
 109                     int flags);
 110 void dump_sc (void);
 111 void do_pmon (int function);
 112
 113 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
 114                                int mmu_idx, int is_softmmu);
 115 void do_interrupt (CPUState *env);
 116 void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra);
 117
 118 void cpu_loop_exit(void);
 119 void do_raise_exception_err (uint32_t exception, int error_code);
 120 void do_raise_exception (uint32_t exception);
 121 void do_raise_exception_direct_err (uint32_t exception, int error_code);
 122 void do_raise_exception_direct (uint32_t exception);
 123
 124 void cpu_dump_state(CPUState *env, FILE *f,
 125                     int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
 126                     int flags);
 127 void cpu_mips_irqctrl_init (void);
 128 uint32_t cpu_mips_get_random (CPUState *env);
 129 uint32_t cpu_mips_get_count (CPUState *env);
 130 void cpu_mips_store_count (CPUState *env, uint32_t value);
 131 void cpu_mips_store_compare (CPUState *env, uint32_t value);
 132 void cpu_mips_start_count(CPUState *env);
 133 void cpu_mips_stop_count(CPUState *env);
 134 void cpu_mips_update_irq (CPUState *env);
 135 void cpu_mips_clock_init (CPUState *env);
 136 void cpu_mips_tlb_flush (CPUState *env, int flush_global);
 137
 138 void do_cfc1 (int reg);
 139 void do_ctc1 (int reg);
 140
 141 #define FOP_PROTO(op)              \
 142 void do_float_ ## op ## _s(void);  \
 143 void do_float_ ## op ## _d(void);
 144 FOP_PROTO(roundl)
 145 FOP_PROTO(roundw)
 146 FOP_PROTO(truncl)
 147 FOP_PROTO(truncw)
 148 FOP_PROTO(ceill)
 149 FOP_PROTO(ceilw)
 150 FOP_PROTO(floorl)
 151 FOP_PROTO(floorw)
 152 FOP_PROTO(rsqrt)
 153 FOP_PROTO(recip)
 154 #undef FOP_PROTO
 155
 156 #define FOP_PROTO(op)              \
 157 void do_float_ ## op ## _s(void);  \
 158 void do_float_ ## op ## _d(void);  \
 159 void do_float_ ## op ## _ps(void);
 160 FOP_PROTO(add)
 161 FOP_PROTO(sub)
 162 FOP_PROTO(mul)
 163 FOP_PROTO(div)
 164 FOP_PROTO(recip1)
 165 FOP_PROTO(recip2)
 166 FOP_PROTO(rsqrt1)
 167 FOP_PROTO(rsqrt2)
 168 #undef FOP_PROTO
 169
 170 void do_float_cvtd_s(void);
 171 void do_float_cvtd_w(void);
 172 void do_float_cvtd_l(void);
 173 void do_float_cvtl_d(void);
 174 void do_float_cvtl_s(void);
 175 void do_float_cvtps_pw(void);
 176 void do_float_cvtpw_ps(void);
 177 void do_float_cvts_d(void);
 178 void do_float_cvts_w(void);
 179 void do_float_cvts_l(void);
 180 void do_float_cvts_pl(void);
 181 void do_float_cvts_pu(void);
 182 void do_float_cvtw_s(void);
 183 void do_float_cvtw_d(void);
 184
 185 void do_float_addr_ps(void);
 186 void do_float_mulr_ps(void);
 187
 188 #define FOP_PROTO(op)                      \
 189 void do_cmp_d_ ## op(long cc);             \
 190 void do_cmpabs_d_ ## op(long cc);          \
 191 void do_cmp_s_ ## op(long cc);             \
 192 void do_cmpabs_s_ ## op(long cc);          \
 193 void do_cmp_ps_ ## op(long cc);            \
 194 void do_cmpabs_ps_ ## op(long cc);
 195
 196 FOP_PROTO(f)
 197 FOP_PROTO(un)
 198 FOP_PROTO(eq)
 199 FOP_PROTO(ueq)
 200 FOP_PROTO(olt)
 201 FOP_PROTO(ult)
 202 FOP_PROTO(ole)
 203 FOP_PROTO(ule)
 204 FOP_PROTO(sf)
 205 FOP_PROTO(ngle)
 206 FOP_PROTO(seq)
 207 FOP_PROTO(ngl)
 208 FOP_PROTO(lt)
 209 FOP_PROTO(nge)
 210 FOP_PROTO(le)
 211 FOP_PROTO(ngt)
 212 #undef FOP_PROTO
 213
 214 static always_inline void env_to_regs(void)
 215 {
 216 }
 217
 218 static always_inline void regs_to_env(void)
 219 {
 220 }
 221
 222 static always_inline int cpu_halted(CPUState *env)
 223 {
 224     if (!env->halted)
 225         return 0;
 226     if (env->interrupt_request &
 227         (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
 228         env->halted = 0;
 229         return 0;
 230     }
 231     return EXCP_HALTED;
 232 }
 233
 234 static always_inline void compute_hflags(CPUState *env)
 235 {
 236     env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
 237                      MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU);
 238     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
 239         !(env->CP0_Status & (1 << CP0St_ERL)) &&
 240         !(env->hflags & MIPS_HFLAG_DM)) {
 241         env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
 242     }
 243 #if defined(TARGET_MIPS64)
 244     if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
 245         (env->CP0_Status & (1 << CP0St_PX)) ||
 246         (env->CP0_Status & (1 << CP0St_UX)))
 247         env->hflags |= MIPS_HFLAG_64;
 248 #endif
 249     if ((env->CP0_Status & (1 << CP0St_CU0)) ||
 250         !(env->hflags & MIPS_HFLAG_KSU))
 251         env->hflags |= MIPS_HFLAG_CP0;
 252     if (env->CP0_Status & (1 << CP0St_CU1))
 253         env->hflags |= MIPS_HFLAG_FPU;
 254     if (env->CP0_Status & (1 << CP0St_FR))
 255         env->hflags |= MIPS_HFLAG_F64;
 256     if (env->insn_flags & ISA_MIPS32R2) {
 257         if (env->fpu->fcr0 & (1 << FCR0_F64))
 258             env->hflags |= MIPS_HFLAG_COP1X;
 259     } else if (env->insn_flags & ISA_MIPS32) {
 260         if (env->hflags & MIPS_HFLAG_64)
 261             env->hflags |= MIPS_HFLAG_COP1X;
 262     } else if (env->insn_flags & ISA_MIPS4) {
 263         /* All supported MIPS IV CPUs use the XX (CU3) to enable
 264            and disable the MIPS IV extensions to the MIPS III ISA.
 265            Some other MIPS IV CPUs ignore the bit, so the check here
 266            would be too restrictive for them.  */
 267         if (env->CP0_Status & (1 << CP0St_CU3))
 268             env->hflags |= MIPS_HFLAG_COP1X;
 269     }
 270 }
 271
 272 #endif /* !defined(__QEMU_MIPS_EXEC_H__) */