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Fix a warning: uint_fast8_t is not 8 bits on OpenBSD/Sparc64
[qemu/hppa.git] / hw / etraxfs_dma.c
blobd465aff1cdd0dda4218a304a5b8ad5014eb34ba4
1 /*
2 * QEMU ETRAX DMA Controller.
3 *
4 * Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include <stdio.h>
25 #include <sys/time.h>
26 #include "hw.h"
27 #include "qemu-common.h"
28 #include "sysemu.h"
29
30 #include "etraxfs_dma.h"
31
32 #define D(x)
33
34 #define RW_DATA (0x0 / 4)
35 #define RW_SAVED_DATA (0x58 / 4)
36 #define RW_SAVED_DATA_BUF (0x5c / 4)
37 #define RW_GROUP (0x60 / 4)
38 #define RW_GROUP_DOWN (0x7c / 4)
39 #define RW_CMD (0x80 / 4)
40 #define RW_CFG (0x84 / 4)
41 #define RW_STAT (0x88 / 4)
42 #define RW_INTR_MASK (0x8c / 4)
43 #define RW_ACK_INTR (0x90 / 4)
44 #define R_INTR (0x94 / 4)
45 #define R_MASKED_INTR (0x98 / 4)
46 #define RW_STREAM_CMD (0x9c / 4)
47
48 #define DMA_REG_MAX (0x100 / 4)
49
50 /* descriptors */
51
52 // ------------------------------------------------------------ dma_descr_group
53 typedef struct dma_descr_group {
54 uint32_t next;
55 unsigned eol : 1;
56 unsigned tol : 1;
57 unsigned bol : 1;
58 unsigned : 1;
59 unsigned intr : 1;
60 unsigned : 2;
61 unsigned en : 1;
62 unsigned : 7;
63 unsigned dis : 1;
64 unsigned md : 16;
65 struct dma_descr_group *up;
66 union {
67 struct dma_descr_context *context;
68 struct dma_descr_group *group;
69 } down;
70 } dma_descr_group;
71
72 // ---------------------------------------------------------- dma_descr_context
73 typedef struct dma_descr_context {
74 uint32_t next;
75 unsigned eol : 1;
76 unsigned : 3;
77 unsigned intr : 1;
78 unsigned : 1;
79 unsigned store_mode : 1;
80 unsigned en : 1;
81 unsigned : 7;
82 unsigned dis : 1;
83 unsigned md0 : 16;
84 unsigned md1;
85 unsigned md2;
86 unsigned md3;
87 unsigned md4;
88 uint32_t saved_data;
89 uint32_t saved_data_buf;
90 } dma_descr_context;
91
92 // ------------------------------------------------------------- dma_descr_data
93 typedef struct dma_descr_data {
94 uint32_t next;
95 uint32_t buf;
96 unsigned eol : 1;
97 unsigned : 2;
98 unsigned out_eop : 1;
99 unsigned intr : 1;
100 unsigned wait : 1;
101 unsigned : 2;
102 unsigned : 3;
103 unsigned in_eop : 1;
104 unsigned : 4;
105 unsigned md : 16;
106 uint32_t after;
107 } dma_descr_data;
108
109 /* Constants */
110 enum {
111 regk_dma_ack_pkt = 0x00000100,
112 regk_dma_anytime = 0x00000001,
113 regk_dma_array = 0x00000008,
114 regk_dma_burst = 0x00000020,
115 regk_dma_client = 0x00000002,
116 regk_dma_copy_next = 0x00000010,
117 regk_dma_copy_up = 0x00000020,
118 regk_dma_data_at_eol = 0x00000001,
119 regk_dma_dis_c = 0x00000010,
120 regk_dma_dis_g = 0x00000020,
121 regk_dma_idle = 0x00000001,
122 regk_dma_intern = 0x00000004,
123 regk_dma_load_c = 0x00000200,
124 regk_dma_load_c_n = 0x00000280,
125 regk_dma_load_c_next = 0x00000240,
126 regk_dma_load_d = 0x00000140,
127 regk_dma_load_g = 0x00000300,
128 regk_dma_load_g_down = 0x000003c0,
129 regk_dma_load_g_next = 0x00000340,
130 regk_dma_load_g_up = 0x00000380,
131 regk_dma_next_en = 0x00000010,
132 regk_dma_next_pkt = 0x00000010,
133 regk_dma_no = 0x00000000,
134 regk_dma_only_at_wait = 0x00000000,
135 regk_dma_restore = 0x00000020,
136 regk_dma_rst = 0x00000001,
137 regk_dma_running = 0x00000004,
138 regk_dma_rw_cfg_default = 0x00000000,
139 regk_dma_rw_cmd_default = 0x00000000,
140 regk_dma_rw_intr_mask_default = 0x00000000,
141 regk_dma_rw_stat_default = 0x00000101,
142 regk_dma_rw_stream_cmd_default = 0x00000000,
143 regk_dma_save_down = 0x00000020,
144 regk_dma_save_up = 0x00000020,
145 regk_dma_set_reg = 0x00000050,
146 regk_dma_set_w_size1 = 0x00000190,
147 regk_dma_set_w_size2 = 0x000001a0,
148 regk_dma_set_w_size4 = 0x000001c0,
149 regk_dma_stopped = 0x00000002,
150 regk_dma_store_c = 0x00000002,
151 regk_dma_store_descr = 0x00000000,
152 regk_dma_store_g = 0x00000004,
153 regk_dma_store_md = 0x00000001,
154 regk_dma_sw = 0x00000008,
155 regk_dma_update_down = 0x00000020,
156 regk_dma_yes = 0x00000001
157 };
158
159 enum dma_ch_state
160 {
161 RST = 1,
162 STOPPED = 2,
163 RUNNING = 4
164 };
165
166 struct fs_dma_channel
167 {
168 qemu_irq irq;
169 struct etraxfs_dma_client *client;
170
171 /* Internal status. */
172 int stream_cmd_src;
173 enum dma_ch_state state;
174
175 unsigned int input : 1;
176 unsigned int eol : 1;
177
178 struct dma_descr_group current_g;
179 struct dma_descr_context current_c;
180 struct dma_descr_data current_d;
181
182 /* Controll registers. */
183 uint32_t regs[DMA_REG_MAX];
184 };
185
186 struct fs_dma_ctrl
187 {
188 int map;
189 CPUState *env;
190
191 int nr_channels;
192 struct fs_dma_channel *channels;
193
194 QEMUBH *bh;
195 };
196
197 static void DMA_run(void *opaque);
198 static int channel_out_run(struct fs_dma_ctrl *ctrl, int c);
199
200 static inline uint32_t channel_reg(struct fs_dma_ctrl *ctrl, int c, int reg)
201 {
202 return ctrl->channels[c].regs[reg];
203 }
204
205 static inline int channel_stopped(struct fs_dma_ctrl *ctrl, int c)
206 {
207 return channel_reg(ctrl, c, RW_CFG) & 2;
208 }
209
210 static inline int channel_en(struct fs_dma_ctrl *ctrl, int c)
211 {
212 return (channel_reg(ctrl, c, RW_CFG) & 1)
213 && ctrl->channels[c].client;
214 }
215
216 static inline int fs_channel(target_phys_addr_t addr)
217 {
218 /* Every channel has a 0x2000 ctrl register map. */
219 return addr >> 13;
220 }
221
222 #ifdef USE_THIS_DEAD_CODE
223 static void channel_load_g(struct fs_dma_ctrl *ctrl, int c)
224 {
225 target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP);
226
227 /* Load and decode. FIXME: handle endianness. */
228 cpu_physical_memory_read (addr,
229 (void *) &ctrl->channels[c].current_g,
230 sizeof ctrl->channels[c].current_g);
231 }
232
233 static void dump_c(int ch, struct dma_descr_context *c)
234 {
235 printf("%s ch=%d\n", __func__, ch);
236 printf("next=%x\n", c->next);
237 printf("saved_data=%x\n", c->saved_data);
238 printf("saved_data_buf=%x\n", c->saved_data_buf);
239 printf("eol=%x\n", (uint32_t) c->eol);
240 }
241
242 static void dump_d(int ch, struct dma_descr_data *d)
243 {
244 printf("%s ch=%d\n", __func__, ch);
245 printf("next=%x\n", d->next);
246 printf("buf=%x\n", d->buf);
247 printf("after=%x\n", d->after);
248 printf("intr=%x\n", (uint32_t) d->intr);
249 printf("out_eop=%x\n", (uint32_t) d->out_eop);
250 printf("in_eop=%x\n", (uint32_t) d->in_eop);
251 printf("eol=%x\n", (uint32_t) d->eol);
252 }
253 #endif
254
255 static void channel_load_c(struct fs_dma_ctrl *ctrl, int c)
256 {
257 target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
258
259 /* Load and decode. FIXME: handle endianness. */
260 cpu_physical_memory_read (addr,
261 (void *) &ctrl->channels[c].current_c,
262 sizeof ctrl->channels[c].current_c);
263
264 D(dump_c(c, &ctrl->channels[c].current_c));
265 /* I guess this should update the current pos. */
266 ctrl->channels[c].regs[RW_SAVED_DATA] =
267 (uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data;
268 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
269 (uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data_buf;
270 }
271
272 static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
273 {
274 target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
275
276 /* Load and decode. FIXME: handle endianness. */
277 D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
278 cpu_physical_memory_read (addr,
279 (void *) &ctrl->channels[c].current_d,
280 sizeof ctrl->channels[c].current_d);
281
282 D(dump_d(c, &ctrl->channels[c].current_d));
283 ctrl->channels[c].regs[RW_DATA] = addr;
284 }
285
286 static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
287 {
288 target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
289
290 /* Encode and store. FIXME: handle endianness. */
291 D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
292 D(dump_d(c, &ctrl->channels[c].current_d));
293 cpu_physical_memory_write (addr,
294 (void *) &ctrl->channels[c].current_c,
295 sizeof ctrl->channels[c].current_c);
296 }
297
298 static void channel_store_d(struct fs_dma_ctrl *ctrl, int c)
299 {
300 target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
301
302 /* Encode and store. FIXME: handle endianness. */
303 D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr));
304 cpu_physical_memory_write (addr,
305 (void *) &ctrl->channels[c].current_d,
306 sizeof ctrl->channels[c].current_d);
307 }
308
309 static inline void channel_stop(struct fs_dma_ctrl *ctrl, int c)
310 {
311 /* FIXME: */
312 }
313
314 static inline void channel_start(struct fs_dma_ctrl *ctrl, int c)
315 {
316 if (ctrl->channels[c].client)
317 {
318 ctrl->channels[c].eol = 0;
319 ctrl->channels[c].state = RUNNING;
320 if (!ctrl->channels[c].input)
321 channel_out_run(ctrl, c);
322 } else
323 printf("WARNING: starting DMA ch %d with no client\n", c);
324
325 qemu_bh_schedule_idle(ctrl->bh);
326 }
327
328 static void channel_continue(struct fs_dma_ctrl *ctrl, int c)
329 {
330 if (!channel_en(ctrl, c)
331 || channel_stopped(ctrl, c)
332 || ctrl->channels[c].state != RUNNING
333 /* Only reload the current data descriptor if it has eol set. */
334 || !ctrl->channels[c].current_d.eol) {
335 D(printf("continue failed ch=%d state=%d stopped=%d en=%d eol=%d\n",
336 c, ctrl->channels[c].state,
337 channel_stopped(ctrl, c),
338 channel_en(ctrl,c),
339 ctrl->channels[c].eol));
340 D(dump_d(c, &ctrl->channels[c].current_d));
341 return;
342 }
343
344 /* Reload the current descriptor. */
345 channel_load_d(ctrl, c);
346
347 /* If the current descriptor cleared the eol flag and we had already
348 reached eol state, do the continue. */
349 if (!ctrl->channels[c].current_d.eol && ctrl->channels[c].eol) {
350 D(printf("continue %d ok %x\n", c,
351 ctrl->channels[c].current_d.next));
352 ctrl->channels[c].regs[RW_SAVED_DATA] =
353 (uint32_t)(unsigned long)ctrl->channels[c].current_d.next;
354 channel_load_d(ctrl, c);
355 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
356 (uint32_t)(unsigned long)ctrl->channels[c].current_d.buf;
357
358 channel_start(ctrl, c);
359 }
360 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
361 (uint32_t)(unsigned long)ctrl->channels[c].current_d.buf;
362 }
363
364 static void channel_stream_cmd(struct fs_dma_ctrl *ctrl, int c, uint32_t v)
365 {
366 unsigned int cmd = v & ((1 << 10) - 1);
367
368 D(printf("%s ch=%d cmd=%x\n",
369 __func__, c, cmd));
370 if (cmd & regk_dma_load_d) {
371 channel_load_d(ctrl, c);
372 if (cmd & regk_dma_burst)
373 channel_start(ctrl, c);
374 }
375
376 if (cmd & regk_dma_load_c) {
377 channel_load_c(ctrl, c);
378 }
379 }
380
381 static void channel_update_irq(struct fs_dma_ctrl *ctrl, int c)
382 {
383 D(printf("%s %d\n", __func__, c));
384 ctrl->channels[c].regs[R_INTR] &=
385 ~(ctrl->channels[c].regs[RW_ACK_INTR]);
386
387 ctrl->channels[c].regs[R_MASKED_INTR] =
388 ctrl->channels[c].regs[R_INTR]
389 & ctrl->channels[c].regs[RW_INTR_MASK];
390
391 D(printf("%s: chan=%d masked_intr=%x\n", __func__,
392 c,
393 ctrl->channels[c].regs[R_MASKED_INTR]));
394
395 qemu_set_irq(ctrl->channels[c].irq,
396 !!ctrl->channels[c].regs[R_MASKED_INTR]);
397 }
398
399 static int channel_out_run(struct fs_dma_ctrl *ctrl, int c)
400 {
401 uint32_t len;
402 uint32_t saved_data_buf;
403 unsigned char buf[2 * 1024];
404
405 if (ctrl->channels[c].eol)
406 return 0;
407
408 do {
409 D(printf("ch=%d buf=%x after=%x\n",
410 c,
411 (uint32_t)ctrl->channels[c].current_d.buf,
412 (uint32_t)ctrl->channels[c].current_d.after));
413
414 channel_load_d(ctrl, c);
415 saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF);
416 len = (uint32_t)(unsigned long)
417 ctrl->channels[c].current_d.after;
418 len -= saved_data_buf;
419
420 if (len > sizeof buf)
421 len = sizeof buf;
422 cpu_physical_memory_read (saved_data_buf, buf, len);
423
424 D(printf("channel %d pushes %x %u bytes\n", c,
425 saved_data_buf, len));
426
427 if (ctrl->channels[c].client->client.push)
428 ctrl->channels[c].client->client.push(
429 ctrl->channels[c].client->client.opaque,
430 buf, len);
431 else
432 printf("WARNING: DMA ch%d dataloss,"
433 " no attached client.\n", c);
434
435 saved_data_buf += len;
436
437 if (saved_data_buf == (uint32_t)(unsigned long)
438 ctrl->channels[c].current_d.after) {
439 /* Done. Step to next. */
440 if (ctrl->channels[c].current_d.out_eop) {
441 /* TODO: signal eop to the client. */
442 D(printf("signal eop\n"));
443 }
444 if (ctrl->channels[c].current_d.intr) {
445 /* TODO: signal eop to the client. */
446 /* data intr. */
447 D(printf("signal intr %d eol=%d\n",
448 len, ctrl->channels[c].current_d.eol));
449 ctrl->channels[c].regs[R_INTR] |= (1 << 2);
450 channel_update_irq(ctrl, c);
451 }
452 channel_store_d(ctrl, c);
453 if (ctrl->channels[c].current_d.eol) {
454 D(printf("channel %d EOL\n", c));
455 ctrl->channels[c].eol = 1;
456
457 /* Mark the context as disabled. */
458 ctrl->channels[c].current_c.dis = 1;
459 channel_store_c(ctrl, c);
460
461 channel_stop(ctrl, c);
462 } else {
463 ctrl->channels[c].regs[RW_SAVED_DATA] =
464 (uint32_t)(unsigned long)ctrl->
465 channels[c].current_d.next;
466 /* Load new descriptor. */
467 channel_load_d(ctrl, c);
468 saved_data_buf = (uint32_t)(unsigned long)
469 ctrl->channels[c].current_d.buf;
470 }
471
472 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
473 saved_data_buf;
474 D(dump_d(c, &ctrl->channels[c].current_d));
475 }
476 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf;
477 } while (!ctrl->channels[c].eol);
478 return 1;
479 }
480
481 static int channel_in_process(struct fs_dma_ctrl *ctrl, int c,
482 unsigned char *buf, int buflen, int eop)
483 {
484 uint32_t len;
485 uint32_t saved_data_buf;
486
487 if (ctrl->channels[c].eol == 1)
488 return 0;
489
490 channel_load_d(ctrl, c);
491 saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF);
492 len = (uint32_t)(unsigned long)ctrl->channels[c].current_d.after;
493 len -= saved_data_buf;
494
495 if (len > buflen)
496 len = buflen;
497
498 cpu_physical_memory_write (saved_data_buf, buf, len);
499 saved_data_buf += len;
500
501 if (saved_data_buf ==
502 (uint32_t)(unsigned long)ctrl->channels[c].current_d.after
503 || eop) {
504 uint32_t r_intr = ctrl->channels[c].regs[R_INTR];
505
506 D(printf("in dscr end len=%d\n",
507 ctrl->channels[c].current_d.after
508 - ctrl->channels[c].current_d.buf));
509 ctrl->channels[c].current_d.after = saved_data_buf;
510
511 /* Done. Step to next. */
512 if (ctrl->channels[c].current_d.intr) {
513 /* TODO: signal eop to the client. */
514 /* data intr. */
515 ctrl->channels[c].regs[R_INTR] |= 3;
516 }
517 if (eop) {
518 ctrl->channels[c].current_d.in_eop = 1;
519 ctrl->channels[c].regs[R_INTR] |= 8;
520 }
521 if (r_intr != ctrl->channels[c].regs[R_INTR])
522 channel_update_irq(ctrl, c);
523
524 channel_store_d(ctrl, c);
525 D(dump_d(c, &ctrl->channels[c].current_d));
526
527 if (ctrl->channels[c].current_d.eol) {
528 D(printf("channel %d EOL\n", c));
529 ctrl->channels[c].eol = 1;
530
531 /* Mark the context as disabled. */
532 ctrl->channels[c].current_c.dis = 1;
533 channel_store_c(ctrl, c);
534
535 channel_stop(ctrl, c);
536 } else {
537 ctrl->channels[c].regs[RW_SAVED_DATA] =
538 (uint32_t)(unsigned long)ctrl->
539 channels[c].current_d.next;
540 /* Load new descriptor. */
541 channel_load_d(ctrl, c);
542 saved_data_buf = (uint32_t)(unsigned long)
543 ctrl->channels[c].current_d.buf;
544 }
545 }
546
547 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf;
548 return len;
549 }
550
551 static inline int channel_in_run(struct fs_dma_ctrl *ctrl, int c)
552 {
553 if (ctrl->channels[c].client->client.pull) {
554 ctrl->channels[c].client->client.pull(
555 ctrl->channels[c].client->client.opaque);
556 return 1;
557 } else
558 return 0;
559 }
560
561 static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr)
562 {
563 hw_error("Unsupported short raccess. reg=" TARGET_FMT_plx "\n", addr);
564 return 0;
565 }
566
567 static uint32_t
568 dma_readl (void *opaque, target_phys_addr_t addr)
569 {
570 struct fs_dma_ctrl *ctrl = opaque;
571 int c;
572 uint32_t r = 0;
573
574 /* Make addr relative to this channel and bounded to nr regs. */
575 c = fs_channel(addr);
576 addr &= 0xff;
577 addr >>= 2;
578 switch (addr)
579 {
580 case RW_STAT:
581 r = ctrl->channels[c].state & 7;
582 r |= ctrl->channels[c].eol << 5;
583 r |= ctrl->channels[c].stream_cmd_src << 8;
584 break;
585
586 default:
587 r = ctrl->channels[c].regs[addr];
588 D(printf ("%s c=%d addr=" TARGET_FMT_plx "\n",
589 __func__, c, addr));
590 break;
591 }
592 return r;
593 }
594
595 static void
596 dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value)
597 {
598 hw_error("Unsupported short waccess. reg=" TARGET_FMT_plx "\n", addr);
599 }
600
601 static void
602 dma_update_state(struct fs_dma_ctrl *ctrl, int c)
603 {
604 if ((ctrl->channels[c].regs[RW_CFG] & 1) != 3) {
605 if (ctrl->channels[c].regs[RW_CFG] & 2)
606 ctrl->channels[c].state = STOPPED;
607 if (!(ctrl->channels[c].regs[RW_CFG] & 1))
608 ctrl->channels[c].state = RST;
609 }
610 }
611
612 static void
613 dma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
614 {
615 struct fs_dma_ctrl *ctrl = opaque;
616 int c;
617
618 /* Make addr relative to this channel and bounded to nr regs. */
619 c = fs_channel(addr);
620 addr &= 0xff;
621 addr >>= 2;
622 switch (addr)
623 {
624 case RW_DATA:
625 ctrl->channels[c].regs[addr] = value;
626 break;
627
628 case RW_CFG:
629 ctrl->channels[c].regs[addr] = value;
630 dma_update_state(ctrl, c);
631 break;
632 case RW_CMD:
633 /* continue. */
634 if (value & ~1)
635 printf("Invalid store to ch=%d RW_CMD %x\n",
636 c, value);
637 ctrl->channels[c].regs[addr] = value;
638 channel_continue(ctrl, c);
639 break;
640
641 case RW_SAVED_DATA:
642 case RW_SAVED_DATA_BUF:
643 case RW_GROUP:
644 case RW_GROUP_DOWN:
645 ctrl->channels[c].regs[addr] = value;
646 break;
647
648 case RW_ACK_INTR:
649 case RW_INTR_MASK:
650 ctrl->channels[c].regs[addr] = value;
651 channel_update_irq(ctrl, c);
652 if (addr == RW_ACK_INTR)
653 ctrl->channels[c].regs[RW_ACK_INTR] = 0;
654 break;
655
656 case RW_STREAM_CMD:
657 if (value & ~1023)
658 printf("Invalid store to ch=%d "
659 "RW_STREAMCMD %x\n",
660 c, value);
661 ctrl->channels[c].regs[addr] = value;
662 D(printf("stream_cmd ch=%d\n", c));
663 channel_stream_cmd(ctrl, c, value);
664 break;
665
666 default:
667 D(printf ("%s c=%d " TARGET_FMT_plx "\n",
668 __func__, c, addr));
669 break;
670 }
671 }
672
673 static CPUReadMemoryFunc *dma_read[] = {
674 &dma_rinvalid,
675 &dma_rinvalid,
676 &dma_readl,
677 };
678
679 static CPUWriteMemoryFunc *dma_write[] = {
680 &dma_winvalid,
681 &dma_winvalid,
682 &dma_writel,
683 };
684
685 static int etraxfs_dmac_run(void *opaque)
686 {
687 struct fs_dma_ctrl *ctrl = opaque;
688 int i;
689 int p = 0;
690
691 for (i = 0;
692 i < ctrl->nr_channels;
693 i++)
694 {
695 if (ctrl->channels[i].state == RUNNING)
696 {
697 if (ctrl->channels[i].input) {
698 p += channel_in_run(ctrl, i);
699 } else {
700 p += channel_out_run(ctrl, i);
701 }
702 }
703 }
704 return p;
705 }
706
707 int etraxfs_dmac_input(struct etraxfs_dma_client *client,
708 void *buf, int len, int eop)
709 {
710 return channel_in_process(client->ctrl, client->channel,
711 buf, len, eop);
712 }
713
714 /* Connect an IRQ line with a channel. */
715 void etraxfs_dmac_connect(void *opaque, int c, qemu_irq *line, int input)
716 {
717 struct fs_dma_ctrl *ctrl = opaque;
718 ctrl->channels[c].irq = *line;
719 ctrl->channels[c].input = input;
720 }
721
722 void etraxfs_dmac_connect_client(void *opaque, int c,
723 struct etraxfs_dma_client *cl)
724 {
725 struct fs_dma_ctrl *ctrl = opaque;
726 cl->ctrl = ctrl;
727 cl->channel = c;
728 ctrl->channels[c].client = cl;
729 }
730
731
732 static void DMA_run(void *opaque)
733 {
734 struct fs_dma_ctrl *etraxfs_dmac = opaque;
735 int p = 1;
736
737 if (vm_running)
738 p = etraxfs_dmac_run(etraxfs_dmac);
739
740 if (p)
741 qemu_bh_schedule_idle(etraxfs_dmac->bh);
742 }
743
744 void *etraxfs_dmac_init(CPUState *env,
745 target_phys_addr_t base, int nr_channels)
746 {
747 struct fs_dma_ctrl *ctrl = NULL;
748
749 ctrl = qemu_mallocz(sizeof *ctrl);
750
751 ctrl->bh = qemu_bh_new(DMA_run, ctrl);
752
753 ctrl->env = env;
754 ctrl->nr_channels = nr_channels;
755 ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels);
756
757 ctrl->map = cpu_register_io_memory(0, dma_read, dma_write, ctrl);
758 cpu_register_physical_memory(base, nr_channels * 0x2000, ctrl->map);
759 return ctrl;
760 }
HPPA (PA-RISC) target for QEMU