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hppa: specify target_phys_bits in configure script
[qemu/hppa.git] / hw / es1370.c
blob12f2ace0a9b41de3d8d741a071e2003e5739d63e
1 /*
2 * QEMU ES1370 emulation
3 *
4 * Copyright (c) 2005 Vassili Karpov (malc)
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 /* #define DEBUG_ES1370 */
26 /* #define VERBOSE_ES1370 */
27 #define SILENT_ES1370
28
29 #include "hw.h"
30 #include "audiodev.h"
31 #include "audio/audio.h"
32 #include "pci.h"
33
34 /* Missing stuff:
35 SCTRL_P[12](END|ST)INC
36 SCTRL_P1SCTRLD
37 SCTRL_P2DACSEN
38 CTRL_DAC_SYNC
39 MIDI
40 non looped mode
41 surely more
42 */
43
44 /*
45 Following macros and samplerate array were copied verbatim from
46 Linux kernel 2.4.30: drivers/sound/es1370.c
47
48 Copyright (C) 1998-2001, 2003 Thomas Sailer (t.sailer@alumni.ethz.ch)
49 */
50
51 /* Start blatant GPL violation */
52
53 #define ES1370_REG_CONTROL 0x00
54 #define ES1370_REG_STATUS 0x04
55 #define ES1370_REG_UART_DATA 0x08
56 #define ES1370_REG_UART_STATUS 0x09
57 #define ES1370_REG_UART_CONTROL 0x09
58 #define ES1370_REG_UART_TEST 0x0a
59 #define ES1370_REG_MEMPAGE 0x0c
60 #define ES1370_REG_CODEC 0x10
61 #define ES1370_REG_SERIAL_CONTROL 0x20
62 #define ES1370_REG_DAC1_SCOUNT 0x24
63 #define ES1370_REG_DAC2_SCOUNT 0x28
64 #define ES1370_REG_ADC_SCOUNT 0x2c
65
66 #define ES1370_REG_DAC1_FRAMEADR 0xc30
67 #define ES1370_REG_DAC1_FRAMECNT 0xc34
68 #define ES1370_REG_DAC2_FRAMEADR 0xc38
69 #define ES1370_REG_DAC2_FRAMECNT 0xc3c
70 #define ES1370_REG_ADC_FRAMEADR 0xd30
71 #define ES1370_REG_ADC_FRAMECNT 0xd34
72 #define ES1370_REG_PHANTOM_FRAMEADR 0xd38
73 #define ES1370_REG_PHANTOM_FRAMECNT 0xd3c
74
75 static const unsigned dac1_samplerate[] = { 5512, 11025, 22050, 44100 };
76
77 #define DAC2_SRTODIV(x) (((1411200+(x)/2)/(x))-2)
78 #define DAC2_DIVTOSR(x) (1411200/((x)+2))
79
80 #define CTRL_ADC_STOP 0x80000000 /* 1 = ADC stopped */
81 #define CTRL_XCTL1 0x40000000 /* electret mic bias */
82 #define CTRL_OPEN 0x20000000 /* no function, can be read and written */
83 #define CTRL_PCLKDIV 0x1fff0000 /* ADC/DAC2 clock divider */
84 #define CTRL_SH_PCLKDIV 16
85 #define CTRL_MSFMTSEL 0x00008000 /* MPEG serial data fmt: 0 = Sony, 1 = I2S */
86 #define CTRL_M_SBB 0x00004000 /* DAC2 clock: 0 = PCLKDIV, 1 = MPEG */
87 #define CTRL_WTSRSEL 0x00003000 /* DAC1 clock freq: 0=5512, 1=11025, 2=22050, 3=44100 */
88 #define CTRL_SH_WTSRSEL 12
89 #define CTRL_DAC_SYNC 0x00000800 /* 1 = DAC2 runs off DAC1 clock */
90 #define CTRL_CCB_INTRM 0x00000400 /* 1 = CCB "voice" ints enabled */
91 #define CTRL_M_CB 0x00000200 /* recording source: 0 = ADC, 1 = MPEG */
92 #define CTRL_XCTL0 0x00000100 /* 0 = Line in, 1 = Line out */
93 #define CTRL_BREQ 0x00000080 /* 1 = test mode (internal mem test) */
94 #define CTRL_DAC1_EN 0x00000040 /* enable DAC1 */
95 #define CTRL_DAC2_EN 0x00000020 /* enable DAC2 */
96 #define CTRL_ADC_EN 0x00000010 /* enable ADC */
97 #define CTRL_UART_EN 0x00000008 /* enable MIDI uart */
98 #define CTRL_JYSTK_EN 0x00000004 /* enable Joystick port (presumably at address 0x200) */
99 #define CTRL_CDC_EN 0x00000002 /* enable serial (CODEC) interface */
100 #define CTRL_SERR_DIS 0x00000001 /* 1 = disable PCI SERR signal */
101
102 #define STAT_INTR 0x80000000 /* wired or of all interrupt bits */
103 #define STAT_CSTAT 0x00000400 /* 1 = codec busy or codec write in progress */
104 #define STAT_CBUSY 0x00000200 /* 1 = codec busy */
105 #define STAT_CWRIP 0x00000100 /* 1 = codec write in progress */
106 #define STAT_VC 0x00000060 /* CCB int source, 0=DAC1, 1=DAC2, 2=ADC, 3=undef */
107 #define STAT_SH_VC 5
108 #define STAT_MCCB 0x00000010 /* CCB int pending */
109 #define STAT_UART 0x00000008 /* UART int pending */
110 #define STAT_DAC1 0x00000004 /* DAC1 int pending */
111 #define STAT_DAC2 0x00000002 /* DAC2 int pending */
112 #define STAT_ADC 0x00000001 /* ADC int pending */
113
114 #define USTAT_RXINT 0x80 /* UART rx int pending */
115 #define USTAT_TXINT 0x04 /* UART tx int pending */
116 #define USTAT_TXRDY 0x02 /* UART tx ready */
117 #define USTAT_RXRDY 0x01 /* UART rx ready */
118
119 #define UCTRL_RXINTEN 0x80 /* 1 = enable RX ints */
120 #define UCTRL_TXINTEN 0x60 /* TX int enable field mask */
121 #define UCTRL_ENA_TXINT 0x20 /* enable TX int */
122 #define UCTRL_CNTRL 0x03 /* control field */
123 #define UCTRL_CNTRL_SWR 0x03 /* software reset command */
124
125 #define SCTRL_P2ENDINC 0x00380000 /* */
126 #define SCTRL_SH_P2ENDINC 19
127 #define SCTRL_P2STINC 0x00070000 /* */
128 #define SCTRL_SH_P2STINC 16
129 #define SCTRL_R1LOOPSEL 0x00008000 /* 0 = loop mode */
130 #define SCTRL_P2LOOPSEL 0x00004000 /* 0 = loop mode */
131 #define SCTRL_P1LOOPSEL 0x00002000 /* 0 = loop mode */
132 #define SCTRL_P2PAUSE 0x00001000 /* 1 = pause mode */
133 #define SCTRL_P1PAUSE 0x00000800 /* 1 = pause mode */
134 #define SCTRL_R1INTEN 0x00000400 /* enable interrupt */
135 #define SCTRL_P2INTEN 0x00000200 /* enable interrupt */
136 #define SCTRL_P1INTEN 0x00000100 /* enable interrupt */
137 #define SCTRL_P1SCTRLD 0x00000080 /* reload sample count register for DAC1 */
138 #define SCTRL_P2DACSEN 0x00000040 /* 1 = DAC2 play back last sample when disabled */
139 #define SCTRL_R1SEB 0x00000020 /* 1 = 16bit */
140 #define SCTRL_R1SMB 0x00000010 /* 1 = stereo */
141 #define SCTRL_R1FMT 0x00000030 /* format mask */
142 #define SCTRL_SH_R1FMT 4
143 #define SCTRL_P2SEB 0x00000008 /* 1 = 16bit */
144 #define SCTRL_P2SMB 0x00000004 /* 1 = stereo */
145 #define SCTRL_P2FMT 0x0000000c /* format mask */
146 #define SCTRL_SH_P2FMT 2
147 #define SCTRL_P1SEB 0x00000002 /* 1 = 16bit */
148 #define SCTRL_P1SMB 0x00000001 /* 1 = stereo */
149 #define SCTRL_P1FMT 0x00000003 /* format mask */
150 #define SCTRL_SH_P1FMT 0
151
152 /* End blatant GPL violation */
153
154 #define NB_CHANNELS 3
155 #define DAC1_CHANNEL 0
156 #define DAC2_CHANNEL 1
157 #define ADC_CHANNEL 2
158
159 #define IO_READ_PROTO(n) \
160 static uint32_t n (void *opaque, uint32_t addr)
161 #define IO_WRITE_PROTO(n) \
162 static void n (void *opaque, uint32_t addr, uint32_t val)
163
164 static void es1370_dac1_callback (void *opaque, int free);
165 static void es1370_dac2_callback (void *opaque, int free);
166 static void es1370_adc_callback (void *opaque, int avail);
167
168 #ifdef DEBUG_ES1370
169
170 #define ldebug(...) AUD_log ("es1370", __VA_ARGS__)
171
172 static void print_ctl (uint32_t val)
173 {
174 char buf[1024];
175
176 buf[0] = '\0';
177 #define a(n) if (val & CTRL_##n) strcat (buf, " "#n)
178 a (ADC_STOP);
179 a (XCTL1);
180 a (OPEN);
181 a (MSFMTSEL);
182 a (M_SBB);
183 a (DAC_SYNC);
184 a (CCB_INTRM);
185 a (M_CB);
186 a (XCTL0);
187 a (BREQ);
188 a (DAC1_EN);
189 a (DAC2_EN);
190 a (ADC_EN);
191 a (UART_EN);
192 a (JYSTK_EN);
193 a (CDC_EN);
194 a (SERR_DIS);
195 #undef a
196 AUD_log ("es1370", "ctl - PCLKDIV %d(DAC2 freq %d), freq %d,%s\n",
197 (val & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV,
198 DAC2_DIVTOSR ((val & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV),
199 dac1_samplerate[(val & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL],
200 buf);
201 }
202
203 static void print_sctl (uint32_t val)
204 {
205 static const char *fmt_names[] = {"8M", "8S", "16M", "16S"};
206 char buf[1024];
207
208 buf[0] = '\0';
209
210 #define a(n) if (val & SCTRL_##n) strcat (buf, " "#n)
211 #define b(n) if (!(val & SCTRL_##n)) strcat (buf, " "#n)
212 b (R1LOOPSEL);
213 b (P2LOOPSEL);
214 b (P1LOOPSEL);
215 a (P2PAUSE);
216 a (P1PAUSE);
217 a (R1INTEN);
218 a (P2INTEN);
219 a (P1INTEN);
220 a (P1SCTRLD);
221 a (P2DACSEN);
222 if (buf[0]) {
223 strcat (buf, "\n ");
224 }
225 else {
226 buf[0] = ' ';
227 buf[1] = '\0';
228 }
229 #undef b
230 #undef a
231 AUD_log ("es1370",
232 "%s"
233 "p2_end_inc %d, p2_st_inc %d, r1_fmt %s, p2_fmt %s, p1_fmt %s\n",
234 buf,
235 (val & SCTRL_P2ENDINC) >> SCTRL_SH_P2ENDINC,
236 (val & SCTRL_P2STINC) >> SCTRL_SH_P2STINC,
237 fmt_names [(val >> SCTRL_SH_R1FMT) & 3],
238 fmt_names [(val >> SCTRL_SH_P2FMT) & 3],
239 fmt_names [(val >> SCTRL_SH_P1FMT) & 3]
240 );
241 }
242 #else
243 #define ldebug(...)
244 #define print_ctl(...)
245 #define print_sctl(...)
246 #endif
247
248 #ifdef VERBOSE_ES1370
249 #define dolog(...) AUD_log ("es1370", __VA_ARGS__)
250 #else
251 #define dolog(...)
252 #endif
253
254 #ifndef SILENT_ES1370
255 #define lwarn(...) AUD_log ("es1370: warning", __VA_ARGS__)
256 #else
257 #define lwarn(...)
258 #endif
259
260 struct chan {
261 uint32_t shift;
262 uint32_t leftover;
263 uint32_t scount;
264 uint32_t frame_addr;
265 uint32_t frame_cnt;
266 };
267
268 typedef struct ES1370State {
269 PCIDevice *pci_dev;
270
271 QEMUSoundCard card;
272 struct chan chan[NB_CHANNELS];
273 SWVoiceOut *dac_voice[2];
274 SWVoiceIn *adc_voice;
275
276 uint32_t ctl;
277 uint32_t status;
278 uint32_t mempage;
279 uint32_t codec;
280 uint32_t sctl;
281 } ES1370State;
282
283 typedef struct PCIES1370State {
284 PCIDevice dev;
285 ES1370State es1370;
286 } PCIES1370State;
287
288 struct chan_bits {
289 uint32_t ctl_en;
290 uint32_t stat_int;
291 uint32_t sctl_pause;
292 uint32_t sctl_inten;
293 uint32_t sctl_fmt;
294 uint32_t sctl_sh_fmt;
295 uint32_t sctl_loopsel;
296 void (*calc_freq) (ES1370State *s, uint32_t ctl,
297 uint32_t *old_freq, uint32_t *new_freq);
298 };
299
300 static void es1370_dac1_calc_freq (ES1370State *s, uint32_t ctl,
301 uint32_t *old_freq, uint32_t *new_freq);
302 static void es1370_dac2_and_adc_calc_freq (ES1370State *s, uint32_t ctl,
303 uint32_t *old_freq,
304 uint32_t *new_freq);
305
306 static const struct chan_bits es1370_chan_bits[] = {
307 {CTRL_DAC1_EN, STAT_DAC1, SCTRL_P1PAUSE, SCTRL_P1INTEN,
308 SCTRL_P1FMT, SCTRL_SH_P1FMT, SCTRL_P1LOOPSEL,
309 es1370_dac1_calc_freq},
310
311 {CTRL_DAC2_EN, STAT_DAC2, SCTRL_P2PAUSE, SCTRL_P2INTEN,
312 SCTRL_P2FMT, SCTRL_SH_P2FMT, SCTRL_P2LOOPSEL,
313 es1370_dac2_and_adc_calc_freq},
314
315 {CTRL_ADC_EN, STAT_ADC, 0, SCTRL_R1INTEN,
316 SCTRL_R1FMT, SCTRL_SH_R1FMT, SCTRL_R1LOOPSEL,
317 es1370_dac2_and_adc_calc_freq}
318 };
319
320 static void es1370_update_status (ES1370State *s, uint32_t new_status)
321 {
322 uint32_t level = new_status & (STAT_DAC1 | STAT_DAC2 | STAT_ADC);
323
324 if (level) {
325 s->status = new_status | STAT_INTR;
326 }
327 else {
328 s->status = new_status & ~STAT_INTR;
329 }
330 qemu_set_irq(s->pci_dev->irq[0], !!level);
331 }
332
333 static void es1370_reset (ES1370State *s)
334 {
335 size_t i;
336
337 s->ctl = 1;
338 s->status = 0x60;
339 s->mempage = 0;
340 s->codec = 0;
341 s->sctl = 0;
342
343 for (i = 0; i < NB_CHANNELS; ++i) {
344 struct chan *d = &s->chan[i];
345 d->scount = 0;
346 d->leftover = 0;
347 if (i == ADC_CHANNEL) {
348 AUD_close_in (&s->card, s->adc_voice);
349 s->adc_voice = NULL;
350 }
351 else {
352 AUD_close_out (&s->card, s->dac_voice[i]);
353 s->dac_voice[i] = NULL;
354 }
355 }
356 qemu_irq_lower(s->pci_dev->irq[0]);
357 }
358
359 static void es1370_maybe_lower_irq (ES1370State *s, uint32_t sctl)
360 {
361 uint32_t new_status = s->status;
362
363 if (!(sctl & SCTRL_P1INTEN) && (s->sctl & SCTRL_P1INTEN)) {
364 new_status &= ~STAT_DAC1;
365 }
366
367 if (!(sctl & SCTRL_P2INTEN) && (s->sctl & SCTRL_P2INTEN)) {
368 new_status &= ~STAT_DAC2;
369 }
370
371 if (!(sctl & SCTRL_R1INTEN) && (s->sctl & SCTRL_R1INTEN)) {
372 new_status &= ~STAT_ADC;
373 }
374
375 if (new_status != s->status) {
376 es1370_update_status (s, new_status);
377 }
378 }
379
380 static void es1370_dac1_calc_freq (ES1370State *s, uint32_t ctl,
381 uint32_t *old_freq, uint32_t *new_freq)
382
383 {
384 *old_freq = dac1_samplerate[(s->ctl & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL];
385 *new_freq = dac1_samplerate[(ctl & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL];
386 }
387
388 static void es1370_dac2_and_adc_calc_freq (ES1370State *s, uint32_t ctl,
389 uint32_t *old_freq,
390 uint32_t *new_freq)
391
392 {
393 uint32_t old_pclkdiv, new_pclkdiv;
394
395 new_pclkdiv = (ctl & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV;
396 old_pclkdiv = (s->ctl & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV;
397 *new_freq = DAC2_DIVTOSR (new_pclkdiv);
398 *old_freq = DAC2_DIVTOSR (old_pclkdiv);
399 }
400
401 static void es1370_update_voices (ES1370State *s, uint32_t ctl, uint32_t sctl)
402 {
403 size_t i;
404 uint32_t old_freq, new_freq, old_fmt, new_fmt;
405
406 for (i = 0; i < NB_CHANNELS; ++i) {
407 struct chan *d = &s->chan[i];
408 const struct chan_bits *b = &es1370_chan_bits[i];
409
410 new_fmt = (sctl & b->sctl_fmt) >> b->sctl_sh_fmt;
411 old_fmt = (s->sctl & b->sctl_fmt) >> b->sctl_sh_fmt;
412
413 b->calc_freq (s, ctl, &old_freq, &new_freq);
414
415 if ((old_fmt != new_fmt) || (old_freq != new_freq)) {
416 d->shift = (new_fmt & 1) + (new_fmt >> 1);
417 ldebug ("channel %d, freq = %d, nchannels %d, fmt %d, shift %d\n",
418 i,
419 new_freq,
420 1 << (new_fmt & 1),
421 (new_fmt & 2) ? AUD_FMT_S16 : AUD_FMT_U8,
422 d->shift);
423 if (new_freq) {
424 struct audsettings as;
425
426 as.freq = new_freq;
427 as.nchannels = 1 << (new_fmt & 1);
428 as.fmt = (new_fmt & 2) ? AUD_FMT_S16 : AUD_FMT_U8;
429 as.endianness = 0;
430
431 if (i == ADC_CHANNEL) {
432 s->adc_voice =
433 AUD_open_in (
434 &s->card,
435 s->adc_voice,
436 "es1370.adc",
437 s,
438 es1370_adc_callback,
439 &as
440 );
441 }
442 else {
443 s->dac_voice[i] =
444 AUD_open_out (
445 &s->card,
446 s->dac_voice[i],
447 i ? "es1370.dac2" : "es1370.dac1",
448 s,
449 i ? es1370_dac2_callback : es1370_dac1_callback,
450 &as
451 );
452 }
453 }
454 }
455
456 if (((ctl ^ s->ctl) & b->ctl_en)
457 || ((sctl ^ s->sctl) & b->sctl_pause)) {
458 int on = (ctl & b->ctl_en) && !(sctl & b->sctl_pause);
459
460 if (i == ADC_CHANNEL) {
461 AUD_set_active_in (s->adc_voice, on);
462 }
463 else {
464 AUD_set_active_out (s->dac_voice[i], on);
465 }
466 }
467 }
468
469 s->ctl = ctl;
470 s->sctl = sctl;
471 }
472
473 static inline uint32_t es1370_fixup (ES1370State *s, uint32_t addr)
474 {
475 addr &= 0xff;
476 if (addr >= 0x30 && addr <= 0x3f)
477 addr |= s->mempage << 8;
478 return addr;
479 }
480
481 IO_WRITE_PROTO (es1370_writeb)
482 {
483 ES1370State *s = opaque;
484 uint32_t shift, mask;
485
486 addr = es1370_fixup (s, addr);
487
488 switch (addr) {
489 case ES1370_REG_CONTROL:
490 case ES1370_REG_CONTROL + 1:
491 case ES1370_REG_CONTROL + 2:
492 case ES1370_REG_CONTROL + 3:
493 shift = (addr - ES1370_REG_CONTROL) << 3;
494 mask = 0xff << shift;
495 val = (s->ctl & ~mask) | ((val & 0xff) << shift);
496 es1370_update_voices (s, val, s->sctl);
497 print_ctl (val);
498 break;
499 case ES1370_REG_MEMPAGE:
500 s->mempage = val;
501 break;
502 case ES1370_REG_SERIAL_CONTROL:
503 case ES1370_REG_SERIAL_CONTROL + 1:
504 case ES1370_REG_SERIAL_CONTROL + 2:
505 case ES1370_REG_SERIAL_CONTROL + 3:
506 shift = (addr - ES1370_REG_SERIAL_CONTROL) << 3;
507 mask = 0xff << shift;
508 val = (s->sctl & ~mask) | ((val & 0xff) << shift);
509 es1370_maybe_lower_irq (s, val);
510 es1370_update_voices (s, s->ctl, val);
511 print_sctl (val);
512 break;
513 default:
514 lwarn ("writeb %#x <- %#x\n", addr, val);
515 break;
516 }
517 }
518
519 IO_WRITE_PROTO (es1370_writew)
520 {
521 ES1370State *s = opaque;
522 addr = es1370_fixup (s, addr);
523 uint32_t shift, mask;
524 struct chan *d = &s->chan[0];
525
526 switch (addr) {
527 case ES1370_REG_CODEC:
528 dolog ("ignored codec write address %#x, data %#x\n",
529 (val >> 8) & 0xff, val & 0xff);
530 s->codec = val;
531 break;
532
533 case ES1370_REG_CONTROL:
534 case ES1370_REG_CONTROL + 2:
535 shift = (addr != ES1370_REG_CONTROL) << 4;
536 mask = 0xffff << shift;
537 val = (s->ctl & ~mask) | ((val & 0xffff) << shift);
538 es1370_update_voices (s, val, s->sctl);
539 print_ctl (val);
540 break;
541
542 case ES1370_REG_ADC_SCOUNT:
543 d++;
544 case ES1370_REG_DAC2_SCOUNT:
545 d++;
546 case ES1370_REG_DAC1_SCOUNT:
547 d->scount = (d->scount & ~0xffff) | (val & 0xffff);
548 break;
549
550 default:
551 lwarn ("writew %#x <- %#x\n", addr, val);
552 break;
553 }
554 }
555
556 IO_WRITE_PROTO (es1370_writel)
557 {
558 ES1370State *s = opaque;
559 struct chan *d = &s->chan[0];
560
561 addr = es1370_fixup (s, addr);
562
563 switch (addr) {
564 case ES1370_REG_CONTROL:
565 es1370_update_voices (s, val, s->sctl);
566 print_ctl (val);
567 break;
568
569 case ES1370_REG_MEMPAGE:
570 s->mempage = val & 0xf;
571 break;
572
573 case ES1370_REG_SERIAL_CONTROL:
574 es1370_maybe_lower_irq (s, val);
575 es1370_update_voices (s, s->ctl, val);
576 print_sctl (val);
577 break;
578
579 case ES1370_REG_ADC_SCOUNT:
580 d++;
581 case ES1370_REG_DAC2_SCOUNT:
582 d++;
583 case ES1370_REG_DAC1_SCOUNT:
584 d->scount = (val & 0xffff) | (d->scount & ~0xffff);
585 ldebug ("chan %d CURR_SAMP_CT %d, SAMP_CT %d\n",
586 d - &s->chan[0], val >> 16, (val & 0xffff));
587 break;
588
589 case ES1370_REG_ADC_FRAMEADR:
590 d++;
591 case ES1370_REG_DAC2_FRAMEADR:
592 d++;
593 case ES1370_REG_DAC1_FRAMEADR:
594 d->frame_addr = val;
595 ldebug ("chan %d frame address %#x\n", d - &s->chan[0], val);
596 break;
597
598 case ES1370_REG_PHANTOM_FRAMECNT:
599 lwarn ("writing to phantom frame count %#x\n", val);
600 break;
601 case ES1370_REG_PHANTOM_FRAMEADR:
602 lwarn ("writing to phantom frame address %#x\n", val);
603 break;
604
605 case ES1370_REG_ADC_FRAMECNT:
606 d++;
607 case ES1370_REG_DAC2_FRAMECNT:
608 d++;
609 case ES1370_REG_DAC1_FRAMECNT:
610 d->frame_cnt = val;
611 d->leftover = 0;
612 ldebug ("chan %d frame count %d, buffer size %d\n",
613 d - &s->chan[0], val >> 16, val & 0xffff);
614 break;
615
616 default:
617 lwarn ("writel %#x <- %#x\n", addr, val);
618 break;
619 }
620 }
621
622 IO_READ_PROTO (es1370_readb)
623 {
624 ES1370State *s = opaque;
625 uint32_t val;
626
627 addr = es1370_fixup (s, addr);
628
629 switch (addr) {
630 case 0x1b: /* Legacy */
631 lwarn ("Attempt to read from legacy register\n");
632 val = 5;
633 break;
634 case ES1370_REG_MEMPAGE:
635 val = s->mempage;
636 break;
637 case ES1370_REG_CONTROL + 0:
638 case ES1370_REG_CONTROL + 1:
639 case ES1370_REG_CONTROL + 2:
640 case ES1370_REG_CONTROL + 3:
641 val = s->ctl >> ((addr - ES1370_REG_CONTROL) << 3);
642 break;
643 case ES1370_REG_STATUS + 0:
644 case ES1370_REG_STATUS + 1:
645 case ES1370_REG_STATUS + 2:
646 case ES1370_REG_STATUS + 3:
647 val = s->status >> ((addr - ES1370_REG_STATUS) << 3);
648 break;
649 default:
650 val = ~0;
651 lwarn ("readb %#x -> %#x\n", addr, val);
652 break;
653 }
654 return val;
655 }
656
657 IO_READ_PROTO (es1370_readw)
658 {
659 ES1370State *s = opaque;
660 struct chan *d = &s->chan[0];
661 uint32_t val;
662
663 addr = es1370_fixup (s, addr);
664
665 switch (addr) {
666 case ES1370_REG_ADC_SCOUNT + 2:
667 d++;
668 case ES1370_REG_DAC2_SCOUNT + 2:
669 d++;
670 case ES1370_REG_DAC1_SCOUNT + 2:
671 val = d->scount >> 16;
672 break;
673
674 case ES1370_REG_ADC_FRAMECNT:
675 d++;
676 case ES1370_REG_DAC2_FRAMECNT:
677 d++;
678 case ES1370_REG_DAC1_FRAMECNT:
679 val = d->frame_cnt & 0xffff;
680 break;
681
682 case ES1370_REG_ADC_FRAMECNT + 2:
683 d++;
684 case ES1370_REG_DAC2_FRAMECNT + 2:
685 d++;
686 case ES1370_REG_DAC1_FRAMECNT + 2:
687 val = d->frame_cnt >> 16;
688 break;
689
690 default:
691 val = ~0;
692 lwarn ("readw %#x -> %#x\n", addr, val);
693 break;
694 }
695
696 return val;
697 }
698
699 IO_READ_PROTO (es1370_readl)
700 {
701 ES1370State *s = opaque;
702 uint32_t val;
703 struct chan *d = &s->chan[0];
704
705 addr = es1370_fixup (s, addr);
706
707 switch (addr) {
708 case ES1370_REG_CONTROL:
709 val = s->ctl;
710 break;
711 case ES1370_REG_STATUS:
712 val = s->status;
713 break;
714 case ES1370_REG_MEMPAGE:
715 val = s->mempage;
716 break;
717 case ES1370_REG_CODEC:
718 val = s->codec;
719 break;
720 case ES1370_REG_SERIAL_CONTROL:
721 val = s->sctl;
722 break;
723
724 case ES1370_REG_ADC_SCOUNT:
725 d++;
726 case ES1370_REG_DAC2_SCOUNT:
727 d++;
728 case ES1370_REG_DAC1_SCOUNT:
729 val = d->scount;
730 #ifdef DEBUG_ES1370
731 {
732 uint32_t curr_count = d->scount >> 16;
733 uint32_t count = d->scount & 0xffff;
734
735 curr_count <<= d->shift;
736 count <<= d->shift;
737 dolog ("read scount curr %d, total %d\n", curr_count, count);
738 }
739 #endif
740 break;
741
742 case ES1370_REG_ADC_FRAMECNT:
743 d++;
744 case ES1370_REG_DAC2_FRAMECNT:
745 d++;
746 case ES1370_REG_DAC1_FRAMECNT:
747 val = d->frame_cnt;
748 #ifdef DEBUG_ES1370
749 {
750 uint32_t size = ((d->frame_cnt & 0xffff) + 1) << 2;
751 uint32_t curr = ((d->frame_cnt >> 16) + 1) << 2;
752 if (curr > size)
753 dolog ("read framecnt curr %d, size %d %d\n", curr, size,
754 curr > size);
755 }
756 #endif
757 break;
758
759 case ES1370_REG_ADC_FRAMEADR:
760 d++;
761 case ES1370_REG_DAC2_FRAMEADR:
762 d++;
763 case ES1370_REG_DAC1_FRAMEADR:
764 val = d->frame_addr;
765 break;
766
767 case ES1370_REG_PHANTOM_FRAMECNT:
768 val = ~0U;
769 lwarn ("reading from phantom frame count\n");
770 break;
771 case ES1370_REG_PHANTOM_FRAMEADR:
772 val = ~0U;
773 lwarn ("reading from phantom frame address\n");
774 break;
775
776 default:
777 val = ~0U;
778 lwarn ("readl %#x -> %#x\n", addr, val);
779 break;
780 }
781 return val;
782 }
783
784
785 static void es1370_transfer_audio (ES1370State *s, struct chan *d, int loop_sel,
786 int max, int *irq)
787 {
788 uint8_t tmpbuf[4096];
789 uint32_t addr = d->frame_addr;
790 int sc = d->scount & 0xffff;
791 int csc = d->scount >> 16;
792 int csc_bytes = (csc + 1) << d->shift;
793 int cnt = d->frame_cnt >> 16;
794 int size = d->frame_cnt & 0xffff;
795 int left = ((size - cnt + 1) << 2) + d->leftover;
796 int transfered = 0;
797 int temp = audio_MIN (max, audio_MIN (left, csc_bytes));
798 int index = d - &s->chan[0];
799
800 addr += (cnt << 2) + d->leftover;
801
802 if (index == ADC_CHANNEL) {
803 while (temp) {
804 int acquired, to_copy;
805
806 to_copy = audio_MIN ((size_t) temp, sizeof (tmpbuf));
807 acquired = AUD_read (s->adc_voice, tmpbuf, to_copy);
808 if (!acquired)
809 break;
810
811 cpu_physical_memory_write (addr, tmpbuf, acquired);
812
813 temp -= acquired;
814 addr += acquired;
815 transfered += acquired;
816 }
817 }
818 else {
819 SWVoiceOut *voice = s->dac_voice[index];
820
821 while (temp) {
822 int copied, to_copy;
823
824 to_copy = audio_MIN ((size_t) temp, sizeof (tmpbuf));
825 cpu_physical_memory_read (addr, tmpbuf, to_copy);
826 copied = AUD_write (voice, tmpbuf, to_copy);
827 if (!copied)
828 break;
829 temp -= copied;
830 addr += copied;
831 transfered += copied;
832 }
833 }
834
835 if (csc_bytes == transfered) {
836 *irq = 1;
837 d->scount = sc | (sc << 16);
838 ldebug ("sc = %d, rate = %f\n",
839 (sc + 1) << d->shift,
840 (sc + 1) / (double) 44100);
841 }
842 else {
843 *irq = 0;
844 d->scount = sc | (((csc_bytes - transfered - 1) >> d->shift) << 16);
845 }
846
847 cnt += (transfered + d->leftover) >> 2;
848
849 if (s->sctl & loop_sel) {
850 /* Bah, how stupid is that having a 0 represent true value?
851 i just spent few hours on this shit */
852 AUD_log ("es1370: warning", "non looping mode\n");
853 }
854 else {
855 d->frame_cnt = size;
856
857 if ((uint32_t) cnt <= d->frame_cnt)
858 d->frame_cnt |= cnt << 16;
859 }
860
861 d->leftover = (transfered + d->leftover) & 3;
862 }
863
864 static void es1370_run_channel (ES1370State *s, size_t chan, int free_or_avail)
865 {
866 uint32_t new_status = s->status;
867 int max_bytes, irq;
868 struct chan *d = &s->chan[chan];
869 const struct chan_bits *b = &es1370_chan_bits[chan];
870
871 if (!(s->ctl & b->ctl_en) || (s->sctl & b->sctl_pause)) {
872 return;
873 }
874
875 max_bytes = free_or_avail;
876 max_bytes &= ~((1 << d->shift) - 1);
877 if (!max_bytes) {
878 return;
879 }
880
881 es1370_transfer_audio (s, d, b->sctl_loopsel, max_bytes, &irq);
882
883 if (irq) {
884 if (s->sctl & b->sctl_inten) {
885 new_status |= b->stat_int;
886 }
887 }
888
889 if (new_status != s->status) {
890 es1370_update_status (s, new_status);
891 }
892 }
893
894 static void es1370_dac1_callback (void *opaque, int free)
895 {
896 ES1370State *s = opaque;
897
898 es1370_run_channel (s, DAC1_CHANNEL, free);
899 }
900
901 static void es1370_dac2_callback (void *opaque, int free)
902 {
903 ES1370State *s = opaque;
904
905 es1370_run_channel (s, DAC2_CHANNEL, free);
906 }
907
908 static void es1370_adc_callback (void *opaque, int avail)
909 {
910 ES1370State *s = opaque;
911
912 es1370_run_channel (s, ADC_CHANNEL, avail);
913 }
914
915 static void es1370_map (PCIDevice *pci_dev, int region_num,
916 uint32_t addr, uint32_t size, int type)
917 {
918 PCIES1370State *d = (PCIES1370State *) pci_dev;
919 ES1370State *s = &d->es1370;
920
921 (void) region_num;
922 (void) size;
923 (void) type;
924
925 register_ioport_write (addr, 0x40 * 4, 1, es1370_writeb, s);
926 register_ioport_write (addr, 0x40 * 2, 2, es1370_writew, s);
927 register_ioport_write (addr, 0x40, 4, es1370_writel, s);
928
929 register_ioport_read (addr, 0x40 * 4, 1, es1370_readb, s);
930 register_ioport_read (addr, 0x40 * 2, 2, es1370_readw, s);
931 register_ioport_read (addr, 0x40, 4, es1370_readl, s);
932 }
933
934 static void es1370_save (QEMUFile *f, void *opaque)
935 {
936 ES1370State *s = opaque;
937 size_t i;
938
939 pci_device_save (s->pci_dev, f);
940 for (i = 0; i < NB_CHANNELS; ++i) {
941 struct chan *d = &s->chan[i];
942 qemu_put_be32s (f, &d->shift);
943 qemu_put_be32s (f, &d->leftover);
944 qemu_put_be32s (f, &d->scount);
945 qemu_put_be32s (f, &d->frame_addr);
946 qemu_put_be32s (f, &d->frame_cnt);
947 }
948 qemu_put_be32s (f, &s->ctl);
949 qemu_put_be32s (f, &s->status);
950 qemu_put_be32s (f, &s->mempage);
951 qemu_put_be32s (f, &s->codec);
952 qemu_put_be32s (f, &s->sctl);
953 }
954
955 static int es1370_load (QEMUFile *f, void *opaque, int version_id)
956 {
957 int ret;
958 uint32_t ctl, sctl;
959 ES1370State *s = opaque;
960 size_t i;
961
962 if (version_id != 2)
963 return -EINVAL;
964
965 ret = pci_device_load (s->pci_dev, f);
966 if (ret)
967 return ret;
968
969 for (i = 0; i < NB_CHANNELS; ++i) {
970 struct chan *d = &s->chan[i];
971 qemu_get_be32s (f, &d->shift);
972 qemu_get_be32s (f, &d->leftover);
973 qemu_get_be32s (f, &d->scount);
974 qemu_get_be32s (f, &d->frame_addr);
975 qemu_get_be32s (f, &d->frame_cnt);
976 if (i == ADC_CHANNEL) {
977 if (s->adc_voice) {
978 AUD_close_in (&s->card, s->adc_voice);
979 s->adc_voice = NULL;
980 }
981 }
982 else {
983 if (s->dac_voice[i]) {
984 AUD_close_out (&s->card, s->dac_voice[i]);
985 s->dac_voice[i] = NULL;
986 }
987 }
988 }
989
990 qemu_get_be32s (f, &ctl);
991 qemu_get_be32s (f, &s->status);
992 qemu_get_be32s (f, &s->mempage);
993 qemu_get_be32s (f, &s->codec);
994 qemu_get_be32s (f, &sctl);
995
996 s->ctl = 0;
997 s->sctl = 0;
998 es1370_update_voices (s, ctl, sctl);
999 return 0;
1000 }
1001
1002 static void es1370_on_reset (void *opaque)
1003 {
1004 ES1370State *s = opaque;
1005 es1370_reset (s);
1006 }
1007
1008 int es1370_init (PCIBus *bus)
1009 {
1010 PCIES1370State *d;
1011 ES1370State *s;
1012 uint8_t *c;
1013
1014 if (!bus) {
1015 dolog ("No PCI bus\n");
1016 return -1;
1017 }
1018
1019 d = (PCIES1370State *) pci_register_device (bus, "ES1370",
1020 sizeof (PCIES1370State),
1021 -1, NULL, NULL);
1022
1023 if (!d) {
1024 AUD_log (NULL, "Failed to register PCI device for ES1370\n");
1025 return -1;
1026 }
1027
1028 c = d->dev.config;
1029 pci_config_set_vendor_id(c, PCI_VENDOR_ID_ENSONIQ);
1030 pci_config_set_device_id(c, PCI_DEVICE_ID_ENSONIQ_ES1370);
1031 c[0x07] = 2 << 1;
1032 pci_config_set_class(c, PCI_CLASS_MULTIMEDIA_AUDIO);
1033
1034 #if 1
1035 c[0x2c] = 0x42;
1036 c[0x2d] = 0x49;
1037 c[0x2e] = 0x4c;
1038 c[0x2f] = 0x4c;
1039 #else
1040 c[0x2c] = 0x74;
1041 c[0x2d] = 0x12;
1042 c[0x2e] = 0x71;
1043 c[0x2f] = 0x13;
1044 c[0x34] = 0xdc;
1045 c[0x3c] = 10;
1046 c[0xdc] = 0x00;
1047 #endif
1048
1049 c[0x3d] = 1;
1050 c[0x3e] = 0x0c;
1051 c[0x3f] = 0x80;
1052
1053 s = &d->es1370;
1054 s->pci_dev = &d->dev;
1055
1056 pci_register_io_region (&d->dev, 0, 256, PCI_ADDRESS_SPACE_IO, es1370_map);
1057 register_savevm ("es1370", 0, 2, es1370_save, es1370_load, s);
1058 qemu_register_reset (es1370_on_reset, 0, s);
1059
1060 AUD_register_card ("es1370", &s->card);
1061 es1370_reset (s);
1062 return 0;
1063 }
HPPA (PA-RISC) target for QEMU