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hppa: specify target_phys_bits in configure script
[qemu/hppa.git] / hw / omap2.c
blob6fccca4a38f719d0b1f9ab1e5e7ba43793862f34
1 /*
2 * TI OMAP processors emulation.
3 *
4 * Copyright (C) 2007-2008 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21 #include "hw.h"
22 #include "arm-misc.h"
23 #include "omap.h"
24 #include "sysemu.h"
25 #include "qemu-timer.h"
26 #include "qemu-char.h"
27 #include "flash.h"
28 #include "soc_dma.h"
29 #include "audio/audio.h"
30
31 /* GP timers */
32 struct omap_gp_timer_s {
33 qemu_irq irq;
34 qemu_irq wkup;
35 qemu_irq in;
36 qemu_irq out;
37 omap_clk clk;
38 QEMUTimer *timer;
39 QEMUTimer *match;
40 struct omap_target_agent_s *ta;
41
42 int in_val;
43 int out_val;
44 int64_t time;
45 int64_t rate;
46 int64_t ticks_per_sec;
47
48 int16_t config;
49 int status;
50 int it_ena;
51 int wu_ena;
52 int enable;
53 int inout;
54 int capt2;
55 int pt;
56 enum {
57 gpt_trigger_none, gpt_trigger_overflow, gpt_trigger_both
58 } trigger;
59 enum {
60 gpt_capture_none, gpt_capture_rising,
61 gpt_capture_falling, gpt_capture_both
62 } capture;
63 int scpwm;
64 int ce;
65 int pre;
66 int ptv;
67 int ar;
68 int st;
69 int posted;
70 uint32_t val;
71 uint32_t load_val;
72 uint32_t capture_val[2];
73 uint32_t match_val;
74 int capt_num;
75
76 uint16_t writeh; /* LSB */
77 uint16_t readh; /* MSB */
78 };
79
80 #define GPT_TCAR_IT (1 << 2)
81 #define GPT_OVF_IT (1 << 1)
82 #define GPT_MAT_IT (1 << 0)
83
84 static inline void omap_gp_timer_intr(struct omap_gp_timer_s *timer, int it)
85 {
86 if (timer->it_ena & it) {
87 if (!timer->status)
88 qemu_irq_raise(timer->irq);
89
90 timer->status |= it;
91 /* Or are the status bits set even when masked?
92 * i.e. is masking applied before or after the status register? */
93 }
94
95 if (timer->wu_ena & it)
96 qemu_irq_pulse(timer->wkup);
97 }
98
99 static inline void omap_gp_timer_out(struct omap_gp_timer_s *timer, int level)
100 {
101 if (!timer->inout && timer->out_val != level) {
102 timer->out_val = level;
103 qemu_set_irq(timer->out, level);
104 }
105 }
106
107 static inline uint32_t omap_gp_timer_read(struct omap_gp_timer_s *timer)
108 {
109 uint64_t distance;
110
111 if (timer->st && timer->rate) {
112 distance = qemu_get_clock(vm_clock) - timer->time;
113 distance = muldiv64(distance, timer->rate, timer->ticks_per_sec);
114
115 if (distance >= 0xffffffff - timer->val)
116 return 0xffffffff;
117 else
118 return timer->val + distance;
119 } else
120 return timer->val;
121 }
122
123 static inline void omap_gp_timer_sync(struct omap_gp_timer_s *timer)
124 {
125 if (timer->st) {
126 timer->val = omap_gp_timer_read(timer);
127 timer->time = qemu_get_clock(vm_clock);
128 }
129 }
130
131 static inline void omap_gp_timer_update(struct omap_gp_timer_s *timer)
132 {
133 int64_t expires, matches;
134
135 if (timer->st && timer->rate) {
136 expires = muldiv64(0x100000000ll - timer->val,
137 timer->ticks_per_sec, timer->rate);
138 qemu_mod_timer(timer->timer, timer->time + expires);
139
140 if (timer->ce && timer->match_val >= timer->val) {
141 matches = muldiv64(timer->match_val - timer->val,
142 timer->ticks_per_sec, timer->rate);
143 qemu_mod_timer(timer->match, timer->time + matches);
144 } else
145 qemu_del_timer(timer->match);
146 } else {
147 qemu_del_timer(timer->timer);
148 qemu_del_timer(timer->match);
149 omap_gp_timer_out(timer, timer->scpwm);
150 }
151 }
152
153 static inline void omap_gp_timer_trigger(struct omap_gp_timer_s *timer)
154 {
155 if (timer->pt)
156 /* TODO in overflow-and-match mode if the first event to
157 * occur is the match, don't toggle. */
158 omap_gp_timer_out(timer, !timer->out_val);
159 else
160 /* TODO inverted pulse on timer->out_val == 1? */
161 qemu_irq_pulse(timer->out);
162 }
163
164 static void omap_gp_timer_tick(void *opaque)
165 {
166 struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
167
168 if (!timer->ar) {
169 timer->st = 0;
170 timer->val = 0;
171 } else {
172 timer->val = timer->load_val;
173 timer->time = qemu_get_clock(vm_clock);
174 }
175
176 if (timer->trigger == gpt_trigger_overflow ||
177 timer->trigger == gpt_trigger_both)
178 omap_gp_timer_trigger(timer);
179
180 omap_gp_timer_intr(timer, GPT_OVF_IT);
181 omap_gp_timer_update(timer);
182 }
183
184 static void omap_gp_timer_match(void *opaque)
185 {
186 struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
187
188 if (timer->trigger == gpt_trigger_both)
189 omap_gp_timer_trigger(timer);
190
191 omap_gp_timer_intr(timer, GPT_MAT_IT);
192 }
193
194 static void omap_gp_timer_input(void *opaque, int line, int on)
195 {
196 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
197 int trigger;
198
199 switch (s->capture) {
200 default:
201 case gpt_capture_none:
202 trigger = 0;
203 break;
204 case gpt_capture_rising:
205 trigger = !s->in_val && on;
206 break;
207 case gpt_capture_falling:
208 trigger = s->in_val && !on;
209 break;
210 case gpt_capture_both:
211 trigger = (s->in_val == !on);
212 break;
213 }
214 s->in_val = on;
215
216 if (s->inout && trigger && s->capt_num < 2) {
217 s->capture_val[s->capt_num] = omap_gp_timer_read(s);
218
219 if (s->capt2 == s->capt_num ++)
220 omap_gp_timer_intr(s, GPT_TCAR_IT);
221 }
222 }
223
224 static void omap_gp_timer_clk_update(void *opaque, int line, int on)
225 {
226 struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
227
228 omap_gp_timer_sync(timer);
229 timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
230 omap_gp_timer_update(timer);
231 }
232
233 static void omap_gp_timer_clk_setup(struct omap_gp_timer_s *timer)
234 {
235 omap_clk_adduser(timer->clk,
236 qemu_allocate_irqs(omap_gp_timer_clk_update, timer, 1)[0]);
237 timer->rate = omap_clk_getrate(timer->clk);
238 }
239
240 static void omap_gp_timer_reset(struct omap_gp_timer_s *s)
241 {
242 s->config = 0x000;
243 s->status = 0;
244 s->it_ena = 0;
245 s->wu_ena = 0;
246 s->inout = 0;
247 s->capt2 = 0;
248 s->capt_num = 0;
249 s->pt = 0;
250 s->trigger = gpt_trigger_none;
251 s->capture = gpt_capture_none;
252 s->scpwm = 0;
253 s->ce = 0;
254 s->pre = 0;
255 s->ptv = 0;
256 s->ar = 0;
257 s->st = 0;
258 s->posted = 1;
259 s->val = 0x00000000;
260 s->load_val = 0x00000000;
261 s->capture_val[0] = 0x00000000;
262 s->capture_val[1] = 0x00000000;
263 s->match_val = 0x00000000;
264 omap_gp_timer_update(s);
265 }
266
267 static uint32_t omap_gp_timer_readw(void *opaque, target_phys_addr_t addr)
268 {
269 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
270
271 switch (addr) {
272 case 0x00: /* TIDR */
273 return 0x21;
274
275 case 0x10: /* TIOCP_CFG */
276 return s->config;
277
278 case 0x14: /* TISTAT */
279 /* ??? When's this bit reset? */
280 return 1; /* RESETDONE */
281
282 case 0x18: /* TISR */
283 return s->status;
284
285 case 0x1c: /* TIER */
286 return s->it_ena;
287
288 case 0x20: /* TWER */
289 return s->wu_ena;
290
291 case 0x24: /* TCLR */
292 return (s->inout << 14) |
293 (s->capt2 << 13) |
294 (s->pt << 12) |
295 (s->trigger << 10) |
296 (s->capture << 8) |
297 (s->scpwm << 7) |
298 (s->ce << 6) |
299 (s->pre << 5) |
300 (s->ptv << 2) |
301 (s->ar << 1) |
302 (s->st << 0);
303
304 case 0x28: /* TCRR */
305 return omap_gp_timer_read(s);
306
307 case 0x2c: /* TLDR */
308 return s->load_val;
309
310 case 0x30: /* TTGR */
311 return 0xffffffff;
312
313 case 0x34: /* TWPS */
314 return 0x00000000; /* No posted writes pending. */
315
316 case 0x38: /* TMAR */
317 return s->match_val;
318
319 case 0x3c: /* TCAR1 */
320 return s->capture_val[0];
321
322 case 0x40: /* TSICR */
323 return s->posted << 2;
324
325 case 0x44: /* TCAR2 */
326 return s->capture_val[1];
327 }
328
329 OMAP_BAD_REG(addr);
330 return 0;
331 }
332
333 static uint32_t omap_gp_timer_readh(void *opaque, target_phys_addr_t addr)
334 {
335 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
336 uint32_t ret;
337
338 if (addr & 2)
339 return s->readh;
340 else {
341 ret = omap_gp_timer_readw(opaque, addr);
342 s->readh = ret >> 16;
343 return ret & 0xffff;
344 }
345 }
346
347 static CPUReadMemoryFunc *omap_gp_timer_readfn[] = {
348 omap_badwidth_read32,
349 omap_gp_timer_readh,
350 omap_gp_timer_readw,
351 };
352
353 static void omap_gp_timer_write(void *opaque, target_phys_addr_t addr,
354 uint32_t value)
355 {
356 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
357
358 switch (addr) {
359 case 0x00: /* TIDR */
360 case 0x14: /* TISTAT */
361 case 0x34: /* TWPS */
362 case 0x3c: /* TCAR1 */
363 case 0x44: /* TCAR2 */
364 OMAP_RO_REG(addr);
365 break;
366
367 case 0x10: /* TIOCP_CFG */
368 s->config = value & 0x33d;
369 if (((value >> 3) & 3) == 3) /* IDLEMODE */
370 fprintf(stderr, "%s: illegal IDLEMODE value in TIOCP_CFG\n",
371 __FUNCTION__);
372 if (value & 2) /* SOFTRESET */
373 omap_gp_timer_reset(s);
374 break;
375
376 case 0x18: /* TISR */
377 if (value & GPT_TCAR_IT)
378 s->capt_num = 0;
379 if (s->status && !(s->status &= ~value))
380 qemu_irq_lower(s->irq);
381 break;
382
383 case 0x1c: /* TIER */
384 s->it_ena = value & 7;
385 break;
386
387 case 0x20: /* TWER */
388 s->wu_ena = value & 7;
389 break;
390
391 case 0x24: /* TCLR */
392 omap_gp_timer_sync(s);
393 s->inout = (value >> 14) & 1;
394 s->capt2 = (value >> 13) & 1;
395 s->pt = (value >> 12) & 1;
396 s->trigger = (value >> 10) & 3;
397 if (s->capture == gpt_capture_none &&
398 ((value >> 8) & 3) != gpt_capture_none)
399 s->capt_num = 0;
400 s->capture = (value >> 8) & 3;
401 s->scpwm = (value >> 7) & 1;
402 s->ce = (value >> 6) & 1;
403 s->pre = (value >> 5) & 1;
404 s->ptv = (value >> 2) & 7;
405 s->ar = (value >> 1) & 1;
406 s->st = (value >> 0) & 1;
407 if (s->inout && s->trigger != gpt_trigger_none)
408 fprintf(stderr, "%s: GP timer pin must be an output "
409 "for this trigger mode\n", __FUNCTION__);
410 if (!s->inout && s->capture != gpt_capture_none)
411 fprintf(stderr, "%s: GP timer pin must be an input "
412 "for this capture mode\n", __FUNCTION__);
413 if (s->trigger == gpt_trigger_none)
414 omap_gp_timer_out(s, s->scpwm);
415 /* TODO: make sure this doesn't overflow 32-bits */
416 s->ticks_per_sec = ticks_per_sec << (s->pre ? s->ptv + 1 : 0);
417 omap_gp_timer_update(s);
418 break;
419
420 case 0x28: /* TCRR */
421 s->time = qemu_get_clock(vm_clock);
422 s->val = value;
423 omap_gp_timer_update(s);
424 break;
425
426 case 0x2c: /* TLDR */
427 s->load_val = value;
428 break;
429
430 case 0x30: /* TTGR */
431 s->time = qemu_get_clock(vm_clock);
432 s->val = s->load_val;
433 omap_gp_timer_update(s);
434 break;
435
436 case 0x38: /* TMAR */
437 omap_gp_timer_sync(s);
438 s->match_val = value;
439 omap_gp_timer_update(s);
440 break;
441
442 case 0x40: /* TSICR */
443 s->posted = (value >> 2) & 1;
444 if (value & 2) /* How much exactly are we supposed to reset? */
445 omap_gp_timer_reset(s);
446 break;
447
448 default:
449 OMAP_BAD_REG(addr);
450 }
451 }
452
453 static void omap_gp_timer_writeh(void *opaque, target_phys_addr_t addr,
454 uint32_t value)
455 {
456 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
457
458 if (addr & 2)
459 return omap_gp_timer_write(opaque, addr, (value << 16) | s->writeh);
460 else
461 s->writeh = (uint16_t) value;
462 }
463
464 static CPUWriteMemoryFunc *omap_gp_timer_writefn[] = {
465 omap_badwidth_write32,
466 omap_gp_timer_writeh,
467 omap_gp_timer_write,
468 };
469
470 struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
471 qemu_irq irq, omap_clk fclk, omap_clk iclk)
472 {
473 int iomemtype;
474 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *)
475 qemu_mallocz(sizeof(struct omap_gp_timer_s));
476
477 s->ta = ta;
478 s->irq = irq;
479 s->clk = fclk;
480 s->timer = qemu_new_timer(vm_clock, omap_gp_timer_tick, s);
481 s->match = qemu_new_timer(vm_clock, omap_gp_timer_match, s);
482 s->in = qemu_allocate_irqs(omap_gp_timer_input, s, 1)[0];
483 omap_gp_timer_reset(s);
484 omap_gp_timer_clk_setup(s);
485
486 iomemtype = l4_register_io_memory(0, omap_gp_timer_readfn,
487 omap_gp_timer_writefn, s);
488 omap_l4_attach(ta, 0, iomemtype);
489
490 return s;
491 }
492
493 /* 32-kHz Sync Timer of the OMAP2 */
494 static uint32_t omap_synctimer_read(struct omap_synctimer_s *s) {
495 return muldiv64(qemu_get_clock(vm_clock), 0x8000, ticks_per_sec);
496 }
497
498 static void omap_synctimer_reset(struct omap_synctimer_s *s)
499 {
500 s->val = omap_synctimer_read(s);
501 }
502
503 static uint32_t omap_synctimer_readw(void *opaque, target_phys_addr_t addr)
504 {
505 struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
506
507 switch (addr) {
508 case 0x00: /* 32KSYNCNT_REV */
509 return 0x21;
510
511 case 0x10: /* CR */
512 return omap_synctimer_read(s) - s->val;
513 }
514
515 OMAP_BAD_REG(addr);
516 return 0;
517 }
518
519 static uint32_t omap_synctimer_readh(void *opaque, target_phys_addr_t addr)
520 {
521 struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
522 uint32_t ret;
523
524 if (addr & 2)
525 return s->readh;
526 else {
527 ret = omap_synctimer_readw(opaque, addr);
528 s->readh = ret >> 16;
529 return ret & 0xffff;
530 }
531 }
532
533 static CPUReadMemoryFunc *omap_synctimer_readfn[] = {
534 omap_badwidth_read32,
535 omap_synctimer_readh,
536 omap_synctimer_readw,
537 };
538
539 static void omap_synctimer_write(void *opaque, target_phys_addr_t addr,
540 uint32_t value)
541 {
542 OMAP_BAD_REG(addr);
543 }
544
545 static CPUWriteMemoryFunc *omap_synctimer_writefn[] = {
546 omap_badwidth_write32,
547 omap_synctimer_write,
548 omap_synctimer_write,
549 };
550
551 void omap_synctimer_init(struct omap_target_agent_s *ta,
552 struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk)
553 {
554 struct omap_synctimer_s *s = &mpu->synctimer;
555
556 omap_synctimer_reset(s);
557 omap_l4_attach(ta, 0, l4_register_io_memory(0,
558 omap_synctimer_readfn, omap_synctimer_writefn, s));
559 }
560
561 /* General-Purpose Interface of OMAP2 */
562 struct omap2_gpio_s {
563 qemu_irq irq[2];
564 qemu_irq wkup;
565 qemu_irq *in;
566 qemu_irq handler[32];
567
568 uint8_t config[2];
569 uint32_t inputs;
570 uint32_t outputs;
571 uint32_t dir;
572 uint32_t level[2];
573 uint32_t edge[2];
574 uint32_t mask[2];
575 uint32_t wumask;
576 uint32_t ints[2];
577 uint32_t debounce;
578 uint8_t delay;
579 };
580
581 static inline void omap_gpio_module_int_update(struct omap2_gpio_s *s,
582 int line)
583 {
584 qemu_set_irq(s->irq[line], s->ints[line] & s->mask[line]);
585 }
586
587 static void omap_gpio_module_wake(struct omap2_gpio_s *s, int line)
588 {
589 if (!(s->config[0] & (1 << 2))) /* ENAWAKEUP */
590 return;
591 if (!(s->config[0] & (3 << 3))) /* Force Idle */
592 return;
593 if (!(s->wumask & (1 << line)))
594 return;
595
596 qemu_irq_raise(s->wkup);
597 }
598
599 static inline void omap_gpio_module_out_update(struct omap2_gpio_s *s,
600 uint32_t diff)
601 {
602 int ln;
603
604 s->outputs ^= diff;
605 diff &= ~s->dir;
606 while ((ln = ffs(diff))) {
607 ln --;
608 qemu_set_irq(s->handler[ln], (s->outputs >> ln) & 1);
609 diff &= ~(1 << ln);
610 }
611 }
612
613 static void omap_gpio_module_level_update(struct omap2_gpio_s *s, int line)
614 {
615 s->ints[line] |= s->dir &
616 ((s->inputs & s->level[1]) | (~s->inputs & s->level[0]));
617 omap_gpio_module_int_update(s, line);
618 }
619
620 static inline void omap_gpio_module_int(struct omap2_gpio_s *s, int line)
621 {
622 s->ints[0] |= 1 << line;
623 omap_gpio_module_int_update(s, 0);
624 s->ints[1] |= 1 << line;
625 omap_gpio_module_int_update(s, 1);
626 omap_gpio_module_wake(s, line);
627 }
628
629 static void omap_gpio_module_set(void *opaque, int line, int level)
630 {
631 struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
632
633 if (level) {
634 if (s->dir & (1 << line) & ((~s->inputs & s->edge[0]) | s->level[1]))
635 omap_gpio_module_int(s, line);
636 s->inputs |= 1 << line;
637 } else {
638 if (s->dir & (1 << line) & ((s->inputs & s->edge[1]) | s->level[0]))
639 omap_gpio_module_int(s, line);
640 s->inputs &= ~(1 << line);
641 }
642 }
643
644 static void omap_gpio_module_reset(struct omap2_gpio_s *s)
645 {
646 s->config[0] = 0;
647 s->config[1] = 2;
648 s->ints[0] = 0;
649 s->ints[1] = 0;
650 s->mask[0] = 0;
651 s->mask[1] = 0;
652 s->wumask = 0;
653 s->dir = ~0;
654 s->level[0] = 0;
655 s->level[1] = 0;
656 s->edge[0] = 0;
657 s->edge[1] = 0;
658 s->debounce = 0;
659 s->delay = 0;
660 }
661
662 static uint32_t omap_gpio_module_read(void *opaque, target_phys_addr_t addr)
663 {
664 struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
665
666 switch (addr) {
667 case 0x00: /* GPIO_REVISION */
668 return 0x18;
669
670 case 0x10: /* GPIO_SYSCONFIG */
671 return s->config[0];
672
673 case 0x14: /* GPIO_SYSSTATUS */
674 return 0x01;
675
676 case 0x18: /* GPIO_IRQSTATUS1 */
677 return s->ints[0];
678
679 case 0x1c: /* GPIO_IRQENABLE1 */
680 case 0x60: /* GPIO_CLEARIRQENABLE1 */
681 case 0x64: /* GPIO_SETIRQENABLE1 */
682 return s->mask[0];
683
684 case 0x20: /* GPIO_WAKEUPENABLE */
685 case 0x80: /* GPIO_CLEARWKUENA */
686 case 0x84: /* GPIO_SETWKUENA */
687 return s->wumask;
688
689 case 0x28: /* GPIO_IRQSTATUS2 */
690 return s->ints[1];
691
692 case 0x2c: /* GPIO_IRQENABLE2 */
693 case 0x70: /* GPIO_CLEARIRQENABLE2 */
694 case 0x74: /* GPIO_SETIREQNEABLE2 */
695 return s->mask[1];
696
697 case 0x30: /* GPIO_CTRL */
698 return s->config[1];
699
700 case 0x34: /* GPIO_OE */
701 return s->dir;
702
703 case 0x38: /* GPIO_DATAIN */
704 return s->inputs;
705
706 case 0x3c: /* GPIO_DATAOUT */
707 case 0x90: /* GPIO_CLEARDATAOUT */
708 case 0x94: /* GPIO_SETDATAOUT */
709 return s->outputs;
710
711 case 0x40: /* GPIO_LEVELDETECT0 */
712 return s->level[0];
713
714 case 0x44: /* GPIO_LEVELDETECT1 */
715 return s->level[1];
716
717 case 0x48: /* GPIO_RISINGDETECT */
718 return s->edge[0];
719
720 case 0x4c: /* GPIO_FALLINGDETECT */
721 return s->edge[1];
722
723 case 0x50: /* GPIO_DEBOUNCENABLE */
724 return s->debounce;
725
726 case 0x54: /* GPIO_DEBOUNCINGTIME */
727 return s->delay;
728 }
729
730 OMAP_BAD_REG(addr);
731 return 0;
732 }
733
734 static void omap_gpio_module_write(void *opaque, target_phys_addr_t addr,
735 uint32_t value)
736 {
737 struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
738 uint32_t diff;
739 int ln;
740
741 switch (addr) {
742 case 0x00: /* GPIO_REVISION */
743 case 0x14: /* GPIO_SYSSTATUS */
744 case 0x38: /* GPIO_DATAIN */
745 OMAP_RO_REG(addr);
746 break;
747
748 case 0x10: /* GPIO_SYSCONFIG */
749 if (((value >> 3) & 3) == 3)
750 fprintf(stderr, "%s: bad IDLEMODE value\n", __FUNCTION__);
751 if (value & 2)
752 omap_gpio_module_reset(s);
753 s->config[0] = value & 0x1d;
754 break;
755
756 case 0x18: /* GPIO_IRQSTATUS1 */
757 if (s->ints[0] & value) {
758 s->ints[0] &= ~value;
759 omap_gpio_module_level_update(s, 0);
760 }
761 break;
762
763 case 0x1c: /* GPIO_IRQENABLE1 */
764 s->mask[0] = value;
765 omap_gpio_module_int_update(s, 0);
766 break;
767
768 case 0x20: /* GPIO_WAKEUPENABLE */
769 s->wumask = value;
770 break;
771
772 case 0x28: /* GPIO_IRQSTATUS2 */
773 if (s->ints[1] & value) {
774 s->ints[1] &= ~value;
775 omap_gpio_module_level_update(s, 1);
776 }
777 break;
778
779 case 0x2c: /* GPIO_IRQENABLE2 */
780 s->mask[1] = value;
781 omap_gpio_module_int_update(s, 1);
782 break;
783
784 case 0x30: /* GPIO_CTRL */
785 s->config[1] = value & 7;
786 break;
787
788 case 0x34: /* GPIO_OE */
789 diff = s->outputs & (s->dir ^ value);
790 s->dir = value;
791
792 value = s->outputs & ~s->dir;
793 while ((ln = ffs(diff))) {
794 diff &= ~(1 <<-- ln);
795 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
796 }
797
798 omap_gpio_module_level_update(s, 0);
799 omap_gpio_module_level_update(s, 1);
800 break;
801
802 case 0x3c: /* GPIO_DATAOUT */
803 omap_gpio_module_out_update(s, s->outputs ^ value);
804 break;
805
806 case 0x40: /* GPIO_LEVELDETECT0 */
807 s->level[0] = value;
808 omap_gpio_module_level_update(s, 0);
809 omap_gpio_module_level_update(s, 1);
810 break;
811
812 case 0x44: /* GPIO_LEVELDETECT1 */
813 s->level[1] = value;
814 omap_gpio_module_level_update(s, 0);
815 omap_gpio_module_level_update(s, 1);
816 break;
817
818 case 0x48: /* GPIO_RISINGDETECT */
819 s->edge[0] = value;
820 break;
821
822 case 0x4c: /* GPIO_FALLINGDETECT */
823 s->edge[1] = value;
824 break;
825
826 case 0x50: /* GPIO_DEBOUNCENABLE */
827 s->debounce = value;
828 break;
829
830 case 0x54: /* GPIO_DEBOUNCINGTIME */
831 s->delay = value;
832 break;
833
834 case 0x60: /* GPIO_CLEARIRQENABLE1 */
835 s->mask[0] &= ~value;
836 omap_gpio_module_int_update(s, 0);
837 break;
838
839 case 0x64: /* GPIO_SETIRQENABLE1 */
840 s->mask[0] |= value;
841 omap_gpio_module_int_update(s, 0);
842 break;
843
844 case 0x70: /* GPIO_CLEARIRQENABLE2 */
845 s->mask[1] &= ~value;
846 omap_gpio_module_int_update(s, 1);
847 break;
848
849 case 0x74: /* GPIO_SETIREQNEABLE2 */
850 s->mask[1] |= value;
851 omap_gpio_module_int_update(s, 1);
852 break;
853
854 case 0x80: /* GPIO_CLEARWKUENA */
855 s->wumask &= ~value;
856 break;
857
858 case 0x84: /* GPIO_SETWKUENA */
859 s->wumask |= value;
860 break;
861
862 case 0x90: /* GPIO_CLEARDATAOUT */
863 omap_gpio_module_out_update(s, s->outputs & value);
864 break;
865
866 case 0x94: /* GPIO_SETDATAOUT */
867 omap_gpio_module_out_update(s, ~s->outputs & value);
868 break;
869
870 default:
871 OMAP_BAD_REG(addr);
872 return;
873 }
874 }
875
876 static uint32_t omap_gpio_module_readp(void *opaque, target_phys_addr_t addr)
877 {
878 return omap_gpio_module_readp(opaque, addr) >> ((addr & 3) << 3);
879 }
880
881 static void omap_gpio_module_writep(void *opaque, target_phys_addr_t addr,
882 uint32_t value)
883 {
884 uint32_t cur = 0;
885 uint32_t mask = 0xffff;
886
887 switch (addr & ~3) {
888 case 0x00: /* GPIO_REVISION */
889 case 0x14: /* GPIO_SYSSTATUS */
890 case 0x38: /* GPIO_DATAIN */
891 OMAP_RO_REG(addr);
892 break;
893
894 case 0x10: /* GPIO_SYSCONFIG */
895 case 0x1c: /* GPIO_IRQENABLE1 */
896 case 0x20: /* GPIO_WAKEUPENABLE */
897 case 0x2c: /* GPIO_IRQENABLE2 */
898 case 0x30: /* GPIO_CTRL */
899 case 0x34: /* GPIO_OE */
900 case 0x3c: /* GPIO_DATAOUT */
901 case 0x40: /* GPIO_LEVELDETECT0 */
902 case 0x44: /* GPIO_LEVELDETECT1 */
903 case 0x48: /* GPIO_RISINGDETECT */
904 case 0x4c: /* GPIO_FALLINGDETECT */
905 case 0x50: /* GPIO_DEBOUNCENABLE */
906 case 0x54: /* GPIO_DEBOUNCINGTIME */
907 cur = omap_gpio_module_read(opaque, addr & ~3) &
908 ~(mask << ((addr & 3) << 3));
909
910 /* Fall through. */
911 case 0x18: /* GPIO_IRQSTATUS1 */
912 case 0x28: /* GPIO_IRQSTATUS2 */
913 case 0x60: /* GPIO_CLEARIRQENABLE1 */
914 case 0x64: /* GPIO_SETIRQENABLE1 */
915 case 0x70: /* GPIO_CLEARIRQENABLE2 */
916 case 0x74: /* GPIO_SETIREQNEABLE2 */
917 case 0x80: /* GPIO_CLEARWKUENA */
918 case 0x84: /* GPIO_SETWKUENA */
919 case 0x90: /* GPIO_CLEARDATAOUT */
920 case 0x94: /* GPIO_SETDATAOUT */
921 value <<= (addr & 3) << 3;
922 omap_gpio_module_write(opaque, addr, cur | value);
923 break;
924
925 default:
926 OMAP_BAD_REG(addr);
927 return;
928 }
929 }
930
931 static CPUReadMemoryFunc *omap_gpio_module_readfn[] = {
932 omap_gpio_module_readp,
933 omap_gpio_module_readp,
934 omap_gpio_module_read,
935 };
936
937 static CPUWriteMemoryFunc *omap_gpio_module_writefn[] = {
938 omap_gpio_module_writep,
939 omap_gpio_module_writep,
940 omap_gpio_module_write,
941 };
942
943 static void omap_gpio_module_init(struct omap2_gpio_s *s,
944 struct omap_target_agent_s *ta, int region,
945 qemu_irq mpu, qemu_irq dsp, qemu_irq wkup,
946 omap_clk fclk, omap_clk iclk)
947 {
948 int iomemtype;
949
950 s->irq[0] = mpu;
951 s->irq[1] = dsp;
952 s->wkup = wkup;
953 s->in = qemu_allocate_irqs(omap_gpio_module_set, s, 32);
954
955 iomemtype = l4_register_io_memory(0, omap_gpio_module_readfn,
956 omap_gpio_module_writefn, s);
957 omap_l4_attach(ta, region, iomemtype);
958 }
959
960 struct omap_gpif_s {
961 struct omap2_gpio_s module[5];
962 int modules;
963
964 int autoidle;
965 int gpo;
966 };
967
968 static void omap_gpif_reset(struct omap_gpif_s *s)
969 {
970 int i;
971
972 for (i = 0; i < s->modules; i ++)
973 omap_gpio_module_reset(s->module + i);
974
975 s->autoidle = 0;
976 s->gpo = 0;
977 }
978
979 static uint32_t omap_gpif_top_read(void *opaque, target_phys_addr_t addr)
980 {
981 struct omap_gpif_s *s = (struct omap_gpif_s *) opaque;
982
983 switch (addr) {
984 case 0x00: /* IPGENERICOCPSPL_REVISION */
985 return 0x18;
986
987 case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */
988 return s->autoidle;
989
990 case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */
991 return 0x01;
992
993 case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */
994 return 0x00;
995
996 case 0x40: /* IPGENERICOCPSPL_GPO */
997 return s->gpo;
998
999 case 0x50: /* IPGENERICOCPSPL_GPI */
1000 return 0x00;
1001 }
1002
1003 OMAP_BAD_REG(addr);
1004 return 0;
1005 }
1006
1007 static void omap_gpif_top_write(void *opaque, target_phys_addr_t addr,
1008 uint32_t value)
1009 {
1010 struct omap_gpif_s *s = (struct omap_gpif_s *) opaque;
1011
1012 switch (addr) {
1013 case 0x00: /* IPGENERICOCPSPL_REVISION */
1014 case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */
1015 case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */
1016 case 0x50: /* IPGENERICOCPSPL_GPI */
1017 OMAP_RO_REG(addr);
1018 break;
1019
1020 case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */
1021 if (value & (1 << 1)) /* SOFTRESET */
1022 omap_gpif_reset(s);
1023 s->autoidle = value & 1;
1024 break;
1025
1026 case 0x40: /* IPGENERICOCPSPL_GPO */
1027 s->gpo = value & 1;
1028 break;
1029
1030 default:
1031 OMAP_BAD_REG(addr);
1032 return;
1033 }
1034 }
1035
1036 static CPUReadMemoryFunc *omap_gpif_top_readfn[] = {
1037 omap_gpif_top_read,
1038 omap_gpif_top_read,
1039 omap_gpif_top_read,
1040 };
1041
1042 static CPUWriteMemoryFunc *omap_gpif_top_writefn[] = {
1043 omap_gpif_top_write,
1044 omap_gpif_top_write,
1045 omap_gpif_top_write,
1046 };
1047
1048 struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta,
1049 qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int modules)
1050 {
1051 int iomemtype, i;
1052 struct omap_gpif_s *s = (struct omap_gpif_s *)
1053 qemu_mallocz(sizeof(struct omap_gpif_s));
1054 int region[4] = { 0, 2, 4, 5 };
1055
1056 s->modules = modules;
1057 for (i = 0; i < modules; i ++)
1058 omap_gpio_module_init(s->module + i, ta, region[i],
1059 irq[i], 0, 0, fclk[i], iclk);
1060
1061 omap_gpif_reset(s);
1062
1063 iomemtype = l4_register_io_memory(0, omap_gpif_top_readfn,
1064 omap_gpif_top_writefn, s);
1065 omap_l4_attach(ta, 1, iomemtype);
1066
1067 return s;
1068 }
1069
1070 qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start)
1071 {
1072 if (start >= s->modules * 32 || start < 0)
1073 hw_error("%s: No GPIO line %i\n", __FUNCTION__, start);
1074 return s->module[start >> 5].in + (start & 31);
1075 }
1076
1077 void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler)
1078 {
1079 if (line >= s->modules * 32 || line < 0)
1080 hw_error("%s: No GPIO line %i\n", __FUNCTION__, line);
1081 s->module[line >> 5].handler[line & 31] = handler;
1082 }
1083
1084 /* Multichannel SPI */
1085 struct omap_mcspi_s {
1086 qemu_irq irq;
1087 int chnum;
1088
1089 uint32_t sysconfig;
1090 uint32_t systest;
1091 uint32_t irqst;
1092 uint32_t irqen;
1093 uint32_t wken;
1094 uint32_t control;
1095
1096 struct omap_mcspi_ch_s {
1097 qemu_irq txdrq;
1098 qemu_irq rxdrq;
1099 uint32_t (*txrx)(void *opaque, uint32_t, int);
1100 void *opaque;
1101
1102 uint32_t tx;
1103 uint32_t rx;
1104
1105 uint32_t config;
1106 uint32_t status;
1107 uint32_t control;
1108 } ch[4];
1109 };
1110
1111 static inline void omap_mcspi_interrupt_update(struct omap_mcspi_s *s)
1112 {
1113 qemu_set_irq(s->irq, s->irqst & s->irqen);
1114 }
1115
1116 static inline void omap_mcspi_dmarequest_update(struct omap_mcspi_ch_s *ch)
1117 {
1118 qemu_set_irq(ch->txdrq,
1119 (ch->control & 1) && /* EN */
1120 (ch->config & (1 << 14)) && /* DMAW */
1121 (ch->status & (1 << 1)) && /* TXS */
1122 ((ch->config >> 12) & 3) != 1); /* TRM */
1123 qemu_set_irq(ch->rxdrq,
1124 (ch->control & 1) && /* EN */
1125 (ch->config & (1 << 15)) && /* DMAW */
1126 (ch->status & (1 << 0)) && /* RXS */
1127 ((ch->config >> 12) & 3) != 2); /* TRM */
1128 }
1129
1130 static void omap_mcspi_transfer_run(struct omap_mcspi_s *s, int chnum)
1131 {
1132 struct omap_mcspi_ch_s *ch = s->ch + chnum;
1133
1134 if (!(ch->control & 1)) /* EN */
1135 return;
1136 if ((ch->status & (1 << 0)) && /* RXS */
1137 ((ch->config >> 12) & 3) != 2 && /* TRM */
1138 !(ch->config & (1 << 19))) /* TURBO */
1139 goto intr_update;
1140 if ((ch->status & (1 << 1)) && /* TXS */
1141 ((ch->config >> 12) & 3) != 1) /* TRM */
1142 goto intr_update;
1143
1144 if (!(s->control & 1) || /* SINGLE */
1145 (ch->config & (1 << 20))) { /* FORCE */
1146 if (ch->txrx)
1147 ch->rx = ch->txrx(ch->opaque, ch->tx, /* WL */
1148 1 + (0x1f & (ch->config >> 7)));
1149 }
1150
1151 ch->tx = 0;
1152 ch->status |= 1 << 2; /* EOT */
1153 ch->status |= 1 << 1; /* TXS */
1154 if (((ch->config >> 12) & 3) != 2) /* TRM */
1155 ch->status |= 1 << 0; /* RXS */
1156
1157 intr_update:
1158 if ((ch->status & (1 << 0)) && /* RXS */
1159 ((ch->config >> 12) & 3) != 2 && /* TRM */
1160 !(ch->config & (1 << 19))) /* TURBO */
1161 s->irqst |= 1 << (2 + 4 * chnum); /* RX_FULL */
1162 if ((ch->status & (1 << 1)) && /* TXS */
1163 ((ch->config >> 12) & 3) != 1) /* TRM */
1164 s->irqst |= 1 << (0 + 4 * chnum); /* TX_EMPTY */
1165 omap_mcspi_interrupt_update(s);
1166 omap_mcspi_dmarequest_update(ch);
1167 }
1168
1169 static void omap_mcspi_reset(struct omap_mcspi_s *s)
1170 {
1171 int ch;
1172
1173 s->sysconfig = 0;
1174 s->systest = 0;
1175 s->irqst = 0;
1176 s->irqen = 0;
1177 s->wken = 0;
1178 s->control = 4;
1179
1180 for (ch = 0; ch < 4; ch ++) {
1181 s->ch[ch].config = 0x060000;
1182 s->ch[ch].status = 2; /* TXS */
1183 s->ch[ch].control = 0;
1184
1185 omap_mcspi_dmarequest_update(s->ch + ch);
1186 }
1187
1188 omap_mcspi_interrupt_update(s);
1189 }
1190
1191 static uint32_t omap_mcspi_read(void *opaque, target_phys_addr_t addr)
1192 {
1193 struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
1194 int ch = 0;
1195 uint32_t ret;
1196
1197 switch (addr) {
1198 case 0x00: /* MCSPI_REVISION */
1199 return 0x91;
1200
1201 case 0x10: /* MCSPI_SYSCONFIG */
1202 return s->sysconfig;
1203
1204 case 0x14: /* MCSPI_SYSSTATUS */
1205 return 1; /* RESETDONE */
1206
1207 case 0x18: /* MCSPI_IRQSTATUS */
1208 return s->irqst;
1209
1210 case 0x1c: /* MCSPI_IRQENABLE */
1211 return s->irqen;
1212
1213 case 0x20: /* MCSPI_WAKEUPENABLE */
1214 return s->wken;
1215
1216 case 0x24: /* MCSPI_SYST */
1217 return s->systest;
1218
1219 case 0x28: /* MCSPI_MODULCTRL */
1220 return s->control;
1221
1222 case 0x68: ch ++;
1223 case 0x54: ch ++;
1224 case 0x40: ch ++;
1225 case 0x2c: /* MCSPI_CHCONF */
1226 return s->ch[ch].config;
1227
1228 case 0x6c: ch ++;
1229 case 0x58: ch ++;
1230 case 0x44: ch ++;
1231 case 0x30: /* MCSPI_CHSTAT */
1232 return s->ch[ch].status;
1233
1234 case 0x70: ch ++;
1235 case 0x5c: ch ++;
1236 case 0x48: ch ++;
1237 case 0x34: /* MCSPI_CHCTRL */
1238 return s->ch[ch].control;
1239
1240 case 0x74: ch ++;
1241 case 0x60: ch ++;
1242 case 0x4c: ch ++;
1243 case 0x38: /* MCSPI_TX */
1244 return s->ch[ch].tx;
1245
1246 case 0x78: ch ++;
1247 case 0x64: ch ++;
1248 case 0x50: ch ++;
1249 case 0x3c: /* MCSPI_RX */
1250 s->ch[ch].status &= ~(1 << 0); /* RXS */
1251 ret = s->ch[ch].rx;
1252 omap_mcspi_transfer_run(s, ch);
1253 return ret;
1254 }
1255
1256 OMAP_BAD_REG(addr);
1257 return 0;
1258 }
1259
1260 static void omap_mcspi_write(void *opaque, target_phys_addr_t addr,
1261 uint32_t value)
1262 {
1263 struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
1264 int ch = 0;
1265
1266 switch (addr) {
1267 case 0x00: /* MCSPI_REVISION */
1268 case 0x14: /* MCSPI_SYSSTATUS */
1269 case 0x30: /* MCSPI_CHSTAT0 */
1270 case 0x3c: /* MCSPI_RX0 */
1271 case 0x44: /* MCSPI_CHSTAT1 */
1272 case 0x50: /* MCSPI_RX1 */
1273 case 0x58: /* MCSPI_CHSTAT2 */
1274 case 0x64: /* MCSPI_RX2 */
1275 case 0x6c: /* MCSPI_CHSTAT3 */
1276 case 0x78: /* MCSPI_RX3 */
1277 OMAP_RO_REG(addr);
1278 return;
1279
1280 case 0x10: /* MCSPI_SYSCONFIG */
1281 if (value & (1 << 1)) /* SOFTRESET */
1282 omap_mcspi_reset(s);
1283 s->sysconfig = value & 0x31d;
1284 break;
1285
1286 case 0x18: /* MCSPI_IRQSTATUS */
1287 if (!((s->control & (1 << 3)) && (s->systest & (1 << 11)))) {
1288 s->irqst &= ~value;
1289 omap_mcspi_interrupt_update(s);
1290 }
1291 break;
1292
1293 case 0x1c: /* MCSPI_IRQENABLE */
1294 s->irqen = value & 0x1777f;
1295 omap_mcspi_interrupt_update(s);
1296 break;
1297
1298 case 0x20: /* MCSPI_WAKEUPENABLE */
1299 s->wken = value & 1;
1300 break;
1301
1302 case 0x24: /* MCSPI_SYST */
1303 if (s->control & (1 << 3)) /* SYSTEM_TEST */
1304 if (value & (1 << 11)) { /* SSB */
1305 s->irqst |= 0x1777f;
1306 omap_mcspi_interrupt_update(s);
1307 }
1308 s->systest = value & 0xfff;
1309 break;
1310
1311 case 0x28: /* MCSPI_MODULCTRL */
1312 if (value & (1 << 3)) /* SYSTEM_TEST */
1313 if (s->systest & (1 << 11)) { /* SSB */
1314 s->irqst |= 0x1777f;
1315 omap_mcspi_interrupt_update(s);
1316 }
1317 s->control = value & 0xf;
1318 break;
1319
1320 case 0x68: ch ++;
1321 case 0x54: ch ++;
1322 case 0x40: ch ++;
1323 case 0x2c: /* MCSPI_CHCONF */
1324 if ((value ^ s->ch[ch].config) & (3 << 14)) /* DMAR | DMAW */
1325 omap_mcspi_dmarequest_update(s->ch + ch);
1326 if (((value >> 12) & 3) == 3) /* TRM */
1327 fprintf(stderr, "%s: invalid TRM value (3)\n", __FUNCTION__);
1328 if (((value >> 7) & 0x1f) < 3) /* WL */
1329 fprintf(stderr, "%s: invalid WL value (%i)\n",
1330 __FUNCTION__, (value >> 7) & 0x1f);
1331 s->ch[ch].config = value & 0x7fffff;
1332 break;
1333
1334 case 0x70: ch ++;
1335 case 0x5c: ch ++;
1336 case 0x48: ch ++;
1337 case 0x34: /* MCSPI_CHCTRL */
1338 if (value & ~s->ch[ch].control & 1) { /* EN */
1339 s->ch[ch].control |= 1;
1340 omap_mcspi_transfer_run(s, ch);
1341 } else
1342 s->ch[ch].control = value & 1;
1343 break;
1344
1345 case 0x74: ch ++;
1346 case 0x60: ch ++;
1347 case 0x4c: ch ++;
1348 case 0x38: /* MCSPI_TX */
1349 s->ch[ch].tx = value;
1350 s->ch[ch].status &= ~(1 << 1); /* TXS */
1351 omap_mcspi_transfer_run(s, ch);
1352 break;
1353
1354 default:
1355 OMAP_BAD_REG(addr);
1356 return;
1357 }
1358 }
1359
1360 static CPUReadMemoryFunc *omap_mcspi_readfn[] = {
1361 omap_badwidth_read32,
1362 omap_badwidth_read32,
1363 omap_mcspi_read,
1364 };
1365
1366 static CPUWriteMemoryFunc *omap_mcspi_writefn[] = {
1367 omap_badwidth_write32,
1368 omap_badwidth_write32,
1369 omap_mcspi_write,
1370 };
1371
1372 struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
1373 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
1374 {
1375 int iomemtype;
1376 struct omap_mcspi_s *s = (struct omap_mcspi_s *)
1377 qemu_mallocz(sizeof(struct omap_mcspi_s));
1378 struct omap_mcspi_ch_s *ch = s->ch;
1379
1380 s->irq = irq;
1381 s->chnum = chnum;
1382 while (chnum --) {
1383 ch->txdrq = *drq ++;
1384 ch->rxdrq = *drq ++;
1385 ch ++;
1386 }
1387 omap_mcspi_reset(s);
1388
1389 iomemtype = l4_register_io_memory(0, omap_mcspi_readfn,
1390 omap_mcspi_writefn, s);
1391 omap_l4_attach(ta, 0, iomemtype);
1392
1393 return s;
1394 }
1395
1396 void omap_mcspi_attach(struct omap_mcspi_s *s,
1397 uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
1398 int chipselect)
1399 {
1400 if (chipselect < 0 || chipselect >= s->chnum)
1401 hw_error("%s: Bad chipselect %i\n", __FUNCTION__, chipselect);
1402
1403 s->ch[chipselect].txrx = txrx;
1404 s->ch[chipselect].opaque = opaque;
1405 }
1406
1407 /* Enhanced Audio Controller (CODEC only) */
1408 struct omap_eac_s {
1409 qemu_irq irq;
1410
1411 uint16_t sysconfig;
1412 uint8_t config[4];
1413 uint8_t control;
1414 uint8_t address;
1415 uint16_t data;
1416 uint8_t vtol;
1417 uint8_t vtsl;
1418 uint16_t mixer;
1419 uint16_t gain[4];
1420 uint8_t att;
1421 uint16_t max[7];
1422
1423 struct {
1424 qemu_irq txdrq;
1425 qemu_irq rxdrq;
1426 uint32_t (*txrx)(void *opaque, uint32_t, int);
1427 void *opaque;
1428
1429 #define EAC_BUF_LEN 1024
1430 uint32_t rxbuf[EAC_BUF_LEN];
1431 int rxoff;
1432 int rxlen;
1433 int rxavail;
1434 uint32_t txbuf[EAC_BUF_LEN];
1435 int txlen;
1436 int txavail;
1437
1438 int enable;
1439 int rate;
1440
1441 uint16_t config[4];
1442
1443 /* These need to be moved to the actual codec */
1444 QEMUSoundCard card;
1445 SWVoiceIn *in_voice;
1446 SWVoiceOut *out_voice;
1447 int hw_enable;
1448 } codec;
1449
1450 struct {
1451 uint8_t control;
1452 uint16_t config;
1453 } modem, bt;
1454 };
1455
1456 static inline void omap_eac_interrupt_update(struct omap_eac_s *s)
1457 {
1458 qemu_set_irq(s->irq, (s->codec.config[1] >> 14) & 1); /* AURDI */
1459 }
1460
1461 static inline void omap_eac_in_dmarequest_update(struct omap_eac_s *s)
1462 {
1463 qemu_set_irq(s->codec.rxdrq, (s->codec.rxavail || s->codec.rxlen) &&
1464 ((s->codec.config[1] >> 12) & 1)); /* DMAREN */
1465 }
1466
1467 static inline void omap_eac_out_dmarequest_update(struct omap_eac_s *s)
1468 {
1469 qemu_set_irq(s->codec.txdrq, s->codec.txlen < s->codec.txavail &&
1470 ((s->codec.config[1] >> 11) & 1)); /* DMAWEN */
1471 }
1472
1473 static inline void omap_eac_in_refill(struct omap_eac_s *s)
1474 {
1475 int left = MIN(EAC_BUF_LEN - s->codec.rxlen, s->codec.rxavail) << 2;
1476 int start = ((s->codec.rxoff + s->codec.rxlen) & (EAC_BUF_LEN - 1)) << 2;
1477 int leftwrap = MIN(left, (EAC_BUF_LEN << 2) - start);
1478 int recv = 1;
1479 uint8_t *buf = (uint8_t *) s->codec.rxbuf + start;
1480
1481 left -= leftwrap;
1482 start = 0;
1483 while (leftwrap && (recv = AUD_read(s->codec.in_voice, buf + start,
1484 leftwrap)) > 0) { /* Be defensive */
1485 start += recv;
1486 leftwrap -= recv;
1487 }
1488 if (recv <= 0)
1489 s->codec.rxavail = 0;
1490 else
1491 s->codec.rxavail -= start >> 2;
1492 s->codec.rxlen += start >> 2;
1493
1494 if (recv > 0 && left > 0) {
1495 start = 0;
1496 while (left && (recv = AUD_read(s->codec.in_voice,
1497 (uint8_t *) s->codec.rxbuf + start,
1498 left)) > 0) { /* Be defensive */
1499 start += recv;
1500 left -= recv;
1501 }
1502 if (recv <= 0)
1503 s->codec.rxavail = 0;
1504 else
1505 s->codec.rxavail -= start >> 2;
1506 s->codec.rxlen += start >> 2;
1507 }
1508 }
1509
1510 static inline void omap_eac_out_empty(struct omap_eac_s *s)
1511 {
1512 int left = s->codec.txlen << 2;
1513 int start = 0;
1514 int sent = 1;
1515
1516 while (left && (sent = AUD_write(s->codec.out_voice,
1517 (uint8_t *) s->codec.txbuf + start,
1518 left)) > 0) { /* Be defensive */
1519 start += sent;
1520 left -= sent;
1521 }
1522
1523 if (!sent) {
1524 s->codec.txavail = 0;
1525 omap_eac_out_dmarequest_update(s);
1526 }
1527
1528 if (start)
1529 s->codec.txlen = 0;
1530 }
1531
1532 static void omap_eac_in_cb(void *opaque, int avail_b)
1533 {
1534 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
1535
1536 s->codec.rxavail = avail_b >> 2;
1537 omap_eac_in_refill(s);
1538 /* TODO: possibly discard current buffer if overrun */
1539 omap_eac_in_dmarequest_update(s);
1540 }
1541
1542 static void omap_eac_out_cb(void *opaque, int free_b)
1543 {
1544 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
1545
1546 s->codec.txavail = free_b >> 2;
1547 if (s->codec.txlen)
1548 omap_eac_out_empty(s);
1549 else
1550 omap_eac_out_dmarequest_update(s);
1551 }
1552
1553 static void omap_eac_enable_update(struct omap_eac_s *s)
1554 {
1555 s->codec.enable = !(s->codec.config[1] & 1) && /* EACPWD */
1556 (s->codec.config[1] & 2) && /* AUDEN */
1557 s->codec.hw_enable;
1558 }
1559
1560 static const int omap_eac_fsint[4] = {
1561 8000,
1562 11025,
1563 22050,
1564 44100,
1565 };
1566
1567 static const int omap_eac_fsint2[8] = {
1568 8000,
1569 11025,
1570 22050,
1571 44100,
1572 48000,
1573 0, 0, 0,
1574 };
1575
1576 static const int omap_eac_fsint3[16] = {
1577 8000,
1578 11025,
1579 16000,
1580 22050,
1581 24000,
1582 32000,
1583 44100,
1584 48000,
1585 0, 0, 0, 0, 0, 0, 0, 0,
1586 };
1587
1588 static void omap_eac_rate_update(struct omap_eac_s *s)
1589 {
1590 int fsint[3];
1591
1592 fsint[2] = (s->codec.config[3] >> 9) & 0xf;
1593 fsint[1] = (s->codec.config[2] >> 0) & 0x7;
1594 fsint[0] = (s->codec.config[0] >> 6) & 0x3;
1595 if (fsint[2] < 0xf)
1596 s->codec.rate = omap_eac_fsint3[fsint[2]];
1597 else if (fsint[1] < 0x7)
1598 s->codec.rate = omap_eac_fsint2[fsint[1]];
1599 else
1600 s->codec.rate = omap_eac_fsint[fsint[0]];
1601 }
1602
1603 static void omap_eac_volume_update(struct omap_eac_s *s)
1604 {
1605 /* TODO */
1606 }
1607
1608 static void omap_eac_format_update(struct omap_eac_s *s)
1609 {
1610 struct audsettings fmt;
1611
1612 /* The hardware buffers at most one sample */
1613 if (s->codec.rxlen)
1614 s->codec.rxlen = 1;
1615
1616 if (s->codec.in_voice) {
1617 AUD_set_active_in(s->codec.in_voice, 0);
1618 AUD_close_in(&s->codec.card, s->codec.in_voice);
1619 s->codec.in_voice = 0;
1620 }
1621 if (s->codec.out_voice) {
1622 omap_eac_out_empty(s);
1623 AUD_set_active_out(s->codec.out_voice, 0);
1624 AUD_close_out(&s->codec.card, s->codec.out_voice);
1625 s->codec.out_voice = 0;
1626 s->codec.txavail = 0;
1627 }
1628 /* Discard what couldn't be written */
1629 s->codec.txlen = 0;
1630
1631 omap_eac_enable_update(s);
1632 if (!s->codec.enable)
1633 return;
1634
1635 omap_eac_rate_update(s);
1636 fmt.endianness = ((s->codec.config[0] >> 8) & 1); /* LI_BI */
1637 fmt.nchannels = ((s->codec.config[0] >> 10) & 1) ? 2 : 1; /* MN_ST */
1638 fmt.freq = s->codec.rate;
1639 /* TODO: signedness possibly depends on the CODEC hardware - or
1640 * does I2S specify it? */
1641 /* All register writes are 16 bits so we we store 16-bit samples
1642 * in the buffers regardless of AGCFR[B8_16] value. */
1643 fmt.fmt = AUD_FMT_U16;
1644
1645 s->codec.in_voice = AUD_open_in(&s->codec.card, s->codec.in_voice,
1646 "eac.codec.in", s, omap_eac_in_cb, &fmt);
1647 s->codec.out_voice = AUD_open_out(&s->codec.card, s->codec.out_voice,
1648 "eac.codec.out", s, omap_eac_out_cb, &fmt);
1649
1650 omap_eac_volume_update(s);
1651
1652 AUD_set_active_in(s->codec.in_voice, 1);
1653 AUD_set_active_out(s->codec.out_voice, 1);
1654 }
1655
1656 static void omap_eac_reset(struct omap_eac_s *s)
1657 {
1658 s->sysconfig = 0;
1659 s->config[0] = 0x0c;
1660 s->config[1] = 0x09;
1661 s->config[2] = 0xab;
1662 s->config[3] = 0x03;
1663 s->control = 0x00;
1664 s->address = 0x00;
1665 s->data = 0x0000;
1666 s->vtol = 0x00;
1667 s->vtsl = 0x00;
1668 s->mixer = 0x0000;
1669 s->gain[0] = 0xe7e7;
1670 s->gain[1] = 0x6767;
1671 s->gain[2] = 0x6767;
1672 s->gain[3] = 0x6767;
1673 s->att = 0xce;
1674 s->max[0] = 0;
1675 s->max[1] = 0;
1676 s->max[2] = 0;
1677 s->max[3] = 0;
1678 s->max[4] = 0;
1679 s->max[5] = 0;
1680 s->max[6] = 0;
1681
1682 s->modem.control = 0x00;
1683 s->modem.config = 0x0000;
1684 s->bt.control = 0x00;
1685 s->bt.config = 0x0000;
1686 s->codec.config[0] = 0x0649;
1687 s->codec.config[1] = 0x0000;
1688 s->codec.config[2] = 0x0007;
1689 s->codec.config[3] = 0x1ffc;
1690 s->codec.rxoff = 0;
1691 s->codec.rxlen = 0;
1692 s->codec.txlen = 0;
1693 s->codec.rxavail = 0;
1694 s->codec.txavail = 0;
1695
1696 omap_eac_format_update(s);
1697 omap_eac_interrupt_update(s);
1698 }
1699
1700 static uint32_t omap_eac_read(void *opaque, target_phys_addr_t addr)
1701 {
1702 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
1703 uint32_t ret;
1704
1705 switch (addr) {
1706 case 0x000: /* CPCFR1 */
1707 return s->config[0];
1708 case 0x004: /* CPCFR2 */
1709 return s->config[1];
1710 case 0x008: /* CPCFR3 */
1711 return s->config[2];
1712 case 0x00c: /* CPCFR4 */
1713 return s->config[3];
1714
1715 case 0x010: /* CPTCTL */
1716 return s->control | ((s->codec.rxavail + s->codec.rxlen > 0) << 7) |
1717 ((s->codec.txlen < s->codec.txavail) << 5);
1718
1719 case 0x014: /* CPTTADR */
1720 return s->address;
1721 case 0x018: /* CPTDATL */
1722 return s->data & 0xff;
1723 case 0x01c: /* CPTDATH */
1724 return s->data >> 8;
1725 case 0x020: /* CPTVSLL */
1726 return s->vtol;
1727 case 0x024: /* CPTVSLH */
1728 return s->vtsl | (3 << 5); /* CRDY1 | CRDY2 */
1729 case 0x040: /* MPCTR */
1730 return s->modem.control;
1731 case 0x044: /* MPMCCFR */
1732 return s->modem.config;
1733 case 0x060: /* BPCTR */
1734 return s->bt.control;
1735 case 0x064: /* BPMCCFR */
1736 return s->bt.config;
1737 case 0x080: /* AMSCFR */
1738 return s->mixer;
1739 case 0x084: /* AMVCTR */
1740 return s->gain[0];
1741 case 0x088: /* AM1VCTR */
1742 return s->gain[1];
1743 case 0x08c: /* AM2VCTR */
1744 return s->gain[2];
1745 case 0x090: /* AM3VCTR */
1746 return s->gain[3];
1747 case 0x094: /* ASTCTR */
1748 return s->att;
1749 case 0x098: /* APD1LCR */
1750 return s->max[0];
1751 case 0x09c: /* APD1RCR */
1752 return s->max[1];
1753 case 0x0a0: /* APD2LCR */
1754 return s->max[2];
1755 case 0x0a4: /* APD2RCR */
1756 return s->max[3];
1757 case 0x0a8: /* APD3LCR */
1758 return s->max[4];
1759 case 0x0ac: /* APD3RCR */
1760 return s->max[5];
1761 case 0x0b0: /* APD4R */
1762 return s->max[6];
1763 case 0x0b4: /* ADWR */
1764 /* This should be write-only? Docs list it as read-only. */
1765 return 0x0000;
1766 case 0x0b8: /* ADRDR */
1767 if (likely(s->codec.rxlen > 1)) {
1768 ret = s->codec.rxbuf[s->codec.rxoff ++];
1769 s->codec.rxlen --;
1770 s->codec.rxoff &= EAC_BUF_LEN - 1;
1771 return ret;
1772 } else if (s->codec.rxlen) {
1773 ret = s->codec.rxbuf[s->codec.rxoff ++];
1774 s->codec.rxlen --;
1775 s->codec.rxoff &= EAC_BUF_LEN - 1;
1776 if (s->codec.rxavail)
1777 omap_eac_in_refill(s);
1778 omap_eac_in_dmarequest_update(s);
1779 return ret;
1780 }
1781 return 0x0000;
1782 case 0x0bc: /* AGCFR */
1783 return s->codec.config[0];
1784 case 0x0c0: /* AGCTR */
1785 return s->codec.config[1] | ((s->codec.config[1] & 2) << 14);
1786 case 0x0c4: /* AGCFR2 */
1787 return s->codec.config[2];
1788 case 0x0c8: /* AGCFR3 */
1789 return s->codec.config[3];
1790 case 0x0cc: /* MBPDMACTR */
1791 case 0x0d0: /* MPDDMARR */
1792 case 0x0d8: /* MPUDMARR */
1793 case 0x0e4: /* BPDDMARR */
1794 case 0x0ec: /* BPUDMARR */
1795 return 0x0000;
1796
1797 case 0x100: /* VERSION_NUMBER */
1798 return 0x0010;
1799
1800 case 0x104: /* SYSCONFIG */
1801 return s->sysconfig;
1802
1803 case 0x108: /* SYSSTATUS */
1804 return 1 | 0xe; /* RESETDONE | stuff */
1805 }
1806
1807 OMAP_BAD_REG(addr);
1808 return 0;
1809 }
1810
1811 static void omap_eac_write(void *opaque, target_phys_addr_t addr,
1812 uint32_t value)
1813 {
1814 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
1815
1816 switch (addr) {
1817 case 0x098: /* APD1LCR */
1818 case 0x09c: /* APD1RCR */
1819 case 0x0a0: /* APD2LCR */
1820 case 0x0a4: /* APD2RCR */
1821 case 0x0a8: /* APD3LCR */
1822 case 0x0ac: /* APD3RCR */
1823 case 0x0b0: /* APD4R */
1824 case 0x0b8: /* ADRDR */
1825 case 0x0d0: /* MPDDMARR */
1826 case 0x0d8: /* MPUDMARR */
1827 case 0x0e4: /* BPDDMARR */
1828 case 0x0ec: /* BPUDMARR */
1829 case 0x100: /* VERSION_NUMBER */
1830 case 0x108: /* SYSSTATUS */
1831 OMAP_RO_REG(addr);
1832 return;
1833
1834 case 0x000: /* CPCFR1 */
1835 s->config[0] = value & 0xff;
1836 omap_eac_format_update(s);
1837 break;
1838 case 0x004: /* CPCFR2 */
1839 s->config[1] = value & 0xff;
1840 omap_eac_format_update(s);
1841 break;
1842 case 0x008: /* CPCFR3 */
1843 s->config[2] = value & 0xff;
1844 omap_eac_format_update(s);
1845 break;
1846 case 0x00c: /* CPCFR4 */
1847 s->config[3] = value & 0xff;
1848 omap_eac_format_update(s);
1849 break;
1850
1851 case 0x010: /* CPTCTL */
1852 /* Assuming TXF and TXE bits are read-only... */
1853 s->control = value & 0x5f;
1854 omap_eac_interrupt_update(s);
1855 break;
1856
1857 case 0x014: /* CPTTADR */
1858 s->address = value & 0xff;
1859 break;
1860 case 0x018: /* CPTDATL */
1861 s->data &= 0xff00;
1862 s->data |= value & 0xff;
1863 break;
1864 case 0x01c: /* CPTDATH */
1865 s->data &= 0x00ff;
1866 s->data |= value << 8;
1867 break;
1868 case 0x020: /* CPTVSLL */
1869 s->vtol = value & 0xf8;
1870 break;
1871 case 0x024: /* CPTVSLH */
1872 s->vtsl = value & 0x9f;
1873 break;
1874 case 0x040: /* MPCTR */
1875 s->modem.control = value & 0x8f;
1876 break;
1877 case 0x044: /* MPMCCFR */
1878 s->modem.config = value & 0x7fff;
1879 break;
1880 case 0x060: /* BPCTR */
1881 s->bt.control = value & 0x8f;
1882 break;
1883 case 0x064: /* BPMCCFR */
1884 s->bt.config = value & 0x7fff;
1885 break;
1886 case 0x080: /* AMSCFR */
1887 s->mixer = value & 0x0fff;
1888 break;
1889 case 0x084: /* AMVCTR */
1890 s->gain[0] = value & 0xffff;
1891 break;
1892 case 0x088: /* AM1VCTR */
1893 s->gain[1] = value & 0xff7f;
1894 break;
1895 case 0x08c: /* AM2VCTR */
1896 s->gain[2] = value & 0xff7f;
1897 break;
1898 case 0x090: /* AM3VCTR */
1899 s->gain[3] = value & 0xff7f;
1900 break;
1901 case 0x094: /* ASTCTR */
1902 s->att = value & 0xff;
1903 break;
1904
1905 case 0x0b4: /* ADWR */
1906 s->codec.txbuf[s->codec.txlen ++] = value;
1907 if (unlikely(s->codec.txlen == EAC_BUF_LEN ||
1908 s->codec.txlen == s->codec.txavail)) {
1909 if (s->codec.txavail)
1910 omap_eac_out_empty(s);
1911 /* Discard what couldn't be written */
1912 s->codec.txlen = 0;
1913 }
1914 break;
1915
1916 case 0x0bc: /* AGCFR */
1917 s->codec.config[0] = value & 0x07ff;
1918 omap_eac_format_update(s);
1919 break;
1920 case 0x0c0: /* AGCTR */
1921 s->codec.config[1] = value & 0x780f;
1922 omap_eac_format_update(s);
1923 break;
1924 case 0x0c4: /* AGCFR2 */
1925 s->codec.config[2] = value & 0x003f;
1926 omap_eac_format_update(s);
1927 break;
1928 case 0x0c8: /* AGCFR3 */
1929 s->codec.config[3] = value & 0xffff;
1930 omap_eac_format_update(s);
1931 break;
1932 case 0x0cc: /* MBPDMACTR */
1933 case 0x0d4: /* MPDDMAWR */
1934 case 0x0e0: /* MPUDMAWR */
1935 case 0x0e8: /* BPDDMAWR */
1936 case 0x0f0: /* BPUDMAWR */
1937 break;
1938
1939 case 0x104: /* SYSCONFIG */
1940 if (value & (1 << 1)) /* SOFTRESET */
1941 omap_eac_reset(s);
1942 s->sysconfig = value & 0x31d;
1943 break;
1944
1945 default:
1946 OMAP_BAD_REG(addr);
1947 return;
1948 }
1949 }
1950
1951 static CPUReadMemoryFunc *omap_eac_readfn[] = {
1952 omap_badwidth_read16,
1953 omap_eac_read,
1954 omap_badwidth_read16,
1955 };
1956
1957 static CPUWriteMemoryFunc *omap_eac_writefn[] = {
1958 omap_badwidth_write16,
1959 omap_eac_write,
1960 omap_badwidth_write16,
1961 };
1962
1963 struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
1964 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
1965 {
1966 int iomemtype;
1967 struct omap_eac_s *s = (struct omap_eac_s *)
1968 qemu_mallocz(sizeof(struct omap_eac_s));
1969
1970 s->irq = irq;
1971 s->codec.rxdrq = *drq ++;
1972 s->codec.txdrq = *drq ++;
1973 omap_eac_reset(s);
1974
1975 #ifdef HAS_AUDIO
1976 AUD_register_card("OMAP EAC", &s->codec.card);
1977
1978 iomemtype = cpu_register_io_memory(0, omap_eac_readfn,
1979 omap_eac_writefn, s);
1980 omap_l4_attach(ta, 0, iomemtype);
1981 #endif
1982
1983 return s;
1984 }
1985
1986 /* STI/XTI (emulation interface) console - reverse engineered only */
1987 struct omap_sti_s {
1988 qemu_irq irq;
1989 CharDriverState *chr;
1990
1991 uint32_t sysconfig;
1992 uint32_t systest;
1993 uint32_t irqst;
1994 uint32_t irqen;
1995 uint32_t clkcontrol;
1996 uint32_t serial_config;
1997 };
1998
1999 #define STI_TRACE_CONSOLE_CHANNEL 239
2000 #define STI_TRACE_CONTROL_CHANNEL 253
2001
2002 static inline void omap_sti_interrupt_update(struct omap_sti_s *s)
2003 {
2004 qemu_set_irq(s->irq, s->irqst & s->irqen);
2005 }
2006
2007 static void omap_sti_reset(struct omap_sti_s *s)
2008 {
2009 s->sysconfig = 0;
2010 s->irqst = 0;
2011 s->irqen = 0;
2012 s->clkcontrol = 0;
2013 s->serial_config = 0;
2014
2015 omap_sti_interrupt_update(s);
2016 }
2017
2018 static uint32_t omap_sti_read(void *opaque, target_phys_addr_t addr)
2019 {
2020 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
2021
2022 switch (addr) {
2023 case 0x00: /* STI_REVISION */
2024 return 0x10;
2025
2026 case 0x10: /* STI_SYSCONFIG */
2027 return s->sysconfig;
2028
2029 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
2030 return 0x00;
2031
2032 case 0x18: /* STI_IRQSTATUS */
2033 return s->irqst;
2034
2035 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
2036 return s->irqen;
2037
2038 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
2039 case 0x28: /* STI_RX_DR / XTI_RXDATA */
2040 /* TODO */
2041 return 0;
2042
2043 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
2044 return s->clkcontrol;
2045
2046 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
2047 return s->serial_config;
2048 }
2049
2050 OMAP_BAD_REG(addr);
2051 return 0;
2052 }
2053
2054 static void omap_sti_write(void *opaque, target_phys_addr_t addr,
2055 uint32_t value)
2056 {
2057 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
2058
2059 switch (addr) {
2060 case 0x00: /* STI_REVISION */
2061 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
2062 OMAP_RO_REG(addr);
2063 return;
2064
2065 case 0x10: /* STI_SYSCONFIG */
2066 if (value & (1 << 1)) /* SOFTRESET */
2067 omap_sti_reset(s);
2068 s->sysconfig = value & 0xfe;
2069 break;
2070
2071 case 0x18: /* STI_IRQSTATUS */
2072 s->irqst &= ~value;
2073 omap_sti_interrupt_update(s);
2074 break;
2075
2076 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
2077 s->irqen = value & 0xffff;
2078 omap_sti_interrupt_update(s);
2079 break;
2080
2081 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
2082 s->clkcontrol = value & 0xff;
2083 break;
2084
2085 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
2086 s->serial_config = value & 0xff;
2087 break;
2088
2089 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
2090 case 0x28: /* STI_RX_DR / XTI_RXDATA */
2091 /* TODO */
2092 return;
2093
2094 default:
2095 OMAP_BAD_REG(addr);
2096 return;
2097 }
2098 }
2099
2100 static CPUReadMemoryFunc *omap_sti_readfn[] = {
2101 omap_badwidth_read32,
2102 omap_badwidth_read32,
2103 omap_sti_read,
2104 };
2105
2106 static CPUWriteMemoryFunc *omap_sti_writefn[] = {
2107 omap_badwidth_write32,
2108 omap_badwidth_write32,
2109 omap_sti_write,
2110 };
2111
2112 static uint32_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr)
2113 {
2114 OMAP_BAD_REG(addr);
2115 return 0;
2116 }
2117
2118 static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr,
2119 uint32_t value)
2120 {
2121 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
2122 int ch = addr >> 6;
2123 uint8_t byte = value;
2124
2125 if (ch == STI_TRACE_CONTROL_CHANNEL) {
2126 /* Flush channel <i>value</i>. */
2127 qemu_chr_write(s->chr, (const uint8_t *) "\r", 1);
2128 } else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) {
2129 if (value == 0xc0 || value == 0xc3) {
2130 /* Open channel <i>ch</i>. */
2131 } else if (value == 0x00)
2132 qemu_chr_write(s->chr, (const uint8_t *) "\n", 1);
2133 else
2134 qemu_chr_write(s->chr, &byte, 1);
2135 }
2136 }
2137
2138 static CPUReadMemoryFunc *omap_sti_fifo_readfn[] = {
2139 omap_sti_fifo_read,
2140 omap_badwidth_read8,
2141 omap_badwidth_read8,
2142 };
2143
2144 static CPUWriteMemoryFunc *omap_sti_fifo_writefn[] = {
2145 omap_sti_fifo_write,
2146 omap_badwidth_write8,
2147 omap_badwidth_write8,
2148 };
2149
2150 static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
2151 target_phys_addr_t channel_base, qemu_irq irq, omap_clk clk,
2152 CharDriverState *chr)
2153 {
2154 int iomemtype;
2155 struct omap_sti_s *s = (struct omap_sti_s *)
2156 qemu_mallocz(sizeof(struct omap_sti_s));
2157
2158 s->irq = irq;
2159 omap_sti_reset(s);
2160
2161 s->chr = chr ?: qemu_chr_open("null", "null", NULL);
2162
2163 iomemtype = l4_register_io_memory(0, omap_sti_readfn,
2164 omap_sti_writefn, s);
2165 omap_l4_attach(ta, 0, iomemtype);
2166
2167 iomemtype = cpu_register_io_memory(0, omap_sti_fifo_readfn,
2168 omap_sti_fifo_writefn, s);
2169 cpu_register_physical_memory(channel_base, 0x10000, iomemtype);
2170
2171 return s;
2172 }
2173
2174 /* L4 Interconnect */
2175 struct omap_target_agent_s {
2176 struct omap_l4_s *bus;
2177 int regions;
2178 struct omap_l4_region_s *start;
2179 target_phys_addr_t base;
2180 uint32_t component;
2181 uint32_t control;
2182 uint32_t status;
2183 };
2184
2185 struct omap_l4_s {
2186 target_phys_addr_t base;
2187 int ta_num;
2188 struct omap_target_agent_s ta[0];
2189 };
2190
2191 #ifdef L4_MUX_HACK
2192 static int omap_l4_io_entries;
2193 static int omap_cpu_io_entry;
2194 static struct omap_l4_entry {
2195 CPUReadMemoryFunc **mem_read;
2196 CPUWriteMemoryFunc **mem_write;
2197 void *opaque;
2198 } *omap_l4_io_entry;
2199 static CPUReadMemoryFunc **omap_l4_io_readb_fn;
2200 static CPUReadMemoryFunc **omap_l4_io_readh_fn;
2201 static CPUReadMemoryFunc **omap_l4_io_readw_fn;
2202 static CPUWriteMemoryFunc **omap_l4_io_writeb_fn;
2203 static CPUWriteMemoryFunc **omap_l4_io_writeh_fn;
2204 static CPUWriteMemoryFunc **omap_l4_io_writew_fn;
2205 static void **omap_l4_io_opaque;
2206
2207 int l4_register_io_memory(int io_index, CPUReadMemoryFunc **mem_read,
2208 CPUWriteMemoryFunc **mem_write, void *opaque)
2209 {
2210 omap_l4_io_entry[omap_l4_io_entries].mem_read = mem_read;
2211 omap_l4_io_entry[omap_l4_io_entries].mem_write = mem_write;
2212 omap_l4_io_entry[omap_l4_io_entries].opaque = opaque;
2213
2214 return omap_l4_io_entries ++;
2215 }
2216
2217 static uint32_t omap_l4_io_readb(void *opaque, target_phys_addr_t addr)
2218 {
2219 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
2220
2221 return omap_l4_io_readb_fn[i](omap_l4_io_opaque[i], addr);
2222 }
2223
2224 static uint32_t omap_l4_io_readh(void *opaque, target_phys_addr_t addr)
2225 {
2226 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
2227
2228 return omap_l4_io_readh_fn[i](omap_l4_io_opaque[i], addr);
2229 }
2230
2231 static uint32_t omap_l4_io_readw(void *opaque, target_phys_addr_t addr)
2232 {
2233 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
2234
2235 return omap_l4_io_readw_fn[i](omap_l4_io_opaque[i], addr);
2236 }
2237
2238 static void omap_l4_io_writeb(void *opaque, target_phys_addr_t addr,
2239 uint32_t value)
2240 {
2241 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
2242
2243 return omap_l4_io_writeb_fn[i](omap_l4_io_opaque[i], addr, value);
2244 }
2245
2246 static void omap_l4_io_writeh(void *opaque, target_phys_addr_t addr,
2247 uint32_t value)
2248 {
2249 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
2250
2251 return omap_l4_io_writeh_fn[i](omap_l4_io_opaque[i], addr, value);
2252 }
2253
2254 static void omap_l4_io_writew(void *opaque, target_phys_addr_t addr,
2255 uint32_t value)
2256 {
2257 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
2258
2259 return omap_l4_io_writew_fn[i](omap_l4_io_opaque[i], addr, value);
2260 }
2261
2262 static CPUReadMemoryFunc *omap_l4_io_readfn[] = {
2263 omap_l4_io_readb,
2264 omap_l4_io_readh,
2265 omap_l4_io_readw,
2266 };
2267
2268 static CPUWriteMemoryFunc *omap_l4_io_writefn[] = {
2269 omap_l4_io_writeb,
2270 omap_l4_io_writeh,
2271 omap_l4_io_writew,
2272 };
2273 #endif
2274
2275 struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num)
2276 {
2277 struct omap_l4_s *bus = qemu_mallocz(
2278 sizeof(*bus) + ta_num * sizeof(*bus->ta));
2279
2280 bus->ta_num = ta_num;
2281 bus->base = base;
2282
2283 #ifdef L4_MUX_HACK
2284 omap_l4_io_entries = 1;
2285 omap_l4_io_entry = qemu_mallocz(125 * sizeof(*omap_l4_io_entry));
2286
2287 omap_cpu_io_entry =
2288 cpu_register_io_memory(0, omap_l4_io_readfn,
2289 omap_l4_io_writefn, bus);
2290 # define L4_PAGES (0xb4000 / TARGET_PAGE_SIZE)
2291 omap_l4_io_readb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
2292 omap_l4_io_readh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
2293 omap_l4_io_readw_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
2294 omap_l4_io_writeb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
2295 omap_l4_io_writeh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
2296 omap_l4_io_writew_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
2297 omap_l4_io_opaque = qemu_mallocz(sizeof(void *) * L4_PAGES);
2298 #endif
2299
2300 return bus;
2301 }
2302
2303 static uint32_t omap_l4ta_read(void *opaque, target_phys_addr_t addr)
2304 {
2305 struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
2306
2307 switch (addr) {
2308 case 0x00: /* COMPONENT */
2309 return s->component;
2310
2311 case 0x20: /* AGENT_CONTROL */
2312 return s->control;
2313
2314 case 0x28: /* AGENT_STATUS */
2315 return s->status;
2316 }
2317
2318 OMAP_BAD_REG(addr);
2319 return 0;
2320 }
2321
2322 static void omap_l4ta_write(void *opaque, target_phys_addr_t addr,
2323 uint32_t value)
2324 {
2325 struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
2326
2327 switch (addr) {
2328 case 0x00: /* COMPONENT */
2329 case 0x28: /* AGENT_STATUS */
2330 OMAP_RO_REG(addr);
2331 break;
2332
2333 case 0x20: /* AGENT_CONTROL */
2334 s->control = value & 0x01000700;
2335 if (value & 1) /* OCP_RESET */
2336 s->status &= ~1; /* REQ_TIMEOUT */
2337 break;
2338
2339 default:
2340 OMAP_BAD_REG(addr);
2341 }
2342 }
2343
2344 static CPUReadMemoryFunc *omap_l4ta_readfn[] = {
2345 omap_badwidth_read16,
2346 omap_l4ta_read,
2347 omap_badwidth_read16,
2348 };
2349
2350 static CPUWriteMemoryFunc *omap_l4ta_writefn[] = {
2351 omap_badwidth_write32,
2352 omap_badwidth_write32,
2353 omap_l4ta_write,
2354 };
2355
2356 #define L4TA(n) (n)
2357 #define L4TAO(n) ((n) + 39)
2358
2359 static struct omap_l4_region_s {
2360 target_phys_addr_t offset;
2361 size_t size;
2362 int access;
2363 } omap_l4_region[125] = {
2364 [ 1] = { 0x40800, 0x800, 32 }, /* Initiator agent */
2365 [ 2] = { 0x41000, 0x1000, 32 }, /* Link agent */
2366 [ 0] = { 0x40000, 0x800, 32 }, /* Address and protection */
2367 [ 3] = { 0x00000, 0x1000, 32 | 16 | 8 }, /* System Control and Pinout */
2368 [ 4] = { 0x01000, 0x1000, 32 | 16 | 8 }, /* L4TAO1 */
2369 [ 5] = { 0x04000, 0x1000, 32 | 16 }, /* 32K Timer */
2370 [ 6] = { 0x05000, 0x1000, 32 | 16 | 8 }, /* L4TAO2 */
2371 [ 7] = { 0x08000, 0x800, 32 }, /* PRCM Region A */
2372 [ 8] = { 0x08800, 0x800, 32 }, /* PRCM Region B */
2373 [ 9] = { 0x09000, 0x1000, 32 | 16 | 8 }, /* L4TAO */
2374 [ 10] = { 0x12000, 0x1000, 32 | 16 | 8 }, /* Test (BCM) */
2375 [ 11] = { 0x13000, 0x1000, 32 | 16 | 8 }, /* L4TA1 */
2376 [ 12] = { 0x14000, 0x1000, 32 }, /* Test/emulation (TAP) */
2377 [ 13] = { 0x15000, 0x1000, 32 | 16 | 8 }, /* L4TA2 */
2378 [ 14] = { 0x18000, 0x1000, 32 | 16 | 8 }, /* GPIO1 */
2379 [ 16] = { 0x1a000, 0x1000, 32 | 16 | 8 }, /* GPIO2 */
2380 [ 18] = { 0x1c000, 0x1000, 32 | 16 | 8 }, /* GPIO3 */
2381 [ 19] = { 0x1e000, 0x1000, 32 | 16 | 8 }, /* GPIO4 */
2382 [ 15] = { 0x19000, 0x1000, 32 | 16 | 8 }, /* Quad GPIO TOP */
2383 [ 17] = { 0x1b000, 0x1000, 32 | 16 | 8 }, /* L4TA3 */
2384 [ 20] = { 0x20000, 0x1000, 32 | 16 | 8 }, /* WD Timer 1 (Secure) */
2385 [ 22] = { 0x22000, 0x1000, 32 | 16 | 8 }, /* WD Timer 2 (OMAP) */
2386 [ 21] = { 0x21000, 0x1000, 32 | 16 | 8 }, /* Dual WD timer TOP */
2387 [ 23] = { 0x23000, 0x1000, 32 | 16 | 8 }, /* L4TA4 */
2388 [ 24] = { 0x28000, 0x1000, 32 | 16 | 8 }, /* GP Timer 1 */
2389 [ 25] = { 0x29000, 0x1000, 32 | 16 | 8 }, /* L4TA7 */
2390 [ 26] = { 0x48000, 0x2000, 32 | 16 | 8 }, /* Emulation (ARM11ETB) */
2391 [ 27] = { 0x4a000, 0x1000, 32 | 16 | 8 }, /* L4TA9 */
2392 [ 28] = { 0x50000, 0x400, 32 | 16 | 8 }, /* Display top */
2393 [ 29] = { 0x50400, 0x400, 32 | 16 | 8 }, /* Display control */
2394 [ 30] = { 0x50800, 0x400, 32 | 16 | 8 }, /* Display RFBI */
2395 [ 31] = { 0x50c00, 0x400, 32 | 16 | 8 }, /* Display encoder */
2396 [ 32] = { 0x51000, 0x1000, 32 | 16 | 8 }, /* L4TA10 */
2397 [ 33] = { 0x52000, 0x400, 32 | 16 | 8 }, /* Camera top */
2398 [ 34] = { 0x52400, 0x400, 32 | 16 | 8 }, /* Camera core */
2399 [ 35] = { 0x52800, 0x400, 32 | 16 | 8 }, /* Camera DMA */
2400 [ 36] = { 0x52c00, 0x400, 32 | 16 | 8 }, /* Camera MMU */
2401 [ 37] = { 0x53000, 0x1000, 32 | 16 | 8 }, /* L4TA11 */
2402 [ 38] = { 0x56000, 0x1000, 32 | 16 | 8 }, /* sDMA */
2403 [ 39] = { 0x57000, 0x1000, 32 | 16 | 8 }, /* L4TA12 */
2404 [ 40] = { 0x58000, 0x1000, 32 | 16 | 8 }, /* SSI top */
2405 [ 41] = { 0x59000, 0x1000, 32 | 16 | 8 }, /* SSI GDD */
2406 [ 42] = { 0x5a000, 0x1000, 32 | 16 | 8 }, /* SSI Port1 */
2407 [ 43] = { 0x5b000, 0x1000, 32 | 16 | 8 }, /* SSI Port2 */
2408 [ 44] = { 0x5c000, 0x1000, 32 | 16 | 8 }, /* L4TA13 */
2409 [ 45] = { 0x5e000, 0x1000, 32 | 16 | 8 }, /* USB OTG */
2410 [ 46] = { 0x5f000, 0x1000, 32 | 16 | 8 }, /* L4TAO4 */
2411 [ 47] = { 0x60000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER1SDRC) */
2412 [ 48] = { 0x61000, 0x1000, 32 | 16 | 8 }, /* L4TA14 */
2413 [ 49] = { 0x62000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER2GPMC) */
2414 [ 50] = { 0x63000, 0x1000, 32 | 16 | 8 }, /* L4TA15 */
2415 [ 51] = { 0x64000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER3OCM) */
2416 [ 52] = { 0x65000, 0x1000, 32 | 16 | 8 }, /* L4TA16 */
2417 [ 53] = { 0x66000, 0x300, 32 | 16 | 8 }, /* Emulation (WIN_TRACER4L4) */
2418 [ 54] = { 0x67000, 0x1000, 32 | 16 | 8 }, /* L4TA17 */
2419 [ 55] = { 0x68000, 0x1000, 32 | 16 | 8 }, /* Emulation (XTI) */
2420 [ 56] = { 0x69000, 0x1000, 32 | 16 | 8 }, /* L4TA18 */
2421 [ 57] = { 0x6a000, 0x1000, 16 | 8 }, /* UART1 */
2422 [ 58] = { 0x6b000, 0x1000, 32 | 16 | 8 }, /* L4TA19 */
2423 [ 59] = { 0x6c000, 0x1000, 16 | 8 }, /* UART2 */
2424 [ 60] = { 0x6d000, 0x1000, 32 | 16 | 8 }, /* L4TA20 */
2425 [ 61] = { 0x6e000, 0x1000, 16 | 8 }, /* UART3 */
2426 [ 62] = { 0x6f000, 0x1000, 32 | 16 | 8 }, /* L4TA21 */
2427 [ 63] = { 0x70000, 0x1000, 16 }, /* I2C1 */
2428 [ 64] = { 0x71000, 0x1000, 32 | 16 | 8 }, /* L4TAO5 */
2429 [ 65] = { 0x72000, 0x1000, 16 }, /* I2C2 */
2430 [ 66] = { 0x73000, 0x1000, 32 | 16 | 8 }, /* L4TAO6 */
2431 [ 67] = { 0x74000, 0x1000, 16 }, /* McBSP1 */
2432 [ 68] = { 0x75000, 0x1000, 32 | 16 | 8 }, /* L4TAO7 */
2433 [ 69] = { 0x76000, 0x1000, 16 }, /* McBSP2 */
2434 [ 70] = { 0x77000, 0x1000, 32 | 16 | 8 }, /* L4TAO8 */
2435 [ 71] = { 0x24000, 0x1000, 32 | 16 | 8 }, /* WD Timer 3 (DSP) */
2436 [ 72] = { 0x25000, 0x1000, 32 | 16 | 8 }, /* L4TA5 */
2437 [ 73] = { 0x26000, 0x1000, 32 | 16 | 8 }, /* WD Timer 4 (IVA) */
2438 [ 74] = { 0x27000, 0x1000, 32 | 16 | 8 }, /* L4TA6 */
2439 [ 75] = { 0x2a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 2 */
2440 [ 76] = { 0x2b000, 0x1000, 32 | 16 | 8 }, /* L4TA8 */
2441 [ 77] = { 0x78000, 0x1000, 32 | 16 | 8 }, /* GP Timer 3 */
2442 [ 78] = { 0x79000, 0x1000, 32 | 16 | 8 }, /* L4TA22 */
2443 [ 79] = { 0x7a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 4 */
2444 [ 80] = { 0x7b000, 0x1000, 32 | 16 | 8 }, /* L4TA23 */
2445 [ 81] = { 0x7c000, 0x1000, 32 | 16 | 8 }, /* GP Timer 5 */
2446 [ 82] = { 0x7d000, 0x1000, 32 | 16 | 8 }, /* L4TA24 */
2447 [ 83] = { 0x7e000, 0x1000, 32 | 16 | 8 }, /* GP Timer 6 */
2448 [ 84] = { 0x7f000, 0x1000, 32 | 16 | 8 }, /* L4TA25 */
2449 [ 85] = { 0x80000, 0x1000, 32 | 16 | 8 }, /* GP Timer 7 */
2450 [ 86] = { 0x81000, 0x1000, 32 | 16 | 8 }, /* L4TA26 */
2451 [ 87] = { 0x82000, 0x1000, 32 | 16 | 8 }, /* GP Timer 8 */
2452 [ 88] = { 0x83000, 0x1000, 32 | 16 | 8 }, /* L4TA27 */
2453 [ 89] = { 0x84000, 0x1000, 32 | 16 | 8 }, /* GP Timer 9 */
2454 [ 90] = { 0x85000, 0x1000, 32 | 16 | 8 }, /* L4TA28 */
2455 [ 91] = { 0x86000, 0x1000, 32 | 16 | 8 }, /* GP Timer 10 */
2456 [ 92] = { 0x87000, 0x1000, 32 | 16 | 8 }, /* L4TA29 */
2457 [ 93] = { 0x88000, 0x1000, 32 | 16 | 8 }, /* GP Timer 11 */
2458 [ 94] = { 0x89000, 0x1000, 32 | 16 | 8 }, /* L4TA30 */
2459 [ 95] = { 0x8a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 12 */
2460 [ 96] = { 0x8b000, 0x1000, 32 | 16 | 8 }, /* L4TA31 */
2461 [ 97] = { 0x90000, 0x1000, 16 }, /* EAC */
2462 [ 98] = { 0x91000, 0x1000, 32 | 16 | 8 }, /* L4TA32 */
2463 [ 99] = { 0x92000, 0x1000, 16 }, /* FAC */
2464 [100] = { 0x93000, 0x1000, 32 | 16 | 8 }, /* L4TA33 */
2465 [101] = { 0x94000, 0x1000, 32 | 16 | 8 }, /* IPC (MAILBOX) */
2466 [102] = { 0x95000, 0x1000, 32 | 16 | 8 }, /* L4TA34 */
2467 [103] = { 0x98000, 0x1000, 32 | 16 | 8 }, /* SPI1 */
2468 [104] = { 0x99000, 0x1000, 32 | 16 | 8 }, /* L4TA35 */
2469 [105] = { 0x9a000, 0x1000, 32 | 16 | 8 }, /* SPI2 */
2470 [106] = { 0x9b000, 0x1000, 32 | 16 | 8 }, /* L4TA36 */
2471 [107] = { 0x9c000, 0x1000, 16 | 8 }, /* MMC SDIO */
2472 [108] = { 0x9d000, 0x1000, 32 | 16 | 8 }, /* L4TAO9 */
2473 [109] = { 0x9e000, 0x1000, 32 | 16 | 8 }, /* MS_PRO */
2474 [110] = { 0x9f000, 0x1000, 32 | 16 | 8 }, /* L4TAO10 */
2475 [111] = { 0xa0000, 0x1000, 32 }, /* RNG */
2476 [112] = { 0xa1000, 0x1000, 32 | 16 | 8 }, /* L4TAO11 */
2477 [113] = { 0xa2000, 0x1000, 32 }, /* DES3DES */
2478 [114] = { 0xa3000, 0x1000, 32 | 16 | 8 }, /* L4TAO12 */
2479 [115] = { 0xa4000, 0x1000, 32 }, /* SHA1MD5 */
2480 [116] = { 0xa5000, 0x1000, 32 | 16 | 8 }, /* L4TAO13 */
2481 [117] = { 0xa6000, 0x1000, 32 }, /* AES */
2482 [118] = { 0xa7000, 0x1000, 32 | 16 | 8 }, /* L4TA37 */
2483 [119] = { 0xa8000, 0x2000, 32 }, /* PKA */
2484 [120] = { 0xaa000, 0x1000, 32 | 16 | 8 }, /* L4TA38 */
2485 [121] = { 0xb0000, 0x1000, 32 }, /* MG */
2486 [122] = { 0xb1000, 0x1000, 32 | 16 | 8 },
2487 [123] = { 0xb2000, 0x1000, 32 }, /* HDQ/1-Wire */
2488 [124] = { 0xb3000, 0x1000, 32 | 16 | 8 }, /* L4TA39 */
2489 };
2490
2491 static struct omap_l4_agent_info_s {
2492 int ta;
2493 int region;
2494 int regions;
2495 int ta_region;
2496 } omap_l4_agent_info[54] = {
2497 { 0, 0, 3, 2 }, /* L4IA initiatior agent */
2498 { L4TAO(1), 3, 2, 1 }, /* Control and pinout module */
2499 { L4TAO(2), 5, 2, 1 }, /* 32K timer */
2500 { L4TAO(3), 7, 3, 2 }, /* PRCM */
2501 { L4TA(1), 10, 2, 1 }, /* BCM */
2502 { L4TA(2), 12, 2, 1 }, /* Test JTAG */
2503 { L4TA(3), 14, 6, 3 }, /* Quad GPIO */
2504 { L4TA(4), 20, 4, 3 }, /* WD timer 1/2 */
2505 { L4TA(7), 24, 2, 1 }, /* GP timer 1 */
2506 { L4TA(9), 26, 2, 1 }, /* ATM11 ETB */
2507 { L4TA(10), 28, 5, 4 }, /* Display subsystem */
2508 { L4TA(11), 33, 5, 4 }, /* Camera subsystem */
2509 { L4TA(12), 38, 2, 1 }, /* sDMA */
2510 { L4TA(13), 40, 5, 4 }, /* SSI */
2511 { L4TAO(4), 45, 2, 1 }, /* USB */
2512 { L4TA(14), 47, 2, 1 }, /* Win Tracer1 */
2513 { L4TA(15), 49, 2, 1 }, /* Win Tracer2 */
2514 { L4TA(16), 51, 2, 1 }, /* Win Tracer3 */
2515 { L4TA(17), 53, 2, 1 }, /* Win Tracer4 */
2516 { L4TA(18), 55, 2, 1 }, /* XTI */
2517 { L4TA(19), 57, 2, 1 }, /* UART1 */
2518 { L4TA(20), 59, 2, 1 }, /* UART2 */
2519 { L4TA(21), 61, 2, 1 }, /* UART3 */
2520 { L4TAO(5), 63, 2, 1 }, /* I2C1 */
2521 { L4TAO(6), 65, 2, 1 }, /* I2C2 */
2522 { L4TAO(7), 67, 2, 1 }, /* McBSP1 */
2523 { L4TAO(8), 69, 2, 1 }, /* McBSP2 */
2524 { L4TA(5), 71, 2, 1 }, /* WD Timer 3 (DSP) */
2525 { L4TA(6), 73, 2, 1 }, /* WD Timer 4 (IVA) */
2526 { L4TA(8), 75, 2, 1 }, /* GP Timer 2 */
2527 { L4TA(22), 77, 2, 1 }, /* GP Timer 3 */
2528 { L4TA(23), 79, 2, 1 }, /* GP Timer 4 */
2529 { L4TA(24), 81, 2, 1 }, /* GP Timer 5 */
2530 { L4TA(25), 83, 2, 1 }, /* GP Timer 6 */
2531 { L4TA(26), 85, 2, 1 }, /* GP Timer 7 */
2532 { L4TA(27), 87, 2, 1 }, /* GP Timer 8 */
2533 { L4TA(28), 89, 2, 1 }, /* GP Timer 9 */
2534 { L4TA(29), 91, 2, 1 }, /* GP Timer 10 */
2535 { L4TA(30), 93, 2, 1 }, /* GP Timer 11 */
2536 { L4TA(31), 95, 2, 1 }, /* GP Timer 12 */
2537 { L4TA(32), 97, 2, 1 }, /* EAC */
2538 { L4TA(33), 99, 2, 1 }, /* FAC */
2539 { L4TA(34), 101, 2, 1 }, /* IPC */
2540 { L4TA(35), 103, 2, 1 }, /* SPI1 */
2541 { L4TA(36), 105, 2, 1 }, /* SPI2 */
2542 { L4TAO(9), 107, 2, 1 }, /* MMC SDIO */
2543 { L4TAO(10), 109, 2, 1 },
2544 { L4TAO(11), 111, 2, 1 }, /* RNG */
2545 { L4TAO(12), 113, 2, 1 }, /* DES3DES */
2546 { L4TAO(13), 115, 2, 1 }, /* SHA1MD5 */
2547 { L4TA(37), 117, 2, 1 }, /* AES */
2548 { L4TA(38), 119, 2, 1 }, /* PKA */
2549 { -1, 121, 2, 1 },
2550 { L4TA(39), 123, 2, 1 }, /* HDQ/1-Wire */
2551 };
2552
2553 #define omap_l4ta(bus, cs) omap_l4ta_get(bus, L4TA(cs))
2554 #define omap_l4tao(bus, cs) omap_l4ta_get(bus, L4TAO(cs))
2555
2556 struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs)
2557 {
2558 int i, iomemtype;
2559 struct omap_target_agent_s *ta = 0;
2560 struct omap_l4_agent_info_s *info = 0;
2561
2562 for (i = 0; i < bus->ta_num; i ++)
2563 if (omap_l4_agent_info[i].ta == cs) {
2564 ta = &bus->ta[i];
2565 info = &omap_l4_agent_info[i];
2566 break;
2567 }
2568 if (!ta) {
2569 fprintf(stderr, "%s: bad target agent (%i)\n", __FUNCTION__, cs);
2570 exit(-1);
2571 }
2572
2573 ta->bus = bus;
2574 ta->start = &omap_l4_region[info->region];
2575 ta->regions = info->regions;
2576
2577 ta->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
2578 ta->status = 0x00000000;
2579 ta->control = 0x00000200; /* XXX 01000200 for L4TAO */
2580
2581 iomemtype = l4_register_io_memory(0, omap_l4ta_readfn,
2582 omap_l4ta_writefn, ta);
2583 ta->base = omap_l4_attach(ta, info->ta_region, iomemtype);
2584
2585 return ta;
2586 }
2587
2588 target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
2589 int iotype)
2590 {
2591 target_phys_addr_t base;
2592 ssize_t size;
2593 #ifdef L4_MUX_HACK
2594 int i;
2595 #endif
2596
2597 if (region < 0 || region >= ta->regions) {
2598 fprintf(stderr, "%s: bad io region (%i)\n", __FUNCTION__, region);
2599 exit(-1);
2600 }
2601
2602 base = ta->bus->base + ta->start[region].offset;
2603 size = ta->start[region].size;
2604 if (iotype) {
2605 #ifndef L4_MUX_HACK
2606 cpu_register_physical_memory(base, size, iotype);
2607 #else
2608 cpu_register_physical_memory(base, size, omap_cpu_io_entry);
2609 i = (base - ta->bus->base) / TARGET_PAGE_SIZE;
2610 for (; size > 0; size -= TARGET_PAGE_SIZE, i ++) {
2611 omap_l4_io_readb_fn[i] = omap_l4_io_entry[iotype].mem_read[0];
2612 omap_l4_io_readh_fn[i] = omap_l4_io_entry[iotype].mem_read[1];
2613 omap_l4_io_readw_fn[i] = omap_l4_io_entry[iotype].mem_read[2];
2614 omap_l4_io_writeb_fn[i] = omap_l4_io_entry[iotype].mem_write[0];
2615 omap_l4_io_writeh_fn[i] = omap_l4_io_entry[iotype].mem_write[1];
2616 omap_l4_io_writew_fn[i] = omap_l4_io_entry[iotype].mem_write[2];
2617 omap_l4_io_opaque[i] = omap_l4_io_entry[iotype].opaque;
2618 }
2619 #endif
2620 }
2621
2622 return base;
2623 }
2624
2625 /* TEST-Chip-level TAP */
2626 static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr)
2627 {
2628 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2629
2630 switch (addr) {
2631 case 0x204: /* IDCODE_reg */
2632 switch (s->mpu_model) {
2633 case omap2420:
2634 case omap2422:
2635 case omap2423:
2636 return 0x5b5d902f; /* ES 2.2 */
2637 case omap2430:
2638 return 0x5b68a02f; /* ES 2.2 */
2639 case omap3430:
2640 return 0x1b7ae02f; /* ES 2 */
2641 default:
2642 hw_error("%s: Bad mpu model\n", __FUNCTION__);
2643 }
2644
2645 case 0x208: /* PRODUCTION_ID_reg for OMAP2 */
2646 case 0x210: /* PRODUCTION_ID_reg for OMAP3 */
2647 switch (s->mpu_model) {
2648 case omap2420:
2649 return 0x000254f0; /* POP ESHS2.1.1 in N91/93/95, ES2 in N800 */
2650 case omap2422:
2651 return 0x000400f0;
2652 case omap2423:
2653 return 0x000800f0;
2654 case omap2430:
2655 return 0x000000f0;
2656 case omap3430:
2657 return 0x000000f0;
2658 default:
2659 hw_error("%s: Bad mpu model\n", __FUNCTION__);
2660 }
2661
2662 case 0x20c:
2663 switch (s->mpu_model) {
2664 case omap2420:
2665 case omap2422:
2666 case omap2423:
2667 return 0xcafeb5d9; /* ES 2.2 */
2668 case omap2430:
2669 return 0xcafeb68a; /* ES 2.2 */
2670 case omap3430:
2671 return 0xcafeb7ae; /* ES 2 */
2672 default:
2673 hw_error("%s: Bad mpu model\n", __FUNCTION__);
2674 }
2675
2676 case 0x218: /* DIE_ID_reg */
2677 return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
2678 case 0x21c: /* DIE_ID_reg */
2679 return 0x54 << 24;
2680 case 0x220: /* DIE_ID_reg */
2681 return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
2682 case 0x224: /* DIE_ID_reg */
2683 return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
2684 }
2685
2686 OMAP_BAD_REG(addr);
2687 return 0;
2688 }
2689
2690 static void omap_tap_write(void *opaque, target_phys_addr_t addr,
2691 uint32_t value)
2692 {
2693 OMAP_BAD_REG(addr);
2694 }
2695
2696 static CPUReadMemoryFunc *omap_tap_readfn[] = {
2697 omap_badwidth_read32,
2698 omap_badwidth_read32,
2699 omap_tap_read,
2700 };
2701
2702 static CPUWriteMemoryFunc *omap_tap_writefn[] = {
2703 omap_badwidth_write32,
2704 omap_badwidth_write32,
2705 omap_tap_write,
2706 };
2707
2708 void omap_tap_init(struct omap_target_agent_s *ta,
2709 struct omap_mpu_state_s *mpu)
2710 {
2711 omap_l4_attach(ta, 0, l4_register_io_memory(0,
2712 omap_tap_readfn, omap_tap_writefn, mpu));
2713 }
2714
2715 /* Power, Reset, and Clock Management */
2716 struct omap_prcm_s {
2717 qemu_irq irq[3];
2718 struct omap_mpu_state_s *mpu;
2719
2720 uint32_t irqst[3];
2721 uint32_t irqen[3];
2722
2723 uint32_t sysconfig;
2724 uint32_t voltctrl;
2725 uint32_t scratch[20];
2726
2727 uint32_t clksrc[1];
2728 uint32_t clkout[1];
2729 uint32_t clkemul[1];
2730 uint32_t clkpol[1];
2731 uint32_t clksel[8];
2732 uint32_t clken[12];
2733 uint32_t clkctrl[4];
2734 uint32_t clkidle[7];
2735 uint32_t setuptime[2];
2736
2737 uint32_t wkup[3];
2738 uint32_t wken[3];
2739 uint32_t wkst[3];
2740 uint32_t rst[4];
2741 uint32_t rstctrl[1];
2742 uint32_t power[4];
2743 uint32_t rsttime_wkup;
2744
2745 uint32_t ev;
2746 uint32_t evtime[2];
2747
2748 int dpll_lock, apll_lock[2];
2749 };
2750
2751 static void omap_prcm_int_update(struct omap_prcm_s *s, int dom)
2752 {
2753 qemu_set_irq(s->irq[dom], s->irqst[dom] & s->irqen[dom]);
2754 /* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
2755 }
2756
2757 static uint32_t omap_prcm_read(void *opaque, target_phys_addr_t addr)
2758 {
2759 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
2760 uint32_t ret;
2761
2762 switch (addr) {
2763 case 0x000: /* PRCM_REVISION */
2764 return 0x10;
2765
2766 case 0x010: /* PRCM_SYSCONFIG */
2767 return s->sysconfig;
2768
2769 case 0x018: /* PRCM_IRQSTATUS_MPU */
2770 return s->irqst[0];
2771
2772 case 0x01c: /* PRCM_IRQENABLE_MPU */
2773 return s->irqen[0];
2774
2775 case 0x050: /* PRCM_VOLTCTRL */
2776 return s->voltctrl;
2777 case 0x054: /* PRCM_VOLTST */
2778 return s->voltctrl & 3;
2779
2780 case 0x060: /* PRCM_CLKSRC_CTRL */
2781 return s->clksrc[0];
2782 case 0x070: /* PRCM_CLKOUT_CTRL */
2783 return s->clkout[0];
2784 case 0x078: /* PRCM_CLKEMUL_CTRL */
2785 return s->clkemul[0];
2786 case 0x080: /* PRCM_CLKCFG_CTRL */
2787 case 0x084: /* PRCM_CLKCFG_STATUS */
2788 return 0;
2789
2790 case 0x090: /* PRCM_VOLTSETUP */
2791 return s->setuptime[0];
2792
2793 case 0x094: /* PRCM_CLKSSETUP */
2794 return s->setuptime[1];
2795
2796 case 0x098: /* PRCM_POLCTRL */
2797 return s->clkpol[0];
2798
2799 case 0x0b0: /* GENERAL_PURPOSE1 */
2800 case 0x0b4: /* GENERAL_PURPOSE2 */
2801 case 0x0b8: /* GENERAL_PURPOSE3 */
2802 case 0x0bc: /* GENERAL_PURPOSE4 */
2803 case 0x0c0: /* GENERAL_PURPOSE5 */
2804 case 0x0c4: /* GENERAL_PURPOSE6 */
2805 case 0x0c8: /* GENERAL_PURPOSE7 */
2806 case 0x0cc: /* GENERAL_PURPOSE8 */
2807 case 0x0d0: /* GENERAL_PURPOSE9 */
2808 case 0x0d4: /* GENERAL_PURPOSE10 */
2809 case 0x0d8: /* GENERAL_PURPOSE11 */
2810 case 0x0dc: /* GENERAL_PURPOSE12 */
2811 case 0x0e0: /* GENERAL_PURPOSE13 */
2812 case 0x0e4: /* GENERAL_PURPOSE14 */
2813 case 0x0e8: /* GENERAL_PURPOSE15 */
2814 case 0x0ec: /* GENERAL_PURPOSE16 */
2815 case 0x0f0: /* GENERAL_PURPOSE17 */
2816 case 0x0f4: /* GENERAL_PURPOSE18 */
2817 case 0x0f8: /* GENERAL_PURPOSE19 */
2818 case 0x0fc: /* GENERAL_PURPOSE20 */
2819 return s->scratch[(addr - 0xb0) >> 2];
2820
2821 case 0x140: /* CM_CLKSEL_MPU */
2822 return s->clksel[0];
2823 case 0x148: /* CM_CLKSTCTRL_MPU */
2824 return s->clkctrl[0];
2825
2826 case 0x158: /* RM_RSTST_MPU */
2827 return s->rst[0];
2828 case 0x1c8: /* PM_WKDEP_MPU */
2829 return s->wkup[0];
2830 case 0x1d4: /* PM_EVGENCTRL_MPU */
2831 return s->ev;
2832 case 0x1d8: /* PM_EVEGENONTIM_MPU */
2833 return s->evtime[0];
2834 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
2835 return s->evtime[1];
2836 case 0x1e0: /* PM_PWSTCTRL_MPU */
2837 return s->power[0];
2838 case 0x1e4: /* PM_PWSTST_MPU */
2839 return 0;
2840
2841 case 0x200: /* CM_FCLKEN1_CORE */
2842 return s->clken[0];
2843 case 0x204: /* CM_FCLKEN2_CORE */
2844 return s->clken[1];
2845 case 0x210: /* CM_ICLKEN1_CORE */
2846 return s->clken[2];
2847 case 0x214: /* CM_ICLKEN2_CORE */
2848 return s->clken[3];
2849 case 0x21c: /* CM_ICLKEN4_CORE */
2850 return s->clken[4];
2851
2852 case 0x220: /* CM_IDLEST1_CORE */
2853 /* TODO: check the actual iclk status */
2854 return 0x7ffffff9;
2855 case 0x224: /* CM_IDLEST2_CORE */
2856 /* TODO: check the actual iclk status */
2857 return 0x00000007;
2858 case 0x22c: /* CM_IDLEST4_CORE */
2859 /* TODO: check the actual iclk status */
2860 return 0x0000001f;
2861
2862 case 0x230: /* CM_AUTOIDLE1_CORE */
2863 return s->clkidle[0];
2864 case 0x234: /* CM_AUTOIDLE2_CORE */
2865 return s->clkidle[1];
2866 case 0x238: /* CM_AUTOIDLE3_CORE */
2867 return s->clkidle[2];
2868 case 0x23c: /* CM_AUTOIDLE4_CORE */
2869 return s->clkidle[3];
2870
2871 case 0x240: /* CM_CLKSEL1_CORE */
2872 return s->clksel[1];
2873 case 0x244: /* CM_CLKSEL2_CORE */
2874 return s->clksel[2];
2875
2876 case 0x248: /* CM_CLKSTCTRL_CORE */
2877 return s->clkctrl[1];
2878
2879 case 0x2a0: /* PM_WKEN1_CORE */
2880 return s->wken[0];
2881 case 0x2a4: /* PM_WKEN2_CORE */
2882 return s->wken[1];
2883
2884 case 0x2b0: /* PM_WKST1_CORE */
2885 return s->wkst[0];
2886 case 0x2b4: /* PM_WKST2_CORE */
2887 return s->wkst[1];
2888 case 0x2c8: /* PM_WKDEP_CORE */
2889 return 0x1e;
2890
2891 case 0x2e0: /* PM_PWSTCTRL_CORE */
2892 return s->power[1];
2893 case 0x2e4: /* PM_PWSTST_CORE */
2894 return 0x000030 | (s->power[1] & 0xfc00);
2895
2896 case 0x300: /* CM_FCLKEN_GFX */
2897 return s->clken[5];
2898 case 0x310: /* CM_ICLKEN_GFX */
2899 return s->clken[6];
2900 case 0x320: /* CM_IDLEST_GFX */
2901 /* TODO: check the actual iclk status */
2902 return 0x00000001;
2903 case 0x340: /* CM_CLKSEL_GFX */
2904 return s->clksel[3];
2905 case 0x348: /* CM_CLKSTCTRL_GFX */
2906 return s->clkctrl[2];
2907 case 0x350: /* RM_RSTCTRL_GFX */
2908 return s->rstctrl[0];
2909 case 0x358: /* RM_RSTST_GFX */
2910 return s->rst[1];
2911 case 0x3c8: /* PM_WKDEP_GFX */
2912 return s->wkup[1];
2913
2914 case 0x3e0: /* PM_PWSTCTRL_GFX */
2915 return s->power[2];
2916 case 0x3e4: /* PM_PWSTST_GFX */
2917 return s->power[2] & 3;
2918
2919 case 0x400: /* CM_FCLKEN_WKUP */
2920 return s->clken[7];
2921 case 0x410: /* CM_ICLKEN_WKUP */
2922 return s->clken[8];
2923 case 0x420: /* CM_IDLEST_WKUP */
2924 /* TODO: check the actual iclk status */
2925 return 0x0000003f;
2926 case 0x430: /* CM_AUTOIDLE_WKUP */
2927 return s->clkidle[4];
2928 case 0x440: /* CM_CLKSEL_WKUP */
2929 return s->clksel[4];
2930 case 0x450: /* RM_RSTCTRL_WKUP */
2931 return 0;
2932 case 0x454: /* RM_RSTTIME_WKUP */
2933 return s->rsttime_wkup;
2934 case 0x458: /* RM_RSTST_WKUP */
2935 return s->rst[2];
2936 case 0x4a0: /* PM_WKEN_WKUP */
2937 return s->wken[2];
2938 case 0x4b0: /* PM_WKST_WKUP */
2939 return s->wkst[2];
2940
2941 case 0x500: /* CM_CLKEN_PLL */
2942 return s->clken[9];
2943 case 0x520: /* CM_IDLEST_CKGEN */
2944 ret = 0x0000070 | (s->apll_lock[0] << 9) | (s->apll_lock[1] << 8);
2945 if (!(s->clksel[6] & 3))
2946 /* Core uses 32-kHz clock */
2947 ret |= 3 << 0;
2948 else if (!s->dpll_lock)
2949 /* DPLL not locked, core uses ref_clk */
2950 ret |= 1 << 0;
2951 else
2952 /* Core uses DPLL */
2953 ret |= 2 << 0;
2954 return ret;
2955 case 0x530: /* CM_AUTOIDLE_PLL */
2956 return s->clkidle[5];
2957 case 0x540: /* CM_CLKSEL1_PLL */
2958 return s->clksel[5];
2959 case 0x544: /* CM_CLKSEL2_PLL */
2960 return s->clksel[6];
2961
2962 case 0x800: /* CM_FCLKEN_DSP */
2963 return s->clken[10];
2964 case 0x810: /* CM_ICLKEN_DSP */
2965 return s->clken[11];
2966 case 0x820: /* CM_IDLEST_DSP */
2967 /* TODO: check the actual iclk status */
2968 return 0x00000103;
2969 case 0x830: /* CM_AUTOIDLE_DSP */
2970 return s->clkidle[6];
2971 case 0x840: /* CM_CLKSEL_DSP */
2972 return s->clksel[7];
2973 case 0x848: /* CM_CLKSTCTRL_DSP */
2974 return s->clkctrl[3];
2975 case 0x850: /* RM_RSTCTRL_DSP */
2976 return 0;
2977 case 0x858: /* RM_RSTST_DSP */
2978 return s->rst[3];
2979 case 0x8c8: /* PM_WKDEP_DSP */
2980 return s->wkup[2];
2981 case 0x8e0: /* PM_PWSTCTRL_DSP */
2982 return s->power[3];
2983 case 0x8e4: /* PM_PWSTST_DSP */
2984 return 0x008030 | (s->power[3] & 0x3003);
2985
2986 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
2987 return s->irqst[1];
2988 case 0x8f4: /* PRCM_IRQENABLE_DSP */
2989 return s->irqen[1];
2990
2991 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
2992 return s->irqst[2];
2993 case 0x8fc: /* PRCM_IRQENABLE_IVA */
2994 return s->irqen[2];
2995 }
2996
2997 OMAP_BAD_REG(addr);
2998 return 0;
2999 }
3000
3001 static void omap_prcm_apll_update(struct omap_prcm_s *s)
3002 {
3003 int mode[2];
3004
3005 mode[0] = (s->clken[9] >> 6) & 3;
3006 s->apll_lock[0] = (mode[0] == 3);
3007 mode[1] = (s->clken[9] >> 2) & 3;
3008 s->apll_lock[1] = (mode[1] == 3);
3009 /* TODO: update clocks */
3010
3011 if (mode[0] == 1 || mode[0] == 2 || mode[1] == 1 || mode[2] == 2)
3012 fprintf(stderr, "%s: bad EN_54M_PLL or bad EN_96M_PLL\n",
3013 __FUNCTION__);
3014 }
3015
3016 static void omap_prcm_dpll_update(struct omap_prcm_s *s)
3017 {
3018 omap_clk dpll = omap_findclk(s->mpu, "dpll");
3019 omap_clk dpll_x2 = omap_findclk(s->mpu, "dpll");
3020 omap_clk core = omap_findclk(s->mpu, "core_clk");
3021 int mode = (s->clken[9] >> 0) & 3;
3022 int mult, div;
3023
3024 mult = (s->clksel[5] >> 12) & 0x3ff;
3025 div = (s->clksel[5] >> 8) & 0xf;
3026 if (mult == 0 || mult == 1)
3027 mode = 1; /* Bypass */
3028
3029 s->dpll_lock = 0;
3030 switch (mode) {
3031 case 0:
3032 fprintf(stderr, "%s: bad EN_DPLL\n", __FUNCTION__);
3033 break;
3034 case 1: /* Low-power bypass mode (Default) */
3035 case 2: /* Fast-relock bypass mode */
3036 omap_clk_setrate(dpll, 1, 1);
3037 omap_clk_setrate(dpll_x2, 1, 1);
3038 break;
3039 case 3: /* Lock mode */
3040 s->dpll_lock = 1; /* After 20 FINT cycles (ref_clk / (div + 1)). */
3041
3042 omap_clk_setrate(dpll, div + 1, mult);
3043 omap_clk_setrate(dpll_x2, div + 1, mult * 2);
3044 break;
3045 }
3046
3047 switch ((s->clksel[6] >> 0) & 3) {
3048 case 0:
3049 omap_clk_reparent(core, omap_findclk(s->mpu, "clk32-kHz"));
3050 break;
3051 case 1:
3052 omap_clk_reparent(core, dpll);
3053 break;
3054 case 2:
3055 /* Default */
3056 omap_clk_reparent(core, dpll_x2);
3057 break;
3058 case 3:
3059 fprintf(stderr, "%s: bad CORE_CLK_SRC\n", __FUNCTION__);
3060 break;
3061 }
3062 }
3063
3064 static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
3065 uint32_t value)
3066 {
3067 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
3068
3069 switch (addr) {
3070 case 0x000: /* PRCM_REVISION */
3071 case 0x054: /* PRCM_VOLTST */
3072 case 0x084: /* PRCM_CLKCFG_STATUS */
3073 case 0x1e4: /* PM_PWSTST_MPU */
3074 case 0x220: /* CM_IDLEST1_CORE */
3075 case 0x224: /* CM_IDLEST2_CORE */
3076 case 0x22c: /* CM_IDLEST4_CORE */
3077 case 0x2c8: /* PM_WKDEP_CORE */
3078 case 0x2e4: /* PM_PWSTST_CORE */
3079 case 0x320: /* CM_IDLEST_GFX */
3080 case 0x3e4: /* PM_PWSTST_GFX */
3081 case 0x420: /* CM_IDLEST_WKUP */
3082 case 0x520: /* CM_IDLEST_CKGEN */
3083 case 0x820: /* CM_IDLEST_DSP */
3084 case 0x8e4: /* PM_PWSTST_DSP */
3085 OMAP_RO_REG(addr);
3086 return;
3087
3088 case 0x010: /* PRCM_SYSCONFIG */
3089 s->sysconfig = value & 1;
3090 break;
3091
3092 case 0x018: /* PRCM_IRQSTATUS_MPU */
3093 s->irqst[0] &= ~value;
3094 omap_prcm_int_update(s, 0);
3095 break;
3096 case 0x01c: /* PRCM_IRQENABLE_MPU */
3097 s->irqen[0] = value & 0x3f;
3098 omap_prcm_int_update(s, 0);
3099 break;
3100
3101 case 0x050: /* PRCM_VOLTCTRL */
3102 s->voltctrl = value & 0xf1c3;
3103 break;
3104
3105 case 0x060: /* PRCM_CLKSRC_CTRL */
3106 s->clksrc[0] = value & 0xdb;
3107 /* TODO update clocks */
3108 break;
3109
3110 case 0x070: /* PRCM_CLKOUT_CTRL */
3111 s->clkout[0] = value & 0xbbbb;
3112 /* TODO update clocks */
3113 break;
3114
3115 case 0x078: /* PRCM_CLKEMUL_CTRL */
3116 s->clkemul[0] = value & 1;
3117 /* TODO update clocks */
3118 break;
3119
3120 case 0x080: /* PRCM_CLKCFG_CTRL */
3121 break;
3122
3123 case 0x090: /* PRCM_VOLTSETUP */
3124 s->setuptime[0] = value & 0xffff;
3125 break;
3126 case 0x094: /* PRCM_CLKSSETUP */
3127 s->setuptime[1] = value & 0xffff;
3128 break;
3129
3130 case 0x098: /* PRCM_POLCTRL */
3131 s->clkpol[0] = value & 0x701;
3132 break;
3133
3134 case 0x0b0: /* GENERAL_PURPOSE1 */
3135 case 0x0b4: /* GENERAL_PURPOSE2 */
3136 case 0x0b8: /* GENERAL_PURPOSE3 */
3137 case 0x0bc: /* GENERAL_PURPOSE4 */
3138 case 0x0c0: /* GENERAL_PURPOSE5 */
3139 case 0x0c4: /* GENERAL_PURPOSE6 */
3140 case 0x0c8: /* GENERAL_PURPOSE7 */
3141 case 0x0cc: /* GENERAL_PURPOSE8 */
3142 case 0x0d0: /* GENERAL_PURPOSE9 */
3143 case 0x0d4: /* GENERAL_PURPOSE10 */
3144 case 0x0d8: /* GENERAL_PURPOSE11 */
3145 case 0x0dc: /* GENERAL_PURPOSE12 */
3146 case 0x0e0: /* GENERAL_PURPOSE13 */
3147 case 0x0e4: /* GENERAL_PURPOSE14 */
3148 case 0x0e8: /* GENERAL_PURPOSE15 */
3149 case 0x0ec: /* GENERAL_PURPOSE16 */
3150 case 0x0f0: /* GENERAL_PURPOSE17 */
3151 case 0x0f4: /* GENERAL_PURPOSE18 */
3152 case 0x0f8: /* GENERAL_PURPOSE19 */
3153 case 0x0fc: /* GENERAL_PURPOSE20 */
3154 s->scratch[(addr - 0xb0) >> 2] = value;
3155 break;
3156
3157 case 0x140: /* CM_CLKSEL_MPU */
3158 s->clksel[0] = value & 0x1f;
3159 /* TODO update clocks */
3160 break;
3161 case 0x148: /* CM_CLKSTCTRL_MPU */
3162 s->clkctrl[0] = value & 0x1f;
3163 break;
3164
3165 case 0x158: /* RM_RSTST_MPU */
3166 s->rst[0] &= ~value;
3167 break;
3168 case 0x1c8: /* PM_WKDEP_MPU */
3169 s->wkup[0] = value & 0x15;
3170 break;
3171
3172 case 0x1d4: /* PM_EVGENCTRL_MPU */
3173 s->ev = value & 0x1f;
3174 break;
3175 case 0x1d8: /* PM_EVEGENONTIM_MPU */
3176 s->evtime[0] = value;
3177 break;
3178 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
3179 s->evtime[1] = value;
3180 break;
3181
3182 case 0x1e0: /* PM_PWSTCTRL_MPU */
3183 s->power[0] = value & 0xc0f;
3184 break;
3185
3186 case 0x200: /* CM_FCLKEN1_CORE */
3187 s->clken[0] = value & 0xbfffffff;
3188 /* TODO update clocks */
3189 /* The EN_EAC bit only gets/puts func_96m_clk. */
3190 break;
3191 case 0x204: /* CM_FCLKEN2_CORE */
3192 s->clken[1] = value & 0x00000007;
3193 /* TODO update clocks */
3194 break;
3195 case 0x210: /* CM_ICLKEN1_CORE */
3196 s->clken[2] = value & 0xfffffff9;
3197 /* TODO update clocks */
3198 /* The EN_EAC bit only gets/puts core_l4_iclk. */
3199 break;
3200 case 0x214: /* CM_ICLKEN2_CORE */
3201 s->clken[3] = value & 0x00000007;
3202 /* TODO update clocks */
3203 break;
3204 case 0x21c: /* CM_ICLKEN4_CORE */
3205 s->clken[4] = value & 0x0000001f;
3206 /* TODO update clocks */
3207 break;
3208
3209 case 0x230: /* CM_AUTOIDLE1_CORE */
3210 s->clkidle[0] = value & 0xfffffff9;
3211 /* TODO update clocks */
3212 break;
3213 case 0x234: /* CM_AUTOIDLE2_CORE */
3214 s->clkidle[1] = value & 0x00000007;
3215 /* TODO update clocks */
3216 break;
3217 case 0x238: /* CM_AUTOIDLE3_CORE */
3218 s->clkidle[2] = value & 0x00000007;
3219 /* TODO update clocks */
3220 break;
3221 case 0x23c: /* CM_AUTOIDLE4_CORE */
3222 s->clkidle[3] = value & 0x0000001f;
3223 /* TODO update clocks */
3224 break;
3225
3226 case 0x240: /* CM_CLKSEL1_CORE */
3227 s->clksel[1] = value & 0x0fffbf7f;
3228 /* TODO update clocks */
3229 break;
3230
3231 case 0x244: /* CM_CLKSEL2_CORE */
3232 s->clksel[2] = value & 0x00fffffc;
3233 /* TODO update clocks */
3234 break;
3235
3236 case 0x248: /* CM_CLKSTCTRL_CORE */
3237 s->clkctrl[1] = value & 0x7;
3238 break;
3239
3240 case 0x2a0: /* PM_WKEN1_CORE */
3241 s->wken[0] = value & 0x04667ff8;
3242 break;
3243 case 0x2a4: /* PM_WKEN2_CORE */
3244 s->wken[1] = value & 0x00000005;
3245 break;
3246
3247 case 0x2b0: /* PM_WKST1_CORE */
3248 s->wkst[0] &= ~value;
3249 break;
3250 case 0x2b4: /* PM_WKST2_CORE */
3251 s->wkst[1] &= ~value;
3252 break;
3253
3254 case 0x2e0: /* PM_PWSTCTRL_CORE */
3255 s->power[1] = (value & 0x00fc3f) | (1 << 2);
3256 break;
3257
3258 case 0x300: /* CM_FCLKEN_GFX */
3259 s->clken[5] = value & 6;
3260 /* TODO update clocks */
3261 break;
3262 case 0x310: /* CM_ICLKEN_GFX */
3263 s->clken[6] = value & 1;
3264 /* TODO update clocks */
3265 break;
3266 case 0x340: /* CM_CLKSEL_GFX */
3267 s->clksel[3] = value & 7;
3268 /* TODO update clocks */
3269 break;
3270 case 0x348: /* CM_CLKSTCTRL_GFX */
3271 s->clkctrl[2] = value & 1;
3272 break;
3273 case 0x350: /* RM_RSTCTRL_GFX */
3274 s->rstctrl[0] = value & 1;
3275 /* TODO: reset */
3276 break;
3277 case 0x358: /* RM_RSTST_GFX */
3278 s->rst[1] &= ~value;
3279 break;
3280 case 0x3c8: /* PM_WKDEP_GFX */
3281 s->wkup[1] = value & 0x13;
3282 break;
3283 case 0x3e0: /* PM_PWSTCTRL_GFX */
3284 s->power[2] = (value & 0x00c0f) | (3 << 2);
3285 break;
3286
3287 case 0x400: /* CM_FCLKEN_WKUP */
3288 s->clken[7] = value & 0xd;
3289 /* TODO update clocks */
3290 break;
3291 case 0x410: /* CM_ICLKEN_WKUP */
3292 s->clken[8] = value & 0x3f;
3293 /* TODO update clocks */
3294 break;
3295 case 0x430: /* CM_AUTOIDLE_WKUP */
3296 s->clkidle[4] = value & 0x0000003f;
3297 /* TODO update clocks */
3298 break;
3299 case 0x440: /* CM_CLKSEL_WKUP */
3300 s->clksel[4] = value & 3;
3301 /* TODO update clocks */
3302 break;
3303 case 0x450: /* RM_RSTCTRL_WKUP */
3304 /* TODO: reset */
3305 if (value & 2)
3306 qemu_system_reset_request();
3307 break;
3308 case 0x454: /* RM_RSTTIME_WKUP */
3309 s->rsttime_wkup = value & 0x1fff;
3310 break;
3311 case 0x458: /* RM_RSTST_WKUP */
3312 s->rst[2] &= ~value;
3313 break;
3314 case 0x4a0: /* PM_WKEN_WKUP */
3315 s->wken[2] = value & 0x00000005;
3316 break;
3317 case 0x4b0: /* PM_WKST_WKUP */
3318 s->wkst[2] &= ~value;
3319 break;
3320
3321 case 0x500: /* CM_CLKEN_PLL */
3322 if (value & 0xffffff30)
3323 fprintf(stderr, "%s: write 0s in CM_CLKEN_PLL for "
3324 "future compatiblity\n", __FUNCTION__);
3325 if ((s->clken[9] ^ value) & 0xcc) {
3326 s->clken[9] &= ~0xcc;
3327 s->clken[9] |= value & 0xcc;
3328 omap_prcm_apll_update(s);
3329 }
3330 if ((s->clken[9] ^ value) & 3) {
3331 s->clken[9] &= ~3;
3332 s->clken[9] |= value & 3;
3333 omap_prcm_dpll_update(s);
3334 }
3335 break;
3336 case 0x530: /* CM_AUTOIDLE_PLL */
3337 s->clkidle[5] = value & 0x000000cf;
3338 /* TODO update clocks */
3339 break;
3340 case 0x540: /* CM_CLKSEL1_PLL */
3341 if (value & 0xfc4000d7)
3342 fprintf(stderr, "%s: write 0s in CM_CLKSEL1_PLL for "
3343 "future compatiblity\n", __FUNCTION__);
3344 if ((s->clksel[5] ^ value) & 0x003fff00) {
3345 s->clksel[5] = value & 0x03bfff28;
3346 omap_prcm_dpll_update(s);
3347 }
3348 /* TODO update the other clocks */
3349
3350 s->clksel[5] = value & 0x03bfff28;
3351 break;
3352 case 0x544: /* CM_CLKSEL2_PLL */
3353 if (value & ~3)
3354 fprintf(stderr, "%s: write 0s in CM_CLKSEL2_PLL[31:2] for "
3355 "future compatiblity\n", __FUNCTION__);
3356 if (s->clksel[6] != (value & 3)) {
3357 s->clksel[6] = value & 3;
3358 omap_prcm_dpll_update(s);
3359 }
3360 break;
3361
3362 case 0x800: /* CM_FCLKEN_DSP */
3363 s->clken[10] = value & 0x501;
3364 /* TODO update clocks */
3365 break;
3366 case 0x810: /* CM_ICLKEN_DSP */
3367 s->clken[11] = value & 0x2;
3368 /* TODO update clocks */
3369 break;
3370 case 0x830: /* CM_AUTOIDLE_DSP */
3371 s->clkidle[6] = value & 0x2;
3372 /* TODO update clocks */
3373 break;
3374 case 0x840: /* CM_CLKSEL_DSP */
3375 s->clksel[7] = value & 0x3fff;
3376 /* TODO update clocks */
3377 break;
3378 case 0x848: /* CM_CLKSTCTRL_DSP */
3379 s->clkctrl[3] = value & 0x101;
3380 break;
3381 case 0x850: /* RM_RSTCTRL_DSP */
3382 /* TODO: reset */
3383 break;
3384 case 0x858: /* RM_RSTST_DSP */
3385 s->rst[3] &= ~value;
3386 break;
3387 case 0x8c8: /* PM_WKDEP_DSP */
3388 s->wkup[2] = value & 0x13;
3389 break;
3390 case 0x8e0: /* PM_PWSTCTRL_DSP */
3391 s->power[3] = (value & 0x03017) | (3 << 2);
3392 break;
3393
3394 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
3395 s->irqst[1] &= ~value;
3396 omap_prcm_int_update(s, 1);
3397 break;
3398 case 0x8f4: /* PRCM_IRQENABLE_DSP */
3399 s->irqen[1] = value & 0x7;
3400 omap_prcm_int_update(s, 1);
3401 break;
3402
3403 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
3404 s->irqst[2] &= ~value;
3405 omap_prcm_int_update(s, 2);
3406 break;
3407 case 0x8fc: /* PRCM_IRQENABLE_IVA */
3408 s->irqen[2] = value & 0x7;
3409 omap_prcm_int_update(s, 2);
3410 break;
3411
3412 default:
3413 OMAP_BAD_REG(addr);
3414 return;
3415 }
3416 }
3417
3418 static CPUReadMemoryFunc *omap_prcm_readfn[] = {
3419 omap_badwidth_read32,
3420 omap_badwidth_read32,
3421 omap_prcm_read,
3422 };
3423
3424 static CPUWriteMemoryFunc *omap_prcm_writefn[] = {
3425 omap_badwidth_write32,
3426 omap_badwidth_write32,
3427 omap_prcm_write,
3428 };
3429
3430 static void omap_prcm_reset(struct omap_prcm_s *s)
3431 {
3432 s->sysconfig = 0;
3433 s->irqst[0] = 0;
3434 s->irqst[1] = 0;
3435 s->irqst[2] = 0;
3436 s->irqen[0] = 0;
3437 s->irqen[1] = 0;
3438 s->irqen[2] = 0;
3439 s->voltctrl = 0x1040;
3440 s->ev = 0x14;
3441 s->evtime[0] = 0;
3442 s->evtime[1] = 0;
3443 s->clkctrl[0] = 0;
3444 s->clkctrl[1] = 0;
3445 s->clkctrl[2] = 0;
3446 s->clkctrl[3] = 0;
3447 s->clken[1] = 7;
3448 s->clken[3] = 7;
3449 s->clken[4] = 0;
3450 s->clken[5] = 0;
3451 s->clken[6] = 0;
3452 s->clken[7] = 0xc;
3453 s->clken[8] = 0x3e;
3454 s->clken[9] = 0x0d;
3455 s->clken[10] = 0;
3456 s->clken[11] = 0;
3457 s->clkidle[0] = 0;
3458 s->clkidle[2] = 7;
3459 s->clkidle[3] = 0;
3460 s->clkidle[4] = 0;
3461 s->clkidle[5] = 0x0c;
3462 s->clkidle[6] = 0;
3463 s->clksel[0] = 0x01;
3464 s->clksel[1] = 0x02100121;
3465 s->clksel[2] = 0x00000000;
3466 s->clksel[3] = 0x01;
3467 s->clksel[4] = 0;
3468 s->clksel[7] = 0x0121;
3469 s->wkup[0] = 0x15;
3470 s->wkup[1] = 0x13;
3471 s->wkup[2] = 0x13;
3472 s->wken[0] = 0x04667ff8;
3473 s->wken[1] = 0x00000005;
3474 s->wken[2] = 5;
3475 s->wkst[0] = 0;
3476 s->wkst[1] = 0;
3477 s->wkst[2] = 0;
3478 s->power[0] = 0x00c;
3479 s->power[1] = 4;
3480 s->power[2] = 0x0000c;
3481 s->power[3] = 0x14;
3482 s->rstctrl[0] = 1;
3483 s->rst[3] = 1;
3484 omap_prcm_apll_update(s);
3485 omap_prcm_dpll_update(s);
3486 }
3487
3488 static void omap_prcm_coldreset(struct omap_prcm_s *s)
3489 {
3490 s->setuptime[0] = 0;
3491 s->setuptime[1] = 0;
3492 memset(&s->scratch, 0, sizeof(s->scratch));
3493 s->rst[0] = 0x01;
3494 s->rst[1] = 0x00;
3495 s->rst[2] = 0x01;
3496 s->clken[0] = 0;
3497 s->clken[2] = 0;
3498 s->clkidle[1] = 0;
3499 s->clksel[5] = 0;
3500 s->clksel[6] = 2;
3501 s->clksrc[0] = 0x43;
3502 s->clkout[0] = 0x0303;
3503 s->clkemul[0] = 0;
3504 s->clkpol[0] = 0x100;
3505 s->rsttime_wkup = 0x1002;
3506
3507 omap_prcm_reset(s);
3508 }
3509
3510 struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
3511 qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
3512 struct omap_mpu_state_s *mpu)
3513 {
3514 int iomemtype;
3515 struct omap_prcm_s *s = (struct omap_prcm_s *)
3516 qemu_mallocz(sizeof(struct omap_prcm_s));
3517
3518 s->irq[0] = mpu_int;
3519 s->irq[1] = dsp_int;
3520 s->irq[2] = iva_int;
3521 s->mpu = mpu;
3522 omap_prcm_coldreset(s);
3523
3524 iomemtype = l4_register_io_memory(0, omap_prcm_readfn,
3525 omap_prcm_writefn, s);
3526 omap_l4_attach(ta, 0, iomemtype);
3527 omap_l4_attach(ta, 1, iomemtype);
3528
3529 return s;
3530 }
3531
3532 /* System and Pinout control */
3533 struct omap_sysctl_s {
3534 struct omap_mpu_state_s *mpu;
3535
3536 uint32_t sysconfig;
3537 uint32_t devconfig;
3538 uint32_t psaconfig;
3539 uint32_t padconf[0x45];
3540 uint8_t obs;
3541 uint32_t msuspendmux[5];
3542 };
3543
3544 static uint32_t omap_sysctl_read8(void *opaque, target_phys_addr_t addr)
3545 {
3546
3547 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
3548 int pad_offset, byte_offset;
3549 int value;
3550
3551 switch (addr) {
3552 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
3553 pad_offset = (addr - 0x30) >> 2;
3554 byte_offset = (addr - 0x30) & (4 - 1);
3555
3556 value = s->padconf[pad_offset];
3557 value = (value >> (byte_offset * 8)) & 0xff;
3558
3559 return value;
3560
3561 default:
3562 break;
3563 }
3564
3565 OMAP_BAD_REG(addr);
3566 return 0;
3567 }
3568
3569 static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr)
3570 {
3571 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
3572
3573 switch (addr) {
3574 case 0x000: /* CONTROL_REVISION */
3575 return 0x20;
3576
3577 case 0x010: /* CONTROL_SYSCONFIG */
3578 return s->sysconfig;
3579
3580 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
3581 return s->padconf[(addr - 0x30) >> 2];
3582
3583 case 0x270: /* CONTROL_DEBOBS */
3584 return s->obs;
3585
3586 case 0x274: /* CONTROL_DEVCONF */
3587 return s->devconfig;
3588
3589 case 0x28c: /* CONTROL_EMU_SUPPORT */
3590 return 0;
3591
3592 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
3593 return s->msuspendmux[0];
3594 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
3595 return s->msuspendmux[1];
3596 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
3597 return s->msuspendmux[2];
3598 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
3599 return s->msuspendmux[3];
3600 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
3601 return s->msuspendmux[4];
3602 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
3603 return 0;
3604
3605 case 0x2b8: /* CONTROL_PSA_CTRL */
3606 return s->psaconfig;
3607 case 0x2bc: /* CONTROL_PSA_CMD */
3608 case 0x2c0: /* CONTROL_PSA_VALUE */
3609 return 0;
3610
3611 case 0x2b0: /* CONTROL_SEC_CTRL */
3612 return 0x800000f1;
3613 case 0x2d0: /* CONTROL_SEC_EMU */
3614 return 0x80000015;
3615 case 0x2d4: /* CONTROL_SEC_TAP */
3616 return 0x8000007f;
3617 case 0x2b4: /* CONTROL_SEC_TEST */
3618 case 0x2f0: /* CONTROL_SEC_STATUS */
3619 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
3620 /* Secure mode is not present on general-pusrpose device. Outside
3621 * secure mode these values cannot be read or written. */
3622 return 0;
3623
3624 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
3625 return 0xff;
3626 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
3627 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
3628 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
3629 /* No secure mode so no Extended Secure RAM present. */
3630 return 0;
3631
3632 case 0x2f8: /* CONTROL_STATUS */
3633 /* Device Type => General-purpose */
3634 return 0x0300;
3635 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
3636
3637 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
3638 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
3639 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
3640 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
3641 return 0xdecafbad;
3642
3643 case 0x310: /* CONTROL_RAND_KEY_0 */
3644 case 0x314: /* CONTROL_RAND_KEY_1 */
3645 case 0x318: /* CONTROL_RAND_KEY_2 */
3646 case 0x31c: /* CONTROL_RAND_KEY_3 */
3647 case 0x320: /* CONTROL_CUST_KEY_0 */
3648 case 0x324: /* CONTROL_CUST_KEY_1 */
3649 case 0x330: /* CONTROL_TEST_KEY_0 */
3650 case 0x334: /* CONTROL_TEST_KEY_1 */
3651 case 0x338: /* CONTROL_TEST_KEY_2 */
3652 case 0x33c: /* CONTROL_TEST_KEY_3 */
3653 case 0x340: /* CONTROL_TEST_KEY_4 */
3654 case 0x344: /* CONTROL_TEST_KEY_5 */
3655 case 0x348: /* CONTROL_TEST_KEY_6 */
3656 case 0x34c: /* CONTROL_TEST_KEY_7 */
3657 case 0x350: /* CONTROL_TEST_KEY_8 */
3658 case 0x354: /* CONTROL_TEST_KEY_9 */
3659 /* Can only be accessed in secure mode and when C_FieldAccEnable
3660 * bit is set in CONTROL_SEC_CTRL.
3661 * TODO: otherwise an interconnect access error is generated. */
3662 return 0;
3663 }
3664
3665 OMAP_BAD_REG(addr);
3666 return 0;
3667 }
3668
3669 static void omap_sysctl_write8(void *opaque, target_phys_addr_t addr,
3670 uint32_t value)
3671 {
3672 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
3673 int pad_offset, byte_offset;
3674 int prev_value;
3675
3676 switch (addr) {
3677 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
3678 pad_offset = (addr - 0x30) >> 2;
3679 byte_offset = (addr - 0x30) & (4 - 1);
3680
3681 prev_value = s->padconf[pad_offset];
3682 prev_value &= ~(0xff << (byte_offset * 8));
3683 prev_value |= ((value & 0x1f1f1f1f) << (byte_offset * 8)) & 0x1f1f1f1f;
3684 s->padconf[pad_offset] = prev_value;
3685 break;
3686
3687 default:
3688 OMAP_BAD_REG(addr);
3689 break;
3690 }
3691 }
3692
3693 static void omap_sysctl_write(void *opaque, target_phys_addr_t addr,
3694 uint32_t value)
3695 {
3696 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
3697
3698 switch (addr) {
3699 case 0x000: /* CONTROL_REVISION */
3700 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
3701 case 0x2c0: /* CONTROL_PSA_VALUE */
3702 case 0x2f8: /* CONTROL_STATUS */
3703 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
3704 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
3705 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
3706 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
3707 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
3708 case 0x310: /* CONTROL_RAND_KEY_0 */
3709 case 0x314: /* CONTROL_RAND_KEY_1 */
3710 case 0x318: /* CONTROL_RAND_KEY_2 */
3711 case 0x31c: /* CONTROL_RAND_KEY_3 */
3712 case 0x320: /* CONTROL_CUST_KEY_0 */
3713 case 0x324: /* CONTROL_CUST_KEY_1 */
3714 case 0x330: /* CONTROL_TEST_KEY_0 */
3715 case 0x334: /* CONTROL_TEST_KEY_1 */
3716 case 0x338: /* CONTROL_TEST_KEY_2 */
3717 case 0x33c: /* CONTROL_TEST_KEY_3 */
3718 case 0x340: /* CONTROL_TEST_KEY_4 */
3719 case 0x344: /* CONTROL_TEST_KEY_5 */
3720 case 0x348: /* CONTROL_TEST_KEY_6 */
3721 case 0x34c: /* CONTROL_TEST_KEY_7 */
3722 case 0x350: /* CONTROL_TEST_KEY_8 */
3723 case 0x354: /* CONTROL_TEST_KEY_9 */
3724 OMAP_RO_REG(addr);
3725 return;
3726
3727 case 0x010: /* CONTROL_SYSCONFIG */
3728 s->sysconfig = value & 0x1e;
3729 break;
3730
3731 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
3732 /* XXX: should check constant bits */
3733 s->padconf[(addr - 0x30) >> 2] = value & 0x1f1f1f1f;
3734 break;
3735
3736 case 0x270: /* CONTROL_DEBOBS */
3737 s->obs = value & 0xff;
3738 break;
3739
3740 case 0x274: /* CONTROL_DEVCONF */
3741 s->devconfig = value & 0xffffc7ff;
3742 break;
3743
3744 case 0x28c: /* CONTROL_EMU_SUPPORT */
3745 break;
3746
3747 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
3748 s->msuspendmux[0] = value & 0x3fffffff;
3749 break;
3750 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
3751 s->msuspendmux[1] = value & 0x3fffffff;
3752 break;
3753 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
3754 s->msuspendmux[2] = value & 0x3fffffff;
3755 break;
3756 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
3757 s->msuspendmux[3] = value & 0x3fffffff;
3758 break;
3759 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
3760 s->msuspendmux[4] = value & 0x3fffffff;
3761 break;
3762
3763 case 0x2b8: /* CONTROL_PSA_CTRL */
3764 s->psaconfig = value & 0x1c;
3765 s->psaconfig |= (value & 0x20) ? 2 : 1;
3766 break;
3767 case 0x2bc: /* CONTROL_PSA_CMD */
3768 break;
3769
3770 case 0x2b0: /* CONTROL_SEC_CTRL */
3771 case 0x2b4: /* CONTROL_SEC_TEST */
3772 case 0x2d0: /* CONTROL_SEC_EMU */
3773 case 0x2d4: /* CONTROL_SEC_TAP */
3774 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
3775 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
3776 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
3777 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
3778 case 0x2f0: /* CONTROL_SEC_STATUS */
3779 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
3780 break;
3781
3782 default:
3783 OMAP_BAD_REG(addr);
3784 return;
3785 }
3786 }
3787
3788 static CPUReadMemoryFunc *omap_sysctl_readfn[] = {
3789 omap_sysctl_read8,
3790 omap_badwidth_read32, /* TODO */
3791 omap_sysctl_read,
3792 };
3793
3794 static CPUWriteMemoryFunc *omap_sysctl_writefn[] = {
3795 omap_sysctl_write8,
3796 omap_badwidth_write32, /* TODO */
3797 omap_sysctl_write,
3798 };
3799
3800 static void omap_sysctl_reset(struct omap_sysctl_s *s)
3801 {
3802 /* (power-on reset) */
3803 s->sysconfig = 0;
3804 s->obs = 0;
3805 s->devconfig = 0x0c000000;
3806 s->msuspendmux[0] = 0x00000000;
3807 s->msuspendmux[1] = 0x00000000;
3808 s->msuspendmux[2] = 0x00000000;
3809 s->msuspendmux[3] = 0x00000000;
3810 s->msuspendmux[4] = 0x00000000;
3811 s->psaconfig = 1;
3812
3813 s->padconf[0x00] = 0x000f0f0f;
3814 s->padconf[0x01] = 0x00000000;
3815 s->padconf[0x02] = 0x00000000;
3816 s->padconf[0x03] = 0x00000000;
3817 s->padconf[0x04] = 0x00000000;
3818 s->padconf[0x05] = 0x00000000;
3819 s->padconf[0x06] = 0x00000000;
3820 s->padconf[0x07] = 0x00000000;
3821 s->padconf[0x08] = 0x08080800;
3822 s->padconf[0x09] = 0x08080808;
3823 s->padconf[0x0a] = 0x08080808;
3824 s->padconf[0x0b] = 0x08080808;
3825 s->padconf[0x0c] = 0x08080808;
3826 s->padconf[0x0d] = 0x08080800;
3827 s->padconf[0x0e] = 0x08080808;
3828 s->padconf[0x0f] = 0x08080808;
3829 s->padconf[0x10] = 0x18181808; /* | 0x07070700 if SBoot3 */
3830 s->padconf[0x11] = 0x18181818; /* | 0x07070707 if SBoot3 */
3831 s->padconf[0x12] = 0x18181818; /* | 0x07070707 if SBoot3 */
3832 s->padconf[0x13] = 0x18181818; /* | 0x07070707 if SBoot3 */
3833 s->padconf[0x14] = 0x18181818; /* | 0x00070707 if SBoot3 */
3834 s->padconf[0x15] = 0x18181818;
3835 s->padconf[0x16] = 0x18181818; /* | 0x07000000 if SBoot3 */
3836 s->padconf[0x17] = 0x1f001f00;
3837 s->padconf[0x18] = 0x1f1f1f1f;
3838 s->padconf[0x19] = 0x00000000;
3839 s->padconf[0x1a] = 0x1f180000;
3840 s->padconf[0x1b] = 0x00001f1f;
3841 s->padconf[0x1c] = 0x1f001f00;
3842 s->padconf[0x1d] = 0x00000000;
3843 s->padconf[0x1e] = 0x00000000;
3844 s->padconf[0x1f] = 0x08000000;
3845 s->padconf[0x20] = 0x08080808;
3846 s->padconf[0x21] = 0x08080808;
3847 s->padconf[0x22] = 0x0f080808;
3848 s->padconf[0x23] = 0x0f0f0f0f;
3849 s->padconf[0x24] = 0x000f0f0f;
3850 s->padconf[0x25] = 0x1f1f1f0f;
3851 s->padconf[0x26] = 0x080f0f1f;
3852 s->padconf[0x27] = 0x070f1808;
3853 s->padconf[0x28] = 0x0f070707;
3854 s->padconf[0x29] = 0x000f0f1f;
3855 s->padconf[0x2a] = 0x0f0f0f1f;
3856 s->padconf[0x2b] = 0x08000000;
3857 s->padconf[0x2c] = 0x0000001f;
3858 s->padconf[0x2d] = 0x0f0f1f00;
3859 s->padconf[0x2e] = 0x1f1f0f0f;
3860 s->padconf[0x2f] = 0x0f1f1f1f;
3861 s->padconf[0x30] = 0x0f0f0f0f;
3862 s->padconf[0x31] = 0x0f1f0f1f;
3863 s->padconf[0x32] = 0x0f0f0f0f;
3864 s->padconf[0x33] = 0x0f1f0f1f;
3865 s->padconf[0x34] = 0x1f1f0f0f;
3866 s->padconf[0x35] = 0x0f0f1f1f;
3867 s->padconf[0x36] = 0x0f0f1f0f;
3868 s->padconf[0x37] = 0x0f0f0f0f;
3869 s->padconf[0x38] = 0x1f18180f;
3870 s->padconf[0x39] = 0x1f1f1f1f;
3871 s->padconf[0x3a] = 0x00001f1f;
3872 s->padconf[0x3b] = 0x00000000;
3873 s->padconf[0x3c] = 0x00000000;
3874 s->padconf[0x3d] = 0x0f0f0f0f;
3875 s->padconf[0x3e] = 0x18000f0f;
3876 s->padconf[0x3f] = 0x00070000;
3877 s->padconf[0x40] = 0x00000707;
3878 s->padconf[0x41] = 0x0f1f0700;
3879 s->padconf[0x42] = 0x1f1f070f;
3880 s->padconf[0x43] = 0x0008081f;
3881 s->padconf[0x44] = 0x00000800;
3882 }
3883
3884 struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
3885 omap_clk iclk, struct omap_mpu_state_s *mpu)
3886 {
3887 int iomemtype;
3888 struct omap_sysctl_s *s = (struct omap_sysctl_s *)
3889 qemu_mallocz(sizeof(struct omap_sysctl_s));
3890
3891 s->mpu = mpu;
3892 omap_sysctl_reset(s);
3893
3894 iomemtype = l4_register_io_memory(0, omap_sysctl_readfn,
3895 omap_sysctl_writefn, s);
3896 omap_l4_attach(ta, 0, iomemtype);
3897
3898 return s;
3899 }
3900
3901 /* SDRAM Controller Subsystem */
3902 struct omap_sdrc_s {
3903 uint8_t config;
3904 };
3905
3906 static void omap_sdrc_reset(struct omap_sdrc_s *s)
3907 {
3908 s->config = 0x10;
3909 }
3910
3911 static uint32_t omap_sdrc_read(void *opaque, target_phys_addr_t addr)
3912 {
3913 struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
3914
3915 switch (addr) {
3916 case 0x00: /* SDRC_REVISION */
3917 return 0x20;
3918
3919 case 0x10: /* SDRC_SYSCONFIG */
3920 return s->config;
3921
3922 case 0x14: /* SDRC_SYSSTATUS */
3923 return 1; /* RESETDONE */
3924
3925 case 0x40: /* SDRC_CS_CFG */
3926 case 0x44: /* SDRC_SHARING */
3927 case 0x48: /* SDRC_ERR_ADDR */
3928 case 0x4c: /* SDRC_ERR_TYPE */
3929 case 0x60: /* SDRC_DLLA_SCTRL */
3930 case 0x64: /* SDRC_DLLA_STATUS */
3931 case 0x68: /* SDRC_DLLB_CTRL */
3932 case 0x6c: /* SDRC_DLLB_STATUS */
3933 case 0x70: /* SDRC_POWER */
3934 case 0x80: /* SDRC_MCFG_0 */
3935 case 0x84: /* SDRC_MR_0 */
3936 case 0x88: /* SDRC_EMR1_0 */
3937 case 0x8c: /* SDRC_EMR2_0 */
3938 case 0x90: /* SDRC_EMR3_0 */
3939 case 0x94: /* SDRC_DCDL1_CTRL */
3940 case 0x98: /* SDRC_DCDL2_CTRL */
3941 case 0x9c: /* SDRC_ACTIM_CTRLA_0 */
3942 case 0xa0: /* SDRC_ACTIM_CTRLB_0 */
3943 case 0xa4: /* SDRC_RFR_CTRL_0 */
3944 case 0xa8: /* SDRC_MANUAL_0 */
3945 case 0xb0: /* SDRC_MCFG_1 */
3946 case 0xb4: /* SDRC_MR_1 */
3947 case 0xb8: /* SDRC_EMR1_1 */
3948 case 0xbc: /* SDRC_EMR2_1 */
3949 case 0xc0: /* SDRC_EMR3_1 */
3950 case 0xc4: /* SDRC_ACTIM_CTRLA_1 */
3951 case 0xc8: /* SDRC_ACTIM_CTRLB_1 */
3952 case 0xd4: /* SDRC_RFR_CTRL_1 */
3953 case 0xd8: /* SDRC_MANUAL_1 */
3954 return 0x00;
3955 }
3956
3957 OMAP_BAD_REG(addr);
3958 return 0;
3959 }
3960
3961 static void omap_sdrc_write(void *opaque, target_phys_addr_t addr,
3962 uint32_t value)
3963 {
3964 struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
3965
3966 switch (addr) {
3967 case 0x00: /* SDRC_REVISION */
3968 case 0x14: /* SDRC_SYSSTATUS */
3969 case 0x48: /* SDRC_ERR_ADDR */
3970 case 0x64: /* SDRC_DLLA_STATUS */
3971 case 0x6c: /* SDRC_DLLB_STATUS */
3972 OMAP_RO_REG(addr);
3973 return;
3974
3975 case 0x10: /* SDRC_SYSCONFIG */
3976 if ((value >> 3) != 0x2)
3977 fprintf(stderr, "%s: bad SDRAM idle mode %i\n",
3978 __FUNCTION__, value >> 3);
3979 if (value & 2)
3980 omap_sdrc_reset(s);
3981 s->config = value & 0x18;
3982 break;
3983
3984 case 0x40: /* SDRC_CS_CFG */
3985 case 0x44: /* SDRC_SHARING */
3986 case 0x4c: /* SDRC_ERR_TYPE */
3987 case 0x60: /* SDRC_DLLA_SCTRL */
3988 case 0x68: /* SDRC_DLLB_CTRL */
3989 case 0x70: /* SDRC_POWER */
3990 case 0x80: /* SDRC_MCFG_0 */
3991 case 0x84: /* SDRC_MR_0 */
3992 case 0x88: /* SDRC_EMR1_0 */
3993 case 0x8c: /* SDRC_EMR2_0 */
3994 case 0x90: /* SDRC_EMR3_0 */
3995 case 0x94: /* SDRC_DCDL1_CTRL */
3996 case 0x98: /* SDRC_DCDL2_CTRL */
3997 case 0x9c: /* SDRC_ACTIM_CTRLA_0 */
3998 case 0xa0: /* SDRC_ACTIM_CTRLB_0 */
3999 case 0xa4: /* SDRC_RFR_CTRL_0 */
4000 case 0xa8: /* SDRC_MANUAL_0 */
4001 case 0xb0: /* SDRC_MCFG_1 */
4002 case 0xb4: /* SDRC_MR_1 */
4003 case 0xb8: /* SDRC_EMR1_1 */
4004 case 0xbc: /* SDRC_EMR2_1 */
4005 case 0xc0: /* SDRC_EMR3_1 */
4006 case 0xc4: /* SDRC_ACTIM_CTRLA_1 */
4007 case 0xc8: /* SDRC_ACTIM_CTRLB_1 */
4008 case 0xd4: /* SDRC_RFR_CTRL_1 */
4009 case 0xd8: /* SDRC_MANUAL_1 */
4010 break;
4011
4012 default:
4013 OMAP_BAD_REG(addr);
4014 return;
4015 }
4016 }
4017
4018 static CPUReadMemoryFunc *omap_sdrc_readfn[] = {
4019 omap_badwidth_read32,
4020 omap_badwidth_read32,
4021 omap_sdrc_read,
4022 };
4023
4024 static CPUWriteMemoryFunc *omap_sdrc_writefn[] = {
4025 omap_badwidth_write32,
4026 omap_badwidth_write32,
4027 omap_sdrc_write,
4028 };
4029
4030 struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base)
4031 {
4032 int iomemtype;
4033 struct omap_sdrc_s *s = (struct omap_sdrc_s *)
4034 qemu_mallocz(sizeof(struct omap_sdrc_s));
4035
4036 omap_sdrc_reset(s);
4037
4038 iomemtype = cpu_register_io_memory(0, omap_sdrc_readfn,
4039 omap_sdrc_writefn, s);
4040 cpu_register_physical_memory(base, 0x1000, iomemtype);
4041
4042 return s;
4043 }
4044
4045 /* General-Purpose Memory Controller */
4046 struct omap_gpmc_s {
4047 qemu_irq irq;
4048
4049 uint8_t sysconfig;
4050 uint16_t irqst;
4051 uint16_t irqen;
4052 uint16_t timeout;
4053 uint16_t config;
4054 uint32_t prefconfig[2];
4055 int prefcontrol;
4056 int preffifo;
4057 int prefcount;
4058 struct omap_gpmc_cs_file_s {
4059 uint32_t config[7];
4060 target_phys_addr_t base;
4061 size_t size;
4062 int iomemtype;
4063 void (*base_update)(void *opaque, target_phys_addr_t new);
4064 void (*unmap)(void *opaque);
4065 void *opaque;
4066 } cs_file[8];
4067 int ecc_cs;
4068 int ecc_ptr;
4069 uint32_t ecc_cfg;
4070 ECCState ecc[9];
4071 };
4072
4073 static void omap_gpmc_int_update(struct omap_gpmc_s *s)
4074 {
4075 qemu_set_irq(s->irq, s->irqen & s->irqst);
4076 }
4077
4078 static void omap_gpmc_cs_map(struct omap_gpmc_cs_file_s *f, int base, int mask)
4079 {
4080 /* TODO: check for overlapping regions and report access errors */
4081 if ((mask != 0x8 && mask != 0xc && mask != 0xe && mask != 0xf) ||
4082 (base < 0 || base >= 0x40) ||
4083 (base & 0x0f & ~mask)) {
4084 fprintf(stderr, "%s: wrong cs address mapping/decoding!\n",
4085 __FUNCTION__);
4086 return;
4087 }
4088
4089 if (!f->opaque)
4090 return;
4091
4092 f->base = base << 24;
4093 f->size = (0x0fffffff & ~(mask << 24)) + 1;
4094 /* TODO: rather than setting the size of the mapping (which should be
4095 * constant), the mask should cause wrapping of the address space, so
4096 * that the same memory becomes accessible at every <i>size</i> bytes
4097 * starting from <i>base</i>. */
4098 if (f->iomemtype)
4099 cpu_register_physical_memory(f->base, f->size, f->iomemtype);
4100
4101 if (f->base_update)
4102 f->base_update(f->opaque, f->base);
4103 }
4104
4105 static void omap_gpmc_cs_unmap(struct omap_gpmc_cs_file_s *f)
4106 {
4107 if (f->size) {
4108 if (f->unmap)
4109 f->unmap(f->opaque);
4110 if (f->iomemtype)
4111 cpu_register_physical_memory(f->base, f->size, IO_MEM_UNASSIGNED);
4112 f->base = 0;
4113 f->size = 0;
4114 }
4115 }
4116
4117 static void omap_gpmc_reset(struct omap_gpmc_s *s)
4118 {
4119 int i;
4120
4121 s->sysconfig = 0;
4122 s->irqst = 0;
4123 s->irqen = 0;
4124 omap_gpmc_int_update(s);
4125 s->timeout = 0;
4126 s->config = 0xa00;
4127 s->prefconfig[0] = 0x00004000;
4128 s->prefconfig[1] = 0x00000000;
4129 s->prefcontrol = 0;
4130 s->preffifo = 0;
4131 s->prefcount = 0;
4132 for (i = 0; i < 8; i ++) {
4133 if (s->cs_file[i].config[6] & (1 << 6)) /* CSVALID */
4134 omap_gpmc_cs_unmap(s->cs_file + i);
4135 s->cs_file[i].config[0] = i ? 1 << 12 : 0;
4136 s->cs_file[i].config[1] = 0x101001;
4137 s->cs_file[i].config[2] = 0x020201;
4138 s->cs_file[i].config[3] = 0x10031003;
4139 s->cs_file[i].config[4] = 0x10f1111;
4140 s->cs_file[i].config[5] = 0;
4141 s->cs_file[i].config[6] = 0xf00 | (i ? 0 : 1 << 6);
4142 if (s->cs_file[i].config[6] & (1 << 6)) /* CSVALID */
4143 omap_gpmc_cs_map(&s->cs_file[i],
4144 s->cs_file[i].config[6] & 0x1f, /* MASKADDR */
4145 (s->cs_file[i].config[6] >> 8 & 0xf)); /* BASEADDR */
4146 }
4147 omap_gpmc_cs_map(s->cs_file, 0, 0xf);
4148 s->ecc_cs = 0;
4149 s->ecc_ptr = 0;
4150 s->ecc_cfg = 0x3fcff000;
4151 for (i = 0; i < 9; i ++)
4152 ecc_reset(&s->ecc[i]);
4153 }
4154
4155 static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr)
4156 {
4157 struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
4158 int cs;
4159 struct omap_gpmc_cs_file_s *f;
4160
4161 switch (addr) {
4162 case 0x000: /* GPMC_REVISION */
4163 return 0x20;
4164
4165 case 0x010: /* GPMC_SYSCONFIG */
4166 return s->sysconfig;
4167
4168 case 0x014: /* GPMC_SYSSTATUS */
4169 return 1; /* RESETDONE */
4170
4171 case 0x018: /* GPMC_IRQSTATUS */
4172 return s->irqst;
4173
4174 case 0x01c: /* GPMC_IRQENABLE */
4175 return s->irqen;
4176
4177 case 0x040: /* GPMC_TIMEOUT_CONTROL */
4178 return s->timeout;
4179
4180 case 0x044: /* GPMC_ERR_ADDRESS */
4181 case 0x048: /* GPMC_ERR_TYPE */
4182 return 0;
4183
4184 case 0x050: /* GPMC_CONFIG */
4185 return s->config;
4186
4187 case 0x054: /* GPMC_STATUS */
4188 return 0x001;
4189
4190 case 0x060 ... 0x1d4:
4191 cs = (addr - 0x060) / 0x30;
4192 addr -= cs * 0x30;
4193 f = s->cs_file + cs;
4194 switch (addr) {
4195 case 0x60: /* GPMC_CONFIG1 */
4196 return f->config[0];
4197 case 0x64: /* GPMC_CONFIG2 */
4198 return f->config[1];
4199 case 0x68: /* GPMC_CONFIG3 */
4200 return f->config[2];
4201 case 0x6c: /* GPMC_CONFIG4 */
4202 return f->config[3];
4203 case 0x70: /* GPMC_CONFIG5 */
4204 return f->config[4];
4205 case 0x74: /* GPMC_CONFIG6 */
4206 return f->config[5];
4207 case 0x78: /* GPMC_CONFIG7 */
4208 return f->config[6];
4209 case 0x84: /* GPMC_NAND_DATA */
4210 return 0;
4211 }
4212 break;
4213
4214 case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */
4215 return s->prefconfig[0];
4216 case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */
4217 return s->prefconfig[1];
4218 case 0x1ec: /* GPMC_PREFETCH_CONTROL */
4219 return s->prefcontrol;
4220 case 0x1f0: /* GPMC_PREFETCH_STATUS */
4221 return (s->preffifo << 24) |
4222 ((s->preffifo >
4223 ((s->prefconfig[0] >> 8) & 0x7f) ? 1 : 0) << 16) |
4224 s->prefcount;
4225
4226 case 0x1f4: /* GPMC_ECC_CONFIG */
4227 return s->ecc_cs;
4228 case 0x1f8: /* GPMC_ECC_CONTROL */
4229 return s->ecc_ptr;
4230 case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */
4231 return s->ecc_cfg;
4232 case 0x200 ... 0x220: /* GPMC_ECC_RESULT */
4233 cs = (addr & 0x1f) >> 2;
4234 /* TODO: check correctness */
4235 return
4236 ((s->ecc[cs].cp & 0x07) << 0) |
4237 ((s->ecc[cs].cp & 0x38) << 13) |
4238 ((s->ecc[cs].lp[0] & 0x1ff) << 3) |
4239 ((s->ecc[cs].lp[1] & 0x1ff) << 19);
4240
4241 case 0x230: /* GPMC_TESTMODE_CTRL */
4242 return 0;
4243 case 0x234: /* GPMC_PSA_LSB */
4244 case 0x238: /* GPMC_PSA_MSB */
4245 return 0x00000000;
4246 }
4247
4248 OMAP_BAD_REG(addr);
4249 return 0;
4250 }
4251
4252 static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
4253 uint32_t value)
4254 {
4255 struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
4256 int cs;
4257 struct omap_gpmc_cs_file_s *f;
4258
4259 switch (addr) {
4260 case 0x000: /* GPMC_REVISION */
4261 case 0x014: /* GPMC_SYSSTATUS */
4262 case 0x054: /* GPMC_STATUS */
4263 case 0x1f0: /* GPMC_PREFETCH_STATUS */
4264 case 0x200 ... 0x220: /* GPMC_ECC_RESULT */
4265 case 0x234: /* GPMC_PSA_LSB */
4266 case 0x238: /* GPMC_PSA_MSB */
4267 OMAP_RO_REG(addr);
4268 break;
4269
4270 case 0x010: /* GPMC_SYSCONFIG */
4271 if ((value >> 3) == 0x3)
4272 fprintf(stderr, "%s: bad SDRAM idle mode %i\n",
4273 __FUNCTION__, value >> 3);
4274 if (value & 2)
4275 omap_gpmc_reset(s);
4276 s->sysconfig = value & 0x19;
4277 break;
4278
4279 case 0x018: /* GPMC_IRQSTATUS */
4280 s->irqen = ~value;
4281 omap_gpmc_int_update(s);
4282 break;
4283
4284 case 0x01c: /* GPMC_IRQENABLE */
4285 s->irqen = value & 0xf03;
4286 omap_gpmc_int_update(s);
4287 break;
4288
4289 case 0x040: /* GPMC_TIMEOUT_CONTROL */
4290 s->timeout = value & 0x1ff1;
4291 break;
4292
4293 case 0x044: /* GPMC_ERR_ADDRESS */
4294 case 0x048: /* GPMC_ERR_TYPE */
4295 break;
4296
4297 case 0x050: /* GPMC_CONFIG */
4298 s->config = value & 0xf13;
4299 break;
4300
4301 case 0x060 ... 0x1d4:
4302 cs = (addr - 0x060) / 0x30;
4303 addr -= cs * 0x30;
4304 f = s->cs_file + cs;
4305 switch (addr) {
4306 case 0x60: /* GPMC_CONFIG1 */
4307 f->config[0] = value & 0xffef3e13;
4308 break;
4309 case 0x64: /* GPMC_CONFIG2 */
4310 f->config[1] = value & 0x001f1f8f;
4311 break;
4312 case 0x68: /* GPMC_CONFIG3 */
4313 f->config[2] = value & 0x001f1f8f;
4314 break;
4315 case 0x6c: /* GPMC_CONFIG4 */
4316 f->config[3] = value & 0x1f8f1f8f;
4317 break;
4318 case 0x70: /* GPMC_CONFIG5 */
4319 f->config[4] = value & 0x0f1f1f1f;
4320 break;
4321 case 0x74: /* GPMC_CONFIG6 */
4322 f->config[5] = value & 0x00000fcf;
4323 break;
4324 case 0x78: /* GPMC_CONFIG7 */
4325 if ((f->config[6] ^ value) & 0xf7f) {
4326 if (f->config[6] & (1 << 6)) /* CSVALID */
4327 omap_gpmc_cs_unmap(f);
4328 if (value & (1 << 6)) /* CSVALID */
4329 omap_gpmc_cs_map(f, value & 0x1f, /* MASKADDR */
4330 (value >> 8 & 0xf)); /* BASEADDR */
4331 }
4332 f->config[6] = value & 0x00000f7f;
4333 break;
4334 case 0x7c: /* GPMC_NAND_COMMAND */
4335 case 0x80: /* GPMC_NAND_ADDRESS */
4336 case 0x84: /* GPMC_NAND_DATA */
4337 break;
4338
4339 default:
4340 goto bad_reg;
4341 }
4342 break;
4343
4344 case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */
4345 s->prefconfig[0] = value & 0x7f8f7fbf;
4346 /* TODO: update interrupts, fifos, dmas */
4347 break;
4348
4349 case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */
4350 s->prefconfig[1] = value & 0x3fff;
4351 break;
4352
4353 case 0x1ec: /* GPMC_PREFETCH_CONTROL */
4354 s->prefcontrol = value & 1;
4355 if (s->prefcontrol) {
4356 if (s->prefconfig[0] & 1)
4357 s->preffifo = 0x40;
4358 else
4359 s->preffifo = 0x00;
4360 }
4361 /* TODO: start */
4362 break;
4363
4364 case 0x1f4: /* GPMC_ECC_CONFIG */
4365 s->ecc_cs = 0x8f;
4366 break;
4367 case 0x1f8: /* GPMC_ECC_CONTROL */
4368 if (value & (1 << 8))
4369 for (cs = 0; cs < 9; cs ++)
4370 ecc_reset(&s->ecc[cs]);
4371 s->ecc_ptr = value & 0xf;
4372 if (s->ecc_ptr == 0 || s->ecc_ptr > 9) {
4373 s->ecc_ptr = 0;
4374 s->ecc_cs &= ~1;
4375 }
4376 break;
4377 case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */
4378 s->ecc_cfg = value & 0x3fcff1ff;
4379 break;
4380 case 0x230: /* GPMC_TESTMODE_CTRL */
4381 if (value & 7)
4382 fprintf(stderr, "%s: test mode enable attempt\n", __FUNCTION__);
4383 break;
4384
4385 default:
4386 bad_reg:
4387 OMAP_BAD_REG(addr);
4388 return;
4389 }
4390 }
4391
4392 static CPUReadMemoryFunc *omap_gpmc_readfn[] = {
4393 omap_badwidth_read32, /* TODO */
4394 omap_badwidth_read32, /* TODO */
4395 omap_gpmc_read,
4396 };
4397
4398 static CPUWriteMemoryFunc *omap_gpmc_writefn[] = {
4399 omap_badwidth_write32, /* TODO */
4400 omap_badwidth_write32, /* TODO */
4401 omap_gpmc_write,
4402 };
4403
4404 struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq)
4405 {
4406 int iomemtype;
4407 struct omap_gpmc_s *s = (struct omap_gpmc_s *)
4408 qemu_mallocz(sizeof(struct omap_gpmc_s));
4409
4410 omap_gpmc_reset(s);
4411
4412 iomemtype = cpu_register_io_memory(0, omap_gpmc_readfn,
4413 omap_gpmc_writefn, s);
4414 cpu_register_physical_memory(base, 0x1000, iomemtype);
4415
4416 return s;
4417 }
4418
4419 void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
4420 void (*base_upd)(void *opaque, target_phys_addr_t new),
4421 void (*unmap)(void *opaque), void *opaque)
4422 {
4423 struct omap_gpmc_cs_file_s *f;
4424
4425 if (cs < 0 || cs >= 8) {
4426 fprintf(stderr, "%s: bad chip-select %i\n", __FUNCTION__, cs);
4427 exit(-1);
4428 }
4429 f = &s->cs_file[cs];
4430
4431 f->iomemtype = iomemtype;
4432 f->base_update = base_upd;
4433 f->unmap = unmap;
4434 f->opaque = opaque;
4435
4436 if (f->config[6] & (1 << 6)) /* CSVALID */
4437 omap_gpmc_cs_map(f, f->config[6] & 0x1f, /* MASKADDR */
4438 (f->config[6] >> 8 & 0xf)); /* BASEADDR */
4439 }
4440
4441 /* General chip reset */
4442 static void omap2_mpu_reset(void *opaque)
4443 {
4444 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
4445
4446 omap_inth_reset(mpu->ih[0]);
4447 omap_dma_reset(mpu->dma);
4448 omap_prcm_reset(mpu->prcm);
4449 omap_sysctl_reset(mpu->sysc);
4450 omap_gp_timer_reset(mpu->gptimer[0]);
4451 omap_gp_timer_reset(mpu->gptimer[1]);
4452 omap_gp_timer_reset(mpu->gptimer[2]);
4453 omap_gp_timer_reset(mpu->gptimer[3]);
4454 omap_gp_timer_reset(mpu->gptimer[4]);
4455 omap_gp_timer_reset(mpu->gptimer[5]);
4456 omap_gp_timer_reset(mpu->gptimer[6]);
4457 omap_gp_timer_reset(mpu->gptimer[7]);
4458 omap_gp_timer_reset(mpu->gptimer[8]);
4459 omap_gp_timer_reset(mpu->gptimer[9]);
4460 omap_gp_timer_reset(mpu->gptimer[10]);
4461 omap_gp_timer_reset(mpu->gptimer[11]);
4462 omap_synctimer_reset(&mpu->synctimer);
4463 omap_sdrc_reset(mpu->sdrc);
4464 omap_gpmc_reset(mpu->gpmc);
4465 omap_dss_reset(mpu->dss);
4466 omap_uart_reset(mpu->uart[0]);
4467 omap_uart_reset(mpu->uart[1]);
4468 omap_uart_reset(mpu->uart[2]);
4469 omap_mmc_reset(mpu->mmc);
4470 omap_gpif_reset(mpu->gpif);
4471 omap_mcspi_reset(mpu->mcspi[0]);
4472 omap_mcspi_reset(mpu->mcspi[1]);
4473 omap_i2c_reset(mpu->i2c[0]);
4474 omap_i2c_reset(mpu->i2c[1]);
4475 cpu_reset(mpu->env);
4476 }
4477
4478 static int omap2_validate_addr(struct omap_mpu_state_s *s,
4479 target_phys_addr_t addr)
4480 {
4481 return 1;
4482 }
4483
4484 static const struct dma_irq_map omap2_dma_irq_map[] = {
4485 { 0, OMAP_INT_24XX_SDMA_IRQ0 },
4486 { 0, OMAP_INT_24XX_SDMA_IRQ1 },
4487 { 0, OMAP_INT_24XX_SDMA_IRQ2 },
4488 { 0, OMAP_INT_24XX_SDMA_IRQ3 },
4489 };
4490
4491 struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
4492 const char *core)
4493 {
4494 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
4495 qemu_mallocz(sizeof(struct omap_mpu_state_s));
4496 ram_addr_t sram_base, q2_base;
4497 qemu_irq *cpu_irq;
4498 qemu_irq dma_irqs[4];
4499 omap_clk gpio_clks[4];
4500 int sdindex;
4501 int i;
4502
4503 /* Core */
4504 s->mpu_model = omap2420;
4505 s->env = cpu_init(core ?: "arm1136-r2");
4506 if (!s->env) {
4507 fprintf(stderr, "Unable to find CPU definition\n");
4508 exit(1);
4509 }
4510 s->sdram_size = sdram_size;
4511 s->sram_size = OMAP242X_SRAM_SIZE;
4512
4513 s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0];
4514
4515 /* Clocks */
4516 omap_clk_init(s);
4517
4518 /* Memory-mapped stuff */
4519 cpu_register_physical_memory(OMAP2_Q2_BASE, s->sdram_size,
4520 (q2_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM);
4521 cpu_register_physical_memory(OMAP2_SRAM_BASE, s->sram_size,
4522 (sram_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM);
4523
4524 s->l4 = omap_l4_init(OMAP2_L4_BASE, 54);
4525
4526 /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
4527 cpu_irq = arm_pic_init_cpu(s->env);
4528 s->ih[0] = omap2_inth_init(0x480fe000, 0x1000, 3, &s->irq[0],
4529 cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ],
4530 omap_findclk(s, "mpu_intc_fclk"),
4531 omap_findclk(s, "mpu_intc_iclk"));
4532
4533 s->prcm = omap_prcm_init(omap_l4tao(s->l4, 3),
4534 s->irq[0][OMAP_INT_24XX_PRCM_MPU_IRQ], NULL, NULL, s);
4535
4536 s->sysc = omap_sysctl_init(omap_l4tao(s->l4, 1),
4537 omap_findclk(s, "omapctrl_iclk"), s);
4538
4539 for (i = 0; i < 4; i ++)
4540 dma_irqs[i] =
4541 s->irq[omap2_dma_irq_map[i].ih][omap2_dma_irq_map[i].intr];
4542 s->dma = omap_dma4_init(0x48056000, dma_irqs, s, 256, 32,
4543 omap_findclk(s, "sdma_iclk"),
4544 omap_findclk(s, "sdma_fclk"));
4545 s->port->addr_valid = omap2_validate_addr;
4546
4547 /* Register SDRAM and SRAM ports for fast DMA transfers. */
4548 soc_dma_port_add_mem_ram(s->dma, q2_base, OMAP2_Q2_BASE, s->sdram_size);
4549 soc_dma_port_add_mem_ram(s->dma, sram_base, OMAP2_SRAM_BASE, s->sram_size);
4550
4551 s->uart[0] = omap2_uart_init(omap_l4ta(s->l4, 19),
4552 s->irq[0][OMAP_INT_24XX_UART1_IRQ],
4553 omap_findclk(s, "uart1_fclk"),
4554 omap_findclk(s, "uart1_iclk"),
4555 s->drq[OMAP24XX_DMA_UART1_TX],
4556 s->drq[OMAP24XX_DMA_UART1_RX], serial_hds[0]);
4557 s->uart[1] = omap2_uart_init(omap_l4ta(s->l4, 20),
4558 s->irq[0][OMAP_INT_24XX_UART2_IRQ],
4559 omap_findclk(s, "uart2_fclk"),
4560 omap_findclk(s, "uart2_iclk"),
4561 s->drq[OMAP24XX_DMA_UART2_TX],
4562 s->drq[OMAP24XX_DMA_UART2_RX],
4563 serial_hds[0] ? serial_hds[1] : 0);
4564 s->uart[2] = omap2_uart_init(omap_l4ta(s->l4, 21),
4565 s->irq[0][OMAP_INT_24XX_UART3_IRQ],
4566 omap_findclk(s, "uart3_fclk"),
4567 omap_findclk(s, "uart3_iclk"),
4568 s->drq[OMAP24XX_DMA_UART3_TX],
4569 s->drq[OMAP24XX_DMA_UART3_RX],
4570 serial_hds[0] && serial_hds[1] ? serial_hds[2] : 0);
4571
4572 s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7),
4573 s->irq[0][OMAP_INT_24XX_GPTIMER1],
4574 omap_findclk(s, "wu_gpt1_clk"),
4575 omap_findclk(s, "wu_l4_iclk"));
4576 s->gptimer[1] = omap_gp_timer_init(omap_l4ta(s->l4, 8),
4577 s->irq[0][OMAP_INT_24XX_GPTIMER2],
4578 omap_findclk(s, "core_gpt2_clk"),
4579 omap_findclk(s, "core_l4_iclk"));
4580 s->gptimer[2] = omap_gp_timer_init(omap_l4ta(s->l4, 22),
4581 s->irq[0][OMAP_INT_24XX_GPTIMER3],
4582 omap_findclk(s, "core_gpt3_clk"),
4583 omap_findclk(s, "core_l4_iclk"));
4584 s->gptimer[3] = omap_gp_timer_init(omap_l4ta(s->l4, 23),
4585 s->irq[0][OMAP_INT_24XX_GPTIMER4],
4586 omap_findclk(s, "core_gpt4_clk"),
4587 omap_findclk(s, "core_l4_iclk"));
4588 s->gptimer[4] = omap_gp_timer_init(omap_l4ta(s->l4, 24),
4589 s->irq[0][OMAP_INT_24XX_GPTIMER5],
4590 omap_findclk(s, "core_gpt5_clk"),
4591 omap_findclk(s, "core_l4_iclk"));
4592 s->gptimer[5] = omap_gp_timer_init(omap_l4ta(s->l4, 25),
4593 s->irq[0][OMAP_INT_24XX_GPTIMER6],
4594 omap_findclk(s, "core_gpt6_clk"),
4595 omap_findclk(s, "core_l4_iclk"));
4596 s->gptimer[6] = omap_gp_timer_init(omap_l4ta(s->l4, 26),
4597 s->irq[0][OMAP_INT_24XX_GPTIMER7],
4598 omap_findclk(s, "core_gpt7_clk"),
4599 omap_findclk(s, "core_l4_iclk"));
4600 s->gptimer[7] = omap_gp_timer_init(omap_l4ta(s->l4, 27),
4601 s->irq[0][OMAP_INT_24XX_GPTIMER8],
4602 omap_findclk(s, "core_gpt8_clk"),
4603 omap_findclk(s, "core_l4_iclk"));
4604 s->gptimer[8] = omap_gp_timer_init(omap_l4ta(s->l4, 28),
4605 s->irq[0][OMAP_INT_24XX_GPTIMER9],
4606 omap_findclk(s, "core_gpt9_clk"),
4607 omap_findclk(s, "core_l4_iclk"));
4608 s->gptimer[9] = omap_gp_timer_init(omap_l4ta(s->l4, 29),
4609 s->irq[0][OMAP_INT_24XX_GPTIMER10],
4610 omap_findclk(s, "core_gpt10_clk"),
4611 omap_findclk(s, "core_l4_iclk"));
4612 s->gptimer[10] = omap_gp_timer_init(omap_l4ta(s->l4, 30),
4613 s->irq[0][OMAP_INT_24XX_GPTIMER11],
4614 omap_findclk(s, "core_gpt11_clk"),
4615 omap_findclk(s, "core_l4_iclk"));
4616 s->gptimer[11] = omap_gp_timer_init(omap_l4ta(s->l4, 31),
4617 s->irq[0][OMAP_INT_24XX_GPTIMER12],
4618 omap_findclk(s, "core_gpt12_clk"),
4619 omap_findclk(s, "core_l4_iclk"));
4620
4621 omap_tap_init(omap_l4ta(s->l4, 2), s);
4622
4623 omap_synctimer_init(omap_l4tao(s->l4, 2), s,
4624 omap_findclk(s, "clk32-kHz"),
4625 omap_findclk(s, "core_l4_iclk"));
4626
4627 s->i2c[0] = omap2_i2c_init(omap_l4tao(s->l4, 5),
4628 s->irq[0][OMAP_INT_24XX_I2C1_IRQ],
4629 &s->drq[OMAP24XX_DMA_I2C1_TX],
4630 omap_findclk(s, "i2c1.fclk"),
4631 omap_findclk(s, "i2c1.iclk"));
4632 s->i2c[1] = omap2_i2c_init(omap_l4tao(s->l4, 6),
4633 s->irq[0][OMAP_INT_24XX_I2C2_IRQ],
4634 &s->drq[OMAP24XX_DMA_I2C2_TX],
4635 omap_findclk(s, "i2c2.fclk"),
4636 omap_findclk(s, "i2c2.iclk"));
4637
4638 gpio_clks[0] = omap_findclk(s, "gpio1_dbclk");
4639 gpio_clks[1] = omap_findclk(s, "gpio2_dbclk");
4640 gpio_clks[2] = omap_findclk(s, "gpio3_dbclk");
4641 gpio_clks[3] = omap_findclk(s, "gpio4_dbclk");
4642 s->gpif = omap2_gpio_init(omap_l4ta(s->l4, 3),
4643 &s->irq[0][OMAP_INT_24XX_GPIO_BANK1],
4644 gpio_clks, omap_findclk(s, "gpio_iclk"), 4);
4645
4646 s->sdrc = omap_sdrc_init(0x68009000);
4647 s->gpmc = omap_gpmc_init(0x6800a000, s->irq[0][OMAP_INT_24XX_GPMC_IRQ]);
4648
4649 sdindex = drive_get_index(IF_SD, 0, 0);
4650 if (sdindex == -1) {
4651 fprintf(stderr, "qemu: missing SecureDigital device\n");
4652 exit(1);
4653 }
4654 s->mmc = omap2_mmc_init(omap_l4tao(s->l4, 9), drives_table[sdindex].bdrv,
4655 s->irq[0][OMAP_INT_24XX_MMC_IRQ],
4656 &s->drq[OMAP24XX_DMA_MMC1_TX],
4657 omap_findclk(s, "mmc_fclk"), omap_findclk(s, "mmc_iclk"));
4658
4659 s->mcspi[0] = omap_mcspi_init(omap_l4ta(s->l4, 35), 4,
4660 s->irq[0][OMAP_INT_24XX_MCSPI1_IRQ],
4661 &s->drq[OMAP24XX_DMA_SPI1_TX0],
4662 omap_findclk(s, "spi1_fclk"),
4663 omap_findclk(s, "spi1_iclk"));
4664 s->mcspi[1] = omap_mcspi_init(omap_l4ta(s->l4, 36), 2,
4665 s->irq[0][OMAP_INT_24XX_MCSPI2_IRQ],
4666 &s->drq[OMAP24XX_DMA_SPI2_TX0],
4667 omap_findclk(s, "spi2_fclk"),
4668 omap_findclk(s, "spi2_iclk"));
4669
4670 s->dss = omap_dss_init(omap_l4ta(s->l4, 10), 0x68000800,
4671 /* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */
4672 s->irq[0][OMAP_INT_24XX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS],
4673 omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"),
4674 omap_findclk(s, "dss_54m_clk"),
4675 omap_findclk(s, "dss_l3_iclk"),
4676 omap_findclk(s, "dss_l4_iclk"));
4677
4678 omap_sti_init(omap_l4ta(s->l4, 18), 0x54000000,
4679 s->irq[0][OMAP_INT_24XX_STI], omap_findclk(s, "emul_ck"),
4680 serial_hds[0] && serial_hds[1] && serial_hds[2] ?
4681 serial_hds[3] : 0);
4682
4683 s->eac = omap_eac_init(omap_l4ta(s->l4, 32),
4684 s->irq[0][OMAP_INT_24XX_EAC_IRQ],
4685 /* Ten consecutive lines */
4686 &s->drq[OMAP24XX_DMA_EAC_AC_RD],
4687 omap_findclk(s, "func_96m_clk"),
4688 omap_findclk(s, "core_l4_iclk"));
4689
4690 /* All register mappings (includin those not currenlty implemented):
4691 * SystemControlMod 48000000 - 48000fff
4692 * SystemControlL4 48001000 - 48001fff
4693 * 32kHz Timer Mod 48004000 - 48004fff
4694 * 32kHz Timer L4 48005000 - 48005fff
4695 * PRCM ModA 48008000 - 480087ff
4696 * PRCM ModB 48008800 - 48008fff
4697 * PRCM L4 48009000 - 48009fff
4698 * TEST-BCM Mod 48012000 - 48012fff
4699 * TEST-BCM L4 48013000 - 48013fff
4700 * TEST-TAP Mod 48014000 - 48014fff
4701 * TEST-TAP L4 48015000 - 48015fff
4702 * GPIO1 Mod 48018000 - 48018fff
4703 * GPIO Top 48019000 - 48019fff
4704 * GPIO2 Mod 4801a000 - 4801afff
4705 * GPIO L4 4801b000 - 4801bfff
4706 * GPIO3 Mod 4801c000 - 4801cfff
4707 * GPIO4 Mod 4801e000 - 4801efff
4708 * WDTIMER1 Mod 48020000 - 48010fff
4709 * WDTIMER Top 48021000 - 48011fff
4710 * WDTIMER2 Mod 48022000 - 48012fff
4711 * WDTIMER L4 48023000 - 48013fff
4712 * WDTIMER3 Mod 48024000 - 48014fff
4713 * WDTIMER3 L4 48025000 - 48015fff
4714 * WDTIMER4 Mod 48026000 - 48016fff
4715 * WDTIMER4 L4 48027000 - 48017fff
4716 * GPTIMER1 Mod 48028000 - 48018fff
4717 * GPTIMER1 L4 48029000 - 48019fff
4718 * GPTIMER2 Mod 4802a000 - 4801afff
4719 * GPTIMER2 L4 4802b000 - 4801bfff
4720 * L4-Config AP 48040000 - 480407ff
4721 * L4-Config IP 48040800 - 48040fff
4722 * L4-Config LA 48041000 - 48041fff
4723 * ARM11ETB Mod 48048000 - 48049fff
4724 * ARM11ETB L4 4804a000 - 4804afff
4725 * DISPLAY Top 48050000 - 480503ff
4726 * DISPLAY DISPC 48050400 - 480507ff
4727 * DISPLAY RFBI 48050800 - 48050bff
4728 * DISPLAY VENC 48050c00 - 48050fff
4729 * DISPLAY L4 48051000 - 48051fff
4730 * CAMERA Top 48052000 - 480523ff
4731 * CAMERA core 48052400 - 480527ff
4732 * CAMERA DMA 48052800 - 48052bff
4733 * CAMERA MMU 48052c00 - 48052fff
4734 * CAMERA L4 48053000 - 48053fff
4735 * SDMA Mod 48056000 - 48056fff
4736 * SDMA L4 48057000 - 48057fff
4737 * SSI Top 48058000 - 48058fff
4738 * SSI GDD 48059000 - 48059fff
4739 * SSI Port1 4805a000 - 4805afff
4740 * SSI Port2 4805b000 - 4805bfff
4741 * SSI L4 4805c000 - 4805cfff
4742 * USB Mod 4805e000 - 480fefff
4743 * USB L4 4805f000 - 480fffff
4744 * WIN_TRACER1 Mod 48060000 - 48060fff
4745 * WIN_TRACER1 L4 48061000 - 48061fff
4746 * WIN_TRACER2 Mod 48062000 - 48062fff
4747 * WIN_TRACER2 L4 48063000 - 48063fff
4748 * WIN_TRACER3 Mod 48064000 - 48064fff
4749 * WIN_TRACER3 L4 48065000 - 48065fff
4750 * WIN_TRACER4 Top 48066000 - 480660ff
4751 * WIN_TRACER4 ETT 48066100 - 480661ff
4752 * WIN_TRACER4 WT 48066200 - 480662ff
4753 * WIN_TRACER4 L4 48067000 - 48067fff
4754 * XTI Mod 48068000 - 48068fff
4755 * XTI L4 48069000 - 48069fff
4756 * UART1 Mod 4806a000 - 4806afff
4757 * UART1 L4 4806b000 - 4806bfff
4758 * UART2 Mod 4806c000 - 4806cfff
4759 * UART2 L4 4806d000 - 4806dfff
4760 * UART3 Mod 4806e000 - 4806efff
4761 * UART3 L4 4806f000 - 4806ffff
4762 * I2C1 Mod 48070000 - 48070fff
4763 * I2C1 L4 48071000 - 48071fff
4764 * I2C2 Mod 48072000 - 48072fff
4765 * I2C2 L4 48073000 - 48073fff
4766 * McBSP1 Mod 48074000 - 48074fff
4767 * McBSP1 L4 48075000 - 48075fff
4768 * McBSP2 Mod 48076000 - 48076fff
4769 * McBSP2 L4 48077000 - 48077fff
4770 * GPTIMER3 Mod 48078000 - 48078fff
4771 * GPTIMER3 L4 48079000 - 48079fff
4772 * GPTIMER4 Mod 4807a000 - 4807afff
4773 * GPTIMER4 L4 4807b000 - 4807bfff
4774 * GPTIMER5 Mod 4807c000 - 4807cfff
4775 * GPTIMER5 L4 4807d000 - 4807dfff
4776 * GPTIMER6 Mod 4807e000 - 4807efff
4777 * GPTIMER6 L4 4807f000 - 4807ffff
4778 * GPTIMER7 Mod 48080000 - 48080fff
4779 * GPTIMER7 L4 48081000 - 48081fff
4780 * GPTIMER8 Mod 48082000 - 48082fff
4781 * GPTIMER8 L4 48083000 - 48083fff
4782 * GPTIMER9 Mod 48084000 - 48084fff
4783 * GPTIMER9 L4 48085000 - 48085fff
4784 * GPTIMER10 Mod 48086000 - 48086fff
4785 * GPTIMER10 L4 48087000 - 48087fff
4786 * GPTIMER11 Mod 48088000 - 48088fff
4787 * GPTIMER11 L4 48089000 - 48089fff
4788 * GPTIMER12 Mod 4808a000 - 4808afff
4789 * GPTIMER12 L4 4808b000 - 4808bfff
4790 * EAC Mod 48090000 - 48090fff
4791 * EAC L4 48091000 - 48091fff
4792 * FAC Mod 48092000 - 48092fff
4793 * FAC L4 48093000 - 48093fff
4794 * MAILBOX Mod 48094000 - 48094fff
4795 * MAILBOX L4 48095000 - 48095fff
4796 * SPI1 Mod 48098000 - 48098fff
4797 * SPI1 L4 48099000 - 48099fff
4798 * SPI2 Mod 4809a000 - 4809afff
4799 * SPI2 L4 4809b000 - 4809bfff
4800 * MMC/SDIO Mod 4809c000 - 4809cfff
4801 * MMC/SDIO L4 4809d000 - 4809dfff
4802 * MS_PRO Mod 4809e000 - 4809efff
4803 * MS_PRO L4 4809f000 - 4809ffff
4804 * RNG Mod 480a0000 - 480a0fff
4805 * RNG L4 480a1000 - 480a1fff
4806 * DES3DES Mod 480a2000 - 480a2fff
4807 * DES3DES L4 480a3000 - 480a3fff
4808 * SHA1MD5 Mod 480a4000 - 480a4fff
4809 * SHA1MD5 L4 480a5000 - 480a5fff
4810 * AES Mod 480a6000 - 480a6fff
4811 * AES L4 480a7000 - 480a7fff
4812 * PKA Mod 480a8000 - 480a9fff
4813 * PKA L4 480aa000 - 480aafff
4814 * MG Mod 480b0000 - 480b0fff
4815 * MG L4 480b1000 - 480b1fff
4816 * HDQ/1-wire Mod 480b2000 - 480b2fff
4817 * HDQ/1-wire L4 480b3000 - 480b3fff
4818 * MPU interrupt 480fe000 - 480fefff
4819 * STI channel base 54000000 - 5400ffff
4820 * IVA RAM 5c000000 - 5c01ffff
4821 * IVA ROM 5c020000 - 5c027fff
4822 * IMG_BUF_A 5c040000 - 5c040fff
4823 * IMG_BUF_B 5c042000 - 5c042fff
4824 * VLCDS 5c048000 - 5c0487ff
4825 * IMX_COEF 5c049000 - 5c04afff
4826 * IMX_CMD 5c051000 - 5c051fff
4827 * VLCDQ 5c053000 - 5c0533ff
4828 * VLCDH 5c054000 - 5c054fff
4829 * SEQ_CMD 5c055000 - 5c055fff
4830 * IMX_REG 5c056000 - 5c0560ff
4831 * VLCD_REG 5c056100 - 5c0561ff
4832 * SEQ_REG 5c056200 - 5c0562ff
4833 * IMG_BUF_REG 5c056300 - 5c0563ff
4834 * SEQIRQ_REG 5c056400 - 5c0564ff
4835 * OCP_REG 5c060000 - 5c060fff
4836 * SYSC_REG 5c070000 - 5c070fff
4837 * MMU_REG 5d000000 - 5d000fff
4838 * sDMA R 68000400 - 680005ff
4839 * sDMA W 68000600 - 680007ff
4840 * Display Control 68000800 - 680009ff
4841 * DSP subsystem 68000a00 - 68000bff
4842 * MPU subsystem 68000c00 - 68000dff
4843 * IVA subsystem 68001000 - 680011ff
4844 * USB 68001200 - 680013ff
4845 * Camera 68001400 - 680015ff
4846 * VLYNQ (firewall) 68001800 - 68001bff
4847 * VLYNQ 68001e00 - 68001fff
4848 * SSI 68002000 - 680021ff
4849 * L4 68002400 - 680025ff
4850 * DSP (firewall) 68002800 - 68002bff
4851 * DSP subsystem 68002e00 - 68002fff
4852 * IVA (firewall) 68003000 - 680033ff
4853 * IVA 68003600 - 680037ff
4854 * GFX 68003a00 - 68003bff
4855 * CMDWR emulation 68003c00 - 68003dff
4856 * SMS 68004000 - 680041ff
4857 * OCM 68004200 - 680043ff
4858 * GPMC 68004400 - 680045ff
4859 * RAM (firewall) 68005000 - 680053ff
4860 * RAM (err login) 68005400 - 680057ff
4861 * ROM (firewall) 68005800 - 68005bff
4862 * ROM (err login) 68005c00 - 68005fff
4863 * GPMC (firewall) 68006000 - 680063ff
4864 * GPMC (err login) 68006400 - 680067ff
4865 * SMS (err login) 68006c00 - 68006fff
4866 * SMS registers 68008000 - 68008fff
4867 * SDRC registers 68009000 - 68009fff
4868 * GPMC registers 6800a000 6800afff
4869 */
4870
4871 qemu_register_reset(omap2_mpu_reset, 0, s);
4872
4873 return s;
4874 }
HPPA (PA-RISC) target for QEMU