?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Convert mulscc
[qemu/hppa.git] / hw / ppc405_uc.c
blobdfe1905c90b0c87b3422e46f8a1c6f693e0059e2
1 /*
2 * QEMU PowerPC 405 embedded processors emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "ppc.h"
26 #include "ppc405.h"
27 #include "pc.h"
28 #include "qemu-timer.h"
29 #include "sysemu.h"
30 #include "qemu-log.h"
31
32 #define DEBUG_OPBA
33 #define DEBUG_SDRAM
34 #define DEBUG_GPIO
35 #define DEBUG_SERIAL
36 #define DEBUG_OCM
37 //#define DEBUG_I2C
38 #define DEBUG_GPT
39 #define DEBUG_MAL
40 #define DEBUG_CLOCKS
41 //#define DEBUG_CLOCKS_LL
42
43 ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
44 uint32_t flags)
45 {
46 ram_addr_t bdloc;
47 int i, n;
48
49 /* We put the bd structure at the top of memory */
50 if (bd->bi_memsize >= 0x01000000UL)
51 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
52 else
53 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
54 stl_phys(bdloc + 0x00, bd->bi_memstart);
55 stl_phys(bdloc + 0x04, bd->bi_memsize);
56 stl_phys(bdloc + 0x08, bd->bi_flashstart);
57 stl_phys(bdloc + 0x0C, bd->bi_flashsize);
58 stl_phys(bdloc + 0x10, bd->bi_flashoffset);
59 stl_phys(bdloc + 0x14, bd->bi_sramstart);
60 stl_phys(bdloc + 0x18, bd->bi_sramsize);
61 stl_phys(bdloc + 0x1C, bd->bi_bootflags);
62 stl_phys(bdloc + 0x20, bd->bi_ipaddr);
63 for (i = 0; i < 6; i++)
64 stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);
65 stw_phys(bdloc + 0x2A, bd->bi_ethspeed);
66 stl_phys(bdloc + 0x2C, bd->bi_intfreq);
67 stl_phys(bdloc + 0x30, bd->bi_busfreq);
68 stl_phys(bdloc + 0x34, bd->bi_baudrate);
69 for (i = 0; i < 4; i++)
70 stb_phys(bdloc + 0x38 + i, bd->bi_s_version[i]);
71 for (i = 0; i < 32; i++)
72 stb_phys(bdloc + 0x3C + i, bd->bi_s_version[i]);
73 stl_phys(bdloc + 0x5C, bd->bi_plb_busfreq);
74 stl_phys(bdloc + 0x60, bd->bi_pci_busfreq);
75 for (i = 0; i < 6; i++)
76 stb_phys(bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
77 n = 0x6A;
78 if (flags & 0x00000001) {
79 for (i = 0; i < 6; i++)
80 stb_phys(bdloc + n++, bd->bi_pci_enetaddr2[i]);
81 }
82 stl_phys(bdloc + n, bd->bi_opbfreq);
83 n += 4;
84 for (i = 0; i < 2; i++) {
85 stl_phys(bdloc + n, bd->bi_iic_fast[i]);
86 n += 4;
87 }
88
89 return bdloc;
90 }
91
92 /*****************************************************************************/
93 /* Shared peripherals */
94
95 /*****************************************************************************/
96 /* Peripheral local bus arbitrer */
97 enum {
98 PLB0_BESR = 0x084,
99 PLB0_BEAR = 0x086,
100 PLB0_ACR = 0x087,
101 };
102
103 typedef struct ppc4xx_plb_t ppc4xx_plb_t;
104 struct ppc4xx_plb_t {
105 uint32_t acr;
106 uint32_t bear;
107 uint32_t besr;
108 };
109
110 static target_ulong dcr_read_plb (void *opaque, int dcrn)
111 {
112 ppc4xx_plb_t *plb;
113 target_ulong ret;
114
115 plb = opaque;
116 switch (dcrn) {
117 case PLB0_ACR:
118 ret = plb->acr;
119 break;
120 case PLB0_BEAR:
121 ret = plb->bear;
122 break;
123 case PLB0_BESR:
124 ret = plb->besr;
125 break;
126 default:
127 /* Avoid gcc warning */
128 ret = 0;
129 break;
130 }
131
132 return ret;
133 }
134
135 static void dcr_write_plb (void *opaque, int dcrn, target_ulong val)
136 {
137 ppc4xx_plb_t *plb;
138
139 plb = opaque;
140 switch (dcrn) {
141 case PLB0_ACR:
142 /* We don't care about the actual parameters written as
143 * we don't manage any priorities on the bus
144 */
145 plb->acr = val & 0xF8000000;
146 break;
147 case PLB0_BEAR:
148 /* Read only */
149 break;
150 case PLB0_BESR:
151 /* Write-clear */
152 plb->besr &= ~val;
153 break;
154 }
155 }
156
157 static void ppc4xx_plb_reset (void *opaque)
158 {
159 ppc4xx_plb_t *plb;
160
161 plb = opaque;
162 plb->acr = 0x00000000;
163 plb->bear = 0x00000000;
164 plb->besr = 0x00000000;
165 }
166
167 void ppc4xx_plb_init (CPUState *env)
168 {
169 ppc4xx_plb_t *plb;
170
171 plb = qemu_mallocz(sizeof(ppc4xx_plb_t));
172 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
173 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
174 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
175 ppc4xx_plb_reset(plb);
176 qemu_register_reset(ppc4xx_plb_reset, plb);
177 }
178
179 /*****************************************************************************/
180 /* PLB to OPB bridge */
181 enum {
182 POB0_BESR0 = 0x0A0,
183 POB0_BESR1 = 0x0A2,
184 POB0_BEAR = 0x0A4,
185 };
186
187 typedef struct ppc4xx_pob_t ppc4xx_pob_t;
188 struct ppc4xx_pob_t {
189 uint32_t bear;
190 uint32_t besr[2];
191 };
192
193 static target_ulong dcr_read_pob (void *opaque, int dcrn)
194 {
195 ppc4xx_pob_t *pob;
196 target_ulong ret;
197
198 pob = opaque;
199 switch (dcrn) {
200 case POB0_BEAR:
201 ret = pob->bear;
202 break;
203 case POB0_BESR0:
204 case POB0_BESR1:
205 ret = pob->besr[dcrn - POB0_BESR0];
206 break;
207 default:
208 /* Avoid gcc warning */
209 ret = 0;
210 break;
211 }
212
213 return ret;
214 }
215
216 static void dcr_write_pob (void *opaque, int dcrn, target_ulong val)
217 {
218 ppc4xx_pob_t *pob;
219
220 pob = opaque;
221 switch (dcrn) {
222 case POB0_BEAR:
223 /* Read only */
224 break;
225 case POB0_BESR0:
226 case POB0_BESR1:
227 /* Write-clear */
228 pob->besr[dcrn - POB0_BESR0] &= ~val;
229 break;
230 }
231 }
232
233 static void ppc4xx_pob_reset (void *opaque)
234 {
235 ppc4xx_pob_t *pob;
236
237 pob = opaque;
238 /* No error */
239 pob->bear = 0x00000000;
240 pob->besr[0] = 0x0000000;
241 pob->besr[1] = 0x0000000;
242 }
243
244 void ppc4xx_pob_init (CPUState *env)
245 {
246 ppc4xx_pob_t *pob;
247
248 pob = qemu_mallocz(sizeof(ppc4xx_pob_t));
249 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
250 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
251 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
252 qemu_register_reset(ppc4xx_pob_reset, pob);
253 ppc4xx_pob_reset(env);
254 }
255
256 /*****************************************************************************/
257 /* OPB arbitrer */
258 typedef struct ppc4xx_opba_t ppc4xx_opba_t;
259 struct ppc4xx_opba_t {
260 target_phys_addr_t base;
261 uint8_t cr;
262 uint8_t pr;
263 };
264
265 static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
266 {
267 ppc4xx_opba_t *opba;
268 uint32_t ret;
269
270 #ifdef DEBUG_OPBA
271 printf("%s: addr " PADDRX "\n", __func__, addr);
272 #endif
273 opba = opaque;
274 switch (addr - opba->base) {
275 case 0x00:
276 ret = opba->cr;
277 break;
278 case 0x01:
279 ret = opba->pr;
280 break;
281 default:
282 ret = 0x00;
283 break;
284 }
285
286 return ret;
287 }
288
289 static void opba_writeb (void *opaque,
290 target_phys_addr_t addr, uint32_t value)
291 {
292 ppc4xx_opba_t *opba;
293
294 #ifdef DEBUG_OPBA
295 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
296 #endif
297 opba = opaque;
298 switch (addr - opba->base) {
299 case 0x00:
300 opba->cr = value & 0xF8;
301 break;
302 case 0x01:
303 opba->pr = value & 0xFF;
304 break;
305 default:
306 break;
307 }
308 }
309
310 static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)
311 {
312 uint32_t ret;
313
314 #ifdef DEBUG_OPBA
315 printf("%s: addr " PADDRX "\n", __func__, addr);
316 #endif
317 ret = opba_readb(opaque, addr) << 8;
318 ret |= opba_readb(opaque, addr + 1);
319
320 return ret;
321 }
322
323 static void opba_writew (void *opaque,
324 target_phys_addr_t addr, uint32_t value)
325 {
326 #ifdef DEBUG_OPBA
327 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
328 #endif
329 opba_writeb(opaque, addr, value >> 8);
330 opba_writeb(opaque, addr + 1, value);
331 }
332
333 static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)
334 {
335 uint32_t ret;
336
337 #ifdef DEBUG_OPBA
338 printf("%s: addr " PADDRX "\n", __func__, addr);
339 #endif
340 ret = opba_readb(opaque, addr) << 24;
341 ret |= opba_readb(opaque, addr + 1) << 16;
342
343 return ret;
344 }
345
346 static void opba_writel (void *opaque,
347 target_phys_addr_t addr, uint32_t value)
348 {
349 #ifdef DEBUG_OPBA
350 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
351 #endif
352 opba_writeb(opaque, addr, value >> 24);
353 opba_writeb(opaque, addr + 1, value >> 16);
354 }
355
356 static CPUReadMemoryFunc *opba_read[] = {
357 &opba_readb,
358 &opba_readw,
359 &opba_readl,
360 };
361
362 static CPUWriteMemoryFunc *opba_write[] = {
363 &opba_writeb,
364 &opba_writew,
365 &opba_writel,
366 };
367
368 static void ppc4xx_opba_reset (void *opaque)
369 {
370 ppc4xx_opba_t *opba;
371
372 opba = opaque;
373 opba->cr = 0x00; /* No dynamic priorities - park disabled */
374 opba->pr = 0x11;
375 }
376
377 void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
378 target_phys_addr_t offset)
379 {
380 ppc4xx_opba_t *opba;
381
382 opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
383 opba->base = offset;
384 #ifdef DEBUG_OPBA
385 printf("%s: offset " PADDRX "\n", __func__, offset);
386 #endif
387 ppc4xx_mmio_register(env, mmio, offset, 0x002,
388 opba_read, opba_write, opba);
389 qemu_register_reset(ppc4xx_opba_reset, opba);
390 ppc4xx_opba_reset(opba);
391 }
392
393 /*****************************************************************************/
394 /* Code decompression controller */
395 /* XXX: TODO */
396
397 /*****************************************************************************/
398 /* Peripheral controller */
399 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
400 struct ppc4xx_ebc_t {
401 uint32_t addr;
402 uint32_t bcr[8];
403 uint32_t bap[8];
404 uint32_t bear;
405 uint32_t besr0;
406 uint32_t besr1;
407 uint32_t cfg;
408 };
409
410 enum {
411 EBC0_CFGADDR = 0x012,
412 EBC0_CFGDATA = 0x013,
413 };
414
415 static target_ulong dcr_read_ebc (void *opaque, int dcrn)
416 {
417 ppc4xx_ebc_t *ebc;
418 target_ulong ret;
419
420 ebc = opaque;
421 switch (dcrn) {
422 case EBC0_CFGADDR:
423 ret = ebc->addr;
424 break;
425 case EBC0_CFGDATA:
426 switch (ebc->addr) {
427 case 0x00: /* B0CR */
428 ret = ebc->bcr[0];
429 break;
430 case 0x01: /* B1CR */
431 ret = ebc->bcr[1];
432 break;
433 case 0x02: /* B2CR */
434 ret = ebc->bcr[2];
435 break;
436 case 0x03: /* B3CR */
437 ret = ebc->bcr[3];
438 break;
439 case 0x04: /* B4CR */
440 ret = ebc->bcr[4];
441 break;
442 case 0x05: /* B5CR */
443 ret = ebc->bcr[5];
444 break;
445 case 0x06: /* B6CR */
446 ret = ebc->bcr[6];
447 break;
448 case 0x07: /* B7CR */
449 ret = ebc->bcr[7];
450 break;
451 case 0x10: /* B0AP */
452 ret = ebc->bap[0];
453 break;
454 case 0x11: /* B1AP */
455 ret = ebc->bap[1];
456 break;
457 case 0x12: /* B2AP */
458 ret = ebc->bap[2];
459 break;
460 case 0x13: /* B3AP */
461 ret = ebc->bap[3];
462 break;
463 case 0x14: /* B4AP */
464 ret = ebc->bap[4];
465 break;
466 case 0x15: /* B5AP */
467 ret = ebc->bap[5];
468 break;
469 case 0x16: /* B6AP */
470 ret = ebc->bap[6];
471 break;
472 case 0x17: /* B7AP */
473 ret = ebc->bap[7];
474 break;
475 case 0x20: /* BEAR */
476 ret = ebc->bear;
477 break;
478 case 0x21: /* BESR0 */
479 ret = ebc->besr0;
480 break;
481 case 0x22: /* BESR1 */
482 ret = ebc->besr1;
483 break;
484 case 0x23: /* CFG */
485 ret = ebc->cfg;
486 break;
487 default:
488 ret = 0x00000000;
489 break;
490 }
491 default:
492 ret = 0x00000000;
493 break;
494 }
495
496 return ret;
497 }
498
499 static void dcr_write_ebc (void *opaque, int dcrn, target_ulong val)
500 {
501 ppc4xx_ebc_t *ebc;
502
503 ebc = opaque;
504 switch (dcrn) {
505 case EBC0_CFGADDR:
506 ebc->addr = val;
507 break;
508 case EBC0_CFGDATA:
509 switch (ebc->addr) {
510 case 0x00: /* B0CR */
511 break;
512 case 0x01: /* B1CR */
513 break;
514 case 0x02: /* B2CR */
515 break;
516 case 0x03: /* B3CR */
517 break;
518 case 0x04: /* B4CR */
519 break;
520 case 0x05: /* B5CR */
521 break;
522 case 0x06: /* B6CR */
523 break;
524 case 0x07: /* B7CR */
525 break;
526 case 0x10: /* B0AP */
527 break;
528 case 0x11: /* B1AP */
529 break;
530 case 0x12: /* B2AP */
531 break;
532 case 0x13: /* B3AP */
533 break;
534 case 0x14: /* B4AP */
535 break;
536 case 0x15: /* B5AP */
537 break;
538 case 0x16: /* B6AP */
539 break;
540 case 0x17: /* B7AP */
541 break;
542 case 0x20: /* BEAR */
543 break;
544 case 0x21: /* BESR0 */
545 break;
546 case 0x22: /* BESR1 */
547 break;
548 case 0x23: /* CFG */
549 break;
550 default:
551 break;
552 }
553 break;
554 default:
555 break;
556 }
557 }
558
559 static void ebc_reset (void *opaque)
560 {
561 ppc4xx_ebc_t *ebc;
562 int i;
563
564 ebc = opaque;
565 ebc->addr = 0x00000000;
566 ebc->bap[0] = 0x7F8FFE80;
567 ebc->bcr[0] = 0xFFE28000;
568 for (i = 0; i < 8; i++) {
569 ebc->bap[i] = 0x00000000;
570 ebc->bcr[i] = 0x00000000;
571 }
572 ebc->besr0 = 0x00000000;
573 ebc->besr1 = 0x00000000;
574 ebc->cfg = 0x80400000;
575 }
576
577 void ppc405_ebc_init (CPUState *env)
578 {
579 ppc4xx_ebc_t *ebc;
580
581 ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
582 ebc_reset(ebc);
583 qemu_register_reset(&ebc_reset, ebc);
584 ppc_dcr_register(env, EBC0_CFGADDR,
585 ebc, &dcr_read_ebc, &dcr_write_ebc);
586 ppc_dcr_register(env, EBC0_CFGDATA,
587 ebc, &dcr_read_ebc, &dcr_write_ebc);
588 }
589
590 /*****************************************************************************/
591 /* DMA controller */
592 enum {
593 DMA0_CR0 = 0x100,
594 DMA0_CT0 = 0x101,
595 DMA0_DA0 = 0x102,
596 DMA0_SA0 = 0x103,
597 DMA0_SG0 = 0x104,
598 DMA0_CR1 = 0x108,
599 DMA0_CT1 = 0x109,
600 DMA0_DA1 = 0x10A,
601 DMA0_SA1 = 0x10B,
602 DMA0_SG1 = 0x10C,
603 DMA0_CR2 = 0x110,
604 DMA0_CT2 = 0x111,
605 DMA0_DA2 = 0x112,
606 DMA0_SA2 = 0x113,
607 DMA0_SG2 = 0x114,
608 DMA0_CR3 = 0x118,
609 DMA0_CT3 = 0x119,
610 DMA0_DA3 = 0x11A,
611 DMA0_SA3 = 0x11B,
612 DMA0_SG3 = 0x11C,
613 DMA0_SR = 0x120,
614 DMA0_SGC = 0x123,
615 DMA0_SLP = 0x125,
616 DMA0_POL = 0x126,
617 };
618
619 typedef struct ppc405_dma_t ppc405_dma_t;
620 struct ppc405_dma_t {
621 qemu_irq irqs[4];
622 uint32_t cr[4];
623 uint32_t ct[4];
624 uint32_t da[4];
625 uint32_t sa[4];
626 uint32_t sg[4];
627 uint32_t sr;
628 uint32_t sgc;
629 uint32_t slp;
630 uint32_t pol;
631 };
632
633 static target_ulong dcr_read_dma (void *opaque, int dcrn)
634 {
635 ppc405_dma_t *dma;
636
637 dma = opaque;
638
639 return 0;
640 }
641
642 static void dcr_write_dma (void *opaque, int dcrn, target_ulong val)
643 {
644 ppc405_dma_t *dma;
645
646 dma = opaque;
647 }
648
649 static void ppc405_dma_reset (void *opaque)
650 {
651 ppc405_dma_t *dma;
652 int i;
653
654 dma = opaque;
655 for (i = 0; i < 4; i++) {
656 dma->cr[i] = 0x00000000;
657 dma->ct[i] = 0x00000000;
658 dma->da[i] = 0x00000000;
659 dma->sa[i] = 0x00000000;
660 dma->sg[i] = 0x00000000;
661 }
662 dma->sr = 0x00000000;
663 dma->sgc = 0x00000000;
664 dma->slp = 0x7C000000;
665 dma->pol = 0x00000000;
666 }
667
668 void ppc405_dma_init (CPUState *env, qemu_irq irqs[4])
669 {
670 ppc405_dma_t *dma;
671
672 dma = qemu_mallocz(sizeof(ppc405_dma_t));
673 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
674 ppc405_dma_reset(dma);
675 qemu_register_reset(&ppc405_dma_reset, dma);
676 ppc_dcr_register(env, DMA0_CR0,
677 dma, &dcr_read_dma, &dcr_write_dma);
678 ppc_dcr_register(env, DMA0_CT0,
679 dma, &dcr_read_dma, &dcr_write_dma);
680 ppc_dcr_register(env, DMA0_DA0,
681 dma, &dcr_read_dma, &dcr_write_dma);
682 ppc_dcr_register(env, DMA0_SA0,
683 dma, &dcr_read_dma, &dcr_write_dma);
684 ppc_dcr_register(env, DMA0_SG0,
685 dma, &dcr_read_dma, &dcr_write_dma);
686 ppc_dcr_register(env, DMA0_CR1,
687 dma, &dcr_read_dma, &dcr_write_dma);
688 ppc_dcr_register(env, DMA0_CT1,
689 dma, &dcr_read_dma, &dcr_write_dma);
690 ppc_dcr_register(env, DMA0_DA1,
691 dma, &dcr_read_dma, &dcr_write_dma);
692 ppc_dcr_register(env, DMA0_SA1,
693 dma, &dcr_read_dma, &dcr_write_dma);
694 ppc_dcr_register(env, DMA0_SG1,
695 dma, &dcr_read_dma, &dcr_write_dma);
696 ppc_dcr_register(env, DMA0_CR2,
697 dma, &dcr_read_dma, &dcr_write_dma);
698 ppc_dcr_register(env, DMA0_CT2,
699 dma, &dcr_read_dma, &dcr_write_dma);
700 ppc_dcr_register(env, DMA0_DA2,
701 dma, &dcr_read_dma, &dcr_write_dma);
702 ppc_dcr_register(env, DMA0_SA2,
703 dma, &dcr_read_dma, &dcr_write_dma);
704 ppc_dcr_register(env, DMA0_SG2,
705 dma, &dcr_read_dma, &dcr_write_dma);
706 ppc_dcr_register(env, DMA0_CR3,
707 dma, &dcr_read_dma, &dcr_write_dma);
708 ppc_dcr_register(env, DMA0_CT3,
709 dma, &dcr_read_dma, &dcr_write_dma);
710 ppc_dcr_register(env, DMA0_DA3,
711 dma, &dcr_read_dma, &dcr_write_dma);
712 ppc_dcr_register(env, DMA0_SA3,
713 dma, &dcr_read_dma, &dcr_write_dma);
714 ppc_dcr_register(env, DMA0_SG3,
715 dma, &dcr_read_dma, &dcr_write_dma);
716 ppc_dcr_register(env, DMA0_SR,
717 dma, &dcr_read_dma, &dcr_write_dma);
718 ppc_dcr_register(env, DMA0_SGC,
719 dma, &dcr_read_dma, &dcr_write_dma);
720 ppc_dcr_register(env, DMA0_SLP,
721 dma, &dcr_read_dma, &dcr_write_dma);
722 ppc_dcr_register(env, DMA0_POL,
723 dma, &dcr_read_dma, &dcr_write_dma);
724 }
725
726 /*****************************************************************************/
727 /* GPIO */
728 typedef struct ppc405_gpio_t ppc405_gpio_t;
729 struct ppc405_gpio_t {
730 target_phys_addr_t base;
731 uint32_t or;
732 uint32_t tcr;
733 uint32_t osrh;
734 uint32_t osrl;
735 uint32_t tsrh;
736 uint32_t tsrl;
737 uint32_t odr;
738 uint32_t ir;
739 uint32_t rr1;
740 uint32_t isr1h;
741 uint32_t isr1l;
742 };
743
744 static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
745 {
746 ppc405_gpio_t *gpio;
747
748 gpio = opaque;
749 #ifdef DEBUG_GPIO
750 printf("%s: addr " PADDRX "\n", __func__, addr);
751 #endif
752
753 return 0;
754 }
755
756 static void ppc405_gpio_writeb (void *opaque,
757 target_phys_addr_t addr, uint32_t value)
758 {
759 ppc405_gpio_t *gpio;
760
761 gpio = opaque;
762 #ifdef DEBUG_GPIO
763 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
764 #endif
765 }
766
767 static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
768 {
769 ppc405_gpio_t *gpio;
770
771 gpio = opaque;
772 #ifdef DEBUG_GPIO
773 printf("%s: addr " PADDRX "\n", __func__, addr);
774 #endif
775
776 return 0;
777 }
778
779 static void ppc405_gpio_writew (void *opaque,
780 target_phys_addr_t addr, uint32_t value)
781 {
782 ppc405_gpio_t *gpio;
783
784 gpio = opaque;
785 #ifdef DEBUG_GPIO
786 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
787 #endif
788 }
789
790 static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
791 {
792 ppc405_gpio_t *gpio;
793
794 gpio = opaque;
795 #ifdef DEBUG_GPIO
796 printf("%s: addr " PADDRX "\n", __func__, addr);
797 #endif
798
799 return 0;
800 }
801
802 static void ppc405_gpio_writel (void *opaque,
803 target_phys_addr_t addr, uint32_t value)
804 {
805 ppc405_gpio_t *gpio;
806
807 gpio = opaque;
808 #ifdef DEBUG_GPIO
809 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
810 #endif
811 }
812
813 static CPUReadMemoryFunc *ppc405_gpio_read[] = {
814 &ppc405_gpio_readb,
815 &ppc405_gpio_readw,
816 &ppc405_gpio_readl,
817 };
818
819 static CPUWriteMemoryFunc *ppc405_gpio_write[] = {
820 &ppc405_gpio_writeb,
821 &ppc405_gpio_writew,
822 &ppc405_gpio_writel,
823 };
824
825 static void ppc405_gpio_reset (void *opaque)
826 {
827 ppc405_gpio_t *gpio;
828
829 gpio = opaque;
830 }
831
832 void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,
833 target_phys_addr_t offset)
834 {
835 ppc405_gpio_t *gpio;
836
837 gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
838 gpio->base = offset;
839 ppc405_gpio_reset(gpio);
840 qemu_register_reset(&ppc405_gpio_reset, gpio);
841 #ifdef DEBUG_GPIO
842 printf("%s: offset " PADDRX "\n", __func__, offset);
843 #endif
844 ppc4xx_mmio_register(env, mmio, offset, 0x038,
845 ppc405_gpio_read, ppc405_gpio_write, gpio);
846 }
847
848 /*****************************************************************************/
849 /* Serial ports */
850 static CPUReadMemoryFunc *serial_mm_read[] = {
851 &serial_mm_readb,
852 &serial_mm_readw,
853 &serial_mm_readl,
854 };
855
856 static CPUWriteMemoryFunc *serial_mm_write[] = {
857 &serial_mm_writeb,
858 &serial_mm_writew,
859 &serial_mm_writel,
860 };
861
862 void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
863 target_phys_addr_t offset, qemu_irq irq,
864 CharDriverState *chr)
865 {
866 void *serial;
867
868 #ifdef DEBUG_SERIAL
869 printf("%s: offset " PADDRX "\n", __func__, offset);
870 #endif
871 serial = serial_mm_init(offset, 0, irq, 399193, chr, 0);
872 ppc4xx_mmio_register(env, mmio, offset, 0x008,
873 serial_mm_read, serial_mm_write, serial);
874 }
875
876 /*****************************************************************************/
877 /* On Chip Memory */
878 enum {
879 OCM0_ISARC = 0x018,
880 OCM0_ISACNTL = 0x019,
881 OCM0_DSARC = 0x01A,
882 OCM0_DSACNTL = 0x01B,
883 };
884
885 typedef struct ppc405_ocm_t ppc405_ocm_t;
886 struct ppc405_ocm_t {
887 target_ulong offset;
888 uint32_t isarc;
889 uint32_t isacntl;
890 uint32_t dsarc;
891 uint32_t dsacntl;
892 };
893
894 static void ocm_update_mappings (ppc405_ocm_t *ocm,
895 uint32_t isarc, uint32_t isacntl,
896 uint32_t dsarc, uint32_t dsacntl)
897 {
898 #ifdef DEBUG_OCM
899 printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32
900 " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32
901 " (%08" PRIx32 " %08" PRIx32 ")\n",
902 isarc, isacntl, dsarc, dsacntl,
903 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
904 #endif
905 if (ocm->isarc != isarc ||
906 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
907 if (ocm->isacntl & 0x80000000) {
908 /* Unmap previously assigned memory region */
909 printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
910 cpu_register_physical_memory(ocm->isarc, 0x04000000,
911 IO_MEM_UNASSIGNED);
912 }
913 if (isacntl & 0x80000000) {
914 /* Map new instruction memory region */
915 #ifdef DEBUG_OCM
916 printf("OCM map ISA %08" PRIx32 "\n", isarc);
917 #endif
918 cpu_register_physical_memory(isarc, 0x04000000,
919 ocm->offset | IO_MEM_RAM);
920 }
921 }
922 if (ocm->dsarc != dsarc ||
923 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
924 if (ocm->dsacntl & 0x80000000) {
925 /* Beware not to unmap the region we just mapped */
926 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
927 /* Unmap previously assigned memory region */
928 #ifdef DEBUG_OCM
929 printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
930 #endif
931 cpu_register_physical_memory(ocm->dsarc, 0x04000000,
932 IO_MEM_UNASSIGNED);
933 }
934 }
935 if (dsacntl & 0x80000000) {
936 /* Beware not to remap the region we just mapped */
937 if (!(isacntl & 0x80000000) || dsarc != isarc) {
938 /* Map new data memory region */
939 #ifdef DEBUG_OCM
940 printf("OCM map DSA %08" PRIx32 "\n", dsarc);
941 #endif
942 cpu_register_physical_memory(dsarc, 0x04000000,
943 ocm->offset | IO_MEM_RAM);
944 }
945 }
946 }
947 }
948
949 static target_ulong dcr_read_ocm (void *opaque, int dcrn)
950 {
951 ppc405_ocm_t *ocm;
952 target_ulong ret;
953
954 ocm = opaque;
955 switch (dcrn) {
956 case OCM0_ISARC:
957 ret = ocm->isarc;
958 break;
959 case OCM0_ISACNTL:
960 ret = ocm->isacntl;
961 break;
962 case OCM0_DSARC:
963 ret = ocm->dsarc;
964 break;
965 case OCM0_DSACNTL:
966 ret = ocm->dsacntl;
967 break;
968 default:
969 ret = 0;
970 break;
971 }
972
973 return ret;
974 }
975
976 static void dcr_write_ocm (void *opaque, int dcrn, target_ulong val)
977 {
978 ppc405_ocm_t *ocm;
979 uint32_t isarc, dsarc, isacntl, dsacntl;
980
981 ocm = opaque;
982 isarc = ocm->isarc;
983 dsarc = ocm->dsarc;
984 isacntl = ocm->isacntl;
985 dsacntl = ocm->dsacntl;
986 switch (dcrn) {
987 case OCM0_ISARC:
988 isarc = val & 0xFC000000;
989 break;
990 case OCM0_ISACNTL:
991 isacntl = val & 0xC0000000;
992 break;
993 case OCM0_DSARC:
994 isarc = val & 0xFC000000;
995 break;
996 case OCM0_DSACNTL:
997 isacntl = val & 0xC0000000;
998 break;
999 }
1000 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
1001 ocm->isarc = isarc;
1002 ocm->dsarc = dsarc;
1003 ocm->isacntl = isacntl;
1004 ocm->dsacntl = dsacntl;
1005 }
1006
1007 static void ocm_reset (void *opaque)
1008 {
1009 ppc405_ocm_t *ocm;
1010 uint32_t isarc, dsarc, isacntl, dsacntl;
1011
1012 ocm = opaque;
1013 isarc = 0x00000000;
1014 isacntl = 0x00000000;
1015 dsarc = 0x00000000;
1016 dsacntl = 0x00000000;
1017 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
1018 ocm->isarc = isarc;
1019 ocm->dsarc = dsarc;
1020 ocm->isacntl = isacntl;
1021 ocm->dsacntl = dsacntl;
1022 }
1023
1024 void ppc405_ocm_init (CPUState *env)
1025 {
1026 ppc405_ocm_t *ocm;
1027
1028 ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
1029 ocm->offset = qemu_ram_alloc(4096);
1030 ocm_reset(ocm);
1031 qemu_register_reset(&ocm_reset, ocm);
1032 ppc_dcr_register(env, OCM0_ISARC,
1033 ocm, &dcr_read_ocm, &dcr_write_ocm);
1034 ppc_dcr_register(env, OCM0_ISACNTL,
1035 ocm, &dcr_read_ocm, &dcr_write_ocm);
1036 ppc_dcr_register(env, OCM0_DSARC,
1037 ocm, &dcr_read_ocm, &dcr_write_ocm);
1038 ppc_dcr_register(env, OCM0_DSACNTL,
1039 ocm, &dcr_read_ocm, &dcr_write_ocm);
1040 }
1041
1042 /*****************************************************************************/
1043 /* I2C controller */
1044 typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
1045 struct ppc4xx_i2c_t {
1046 target_phys_addr_t base;
1047 qemu_irq irq;
1048 uint8_t mdata;
1049 uint8_t lmadr;
1050 uint8_t hmadr;
1051 uint8_t cntl;
1052 uint8_t mdcntl;
1053 uint8_t sts;
1054 uint8_t extsts;
1055 uint8_t sdata;
1056 uint8_t lsadr;
1057 uint8_t hsadr;
1058 uint8_t clkdiv;
1059 uint8_t intrmsk;
1060 uint8_t xfrcnt;
1061 uint8_t xtcntlss;
1062 uint8_t directcntl;
1063 };
1064
1065 static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
1066 {
1067 ppc4xx_i2c_t *i2c;
1068 uint32_t ret;
1069
1070 #ifdef DEBUG_I2C
1071 printf("%s: addr " PADDRX "\n", __func__, addr);
1072 #endif
1073 i2c = opaque;
1074 switch (addr - i2c->base) {
1075 case 0x00:
1076 // i2c_readbyte(&i2c->mdata);
1077 ret = i2c->mdata;
1078 break;
1079 case 0x02:
1080 ret = i2c->sdata;
1081 break;
1082 case 0x04:
1083 ret = i2c->lmadr;
1084 break;
1085 case 0x05:
1086 ret = i2c->hmadr;
1087 break;
1088 case 0x06:
1089 ret = i2c->cntl;
1090 break;
1091 case 0x07:
1092 ret = i2c->mdcntl;
1093 break;
1094 case 0x08:
1095 ret = i2c->sts;
1096 break;
1097 case 0x09:
1098 ret = i2c->extsts;
1099 break;
1100 case 0x0A:
1101 ret = i2c->lsadr;
1102 break;
1103 case 0x0B:
1104 ret = i2c->hsadr;
1105 break;
1106 case 0x0C:
1107 ret = i2c->clkdiv;
1108 break;
1109 case 0x0D:
1110 ret = i2c->intrmsk;
1111 break;
1112 case 0x0E:
1113 ret = i2c->xfrcnt;
1114 break;
1115 case 0x0F:
1116 ret = i2c->xtcntlss;
1117 break;
1118 case 0x10:
1119 ret = i2c->directcntl;
1120 break;
1121 default:
1122 ret = 0x00;
1123 break;
1124 }
1125 #ifdef DEBUG_I2C
1126 printf("%s: addr " PADDRX " %02" PRIx32 "\n", __func__, addr, ret);
1127 #endif
1128
1129 return ret;
1130 }
1131
1132 static void ppc4xx_i2c_writeb (void *opaque,
1133 target_phys_addr_t addr, uint32_t value)
1134 {
1135 ppc4xx_i2c_t *i2c;
1136
1137 #ifdef DEBUG_I2C
1138 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
1139 #endif
1140 i2c = opaque;
1141 switch (addr - i2c->base) {
1142 case 0x00:
1143 i2c->mdata = value;
1144 // i2c_sendbyte(&i2c->mdata);
1145 break;
1146 case 0x02:
1147 i2c->sdata = value;
1148 break;
1149 case 0x04:
1150 i2c->lmadr = value;
1151 break;
1152 case 0x05:
1153 i2c->hmadr = value;
1154 break;
1155 case 0x06:
1156 i2c->cntl = value;
1157 break;
1158 case 0x07:
1159 i2c->mdcntl = value & 0xDF;
1160 break;
1161 case 0x08:
1162 i2c->sts &= ~(value & 0x0A);
1163 break;
1164 case 0x09:
1165 i2c->extsts &= ~(value & 0x8F);
1166 break;
1167 case 0x0A:
1168 i2c->lsadr = value;
1169 break;
1170 case 0x0B:
1171 i2c->hsadr = value;
1172 break;
1173 case 0x0C:
1174 i2c->clkdiv = value;
1175 break;
1176 case 0x0D:
1177 i2c->intrmsk = value;
1178 break;
1179 case 0x0E:
1180 i2c->xfrcnt = value & 0x77;
1181 break;
1182 case 0x0F:
1183 i2c->xtcntlss = value;
1184 break;
1185 case 0x10:
1186 i2c->directcntl = value & 0x7;
1187 break;
1188 }
1189 }
1190
1191 static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr)
1192 {
1193 uint32_t ret;
1194
1195 #ifdef DEBUG_I2C
1196 printf("%s: addr " PADDRX "\n", __func__, addr);
1197 #endif
1198 ret = ppc4xx_i2c_readb(opaque, addr) << 8;
1199 ret |= ppc4xx_i2c_readb(opaque, addr + 1);
1200
1201 return ret;
1202 }
1203
1204 static void ppc4xx_i2c_writew (void *opaque,
1205 target_phys_addr_t addr, uint32_t value)
1206 {
1207 #ifdef DEBUG_I2C
1208 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
1209 #endif
1210 ppc4xx_i2c_writeb(opaque, addr, value >> 8);
1211 ppc4xx_i2c_writeb(opaque, addr + 1, value);
1212 }
1213
1214 static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr)
1215 {
1216 uint32_t ret;
1217
1218 #ifdef DEBUG_I2C
1219 printf("%s: addr " PADDRX "\n", __func__, addr);
1220 #endif
1221 ret = ppc4xx_i2c_readb(opaque, addr) << 24;
1222 ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
1223 ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;
1224 ret |= ppc4xx_i2c_readb(opaque, addr + 3);
1225
1226 return ret;
1227 }
1228
1229 static void ppc4xx_i2c_writel (void *opaque,
1230 target_phys_addr_t addr, uint32_t value)
1231 {
1232 #ifdef DEBUG_I2C
1233 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
1234 #endif
1235 ppc4xx_i2c_writeb(opaque, addr, value >> 24);
1236 ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
1237 ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);
1238 ppc4xx_i2c_writeb(opaque, addr + 3, value);
1239 }
1240
1241 static CPUReadMemoryFunc *i2c_read[] = {
1242 &ppc4xx_i2c_readb,
1243 &ppc4xx_i2c_readw,
1244 &ppc4xx_i2c_readl,
1245 };
1246
1247 static CPUWriteMemoryFunc *i2c_write[] = {
1248 &ppc4xx_i2c_writeb,
1249 &ppc4xx_i2c_writew,
1250 &ppc4xx_i2c_writel,
1251 };
1252
1253 static void ppc4xx_i2c_reset (void *opaque)
1254 {
1255 ppc4xx_i2c_t *i2c;
1256
1257 i2c = opaque;
1258 i2c->mdata = 0x00;
1259 i2c->sdata = 0x00;
1260 i2c->cntl = 0x00;
1261 i2c->mdcntl = 0x00;
1262 i2c->sts = 0x00;
1263 i2c->extsts = 0x00;
1264 i2c->clkdiv = 0x00;
1265 i2c->xfrcnt = 0x00;
1266 i2c->directcntl = 0x0F;
1267 }
1268
1269 void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio,
1270 target_phys_addr_t offset, qemu_irq irq)
1271 {
1272 ppc4xx_i2c_t *i2c;
1273
1274 i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
1275 i2c->base = offset;
1276 i2c->irq = irq;
1277 ppc4xx_i2c_reset(i2c);
1278 #ifdef DEBUG_I2C
1279 printf("%s: offset " PADDRX "\n", __func__, offset);
1280 #endif
1281 ppc4xx_mmio_register(env, mmio, offset, 0x011,
1282 i2c_read, i2c_write, i2c);
1283 qemu_register_reset(ppc4xx_i2c_reset, i2c);
1284 }
1285
1286 /*****************************************************************************/
1287 /* General purpose timers */
1288 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
1289 struct ppc4xx_gpt_t {
1290 target_phys_addr_t base;
1291 int64_t tb_offset;
1292 uint32_t tb_freq;
1293 struct QEMUTimer *timer;
1294 qemu_irq irqs[5];
1295 uint32_t oe;
1296 uint32_t ol;
1297 uint32_t im;
1298 uint32_t is;
1299 uint32_t ie;
1300 uint32_t comp[5];
1301 uint32_t mask[5];
1302 };
1303
1304 static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr)
1305 {
1306 #ifdef DEBUG_GPT
1307 printf("%s: addr " PADDRX "\n", __func__, addr);
1308 #endif
1309 /* XXX: generate a bus fault */
1310 return -1;
1311 }
1312
1313 static void ppc4xx_gpt_writeb (void *opaque,
1314 target_phys_addr_t addr, uint32_t value)
1315 {
1316 #ifdef DEBUG_I2C
1317 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
1318 #endif
1319 /* XXX: generate a bus fault */
1320 }
1321
1322 static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr)
1323 {
1324 #ifdef DEBUG_GPT
1325 printf("%s: addr " PADDRX "\n", __func__, addr);
1326 #endif
1327 /* XXX: generate a bus fault */
1328 return -1;
1329 }
1330
1331 static void ppc4xx_gpt_writew (void *opaque,
1332 target_phys_addr_t addr, uint32_t value)
1333 {
1334 #ifdef DEBUG_I2C
1335 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
1336 #endif
1337 /* XXX: generate a bus fault */
1338 }
1339
1340 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
1341 {
1342 /* XXX: TODO */
1343 return 0;
1344 }
1345
1346 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
1347 {
1348 /* XXX: TODO */
1349 }
1350
1351 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
1352 {
1353 uint32_t mask;
1354 int i;
1355
1356 mask = 0x80000000;
1357 for (i = 0; i < 5; i++) {
1358 if (gpt->oe & mask) {
1359 /* Output is enabled */
1360 if (ppc4xx_gpt_compare(gpt, i)) {
1361 /* Comparison is OK */
1362 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask);
1363 } else {
1364 /* Comparison is KO */
1365 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1);
1366 }
1367 }
1368 mask = mask >> 1;
1369 }
1370 }
1371
1372 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
1373 {
1374 uint32_t mask;
1375 int i;
1376
1377 mask = 0x00008000;
1378 for (i = 0; i < 5; i++) {
1379 if (gpt->is & gpt->im & mask)
1380 qemu_irq_raise(gpt->irqs[i]);
1381 else
1382 qemu_irq_lower(gpt->irqs[i]);
1383 mask = mask >> 1;
1384 }
1385 }
1386
1387 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
1388 {
1389 /* XXX: TODO */
1390 }
1391
1392 static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
1393 {
1394 ppc4xx_gpt_t *gpt;
1395 uint32_t ret;
1396 int idx;
1397
1398 #ifdef DEBUG_GPT
1399 printf("%s: addr " PADDRX "\n", __func__, addr);
1400 #endif
1401 gpt = opaque;
1402 switch (addr - gpt->base) {
1403 case 0x00:
1404 /* Time base counter */
1405 ret = muldiv64(qemu_get_clock(vm_clock) + gpt->tb_offset,
1406 gpt->tb_freq, ticks_per_sec);
1407 break;
1408 case 0x10:
1409 /* Output enable */
1410 ret = gpt->oe;
1411 break;
1412 case 0x14:
1413 /* Output level */
1414 ret = gpt->ol;
1415 break;
1416 case 0x18:
1417 /* Interrupt mask */
1418 ret = gpt->im;
1419 break;
1420 case 0x1C:
1421 case 0x20:
1422 /* Interrupt status */
1423 ret = gpt->is;
1424 break;
1425 case 0x24:
1426 /* Interrupt enable */
1427 ret = gpt->ie;
1428 break;
1429 case 0x80 ... 0x90:
1430 /* Compare timer */
1431 idx = ((addr - gpt->base) - 0x80) >> 2;
1432 ret = gpt->comp[idx];
1433 break;
1434 case 0xC0 ... 0xD0:
1435 /* Compare mask */
1436 idx = ((addr - gpt->base) - 0xC0) >> 2;
1437 ret = gpt->mask[idx];
1438 break;
1439 default:
1440 ret = -1;
1441 break;
1442 }
1443
1444 return ret;
1445 }
1446
1447 static void ppc4xx_gpt_writel (void *opaque,
1448 target_phys_addr_t addr, uint32_t value)
1449 {
1450 ppc4xx_gpt_t *gpt;
1451 int idx;
1452
1453 #ifdef DEBUG_I2C
1454 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
1455 #endif
1456 gpt = opaque;
1457 switch (addr - gpt->base) {
1458 case 0x00:
1459 /* Time base counter */
1460 gpt->tb_offset = muldiv64(value, ticks_per_sec, gpt->tb_freq)
1461 - qemu_get_clock(vm_clock);
1462 ppc4xx_gpt_compute_timer(gpt);
1463 break;
1464 case 0x10:
1465 /* Output enable */
1466 gpt->oe = value & 0xF8000000;
1467 ppc4xx_gpt_set_outputs(gpt);
1468 break;
1469 case 0x14:
1470 /* Output level */
1471 gpt->ol = value & 0xF8000000;
1472 ppc4xx_gpt_set_outputs(gpt);
1473 break;
1474 case 0x18:
1475 /* Interrupt mask */
1476 gpt->im = value & 0x0000F800;
1477 break;
1478 case 0x1C:
1479 /* Interrupt status set */
1480 gpt->is |= value & 0x0000F800;
1481 ppc4xx_gpt_set_irqs(gpt);
1482 break;
1483 case 0x20:
1484 /* Interrupt status clear */
1485 gpt->is &= ~(value & 0x0000F800);
1486 ppc4xx_gpt_set_irqs(gpt);
1487 break;
1488 case 0x24:
1489 /* Interrupt enable */
1490 gpt->ie = value & 0x0000F800;
1491 ppc4xx_gpt_set_irqs(gpt);
1492 break;
1493 case 0x80 ... 0x90:
1494 /* Compare timer */
1495 idx = ((addr - gpt->base) - 0x80) >> 2;
1496 gpt->comp[idx] = value & 0xF8000000;
1497 ppc4xx_gpt_compute_timer(gpt);
1498 break;
1499 case 0xC0 ... 0xD0:
1500 /* Compare mask */
1501 idx = ((addr - gpt->base) - 0xC0) >> 2;
1502 gpt->mask[idx] = value & 0xF8000000;
1503 ppc4xx_gpt_compute_timer(gpt);
1504 break;
1505 }
1506 }
1507
1508 static CPUReadMemoryFunc *gpt_read[] = {
1509 &ppc4xx_gpt_readb,
1510 &ppc4xx_gpt_readw,
1511 &ppc4xx_gpt_readl,
1512 };
1513
1514 static CPUWriteMemoryFunc *gpt_write[] = {
1515 &ppc4xx_gpt_writeb,
1516 &ppc4xx_gpt_writew,
1517 &ppc4xx_gpt_writel,
1518 };
1519
1520 static void ppc4xx_gpt_cb (void *opaque)
1521 {
1522 ppc4xx_gpt_t *gpt;
1523
1524 gpt = opaque;
1525 ppc4xx_gpt_set_irqs(gpt);
1526 ppc4xx_gpt_set_outputs(gpt);
1527 ppc4xx_gpt_compute_timer(gpt);
1528 }
1529
1530 static void ppc4xx_gpt_reset (void *opaque)
1531 {
1532 ppc4xx_gpt_t *gpt;
1533 int i;
1534
1535 gpt = opaque;
1536 qemu_del_timer(gpt->timer);
1537 gpt->oe = 0x00000000;
1538 gpt->ol = 0x00000000;
1539 gpt->im = 0x00000000;
1540 gpt->is = 0x00000000;
1541 gpt->ie = 0x00000000;
1542 for (i = 0; i < 5; i++) {
1543 gpt->comp[i] = 0x00000000;
1544 gpt->mask[i] = 0x00000000;
1545 }
1546 }
1547
1548 void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
1549 target_phys_addr_t offset, qemu_irq irqs[5])
1550 {
1551 ppc4xx_gpt_t *gpt;
1552 int i;
1553
1554 gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
1555 gpt->base = offset;
1556 for (i = 0; i < 5; i++)
1557 gpt->irqs[i] = irqs[i];
1558 gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt);
1559 ppc4xx_gpt_reset(gpt);
1560 #ifdef DEBUG_GPT
1561 printf("%s: offset " PADDRX "\n", __func__, offset);
1562 #endif
1563 ppc4xx_mmio_register(env, mmio, offset, 0x0D4,
1564 gpt_read, gpt_write, gpt);
1565 qemu_register_reset(ppc4xx_gpt_reset, gpt);
1566 }
1567
1568 /*****************************************************************************/
1569 /* MAL */
1570 enum {
1571 MAL0_CFG = 0x180,
1572 MAL0_ESR = 0x181,
1573 MAL0_IER = 0x182,
1574 MAL0_TXCASR = 0x184,
1575 MAL0_TXCARR = 0x185,
1576 MAL0_TXEOBISR = 0x186,
1577 MAL0_TXDEIR = 0x187,
1578 MAL0_RXCASR = 0x190,
1579 MAL0_RXCARR = 0x191,
1580 MAL0_RXEOBISR = 0x192,
1581 MAL0_RXDEIR = 0x193,
1582 MAL0_TXCTP0R = 0x1A0,
1583 MAL0_TXCTP1R = 0x1A1,
1584 MAL0_TXCTP2R = 0x1A2,
1585 MAL0_TXCTP3R = 0x1A3,
1586 MAL0_RXCTP0R = 0x1C0,
1587 MAL0_RXCTP1R = 0x1C1,
1588 MAL0_RCBS0 = 0x1E0,
1589 MAL0_RCBS1 = 0x1E1,
1590 };
1591
1592 typedef struct ppc40x_mal_t ppc40x_mal_t;
1593 struct ppc40x_mal_t {
1594 qemu_irq irqs[4];
1595 uint32_t cfg;
1596 uint32_t esr;
1597 uint32_t ier;
1598 uint32_t txcasr;
1599 uint32_t txcarr;
1600 uint32_t txeobisr;
1601 uint32_t txdeir;
1602 uint32_t rxcasr;
1603 uint32_t rxcarr;
1604 uint32_t rxeobisr;
1605 uint32_t rxdeir;
1606 uint32_t txctpr[4];
1607 uint32_t rxctpr[2];
1608 uint32_t rcbs[2];
1609 };
1610
1611 static void ppc40x_mal_reset (void *opaque);
1612
1613 static target_ulong dcr_read_mal (void *opaque, int dcrn)
1614 {
1615 ppc40x_mal_t *mal;
1616 target_ulong ret;
1617
1618 mal = opaque;
1619 switch (dcrn) {
1620 case MAL0_CFG:
1621 ret = mal->cfg;
1622 break;
1623 case MAL0_ESR:
1624 ret = mal->esr;
1625 break;
1626 case MAL0_IER:
1627 ret = mal->ier;
1628 break;
1629 case MAL0_TXCASR:
1630 ret = mal->txcasr;
1631 break;
1632 case MAL0_TXCARR:
1633 ret = mal->txcarr;
1634 break;
1635 case MAL0_TXEOBISR:
1636 ret = mal->txeobisr;
1637 break;
1638 case MAL0_TXDEIR:
1639 ret = mal->txdeir;
1640 break;
1641 case MAL0_RXCASR:
1642 ret = mal->rxcasr;
1643 break;
1644 case MAL0_RXCARR:
1645 ret = mal->rxcarr;
1646 break;
1647 case MAL0_RXEOBISR:
1648 ret = mal->rxeobisr;
1649 break;
1650 case MAL0_RXDEIR:
1651 ret = mal->rxdeir;
1652 break;
1653 case MAL0_TXCTP0R:
1654 ret = mal->txctpr[0];
1655 break;
1656 case MAL0_TXCTP1R:
1657 ret = mal->txctpr[1];
1658 break;
1659 case MAL0_TXCTP2R:
1660 ret = mal->txctpr[2];
1661 break;
1662 case MAL0_TXCTP3R:
1663 ret = mal->txctpr[3];
1664 break;
1665 case MAL0_RXCTP0R:
1666 ret = mal->rxctpr[0];
1667 break;
1668 case MAL0_RXCTP1R:
1669 ret = mal->rxctpr[1];
1670 break;
1671 case MAL0_RCBS0:
1672 ret = mal->rcbs[0];
1673 break;
1674 case MAL0_RCBS1:
1675 ret = mal->rcbs[1];
1676 break;
1677 default:
1678 ret = 0;
1679 break;
1680 }
1681
1682 return ret;
1683 }
1684
1685 static void dcr_write_mal (void *opaque, int dcrn, target_ulong val)
1686 {
1687 ppc40x_mal_t *mal;
1688 int idx;
1689
1690 mal = opaque;
1691 switch (dcrn) {
1692 case MAL0_CFG:
1693 if (val & 0x80000000)
1694 ppc40x_mal_reset(mal);
1695 mal->cfg = val & 0x00FFC087;
1696 break;
1697 case MAL0_ESR:
1698 /* Read/clear */
1699 mal->esr &= ~val;
1700 break;
1701 case MAL0_IER:
1702 mal->ier = val & 0x0000001F;
1703 break;
1704 case MAL0_TXCASR:
1705 mal->txcasr = val & 0xF0000000;
1706 break;
1707 case MAL0_TXCARR:
1708 mal->txcarr = val & 0xF0000000;
1709 break;
1710 case MAL0_TXEOBISR:
1711 /* Read/clear */
1712 mal->txeobisr &= ~val;
1713 break;
1714 case MAL0_TXDEIR:
1715 /* Read/clear */
1716 mal->txdeir &= ~val;
1717 break;
1718 case MAL0_RXCASR:
1719 mal->rxcasr = val & 0xC0000000;
1720 break;
1721 case MAL0_RXCARR:
1722 mal->rxcarr = val & 0xC0000000;
1723 break;
1724 case MAL0_RXEOBISR:
1725 /* Read/clear */
1726 mal->rxeobisr &= ~val;
1727 break;
1728 case MAL0_RXDEIR:
1729 /* Read/clear */
1730 mal->rxdeir &= ~val;
1731 break;
1732 case MAL0_TXCTP0R:
1733 idx = 0;
1734 goto update_tx_ptr;
1735 case MAL0_TXCTP1R:
1736 idx = 1;
1737 goto update_tx_ptr;
1738 case MAL0_TXCTP2R:
1739 idx = 2;
1740 goto update_tx_ptr;
1741 case MAL0_TXCTP3R:
1742 idx = 3;
1743 update_tx_ptr:
1744 mal->txctpr[idx] = val;
1745 break;
1746 case MAL0_RXCTP0R:
1747 idx = 0;
1748 goto update_rx_ptr;
1749 case MAL0_RXCTP1R:
1750 idx = 1;
1751 update_rx_ptr:
1752 mal->rxctpr[idx] = val;
1753 break;
1754 case MAL0_RCBS0:
1755 idx = 0;
1756 goto update_rx_size;
1757 case MAL0_RCBS1:
1758 idx = 1;
1759 update_rx_size:
1760 mal->rcbs[idx] = val & 0x000000FF;
1761 break;
1762 }
1763 }
1764
1765 static void ppc40x_mal_reset (void *opaque)
1766 {
1767 ppc40x_mal_t *mal;
1768
1769 mal = opaque;
1770 mal->cfg = 0x0007C000;
1771 mal->esr = 0x00000000;
1772 mal->ier = 0x00000000;
1773 mal->rxcasr = 0x00000000;
1774 mal->rxdeir = 0x00000000;
1775 mal->rxeobisr = 0x00000000;
1776 mal->txcasr = 0x00000000;
1777 mal->txdeir = 0x00000000;
1778 mal->txeobisr = 0x00000000;
1779 }
1780
1781 void ppc405_mal_init (CPUState *env, qemu_irq irqs[4])
1782 {
1783 ppc40x_mal_t *mal;
1784 int i;
1785
1786 mal = qemu_mallocz(sizeof(ppc40x_mal_t));
1787 for (i = 0; i < 4; i++)
1788 mal->irqs[i] = irqs[i];
1789 ppc40x_mal_reset(mal);
1790 qemu_register_reset(&ppc40x_mal_reset, mal);
1791 ppc_dcr_register(env, MAL0_CFG,
1792 mal, &dcr_read_mal, &dcr_write_mal);
1793 ppc_dcr_register(env, MAL0_ESR,
1794 mal, &dcr_read_mal, &dcr_write_mal);
1795 ppc_dcr_register(env, MAL0_IER,
1796 mal, &dcr_read_mal, &dcr_write_mal);
1797 ppc_dcr_register(env, MAL0_TXCASR,
1798 mal, &dcr_read_mal, &dcr_write_mal);
1799 ppc_dcr_register(env, MAL0_TXCARR,
1800 mal, &dcr_read_mal, &dcr_write_mal);
1801 ppc_dcr_register(env, MAL0_TXEOBISR,
1802 mal, &dcr_read_mal, &dcr_write_mal);
1803 ppc_dcr_register(env, MAL0_TXDEIR,
1804 mal, &dcr_read_mal, &dcr_write_mal);
1805 ppc_dcr_register(env, MAL0_RXCASR,
1806 mal, &dcr_read_mal, &dcr_write_mal);
1807 ppc_dcr_register(env, MAL0_RXCARR,
1808 mal, &dcr_read_mal, &dcr_write_mal);
1809 ppc_dcr_register(env, MAL0_RXEOBISR,
1810 mal, &dcr_read_mal, &dcr_write_mal);
1811 ppc_dcr_register(env, MAL0_RXDEIR,
1812 mal, &dcr_read_mal, &dcr_write_mal);
1813 ppc_dcr_register(env, MAL0_TXCTP0R,
1814 mal, &dcr_read_mal, &dcr_write_mal);
1815 ppc_dcr_register(env, MAL0_TXCTP1R,
1816 mal, &dcr_read_mal, &dcr_write_mal);
1817 ppc_dcr_register(env, MAL0_TXCTP2R,
1818 mal, &dcr_read_mal, &dcr_write_mal);
1819 ppc_dcr_register(env, MAL0_TXCTP3R,
1820 mal, &dcr_read_mal, &dcr_write_mal);
1821 ppc_dcr_register(env, MAL0_RXCTP0R,
1822 mal, &dcr_read_mal, &dcr_write_mal);
1823 ppc_dcr_register(env, MAL0_RXCTP1R,
1824 mal, &dcr_read_mal, &dcr_write_mal);
1825 ppc_dcr_register(env, MAL0_RCBS0,
1826 mal, &dcr_read_mal, &dcr_write_mal);
1827 ppc_dcr_register(env, MAL0_RCBS1,
1828 mal, &dcr_read_mal, &dcr_write_mal);
1829 }
1830
1831 /*****************************************************************************/
1832 /* SPR */
1833 void ppc40x_core_reset (CPUState *env)
1834 {
1835 target_ulong dbsr;
1836
1837 printf("Reset PowerPC core\n");
1838 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1839 /* XXX: TOFIX */
1840 #if 0
1841 cpu_ppc_reset(env);
1842 #else
1843 qemu_system_reset_request();
1844 #endif
1845 dbsr = env->spr[SPR_40x_DBSR];
1846 dbsr &= ~0x00000300;
1847 dbsr |= 0x00000100;
1848 env->spr[SPR_40x_DBSR] = dbsr;
1849 }
1850
1851 void ppc40x_chip_reset (CPUState *env)
1852 {
1853 target_ulong dbsr;
1854
1855 printf("Reset PowerPC chip\n");
1856 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1857 /* XXX: TOFIX */
1858 #if 0
1859 cpu_ppc_reset(env);
1860 #else
1861 qemu_system_reset_request();
1862 #endif
1863 /* XXX: TODO reset all internal peripherals */
1864 dbsr = env->spr[SPR_40x_DBSR];
1865 dbsr &= ~0x00000300;
1866 dbsr |= 0x00000200;
1867 env->spr[SPR_40x_DBSR] = dbsr;
1868 }
1869
1870 void ppc40x_system_reset (CPUState *env)
1871 {
1872 printf("Reset PowerPC system\n");
1873 qemu_system_reset_request();
1874 }
1875
1876 void store_40x_dbcr0 (CPUState *env, uint32_t val)
1877 {
1878 switch ((val >> 28) & 0x3) {
1879 case 0x0:
1880 /* No action */
1881 break;
1882 case 0x1:
1883 /* Core reset */
1884 ppc40x_core_reset(env);
1885 break;
1886 case 0x2:
1887 /* Chip reset */
1888 ppc40x_chip_reset(env);
1889 break;
1890 case 0x3:
1891 /* System reset */
1892 ppc40x_system_reset(env);
1893 break;
1894 }
1895 }
1896
1897 /*****************************************************************************/
1898 /* PowerPC 405CR */
1899 enum {
1900 PPC405CR_CPC0_PLLMR = 0x0B0,
1901 PPC405CR_CPC0_CR0 = 0x0B1,
1902 PPC405CR_CPC0_CR1 = 0x0B2,
1903 PPC405CR_CPC0_PSR = 0x0B4,
1904 PPC405CR_CPC0_JTAGID = 0x0B5,
1905 PPC405CR_CPC0_ER = 0x0B9,
1906 PPC405CR_CPC0_FR = 0x0BA,
1907 PPC405CR_CPC0_SR = 0x0BB,
1908 };
1909
1910 enum {
1911 PPC405CR_CPU_CLK = 0,
1912 PPC405CR_TMR_CLK = 1,
1913 PPC405CR_PLB_CLK = 2,
1914 PPC405CR_SDRAM_CLK = 3,
1915 PPC405CR_OPB_CLK = 4,
1916 PPC405CR_EXT_CLK = 5,
1917 PPC405CR_UART_CLK = 6,
1918 PPC405CR_CLK_NB = 7,
1919 };
1920
1921 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
1922 struct ppc405cr_cpc_t {
1923 clk_setup_t clk_setup[PPC405CR_CLK_NB];
1924 uint32_t sysclk;
1925 uint32_t psr;
1926 uint32_t cr0;
1927 uint32_t cr1;
1928 uint32_t jtagid;
1929 uint32_t pllmr;
1930 uint32_t er;
1931 uint32_t fr;
1932 };
1933
1934 static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
1935 {
1936 uint64_t VCO_out, PLL_out;
1937 uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk;
1938 int M, D0, D1, D2;
1939
1940 D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */
1941 if (cpc->pllmr & 0x80000000) {
1942 D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */
1943 D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */
1944 M = D0 * D1 * D2;
1945 VCO_out = cpc->sysclk * M;
1946 if (VCO_out < 400000000 || VCO_out > 800000000) {
1947 /* PLL cannot lock */
1948 cpc->pllmr &= ~0x80000000;
1949 goto bypass_pll;
1950 }
1951 PLL_out = VCO_out / D2;
1952 } else {
1953 /* Bypass PLL */
1954 bypass_pll:
1955 M = D0;
1956 PLL_out = cpc->sysclk * M;
1957 }
1958 CPU_clk = PLL_out;
1959 if (cpc->cr1 & 0x00800000)
1960 TMR_clk = cpc->sysclk; /* Should have a separate clock */
1961 else
1962 TMR_clk = CPU_clk;
1963 PLB_clk = CPU_clk / D0;
1964 SDRAM_clk = PLB_clk;
1965 D0 = ((cpc->pllmr >> 10) & 0x3) + 1;
1966 OPB_clk = PLB_clk / D0;
1967 D0 = ((cpc->pllmr >> 24) & 0x3) + 2;
1968 EXT_clk = PLB_clk / D0;
1969 D0 = ((cpc->cr0 >> 1) & 0x1F) + 1;
1970 UART_clk = CPU_clk / D0;
1971 /* Setup CPU clocks */
1972 clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk);
1973 /* Setup time-base clock */
1974 clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk);
1975 /* Setup PLB clock */
1976 clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk);
1977 /* Setup SDRAM clock */
1978 clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk);
1979 /* Setup OPB clock */
1980 clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk);
1981 /* Setup external clock */
1982 clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk);
1983 /* Setup UART clock */
1984 clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
1985 }
1986
1987 static target_ulong dcr_read_crcpc (void *opaque, int dcrn)
1988 {
1989 ppc405cr_cpc_t *cpc;
1990 target_ulong ret;
1991
1992 cpc = opaque;
1993 switch (dcrn) {
1994 case PPC405CR_CPC0_PLLMR:
1995 ret = cpc->pllmr;
1996 break;
1997 case PPC405CR_CPC0_CR0:
1998 ret = cpc->cr0;
1999 break;
2000 case PPC405CR_CPC0_CR1:
2001 ret = cpc->cr1;
2002 break;
2003 case PPC405CR_CPC0_PSR:
2004 ret = cpc->psr;
2005 break;
2006 case PPC405CR_CPC0_JTAGID:
2007 ret = cpc->jtagid;
2008 break;
2009 case PPC405CR_CPC0_ER:
2010 ret = cpc->er;
2011 break;
2012 case PPC405CR_CPC0_FR:
2013 ret = cpc->fr;
2014 break;
2015 case PPC405CR_CPC0_SR:
2016 ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
2017 break;
2018 default:
2019 /* Avoid gcc warning */
2020 ret = 0;
2021 break;
2022 }
2023
2024 return ret;
2025 }
2026
2027 static void dcr_write_crcpc (void *opaque, int dcrn, target_ulong val)
2028 {
2029 ppc405cr_cpc_t *cpc;
2030
2031 cpc = opaque;
2032 switch (dcrn) {
2033 case PPC405CR_CPC0_PLLMR:
2034 cpc->pllmr = val & 0xFFF77C3F;
2035 break;
2036 case PPC405CR_CPC0_CR0:
2037 cpc->cr0 = val & 0x0FFFFFFE;
2038 break;
2039 case PPC405CR_CPC0_CR1:
2040 cpc->cr1 = val & 0x00800000;
2041 break;
2042 case PPC405CR_CPC0_PSR:
2043 /* Read-only */
2044 break;
2045 case PPC405CR_CPC0_JTAGID:
2046 /* Read-only */
2047 break;
2048 case PPC405CR_CPC0_ER:
2049 cpc->er = val & 0xBFFC0000;
2050 break;
2051 case PPC405CR_CPC0_FR:
2052 cpc->fr = val & 0xBFFC0000;
2053 break;
2054 case PPC405CR_CPC0_SR:
2055 /* Read-only */
2056 break;
2057 }
2058 }
2059
2060 static void ppc405cr_cpc_reset (void *opaque)
2061 {
2062 ppc405cr_cpc_t *cpc;
2063 int D;
2064
2065 cpc = opaque;
2066 /* Compute PLLMR value from PSR settings */
2067 cpc->pllmr = 0x80000000;
2068 /* PFWD */
2069 switch ((cpc->psr >> 30) & 3) {
2070 case 0:
2071 /* Bypass */
2072 cpc->pllmr &= ~0x80000000;
2073 break;
2074 case 1:
2075 /* Divide by 3 */
2076 cpc->pllmr |= 5 << 16;
2077 break;
2078 case 2:
2079 /* Divide by 4 */
2080 cpc->pllmr |= 4 << 16;
2081 break;
2082 case 3:
2083 /* Divide by 6 */
2084 cpc->pllmr |= 2 << 16;
2085 break;
2086 }
2087 /* PFBD */
2088 D = (cpc->psr >> 28) & 3;
2089 cpc->pllmr |= (D + 1) << 20;
2090 /* PT */
2091 D = (cpc->psr >> 25) & 7;
2092 switch (D) {
2093 case 0x2:
2094 cpc->pllmr |= 0x13;
2095 break;
2096 case 0x4:
2097 cpc->pllmr |= 0x15;
2098 break;
2099 case 0x5:
2100 cpc->pllmr |= 0x16;
2101 break;
2102 default:
2103 break;
2104 }
2105 /* PDC */
2106 D = (cpc->psr >> 23) & 3;
2107 cpc->pllmr |= D << 26;
2108 /* ODP */
2109 D = (cpc->psr >> 21) & 3;
2110 cpc->pllmr |= D << 10;
2111 /* EBPD */
2112 D = (cpc->psr >> 17) & 3;
2113 cpc->pllmr |= D << 24;
2114 cpc->cr0 = 0x0000003C;
2115 cpc->cr1 = 0x2B0D8800;
2116 cpc->er = 0x00000000;
2117 cpc->fr = 0x00000000;
2118 ppc405cr_clk_setup(cpc);
2119 }
2120
2121 static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
2122 {
2123 int D;
2124
2125 /* XXX: this should be read from IO pins */
2126 cpc->psr = 0x00000000; /* 8 bits ROM */
2127 /* PFWD */
2128 D = 0x2; /* Divide by 4 */
2129 cpc->psr |= D << 30;
2130 /* PFBD */
2131 D = 0x1; /* Divide by 2 */
2132 cpc->psr |= D << 28;
2133 /* PDC */
2134 D = 0x1; /* Divide by 2 */
2135 cpc->psr |= D << 23;
2136 /* PT */
2137 D = 0x5; /* M = 16 */
2138 cpc->psr |= D << 25;
2139 /* ODP */
2140 D = 0x1; /* Divide by 2 */
2141 cpc->psr |= D << 21;
2142 /* EBDP */
2143 D = 0x2; /* Divide by 4 */
2144 cpc->psr |= D << 17;
2145 }
2146
2147 static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
2148 uint32_t sysclk)
2149 {
2150 ppc405cr_cpc_t *cpc;
2151
2152 cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t));
2153 memcpy(cpc->clk_setup, clk_setup,
2154 PPC405CR_CLK_NB * sizeof(clk_setup_t));
2155 cpc->sysclk = sysclk;
2156 cpc->jtagid = 0x42051049;
2157 ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
2158 &dcr_read_crcpc, &dcr_write_crcpc);
2159 ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
2160 &dcr_read_crcpc, &dcr_write_crcpc);
2161 ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
2162 &dcr_read_crcpc, &dcr_write_crcpc);
2163 ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
2164 &dcr_read_crcpc, &dcr_write_crcpc);
2165 ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
2166 &dcr_read_crcpc, &dcr_write_crcpc);
2167 ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
2168 &dcr_read_crcpc, &dcr_write_crcpc);
2169 ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
2170 &dcr_read_crcpc, &dcr_write_crcpc);
2171 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
2172 &dcr_read_crcpc, &dcr_write_crcpc);
2173 ppc405cr_clk_init(cpc);
2174 qemu_register_reset(ppc405cr_cpc_reset, cpc);
2175 ppc405cr_cpc_reset(cpc);
2176 }
2177
2178 CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
2179 target_phys_addr_t ram_sizes[4],
2180 uint32_t sysclk, qemu_irq **picp,
2181 int do_init)
2182 {
2183 clk_setup_t clk_setup[PPC405CR_CLK_NB];
2184 qemu_irq dma_irqs[4];
2185 CPUState *env;
2186 ppc4xx_mmio_t *mmio;
2187 qemu_irq *pic, *irqs;
2188
2189 memset(clk_setup, 0, sizeof(clk_setup));
2190 env = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
2191 &clk_setup[PPC405CR_TMR_CLK], sysclk);
2192 /* Memory mapped devices registers */
2193 mmio = ppc4xx_mmio_init(env, 0xEF600000);
2194 /* PLB arbitrer */
2195 ppc4xx_plb_init(env);
2196 /* PLB to OPB bridge */
2197 ppc4xx_pob_init(env);
2198 /* OBP arbitrer */
2199 ppc4xx_opba_init(env, mmio, 0x600);
2200 /* Universal interrupt controller */
2201 irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2202 irqs[PPCUIC_OUTPUT_INT] =
2203 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2204 irqs[PPCUIC_OUTPUT_CINT] =
2205 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2206 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2207 *picp = pic;
2208 /* SDRAM controller */
2209 ppc4xx_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init);
2210 /* External bus controller */
2211 ppc405_ebc_init(env);
2212 /* DMA controller */
2213 dma_irqs[0] = pic[26];
2214 dma_irqs[1] = pic[25];
2215 dma_irqs[2] = pic[24];
2216 dma_irqs[3] = pic[23];
2217 ppc405_dma_init(env, dma_irqs);
2218 /* Serial ports */
2219 if (serial_hds[0] != NULL) {
2220 ppc405_serial_init(env, mmio, 0x300, pic[0], serial_hds[0]);
2221 }
2222 if (serial_hds[1] != NULL) {
2223 ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]);
2224 }
2225 /* IIC controller */
2226 ppc405_i2c_init(env, mmio, 0x500, pic[2]);
2227 /* GPIO */
2228 ppc405_gpio_init(env, mmio, 0x700);
2229 /* CPU control */
2230 ppc405cr_cpc_init(env, clk_setup, sysclk);
2231
2232 return env;
2233 }
2234
2235 /*****************************************************************************/
2236 /* PowerPC 405EP */
2237 /* CPU control */
2238 enum {
2239 PPC405EP_CPC0_PLLMR0 = 0x0F0,
2240 PPC405EP_CPC0_BOOT = 0x0F1,
2241 PPC405EP_CPC0_EPCTL = 0x0F3,
2242 PPC405EP_CPC0_PLLMR1 = 0x0F4,
2243 PPC405EP_CPC0_UCR = 0x0F5,
2244 PPC405EP_CPC0_SRR = 0x0F6,
2245 PPC405EP_CPC0_JTAGID = 0x0F7,
2246 PPC405EP_CPC0_PCI = 0x0F9,
2247 #if 0
2248 PPC405EP_CPC0_ER = xxx,
2249 PPC405EP_CPC0_FR = xxx,
2250 PPC405EP_CPC0_SR = xxx,
2251 #endif
2252 };
2253
2254 enum {
2255 PPC405EP_CPU_CLK = 0,
2256 PPC405EP_PLB_CLK = 1,
2257 PPC405EP_OPB_CLK = 2,
2258 PPC405EP_EBC_CLK = 3,
2259 PPC405EP_MAL_CLK = 4,
2260 PPC405EP_PCI_CLK = 5,
2261 PPC405EP_UART0_CLK = 6,
2262 PPC405EP_UART1_CLK = 7,
2263 PPC405EP_CLK_NB = 8,
2264 };
2265
2266 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
2267 struct ppc405ep_cpc_t {
2268 uint32_t sysclk;
2269 clk_setup_t clk_setup[PPC405EP_CLK_NB];
2270 uint32_t boot;
2271 uint32_t epctl;
2272 uint32_t pllmr[2];
2273 uint32_t ucr;
2274 uint32_t srr;
2275 uint32_t jtagid;
2276 uint32_t pci;
2277 /* Clock and power management */
2278 uint32_t er;
2279 uint32_t fr;
2280 uint32_t sr;
2281 };
2282
2283 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
2284 {
2285 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
2286 uint32_t UART0_clk, UART1_clk;
2287 uint64_t VCO_out, PLL_out;
2288 int M, D;
2289
2290 VCO_out = 0;
2291 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
2292 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
2293 #ifdef DEBUG_CLOCKS_LL
2294 printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
2295 #endif
2296 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
2297 #ifdef DEBUG_CLOCKS_LL
2298 printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
2299 #endif
2300 VCO_out = cpc->sysclk * M * D;
2301 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
2302 /* Error - unlock the PLL */
2303 printf("VCO out of range %" PRIu64 "\n", VCO_out);
2304 #if 0
2305 cpc->pllmr[1] &= ~0x80000000;
2306 goto pll_bypass;
2307 #endif
2308 }
2309 PLL_out = VCO_out / D;
2310 /* Pretend the PLL is locked */
2311 cpc->boot |= 0x00000001;
2312 } else {
2313 #if 0
2314 pll_bypass:
2315 #endif
2316 PLL_out = cpc->sysclk;
2317 if (cpc->pllmr[1] & 0x40000000) {
2318 /* Pretend the PLL is not locked */
2319 cpc->boot &= ~0x00000001;
2320 }
2321 }
2322 /* Now, compute all other clocks */
2323 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
2324 #ifdef DEBUG_CLOCKS_LL
2325 printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
2326 #endif
2327 CPU_clk = PLL_out / D;
2328 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
2329 #ifdef DEBUG_CLOCKS_LL
2330 printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
2331 #endif
2332 PLB_clk = CPU_clk / D;
2333 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
2334 #ifdef DEBUG_CLOCKS_LL
2335 printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
2336 #endif
2337 OPB_clk = PLB_clk / D;
2338 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
2339 #ifdef DEBUG_CLOCKS_LL
2340 printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
2341 #endif
2342 EBC_clk = PLB_clk / D;
2343 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
2344 #ifdef DEBUG_CLOCKS_LL
2345 printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
2346 #endif
2347 MAL_clk = PLB_clk / D;
2348 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
2349 #ifdef DEBUG_CLOCKS_LL
2350 printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D);
2351 #endif
2352 PCI_clk = PLB_clk / D;
2353 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
2354 #ifdef DEBUG_CLOCKS_LL
2355 printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D);
2356 #endif
2357 UART0_clk = PLL_out / D;
2358 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
2359 #ifdef DEBUG_CLOCKS_LL
2360 printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D);
2361 #endif
2362 UART1_clk = PLL_out / D;
2363 #ifdef DEBUG_CLOCKS
2364 printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
2365 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
2366 printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
2367 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
2368 " UART1 %" PRIu32 "\n",
2369 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
2370 UART0_clk, UART1_clk);
2371 #endif
2372 /* Setup CPU clocks */
2373 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
2374 /* Setup PLB clock */
2375 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
2376 /* Setup OPB clock */
2377 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
2378 /* Setup external clock */
2379 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
2380 /* Setup MAL clock */
2381 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
2382 /* Setup PCI clock */
2383 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
2384 /* Setup UART0 clock */
2385 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
2386 /* Setup UART1 clock */
2387 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
2388 }
2389
2390 static target_ulong dcr_read_epcpc (void *opaque, int dcrn)
2391 {
2392 ppc405ep_cpc_t *cpc;
2393 target_ulong ret;
2394
2395 cpc = opaque;
2396 switch (dcrn) {
2397 case PPC405EP_CPC0_BOOT:
2398 ret = cpc->boot;
2399 break;
2400 case PPC405EP_CPC0_EPCTL:
2401 ret = cpc->epctl;
2402 break;
2403 case PPC405EP_CPC0_PLLMR0:
2404 ret = cpc->pllmr[0];
2405 break;
2406 case PPC405EP_CPC0_PLLMR1:
2407 ret = cpc->pllmr[1];
2408 break;
2409 case PPC405EP_CPC0_UCR:
2410 ret = cpc->ucr;
2411 break;
2412 case PPC405EP_CPC0_SRR:
2413 ret = cpc->srr;
2414 break;
2415 case PPC405EP_CPC0_JTAGID:
2416 ret = cpc->jtagid;
2417 break;
2418 case PPC405EP_CPC0_PCI:
2419 ret = cpc->pci;
2420 break;
2421 default:
2422 /* Avoid gcc warning */
2423 ret = 0;
2424 break;
2425 }
2426
2427 return ret;
2428 }
2429
2430 static void dcr_write_epcpc (void *opaque, int dcrn, target_ulong val)
2431 {
2432 ppc405ep_cpc_t *cpc;
2433
2434 cpc = opaque;
2435 switch (dcrn) {
2436 case PPC405EP_CPC0_BOOT:
2437 /* Read-only register */
2438 break;
2439 case PPC405EP_CPC0_EPCTL:
2440 /* Don't care for now */
2441 cpc->epctl = val & 0xC00000F3;
2442 break;
2443 case PPC405EP_CPC0_PLLMR0:
2444 cpc->pllmr[0] = val & 0x00633333;
2445 ppc405ep_compute_clocks(cpc);
2446 break;
2447 case PPC405EP_CPC0_PLLMR1:
2448 cpc->pllmr[1] = val & 0xC0F73FFF;
2449 ppc405ep_compute_clocks(cpc);
2450 break;
2451 case PPC405EP_CPC0_UCR:
2452 /* UART control - don't care for now */
2453 cpc->ucr = val & 0x003F7F7F;
2454 break;
2455 case PPC405EP_CPC0_SRR:
2456 cpc->srr = val;
2457 break;
2458 case PPC405EP_CPC0_JTAGID:
2459 /* Read-only */
2460 break;
2461 case PPC405EP_CPC0_PCI:
2462 cpc->pci = val;
2463 break;
2464 }
2465 }
2466
2467 static void ppc405ep_cpc_reset (void *opaque)
2468 {
2469 ppc405ep_cpc_t *cpc = opaque;
2470
2471 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
2472 cpc->epctl = 0x00000000;
2473 cpc->pllmr[0] = 0x00011010;
2474 cpc->pllmr[1] = 0x40000000;
2475 cpc->ucr = 0x00000000;
2476 cpc->srr = 0x00040000;
2477 cpc->pci = 0x00000000;
2478 cpc->er = 0x00000000;
2479 cpc->fr = 0x00000000;
2480 cpc->sr = 0x00000000;
2481 ppc405ep_compute_clocks(cpc);
2482 }
2483
2484 /* XXX: sysclk should be between 25 and 100 MHz */
2485 static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
2486 uint32_t sysclk)
2487 {
2488 ppc405ep_cpc_t *cpc;
2489
2490 cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t));
2491 memcpy(cpc->clk_setup, clk_setup,
2492 PPC405EP_CLK_NB * sizeof(clk_setup_t));
2493 cpc->jtagid = 0x20267049;
2494 cpc->sysclk = sysclk;
2495 ppc405ep_cpc_reset(cpc);
2496 qemu_register_reset(&ppc405ep_cpc_reset, cpc);
2497 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
2498 &dcr_read_epcpc, &dcr_write_epcpc);
2499 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
2500 &dcr_read_epcpc, &dcr_write_epcpc);
2501 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
2502 &dcr_read_epcpc, &dcr_write_epcpc);
2503 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
2504 &dcr_read_epcpc, &dcr_write_epcpc);
2505 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
2506 &dcr_read_epcpc, &dcr_write_epcpc);
2507 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
2508 &dcr_read_epcpc, &dcr_write_epcpc);
2509 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
2510 &dcr_read_epcpc, &dcr_write_epcpc);
2511 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
2512 &dcr_read_epcpc, &dcr_write_epcpc);
2513 #if 0
2514 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
2515 &dcr_read_epcpc, &dcr_write_epcpc);
2516 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
2517 &dcr_read_epcpc, &dcr_write_epcpc);
2518 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
2519 &dcr_read_epcpc, &dcr_write_epcpc);
2520 #endif
2521 }
2522
2523 CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
2524 target_phys_addr_t ram_sizes[2],
2525 uint32_t sysclk, qemu_irq **picp,
2526 int do_init)
2527 {
2528 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
2529 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
2530 CPUState *env;
2531 ppc4xx_mmio_t *mmio;
2532 qemu_irq *pic, *irqs;
2533
2534 memset(clk_setup, 0, sizeof(clk_setup));
2535 /* init CPUs */
2536 env = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
2537 &tlb_clk_setup, sysclk);
2538 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
2539 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
2540 /* Internal devices init */
2541 /* Memory mapped devices registers */
2542 mmio = ppc4xx_mmio_init(env, 0xEF600000);
2543 /* PLB arbitrer */
2544 ppc4xx_plb_init(env);
2545 /* PLB to OPB bridge */
2546 ppc4xx_pob_init(env);
2547 /* OBP arbitrer */
2548 ppc4xx_opba_init(env, mmio, 0x600);
2549 /* Universal interrupt controller */
2550 irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2551 irqs[PPCUIC_OUTPUT_INT] =
2552 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2553 irqs[PPCUIC_OUTPUT_CINT] =
2554 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2555 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2556 *picp = pic;
2557 /* SDRAM controller */
2558 /* XXX 405EP has no ECC interrupt */
2559 ppc4xx_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init);
2560 /* External bus controller */
2561 ppc405_ebc_init(env);
2562 /* DMA controller */
2563 dma_irqs[0] = pic[5];
2564 dma_irqs[1] = pic[6];
2565 dma_irqs[2] = pic[7];
2566 dma_irqs[3] = pic[8];
2567 ppc405_dma_init(env, dma_irqs);
2568 /* IIC controller */
2569 ppc405_i2c_init(env, mmio, 0x500, pic[2]);
2570 /* GPIO */
2571 ppc405_gpio_init(env, mmio, 0x700);
2572 /* Serial ports */
2573 if (serial_hds[0] != NULL) {
2574 ppc405_serial_init(env, mmio, 0x300, pic[0], serial_hds[0]);
2575 }
2576 if (serial_hds[1] != NULL) {
2577 ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]);
2578 }
2579 /* OCM */
2580 ppc405_ocm_init(env);
2581 /* GPT */
2582 gpt_irqs[0] = pic[19];
2583 gpt_irqs[1] = pic[20];
2584 gpt_irqs[2] = pic[21];
2585 gpt_irqs[3] = pic[22];
2586 gpt_irqs[4] = pic[23];
2587 ppc4xx_gpt_init(env, mmio, 0x000, gpt_irqs);
2588 /* PCI */
2589 /* Uses pic[3], pic[16], pic[18] */
2590 /* MAL */
2591 mal_irqs[0] = pic[11];
2592 mal_irqs[1] = pic[12];
2593 mal_irqs[2] = pic[13];
2594 mal_irqs[3] = pic[14];
2595 ppc405_mal_init(env, mal_irqs);
2596 /* Ethernet */
2597 /* Uses pic[9], pic[15], pic[17] */
2598 /* CPU control */
2599 ppc405ep_cpc_init(env, clk_setup, sysclk);
2600
2601 return env;
2602 }
HPPA (PA-RISC) target for QEMU