hw/mac_dbdma.c

   1 /*
   2  * PowerMac descriptor-based DMA emulation
   3  *
   4  * Copyright (c) 2005-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  * Copyright (c) 2009 Laurent Vivier
   7  *
   8  * some parts from linux-2.6.28, arch/powerpc/include/asm/dbdma.h
   9  *
  10  *   Definitions for using the Apple Descriptor-Based DMA controller
  11  *   in Power Macintosh computers.
  12  *
  13  *   Copyright (C) 1996 Paul Mackerras.
  14  *
  15  * some parts from mol 0.9.71
  16  *
  17  *   Descriptor based DMA emulation
  18  *
  19  *   Copyright (C) 1998-2004 Samuel Rydh (samuel@ibrium.se)
  20  *
  21  * Permission is hereby granted, free of charge, to any person obtaining a copy
  22  * of this software and associated documentation files (the "Software"), to deal
  23  * in the Software without restriction, including without limitation the rights
  24  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  25  * copies of the Software, and to permit persons to whom the Software is
  26  * furnished to do so, subject to the following conditions:
  27  *
  28  * The above copyright notice and this permission notice shall be included in
  29  * all copies or substantial portions of the Software.
  30  *
  31  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  32  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  33  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  34  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  35  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  36  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  37  * THE SOFTWARE.
  38  */
  39 #include "hw.h"
  40 #include "isa.h"
  41 #include "mac_dbdma.h"
  42
  43 /* debug DBDMA */
  44 //#define DEBUG_DBDMA
  45
  46 #ifdef DEBUG_DBDMA
  47 #define DBDMA_DPRINTF(fmt, args...) \
  48 do { printf("DBDMA: " fmt , ##args); } while (0)
  49 #else
  50 #define DBDMA_DPRINTF(fmt, args...)
  51 #endif
  52
  53 /*
  54  */
  55
  56 /*
  57  * DBDMA control/status registers.  All little-endian.
  58  */
  59
  60 #define DBDMA_CONTROL         0x00
  61 #define DBDMA_STATUS          0x01
  62 #define DBDMA_CMDPTR_HI       0x02
  63 #define DBDMA_CMDPTR_LO       0x03
  64 #define DBDMA_INTR_SEL        0x04
  65 #define DBDMA_BRANCH_SEL      0x05
  66 #define DBDMA_WAIT_SEL        0x06
  67 #define DBDMA_XFER_MODE       0x07
  68 #define DBDMA_DATA2PTR_HI     0x08
  69 #define DBDMA_DATA2PTR_LO     0x09
  70 #define DBDMA_RES1            0x0A
  71 #define DBDMA_ADDRESS_HI      0x0B
  72 #define DBDMA_BRANCH_ADDR_HI  0x0C
  73 #define DBDMA_RES2            0x0D
  74 #define DBDMA_RES3            0x0E
  75 #define DBDMA_RES4            0x0F
  76
  77 #define DBDMA_REGS            16
  78 #define DBDMA_SIZE            (DBDMA_REGS * sizeof(uint32_t))
  79
  80 #define DBDMA_CHANNEL_SHIFT   7
  81 #define DBDMA_CHANNEL_SIZE    (1 << DBDMA_CHANNEL_SHIFT)
  82
  83 #define DBDMA_CHANNELS        (0x1000 >> DBDMA_CHANNEL_SHIFT)
  84
  85 /* Bits in control and status registers */
  86
  87 #define RUN     0x8000
  88 #define PAUSE   0x4000
  89 #define FLUSH   0x2000
  90 #define WAKE    0x1000
  91 #define DEAD    0x0800
  92 #define ACTIVE  0x0400
  93 #define BT      0x0100
  94 #define DEVSTAT 0x00ff
  95
  96 /*
  97  * DBDMA command structure.  These fields are all little-endian!
  98  */
  99
 100 typedef struct dbdma_cmd {
 101     uint16_t req_count;   /* requested byte transfer count */
 102     uint16_t command;     /* command word (has bit-fields) */
 103     uint32_t phy_addr;    /* physical data address */
 104     uint32_t cmd_dep;     /* command-dependent field */
 105     uint16_t res_count;   /* residual count after completion */
 106     uint16_t xfer_status; /* transfer status */
 107 } dbdma_cmd;
 108
 109 /* DBDMA command values in command field */
 110
 111 #define COMMAND_MASK    0xf000
 112 #define OUTPUT_MORE     0x0000  /* transfer memory data to stream */
 113 #define OUTPUT_LAST     0x1000  /* ditto followed by end marker */
 114 #define INPUT_MORE      0x2000  /* transfer stream data to memory */
 115 #define INPUT_LAST      0x3000  /* ditto, expect end marker */
 116 #define STORE_WORD      0x4000  /* write word (4 bytes) to device reg */
 117 #define LOAD_WORD       0x5000  /* read word (4 bytes) from device reg */
 118 #define DBDMA_NOP       0x6000  /* do nothing */
 119 #define DBDMA_STOP      0x7000  /* suspend processing */
 120
 121 /* Key values in command field */
 122
 123 #define KEY_MASK        0x0700
 124 #define KEY_STREAM0     0x0000  /* usual data stream */
 125 #define KEY_STREAM1     0x0100  /* control/status stream */
 126 #define KEY_STREAM2     0x0200  /* device-dependent stream */
 127 #define KEY_STREAM3     0x0300  /* device-dependent stream */
 128 #define KEY_STREAM4     0x0400  /* reserved */
 129 #define KEY_REGS        0x0500  /* device register space */
 130 #define KEY_SYSTEM      0x0600  /* system memory-mapped space */
 131 #define KEY_DEVICE      0x0700  /* device memory-mapped space */
 132
 133 /* Interrupt control values in command field */
 134
 135 #define INTR_MASK       0x0030
 136 #define INTR_NEVER      0x0000  /* don't interrupt */
 137 #define INTR_IFSET      0x0010  /* intr if condition bit is 1 */
 138 #define INTR_IFCLR      0x0020  /* intr if condition bit is 0 */
 139 #define INTR_ALWAYS     0x0030  /* always interrupt */
 140
 141 /* Branch control values in command field */
 142
 143 #define BR_MASK         0x000c
 144 #define BR_NEVER        0x0000  /* don't branch */
 145 #define BR_IFSET        0x0004  /* branch if condition bit is 1 */
 146 #define BR_IFCLR        0x0008  /* branch if condition bit is 0 */
 147 #define BR_ALWAYS       0x000c  /* always branch */
 148
 149 /* Wait control values in command field */
 150
 151 #define WAIT_MASK       0x0003
 152 #define WAIT_NEVER      0x0000  /* don't wait */
 153 #define WAIT_IFSET      0x0001  /* wait if condition bit is 1 */
 154 #define WAIT_IFCLR      0x0002  /* wait if condition bit is 0 */
 155 #define WAIT_ALWAYS     0x0003  /* always wait */
 156
 157 typedef struct DBDMA_channel {
 158     int channel;
 159     uint32_t regs[DBDMA_REGS];
 160     qemu_irq irq;
 161     DBDMA_transfer io;
 162     DBDMA_transfer_handler transfer_handler;
 163     dbdma_cmd current;
 164 } DBDMA_channel;
 165
 166 #ifdef DEBUG_DBDMA
 167 static void dump_dbdma_cmd(dbdma_cmd *cmd)
 168 {
 169     printf("dbdma_cmd %p\n", cmd);
 170     printf("    req_count 0x%04x\n", le16_to_cpu(cmd->req_count));
 171     printf("    command 0x%04x\n", le16_to_cpu(cmd->command));
 172     printf("    phy_addr 0x%08x\n", le32_to_cpu(cmd->phy_addr));
 173     printf("    cmd_dep 0x%08x\n", le32_to_cpu(cmd->cmd_dep));
 174     printf("    res_count 0x%04x\n", le16_to_cpu(cmd->res_count));
 175     printf("    xfer_status 0x%04x\n", le16_to_cpu(cmd->xfer_status));
 176 }
 177 #else
 178 static void dump_dbdma_cmd(dbdma_cmd *cmd)
 179 {
 180 }
 181 #endif
 182 static void dbdma_cmdptr_load(DBDMA_channel *ch)
 183 {
 184     DBDMA_DPRINTF("dbdma_cmdptr_load 0x%08x\n",
 185                   be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]));
 186     cpu_physical_memory_read(be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]),
 187                              (uint8_t*)&ch->current, sizeof(dbdma_cmd));
 188 }
 189
 190 static void dbdma_cmdptr_save(DBDMA_channel *ch)
 191 {
 192     DBDMA_DPRINTF("dbdma_cmdptr_save 0x%08x\n",
 193                   be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]));
 194     DBDMA_DPRINTF("xfer_status 0x%08x res_count 0x%04x\n",
 195                   le16_to_cpu(ch->current.xfer_status),
 196                   le16_to_cpu(ch->current.res_count));
 197     cpu_physical_memory_write(be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]),
 198                               (uint8_t*)&ch->current, sizeof(dbdma_cmd));
 199 }
 200
 201 static void kill_channel(DBDMA_channel *ch)
 202 {
 203     DBDMA_DPRINTF("kill_channel\n");
 204
 205     ch->regs[DBDMA_STATUS] |= cpu_to_be32(DEAD);
 206     ch->regs[DBDMA_STATUS] &= cpu_to_be32(~ACTIVE);
 207
 208     qemu_irq_raise(ch->irq);
 209 }
 210
 211 static void conditional_interrupt(DBDMA_channel *ch)
 212 {
 213     dbdma_cmd *current = &ch->current;
 214     uint16_t intr;
 215     uint16_t sel_mask, sel_value;
 216     uint32_t status;
 217     int cond;
 218
 219     DBDMA_DPRINTF("conditional_interrupt\n");
 220
 221     intr = be16_to_cpu(current->command) & INTR_MASK;
 222
 223     switch(intr) {
 224     case INTR_NEVER:  /* don't interrupt */
 225         return;
 226     case INTR_ALWAYS: /* always interrupt */
 227         qemu_irq_raise(ch->irq);
 228         return;
 229     }
 230
 231     status = be32_to_cpu(ch->regs[DBDMA_STATUS]) & DEVSTAT;
 232
 233     sel_mask = (be32_to_cpu(ch->regs[DBDMA_INTR_SEL]) >> 16) & 0x0f;
 234     sel_value = be32_to_cpu(ch->regs[DBDMA_INTR_SEL]) & 0x0f;
 235
 236     cond = (status & sel_mask) == (sel_value & sel_mask);
 237
 238     switch(intr) {
 239     case INTR_IFSET:  /* intr if condition bit is 1 */
 240         if (cond)
 241             qemu_irq_raise(ch->irq);
 242         return;
 243     case INTR_IFCLR:  /* intr if condition bit is 0 */
 244         if (!cond)
 245             qemu_irq_raise(ch->irq);
 246         return;
 247     }
 248 }
 249
 250 static int conditional_wait(DBDMA_channel *ch)
 251 {
 252     dbdma_cmd *current = &ch->current;
 253     uint16_t wait;
 254     uint16_t sel_mask, sel_value;
 255     uint32_t status;
 256     int cond;
 257
 258     DBDMA_DPRINTF("conditional_wait\n");
 259
 260     wait = be16_to_cpu(current->command) & WAIT_MASK;
 261
 262     switch(wait) {
 263     case WAIT_NEVER:  /* don't wait */
 264         return 0;
 265     case WAIT_ALWAYS: /* always wait */
 266         return 1;
 267     }
 268
 269     status = be32_to_cpu(ch->regs[DBDMA_STATUS]) & DEVSTAT;
 270
 271     sel_mask = (be32_to_cpu(ch->regs[DBDMA_WAIT_SEL]) >> 16) & 0x0f;
 272     sel_value = be32_to_cpu(ch->regs[DBDMA_WAIT_SEL]) & 0x0f;
 273
 274     cond = (status & sel_mask) == (sel_value & sel_mask);
 275
 276     switch(wait) {
 277     case WAIT_IFSET:  /* wait if condition bit is 1 */
 278         if (cond)
 279             return 1;
 280         return 0;
 281     case WAIT_IFCLR:  /* wait if condition bit is 0 */
 282         if (!cond)
 283             return 1;
 284         return 0;
 285     }
 286     return 0;
 287 }
 288
 289 static void next(DBDMA_channel *ch)
 290 {
 291     uint32_t cp;
 292
 293     ch->regs[DBDMA_STATUS] &= cpu_to_be32(~BT);
 294
 295     cp = be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]);
 296     ch->regs[DBDMA_CMDPTR_LO] = cpu_to_be32(cp + sizeof(dbdma_cmd));
 297     dbdma_cmdptr_load(ch);
 298 }
 299
 300 static void branch(DBDMA_channel *ch)
 301 {
 302     dbdma_cmd *current = &ch->current;
 303
 304     ch->regs[DBDMA_CMDPTR_LO] = current->cmd_dep;
 305     ch->regs[DBDMA_STATUS] |= cpu_to_be32(BT);
 306     dbdma_cmdptr_load(ch);
 307 }
 308
 309 static void conditional_branch(DBDMA_channel *ch)
 310 {
 311     dbdma_cmd *current = &ch->current;
 312     uint16_t br;
 313     uint16_t sel_mask, sel_value;
 314     uint32_t status;
 315     int cond;
 316
 317     DBDMA_DPRINTF("conditional_branch\n");
 318
 319     /* check if we must branch */
 320
 321     br = be16_to_cpu(current->command) & BR_MASK;
 322
 323     switch(br) {
 324     case BR_NEVER:  /* don't branch */
 325         next(ch);
 326         return;
 327     case BR_ALWAYS: /* always branch */
 328         branch(ch);
 329         return;
 330     }
 331
 332     status = be32_to_cpu(ch->regs[DBDMA_STATUS]) & DEVSTAT;
 333
 334     sel_mask = (be32_to_cpu(ch->regs[DBDMA_BRANCH_SEL]) >> 16) & 0x0f;
 335     sel_value = be32_to_cpu(ch->regs[DBDMA_BRANCH_SEL]) & 0x0f;
 336
 337     cond = (status & sel_mask) == (sel_value & sel_mask);
 338
 339     switch(br) {
 340     case BR_IFSET:  /* branch if condition bit is 1 */
 341         if (cond)
 342             branch(ch);
 343         else
 344             next(ch);
 345         return;
 346     case BR_IFCLR:  /* branch if condition bit is 0 */
 347         if (!cond)
 348             branch(ch);
 349         else
 350             next(ch);
 351         return;
 352     }
 353 }
 354
 355 static int dbdma_read_memory(DBDMA_transfer *io)
 356 {
 357     DBDMA_channel *ch = io->channel;
 358     dbdma_cmd *current = &ch->current;
 359
 360     DBDMA_DPRINTF("DBDMA_read_memory\n");
 361
 362     cpu_physical_memory_read(le32_to_cpu(current->phy_addr) + io->buf_pos,
 363                              io->buf, io->buf_len);
 364
 365     return io->buf_len;
 366 }
 367
 368 static int dbdma_write_memory(DBDMA_transfer *io)
 369 {
 370     DBDMA_channel *ch = io->channel;
 371     dbdma_cmd *current = &ch->current;
 372
 373     DBDMA_DPRINTF("DBDMA_write_memory\n");
 374
 375     cpu_physical_memory_write(le32_to_cpu(current->phy_addr) + io->buf_pos,
 376                               io->buf, io->buf_len);
 377
 378     return io->buf_len;
 379 }
 380
 381 static int start_output(DBDMA_channel *ch, int key, uint32_t addr,
 382                         uint16_t req_count, int is_last)
 383 {
 384     dbdma_cmd *current = &ch->current;
 385     uint32_t n;
 386
 387     DBDMA_DPRINTF("start_output\n");
 388
 389     /* KEY_REGS, KEY_DEVICE and KEY_STREAM
 390      * are not implemented in the mac-io chip
 391      */
 392
 393     DBDMA_DPRINTF("addr 0x%x key 0x%x\n", addr, key);
 394     if (!addr || key > KEY_STREAM3) {
 395         kill_channel(ch);
 396         return 0;
 397     }
 398
 399     ch->io.buf = NULL;
 400     ch->io.buf_pos = 0;
 401     ch->io.buf_len = 0;
 402     ch->io.len = req_count;
 403     ch->io.is_last = is_last;
 404     n = ch->transfer_handler(&ch->io, dbdma_read_memory);
 405
 406     if (conditional_wait(ch))
 407         return 1;
 408
 409     current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
 410     current->res_count = cpu_to_le16(0);
 411     dbdma_cmdptr_save(ch);
 412
 413     conditional_interrupt(ch);
 414     conditional_branch(ch);
 415
 416     return 1;
 417 }
 418
 419 static int start_input(DBDMA_channel *ch, int key, uint32_t addr,
 420                        uint16_t req_count, int is_last)
 421 {
 422     dbdma_cmd *current = &ch->current;
 423     uint32_t n;
 424
 425     DBDMA_DPRINTF("start_input\n");
 426
 427     /* KEY_REGS, KEY_DEVICE and KEY_STREAM
 428      * are not implemented in the mac-io chip
 429      */
 430
 431     if (!addr || key > KEY_STREAM3) {
 432         kill_channel(ch);
 433         return 0;
 434     }
 435
 436     ch->io.buf = NULL;
 437     ch->io.buf_pos = 0;
 438     ch->io.buf_len = 0;
 439     ch->io.len = req_count;
 440     ch->io.is_last = is_last;
 441     n = ch->transfer_handler(&ch->io, dbdma_write_memory);
 442
 443     if (conditional_wait(ch))
 444         return 1;
 445
 446     current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
 447     current->res_count = cpu_to_le16(0);
 448     dbdma_cmdptr_save(ch);
 449
 450     conditional_interrupt(ch);
 451     conditional_branch(ch);
 452
 453     return 1;
 454 }
 455
 456 static int load_word(DBDMA_channel *ch, int key, uint32_t addr,
 457                      uint16_t len)
 458 {
 459     dbdma_cmd *current = &ch->current;
 460     uint32_t val;
 461
 462     DBDMA_DPRINTF("load_word\n");
 463
 464     /* only implements KEY_SYSTEM */
 465
 466     if (key != KEY_SYSTEM) {
 467         printf("DBDMA: LOAD_WORD, unimplemented key %x\n", key);
 468         kill_channel(ch);
 469         return 0;
 470     }
 471
 472     cpu_physical_memory_read(addr, (uint8_t*)&val, len);
 473
 474     if (len == 2)
 475         val = (val << 16) | (current->cmd_dep & 0x0000ffff);
 476     else if (len == 1)
 477         val = (val << 24) | (current->cmd_dep & 0x00ffffff);
 478
 479     current->cmd_dep = val;
 480
 481     if (conditional_wait(ch))
 482         return 1;
 483
 484     current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
 485     dbdma_cmdptr_save(ch);
 486
 487     conditional_interrupt(ch);
 488     next(ch);
 489
 490     return 1;
 491 }
 492
 493 static int store_word(DBDMA_channel *ch, int key, uint32_t addr,
 494                       uint16_t len)
 495 {
 496     dbdma_cmd *current = &ch->current;
 497     uint32_t val;
 498
 499     DBDMA_DPRINTF("store_word\n");
 500
 501     /* only implements KEY_SYSTEM */
 502
 503     if (key != KEY_SYSTEM) {
 504         printf("DBDMA: STORE_WORD, unimplemented key %x\n", key);
 505         kill_channel(ch);
 506         return 0;
 507     }
 508
 509     val = current->cmd_dep;
 510     if (len == 2)
 511         val >>= 16;
 512     else if (len == 1)
 513         val >>= 24;
 514
 515     cpu_physical_memory_write(addr, (uint8_t*)&val, len);
 516
 517     if (conditional_wait(ch))
 518         return 1;
 519
 520     current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
 521     dbdma_cmdptr_save(ch);
 522
 523     conditional_interrupt(ch);
 524     next(ch);
 525
 526     return 1;
 527 }
 528
 529 static int nop(DBDMA_channel *ch)
 530 {
 531     dbdma_cmd *current = &ch->current;
 532
 533     if (conditional_wait(ch))
 534         return 1;
 535
 536     current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS]));
 537     dbdma_cmdptr_save(ch);
 538
 539     conditional_interrupt(ch);
 540     conditional_branch(ch);
 541
 542     return 1;
 543 }
 544
 545 static int stop(DBDMA_channel *ch)
 546 {
 547     ch->regs[DBDMA_STATUS] &= cpu_to_be32(~(ACTIVE|DEAD));
 548
 549     /* the stop command does not increment command pointer */
 550
 551     return 0;
 552 }
 553
 554 static int channel_run(DBDMA_channel *ch)
 555 {
 556     dbdma_cmd *current = &ch->current;
 557     uint16_t cmd, key;
 558     uint16_t req_count;
 559     uint32_t phy_addr;
 560
 561     DBDMA_DPRINTF("channel_run\n");
 562     dump_dbdma_cmd(current);
 563
 564     /* clear WAKE flag at command fetch */
 565
 566     ch->regs[DBDMA_STATUS] &= cpu_to_be32(~WAKE);
 567
 568     cmd = le16_to_cpu(current->command) & COMMAND_MASK;
 569
 570     switch (cmd) {
 571     case DBDMA_NOP:
 572         return nop(ch);
 573
 574     case DBDMA_STOP:
 575         return stop(ch);
 576     }
 577
 578     key = le16_to_cpu(current->command) & 0x0700;
 579     req_count = le16_to_cpu(current->req_count);
 580     phy_addr = le32_to_cpu(current->phy_addr);
 581
 582     if (key == KEY_STREAM4) {
 583         printf("command %x, invalid key 4\n", cmd);
 584         kill_channel(ch);
 585         return 0;
 586     }
 587
 588     switch (cmd) {
 589     case OUTPUT_MORE:
 590         return start_output(ch, key, phy_addr, req_count, 0);
 591
 592     case OUTPUT_LAST:
 593         return start_output(ch, key, phy_addr, req_count, 1);
 594
 595     case INPUT_MORE:
 596         return start_input(ch, key, phy_addr, req_count, 0);
 597
 598     case INPUT_LAST:
 599         return start_input(ch, key, phy_addr, req_count, 1);
 600     }
 601
 602     if (key < KEY_REGS) {
 603         printf("command %x, invalid key %x\n", cmd, key);
 604         key = KEY_SYSTEM;
 605     }
 606
 607     /* for LOAD_WORD and STORE_WORD, req_count is on 3 bits
 608      * and BRANCH is invalid
 609      */
 610
 611     req_count = req_count & 0x0007;
 612     if (req_count & 0x4) {
 613         req_count = 4;
 614         phy_addr &= ~3;
 615     } else if (req_count & 0x2) {
 616         req_count = 2;
 617         phy_addr &= ~1;
 618     } else
 619         req_count = 1;
 620
 621     switch (cmd) {
 622     case LOAD_WORD:
 623         return load_word(ch, key, phy_addr, req_count);
 624
 625     case STORE_WORD:
 626         return store_word(ch, key, phy_addr, req_count);
 627     }
 628
 629     return 0;
 630 }
 631
 632 static QEMUBH *dbdma_bh;
 633
 634 static void DBDMA_run (DBDMA_channel *ch)
 635 {
 636     int channel;
 637     int rearm = 0;
 638
 639     for (channel = 0; channel < DBDMA_CHANNELS; channel++, ch++) {
 640             uint32_t status = be32_to_cpu(ch->regs[DBDMA_STATUS]);
 641             if ((status & RUN) && (status & ACTIVE)) {
 642                 if (status & FLUSH)
 643                     while (channel_run(ch));
 644                 else if (channel_run(ch))
 645                     rearm = 1;
 646             }
 647             ch->regs[DBDMA_STATUS] &= cpu_to_be32(~FLUSH);
 648     }
 649
 650     if (rearm)
 651         qemu_bh_schedule_idle(dbdma_bh);
 652 }
 653
 654 static void DBDMA_run_bh(void *opaque)
 655 {
 656     DBDMA_channel *ch = opaque;
 657
 658     DBDMA_DPRINTF("DBDMA_run_bh\n");
 659
 660     DBDMA_run(ch);
 661 }
 662
 663 void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq,
 664                             DBDMA_transfer_handler transfer_handler,
 665                             void *opaque)
 666 {
 667     DBDMA_channel *ch = ( DBDMA_channel *)dbdma + nchan;
 668
 669     DBDMA_DPRINTF("DBDMA_register_channel 0x%x\n", nchan);
 670
 671     ch->irq = irq;
 672     ch->channel = nchan;
 673     ch->transfer_handler = transfer_handler;
 674     ch->io.opaque = opaque;
 675     ch->io.channel = ch;
 676 }
 677
 678 void DBDMA_schedule(void)
 679 {
 680     CPUState *env = cpu_single_env;
 681     if (env)
 682         cpu_interrupt(env, CPU_INTERRUPT_EXIT);
 683 }
 684
 685 static void
 686 dbdma_control_write(DBDMA_channel *ch)
 687 {
 688     uint16_t mask, value;
 689     uint32_t status;
 690
 691     mask = (be32_to_cpu(ch->regs[DBDMA_CONTROL]) >> 16) & 0xffff;
 692     value = be32_to_cpu(ch->regs[DBDMA_CONTROL]) & 0xffff;
 693
 694     value &= (RUN | PAUSE | FLUSH | WAKE | DEVSTAT);
 695
 696     status = be32_to_cpu(ch->regs[DBDMA_STATUS]);
 697
 698     status = (value & mask) | (status & ~mask);
 699
 700     if (status & WAKE)
 701         status |= ACTIVE;
 702     if (status & RUN) {
 703         status |= ACTIVE;
 704         status &= ~DEAD;
 705     }
 706     if (status & PAUSE)
 707         status &= ~ACTIVE;
 708     if ((be32_to_cpu(ch->regs[DBDMA_STATUS]) & RUN) && !(status & RUN)) {
 709         /* RUN is cleared */
 710         status &= ~(ACTIVE|DEAD);
 711     }
 712
 713     DBDMA_DPRINTF("    status 0x%08x\n", status);
 714
 715     ch->regs[DBDMA_STATUS] = cpu_to_be32(status);
 716
 717     if (status & ACTIVE) {
 718         qemu_bh_schedule_idle(dbdma_bh);
 719         if (status & FLUSH)
 720             DBDMA_schedule();
 721     }
 722 }
 723
 724 static void dbdma_writel (void *opaque,
 725                           target_phys_addr_t addr, uint32_t value)
 726 {
 727     int channel = addr >> DBDMA_CHANNEL_SHIFT;
 728     DBDMA_channel *ch = (DBDMA_channel *)opaque + channel;
 729     int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2;
 730
 731     DBDMA_DPRINTF("writel 0x" TARGET_FMT_plx " <= 0x%08x\n", addr, value);
 732     DBDMA_DPRINTF("channel 0x%x reg 0x%x\n",
 733                   (uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg);
 734
 735     /* cmdptr cannot be modified if channel is RUN or ACTIVE */
 736
 737     if (reg == DBDMA_CMDPTR_LO &&
 738         (ch->regs[DBDMA_STATUS] & cpu_to_be32(RUN | ACTIVE)))
 739         return;
 740
 741     ch->regs[reg] = value;
 742
 743     switch(reg) {
 744     case DBDMA_CONTROL:
 745         dbdma_control_write(ch);
 746         break;
 747     case DBDMA_CMDPTR_LO:
 748         /* 16-byte aligned */
 749         ch->regs[DBDMA_CMDPTR_LO] &= cpu_to_be32(~0xf);
 750         dbdma_cmdptr_load(ch);
 751         break;
 752     case DBDMA_STATUS:
 753     case DBDMA_INTR_SEL:
 754     case DBDMA_BRANCH_SEL:
 755     case DBDMA_WAIT_SEL:
 756         /* nothing to do */
 757         break;
 758     case DBDMA_XFER_MODE:
 759     case DBDMA_CMDPTR_HI:
 760     case DBDMA_DATA2PTR_HI:
 761     case DBDMA_DATA2PTR_LO:
 762     case DBDMA_ADDRESS_HI:
 763     case DBDMA_BRANCH_ADDR_HI:
 764     case DBDMA_RES1:
 765     case DBDMA_RES2:
 766     case DBDMA_RES3:
 767     case DBDMA_RES4:
 768         /* unused */
 769         break;
 770     }
 771 }
 772
 773 static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr)
 774 {
 775     uint32_t value;
 776     int channel = addr >> DBDMA_CHANNEL_SHIFT;
 777     DBDMA_channel *ch = (DBDMA_channel *)opaque + channel;
 778     int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2;
 779
 780     value = ch->regs[reg];
 781
 782     DBDMA_DPRINTF("readl 0x" TARGET_FMT_plx " => 0x%08x\n", addr, value);
 783     DBDMA_DPRINTF("channel 0x%x reg 0x%x\n",
 784                   (uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg);
 785
 786     switch(reg) {
 787     case DBDMA_CONTROL:
 788         value = 0;
 789         break;
 790     case DBDMA_STATUS:
 791     case DBDMA_CMDPTR_LO:
 792     case DBDMA_INTR_SEL:
 793     case DBDMA_BRANCH_SEL:
 794     case DBDMA_WAIT_SEL:
 795         /* nothing to do */
 796         break;
 797     case DBDMA_XFER_MODE:
 798     case DBDMA_CMDPTR_HI:
 799     case DBDMA_DATA2PTR_HI:
 800     case DBDMA_DATA2PTR_LO:
 801     case DBDMA_ADDRESS_HI:
 802     case DBDMA_BRANCH_ADDR_HI:
 803         /* unused */
 804         value = 0;
 805         break;
 806     case DBDMA_RES1:
 807     case DBDMA_RES2:
 808     case DBDMA_RES3:
 809     case DBDMA_RES4:
 810         /* reserved */
 811         break;
 812     }
 813
 814     return value;
 815 }
 816
 817 static CPUWriteMemoryFunc *dbdma_write[] = {
 818     NULL,
 819     NULL,
 820     dbdma_writel,
 821 };
 822
 823 static CPUReadMemoryFunc *dbdma_read[] = {
 824     NULL,
 825     NULL,
 826     dbdma_readl,
 827 };
 828
 829 static void dbdma_save(QEMUFile *f, void *opaque)
 830 {
 831     DBDMA_channel *s = opaque;
 832     unsigned int i, j;
 833
 834     for (i = 0; i < DBDMA_CHANNELS; i++)
 835         for (j = 0; j < DBDMA_REGS; j++)
 836             qemu_put_be32s(f, &s[i].regs[j]);
 837 }
 838
 839 static int dbdma_load(QEMUFile *f, void *opaque, int version_id)
 840 {
 841     DBDMA_channel *s = opaque;
 842     unsigned int i, j;
 843
 844     if (version_id != 2)
 845         return -EINVAL;
 846
 847     for (i = 0; i < DBDMA_CHANNELS; i++)
 848         for (j = 0; j < DBDMA_REGS; j++)
 849             qemu_get_be32s(f, &s[i].regs[j]);
 850
 851     return 0;
 852 }
 853
 854 static void dbdma_reset(void *opaque)
 855 {
 856     DBDMA_channel *s = opaque;
 857     int i;
 858
 859     for (i = 0; i < DBDMA_CHANNELS; i++)
 860         memset(s[i].regs, 0, DBDMA_SIZE);
 861 }
 862
 863 void* DBDMA_init (int *dbdma_mem_index)
 864 {
 865     DBDMA_channel *s;
 866
 867     s = qemu_mallocz(sizeof(DBDMA_channel) * DBDMA_CHANNELS);
 868
 869     *dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, s);
 870     register_savevm("dbdma", -1, 1, dbdma_save, dbdma_load, s);
 871     qemu_register_reset(dbdma_reset, s);
 872     dbdma_reset(s);
 873
 874     dbdma_bh = qemu_bh_new(DBDMA_run_bh, s);
 875
 876     return s;
 877 }