hw/ppc4xx_devs.c

   1 /*
   2  * QEMU PowerPC 4xx embedded processors shared devices emulation
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "ppc.h"
  26 #include "ppc4xx.h"
  27 #include "sysemu.h"
  28 #include "qemu-log.h"
  29
  30 //#define DEBUG_MMIO
  31 //#define DEBUG_UNASSIGNED
  32 #define DEBUG_UIC
  33
  34
  35 #ifdef DEBUG_UIC
  36 #  define LOG_UIC(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
  37 #else
  38 #  define LOG_UIC(...) do { } while (0)
  39 #endif
  40
  41 /*****************************************************************************/
  42 /* Generic PowerPC 4xx processor instanciation */
  43 CPUState *ppc4xx_init (const char *cpu_model,
  44                        clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
  45                        uint32_t sysclk)
  46 {
  47     CPUState *env;
  48
  49     /* init CPUs */
  50     env = cpu_init(cpu_model);
  51     if (!env) {
  52         fprintf(stderr, "Unable to find PowerPC %s CPU definition\n",
  53                 cpu_model);
  54         exit(1);
  55     }
  56     cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */
  57     cpu_clk->opaque = env;
  58     /* Set time-base frequency to sysclk */
  59     tb_clk->cb = ppc_emb_timers_init(env, sysclk);
  60     tb_clk->opaque = env;
  61     ppc_dcr_init(env, NULL, NULL);
  62     /* Register qemu callbacks */
  63     qemu_register_reset(&cpu_ppc_reset, env);
  64
  65     return env;
  66 }
  67
  68 /*****************************************************************************/
  69 /* Fake device used to map multiple devices in a single memory page */
  70 #define MMIO_AREA_BITS 8
  71 #define MMIO_AREA_LEN (1 << MMIO_AREA_BITS)
  72 #define MMIO_AREA_NB (1 << (TARGET_PAGE_BITS - MMIO_AREA_BITS))
  73 #define MMIO_IDX(addr) (((addr) >> MMIO_AREA_BITS) & (MMIO_AREA_NB - 1))
  74 struct ppc4xx_mmio_t {
  75     target_phys_addr_t base;
  76     CPUReadMemoryFunc **mem_read[MMIO_AREA_NB];
  77     CPUWriteMemoryFunc **mem_write[MMIO_AREA_NB];
  78     void *opaque[MMIO_AREA_NB];
  79 };
  80
  81 static uint32_t unassigned_mmio_readb (void *opaque, target_phys_addr_t addr)
  82 {
  83 #ifdef DEBUG_UNASSIGNED
  84     ppc4xx_mmio_t *mmio;
  85
  86     mmio = opaque;
  87     printf("Unassigned mmio read 0x" PADDRX " base " PADDRX "\n",
  88            addr, mmio->base);
  89 #endif
  90
  91     return 0;
  92 }
  93
  94 static void unassigned_mmio_writeb (void *opaque,
  95                                     target_phys_addr_t addr, uint32_t val)
  96 {
  97 #ifdef DEBUG_UNASSIGNED
  98     ppc4xx_mmio_t *mmio;
  99
 100     mmio = opaque;
 101     printf("Unassigned mmio write 0x" PADDRX " = 0x%x base " PADDRX "\n",
 102            addr, val, mmio->base);
 103 #endif
 104 }
 105
 106 static CPUReadMemoryFunc *unassigned_mmio_read[3] = {
 107     unassigned_mmio_readb,
 108     unassigned_mmio_readb,
 109     unassigned_mmio_readb,
 110 };
 111
 112 static CPUWriteMemoryFunc *unassigned_mmio_write[3] = {
 113     unassigned_mmio_writeb,
 114     unassigned_mmio_writeb,
 115     unassigned_mmio_writeb,
 116 };
 117
 118 static uint32_t mmio_readlen (ppc4xx_mmio_t *mmio,
 119                               target_phys_addr_t addr, int len)
 120 {
 121     CPUReadMemoryFunc **mem_read;
 122     uint32_t ret;
 123     int idx;
 124
 125     idx = MMIO_IDX(addr);
 126 #if defined(DEBUG_MMIO)
 127     printf("%s: mmio %p len %d addr " PADDRX " idx %d\n", __func__,
 128            mmio, len, addr, idx);
 129 #endif
 130     mem_read = mmio->mem_read[idx];
 131     ret = (*mem_read[len])(mmio->opaque[idx], addr);
 132
 133     return ret;
 134 }
 135
 136 static void mmio_writelen (ppc4xx_mmio_t *mmio,
 137                            target_phys_addr_t addr, uint32_t value, int len)
 138 {
 139     CPUWriteMemoryFunc **mem_write;
 140     int idx;
 141
 142     idx = MMIO_IDX(addr);
 143 #if defined(DEBUG_MMIO)
 144     printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08" PRIx32 "\n",
 145            __func__, mmio, len, addr, idx, value);
 146 #endif
 147     mem_write = mmio->mem_write[idx];
 148     (*mem_write[len])(mmio->opaque[idx], addr, value);
 149 }
 150
 151 static uint32_t mmio_readb (void *opaque, target_phys_addr_t addr)
 152 {
 153 #if defined(DEBUG_MMIO)
 154     printf("%s: addr " PADDRX "\n", __func__, addr);
 155 #endif
 156
 157     return mmio_readlen(opaque, addr, 0);
 158 }
 159
 160 static void mmio_writeb (void *opaque,
 161                          target_phys_addr_t addr, uint32_t value)
 162 {
 163 #if defined(DEBUG_MMIO)
 164     printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
 165 #endif
 166     mmio_writelen(opaque, addr, value, 0);
 167 }
 168
 169 static uint32_t mmio_readw (void *opaque, target_phys_addr_t addr)
 170 {
 171 #if defined(DEBUG_MMIO)
 172     printf("%s: addr " PADDRX "\n", __func__, addr);
 173 #endif
 174
 175     return mmio_readlen(opaque, addr, 1);
 176 }
 177
 178 static void mmio_writew (void *opaque,
 179                          target_phys_addr_t addr, uint32_t value)
 180 {
 181 #if defined(DEBUG_MMIO)
 182     printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
 183 #endif
 184     mmio_writelen(opaque, addr, value, 1);
 185 }
 186
 187 static uint32_t mmio_readl (void *opaque, target_phys_addr_t addr)
 188 {
 189 #if defined(DEBUG_MMIO)
 190     printf("%s: addr " PADDRX "\n", __func__, addr);
 191 #endif
 192
 193     return mmio_readlen(opaque, addr, 2);
 194 }
 195
 196 static void mmio_writel (void *opaque,
 197                          target_phys_addr_t addr, uint32_t value)
 198 {
 199 #if defined(DEBUG_MMIO)
 200     printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
 201 #endif
 202     mmio_writelen(opaque, addr, value, 2);
 203 }
 204
 205 static CPUReadMemoryFunc *mmio_read[] = {
 206     &mmio_readb,
 207     &mmio_readw,
 208     &mmio_readl,
 209 };
 210
 211 static CPUWriteMemoryFunc *mmio_write[] = {
 212     &mmio_writeb,
 213     &mmio_writew,
 214     &mmio_writel,
 215 };
 216
 217 int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
 218                           target_phys_addr_t offset, uint32_t len,
 219                           CPUReadMemoryFunc **mem_read,
 220                           CPUWriteMemoryFunc **mem_write, void *opaque)
 221 {
 222     target_phys_addr_t end;
 223     int idx, eidx;
 224
 225     if ((offset + len) > TARGET_PAGE_SIZE)
 226         return -1;
 227     idx = MMIO_IDX(offset);
 228     end = offset + len - 1;
 229     eidx = MMIO_IDX(end);
 230 #if defined(DEBUG_MMIO)
 231     printf("%s: offset " PADDRX " len %08" PRIx32 " " PADDRX " %d %d\n",
 232            __func__, offset, len, end, idx, eidx);
 233 #endif
 234     for (; idx <= eidx; idx++) {
 235         mmio->mem_read[idx] = mem_read;
 236         mmio->mem_write[idx] = mem_write;
 237         mmio->opaque[idx] = opaque;
 238     }
 239
 240     return 0;
 241 }
 242
 243 ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base)
 244 {
 245     ppc4xx_mmio_t *mmio;
 246     int mmio_memory;
 247
 248     mmio = qemu_mallocz(sizeof(ppc4xx_mmio_t));
 249     if (mmio != NULL) {
 250         mmio->base = base;
 251         mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio);
 252 #if defined(DEBUG_MMIO)
 253         printf("%s: base " PADDRX " len %08x %d\n", __func__,
 254                base, TARGET_PAGE_SIZE, mmio_memory);
 255 #endif
 256         cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory);
 257         ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE,
 258                              unassigned_mmio_read, unassigned_mmio_write,
 259                              mmio);
 260     }
 261
 262     return mmio;
 263 }
 264
 265 /*****************************************************************************/
 266 /* "Universal" Interrupt controller */
 267 enum {
 268     DCR_UICSR  = 0x000,
 269     DCR_UICSRS = 0x001,
 270     DCR_UICER  = 0x002,
 271     DCR_UICCR  = 0x003,
 272     DCR_UICPR  = 0x004,
 273     DCR_UICTR  = 0x005,
 274     DCR_UICMSR = 0x006,
 275     DCR_UICVR  = 0x007,
 276     DCR_UICVCR = 0x008,
 277     DCR_UICMAX = 0x009,
 278 };
 279
 280 #define UIC_MAX_IRQ 32
 281 typedef struct ppcuic_t ppcuic_t;
 282 struct ppcuic_t {
 283     uint32_t dcr_base;
 284     int use_vectors;
 285     uint32_t level;  /* Remembers the state of level-triggered interrupts. */
 286     uint32_t uicsr;  /* Status register */
 287     uint32_t uicer;  /* Enable register */
 288     uint32_t uiccr;  /* Critical register */
 289     uint32_t uicpr;  /* Polarity register */
 290     uint32_t uictr;  /* Triggering register */
 291     uint32_t uicvcr; /* Vector configuration register */
 292     uint32_t uicvr;
 293     qemu_irq *irqs;
 294 };
 295
 296 static void ppcuic_trigger_irq (ppcuic_t *uic)
 297 {
 298     uint32_t ir, cr;
 299     int start, end, inc, i;
 300
 301     /* Trigger interrupt if any is pending */
 302     ir = uic->uicsr & uic->uicer & (~uic->uiccr);
 303     cr = uic->uicsr & uic->uicer & uic->uiccr;
 304     LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32
 305                 " uiccr %08" PRIx32 "\n"
 306                 "   %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n",
 307                 __func__, uic->uicsr, uic->uicer, uic->uiccr,
 308                 uic->uicsr & uic->uicer, ir, cr);
 309     if (ir != 0x0000000) {
 310         LOG_UIC("Raise UIC interrupt\n");
 311         qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]);
 312     } else {
 313         LOG_UIC("Lower UIC interrupt\n");
 314         qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]);
 315     }
 316     /* Trigger critical interrupt if any is pending and update vector */
 317     if (cr != 0x0000000) {
 318         qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]);
 319         if (uic->use_vectors) {
 320             /* Compute critical IRQ vector */
 321             if (uic->uicvcr & 1) {
 322                 start = 31;
 323                 end = 0;
 324                 inc = -1;
 325             } else {
 326                 start = 0;
 327                 end = 31;
 328                 inc = 1;
 329             }
 330             uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
 331             for (i = start; i <= end; i += inc) {
 332                 if (cr & (1 << i)) {
 333                     uic->uicvr += (i - start) * 512 * inc;
 334                     break;
 335                 }
 336             }
 337         }
 338         LOG_UIC("Raise UIC critical interrupt - "
 339                     "vector %08" PRIx32 "\n", uic->uicvr);
 340     } else {
 341         LOG_UIC("Lower UIC critical interrupt\n");
 342         qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]);
 343         uic->uicvr = 0x00000000;
 344     }
 345 }
 346
 347 static void ppcuic_set_irq (void *opaque, int irq_num, int level)
 348 {
 349     ppcuic_t *uic;
 350     uint32_t mask, sr;
 351
 352     uic = opaque;
 353     mask = 1 << (31-irq_num);
 354     LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32
 355                 " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
 356                 __func__, irq_num, level,
 357                 uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
 358     if (irq_num < 0 || irq_num > 31)
 359         return;
 360     sr = uic->uicsr;
 361
 362     /* Update status register */
 363     if (uic->uictr & mask) {
 364         /* Edge sensitive interrupt */
 365         if (level == 1)
 366             uic->uicsr |= mask;
 367     } else {
 368         /* Level sensitive interrupt */
 369         if (level == 1) {
 370             uic->uicsr |= mask;
 371             uic->level |= mask;
 372         } else {
 373             uic->uicsr &= ~mask;
 374             uic->level &= ~mask;
 375         }
 376     }
 377     LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => "
 378                 "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr);
 379     if (sr != uic->uicsr)
 380         ppcuic_trigger_irq(uic);
 381 }
 382
 383 static target_ulong dcr_read_uic (void *opaque, int dcrn)
 384 {
 385     ppcuic_t *uic;
 386     target_ulong ret;
 387
 388     uic = opaque;
 389     dcrn -= uic->dcr_base;
 390     switch (dcrn) {
 391     case DCR_UICSR:
 392     case DCR_UICSRS:
 393         ret = uic->uicsr;
 394         break;
 395     case DCR_UICER:
 396         ret = uic->uicer;
 397         break;
 398     case DCR_UICCR:
 399         ret = uic->uiccr;
 400         break;
 401     case DCR_UICPR:
 402         ret = uic->uicpr;
 403         break;
 404     case DCR_UICTR:
 405         ret = uic->uictr;
 406         break;
 407     case DCR_UICMSR:
 408         ret = uic->uicsr & uic->uicer;
 409         break;
 410     case DCR_UICVR:
 411         if (!uic->use_vectors)
 412             goto no_read;
 413         ret = uic->uicvr;
 414         break;
 415     case DCR_UICVCR:
 416         if (!uic->use_vectors)
 417             goto no_read;
 418         ret = uic->uicvcr;
 419         break;
 420     default:
 421     no_read:
 422         ret = 0x00000000;
 423         break;
 424     }
 425
 426     return ret;
 427 }
 428
 429 static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
 430 {
 431     ppcuic_t *uic;
 432
 433     uic = opaque;
 434     dcrn -= uic->dcr_base;
 435     LOG_UIC("%s: dcr %d val " ADDRX "\n", __func__, dcrn, val);
 436     switch (dcrn) {
 437     case DCR_UICSR:
 438         uic->uicsr &= ~val;
 439         uic->uicsr |= uic->level;
 440         ppcuic_trigger_irq(uic);
 441         break;
 442     case DCR_UICSRS:
 443         uic->uicsr |= val;
 444         ppcuic_trigger_irq(uic);
 445         break;
 446     case DCR_UICER:
 447         uic->uicer = val;
 448         ppcuic_trigger_irq(uic);
 449         break;
 450     case DCR_UICCR:
 451         uic->uiccr = val;
 452         ppcuic_trigger_irq(uic);
 453         break;
 454     case DCR_UICPR:
 455         uic->uicpr = val;
 456         break;
 457     case DCR_UICTR:
 458         uic->uictr = val;
 459         ppcuic_trigger_irq(uic);
 460         break;
 461     case DCR_UICMSR:
 462         break;
 463     case DCR_UICVR:
 464         break;
 465     case DCR_UICVCR:
 466         uic->uicvcr = val & 0xFFFFFFFD;
 467         ppcuic_trigger_irq(uic);
 468         break;
 469     }
 470 }
 471
 472 static void ppcuic_reset (void *opaque)
 473 {
 474     ppcuic_t *uic;
 475
 476     uic = opaque;
 477     uic->uiccr = 0x00000000;
 478     uic->uicer = 0x00000000;
 479     uic->uicpr = 0x00000000;
 480     uic->uicsr = 0x00000000;
 481     uic->uictr = 0x00000000;
 482     if (uic->use_vectors) {
 483         uic->uicvcr = 0x00000000;
 484         uic->uicvr = 0x0000000;
 485     }
 486 }
 487
 488 qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
 489                        uint32_t dcr_base, int has_ssr, int has_vr)
 490 {
 491     ppcuic_t *uic;
 492     int i;
 493
 494     uic = qemu_mallocz(sizeof(ppcuic_t));
 495     if (uic != NULL) {
 496         uic->dcr_base = dcr_base;
 497         uic->irqs = irqs;
 498         if (has_vr)
 499             uic->use_vectors = 1;
 500         for (i = 0; i < DCR_UICMAX; i++) {
 501             ppc_dcr_register(env, dcr_base + i, uic,
 502                              &dcr_read_uic, &dcr_write_uic);
 503         }
 504         qemu_register_reset(ppcuic_reset, uic);
 505         ppcuic_reset(uic);
 506     }
 507
 508     return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
 509 }
 510
 511 /*****************************************************************************/
 512 /* SDRAM controller */
 513 typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
 514 struct ppc4xx_sdram_t {
 515     uint32_t addr;
 516     int nbanks;
 517     target_phys_addr_t ram_bases[4];
 518     target_phys_addr_t ram_sizes[4];
 519     uint32_t besr0;
 520     uint32_t besr1;
 521     uint32_t bear;
 522     uint32_t cfg;
 523     uint32_t status;
 524     uint32_t rtr;
 525     uint32_t pmit;
 526     uint32_t bcr[4];
 527     uint32_t tr;
 528     uint32_t ecccfg;
 529     uint32_t eccesr;
 530     qemu_irq irq;
 531 };
 532
 533 enum {
 534     SDRAM0_CFGADDR = 0x010,
 535     SDRAM0_CFGDATA = 0x011,
 536 };
 537
 538 /* XXX: TOFIX: some patches have made this code become inconsistent:
 539  *      there are type inconsistencies, mixing target_phys_addr_t, target_ulong
 540  *      and uint32_t
 541  */
 542 static uint32_t sdram_bcr (target_phys_addr_t ram_base,
 543                            target_phys_addr_t ram_size)
 544 {
 545     uint32_t bcr;
 546
 547     switch (ram_size) {
 548     case (4 * 1024 * 1024):
 549         bcr = 0x00000000;
 550         break;
 551     case (8 * 1024 * 1024):
 552         bcr = 0x00020000;
 553         break;
 554     case (16 * 1024 * 1024):
 555         bcr = 0x00040000;
 556         break;
 557     case (32 * 1024 * 1024):
 558         bcr = 0x00060000;
 559         break;
 560     case (64 * 1024 * 1024):
 561         bcr = 0x00080000;
 562         break;
 563     case (128 * 1024 * 1024):
 564         bcr = 0x000A0000;
 565         break;
 566     case (256 * 1024 * 1024):
 567         bcr = 0x000C0000;
 568         break;
 569     default:
 570         printf("%s: invalid RAM size " PADDRX "\n", __func__, ram_size);
 571         return 0x00000000;
 572     }
 573     bcr |= ram_base & 0xFF800000;
 574     bcr |= 1;
 575
 576     return bcr;
 577 }
 578
 579 static always_inline target_phys_addr_t sdram_base (uint32_t bcr)
 580 {
 581     return bcr & 0xFF800000;
 582 }
 583
 584 static target_ulong sdram_size (uint32_t bcr)
 585 {
 586     target_ulong size;
 587     int sh;
 588
 589     sh = (bcr >> 17) & 0x7;
 590     if (sh == 7)
 591         size = -1;
 592     else
 593         size = (4 * 1024 * 1024) << sh;
 594
 595     return size;
 596 }
 597
 598 static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
 599 {
 600     if (*bcrp & 0x00000001) {
 601         /* Unmap RAM */
 602 #ifdef DEBUG_SDRAM
 603         printf("%s: unmap RAM area " PADDRX " " ADDRX "\n",
 604                __func__, sdram_base(*bcrp), sdram_size(*bcrp));
 605 #endif
 606         cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp),
 607                                      IO_MEM_UNASSIGNED);
 608     }
 609     *bcrp = bcr & 0xFFDEE001;
 610     if (enabled && (bcr & 0x00000001)) {
 611 #ifdef DEBUG_SDRAM
 612         printf("%s: Map RAM area " PADDRX " " ADDRX "\n",
 613                __func__, sdram_base(bcr), sdram_size(bcr));
 614 #endif
 615         cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr),
 616                                      sdram_base(bcr) | IO_MEM_RAM);
 617     }
 618 }
 619
 620 static void sdram_map_bcr (ppc4xx_sdram_t *sdram)
 621 {
 622     int i;
 623
 624     for (i = 0; i < sdram->nbanks; i++) {
 625         if (sdram->ram_sizes[i] != 0) {
 626             sdram_set_bcr(&sdram->bcr[i],
 627                           sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]),
 628                           1);
 629         } else {
 630             sdram_set_bcr(&sdram->bcr[i], 0x00000000, 0);
 631         }
 632     }
 633 }
 634
 635 static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
 636 {
 637     int i;
 638
 639     for (i = 0; i < sdram->nbanks; i++) {
 640 #ifdef DEBUG_SDRAM
 641         printf("%s: Unmap RAM area " PADDRX " " ADDRX "\n",
 642                __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));
 643 #endif
 644         cpu_register_physical_memory(sdram_base(sdram->bcr[i]),
 645                                      sdram_size(sdram->bcr[i]),
 646                                      IO_MEM_UNASSIGNED);
 647     }
 648 }
 649
 650 static target_ulong dcr_read_sdram (void *opaque, int dcrn)
 651 {
 652     ppc4xx_sdram_t *sdram;
 653     target_ulong ret;
 654
 655     sdram = opaque;
 656     switch (dcrn) {
 657     case SDRAM0_CFGADDR:
 658         ret = sdram->addr;
 659         break;
 660     case SDRAM0_CFGDATA:
 661         switch (sdram->addr) {
 662         case 0x00: /* SDRAM_BESR0 */
 663             ret = sdram->besr0;
 664             break;
 665         case 0x08: /* SDRAM_BESR1 */
 666             ret = sdram->besr1;
 667             break;
 668         case 0x10: /* SDRAM_BEAR */
 669             ret = sdram->bear;
 670             break;
 671         case 0x20: /* SDRAM_CFG */
 672             ret = sdram->cfg;
 673             break;
 674         case 0x24: /* SDRAM_STATUS */
 675             ret = sdram->status;
 676             break;
 677         case 0x30: /* SDRAM_RTR */
 678             ret = sdram->rtr;
 679             break;
 680         case 0x34: /* SDRAM_PMIT */
 681             ret = sdram->pmit;
 682             break;
 683         case 0x40: /* SDRAM_B0CR */
 684             ret = sdram->bcr[0];
 685             break;
 686         case 0x44: /* SDRAM_B1CR */
 687             ret = sdram->bcr[1];
 688             break;
 689         case 0x48: /* SDRAM_B2CR */
 690             ret = sdram->bcr[2];
 691             break;
 692         case 0x4C: /* SDRAM_B3CR */
 693             ret = sdram->bcr[3];
 694             break;
 695         case 0x80: /* SDRAM_TR */
 696             ret = -1; /* ? */
 697             break;
 698         case 0x94: /* SDRAM_ECCCFG */
 699             ret = sdram->ecccfg;
 700             break;
 701         case 0x98: /* SDRAM_ECCESR */
 702             ret = sdram->eccesr;
 703             break;
 704         default: /* Error */
 705             ret = -1;
 706             break;
 707         }
 708         break;
 709     default:
 710         /* Avoid gcc warning */
 711         ret = 0x00000000;
 712         break;
 713     }
 714
 715     return ret;
 716 }
 717
 718 static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val)
 719 {
 720     ppc4xx_sdram_t *sdram;
 721
 722     sdram = opaque;
 723     switch (dcrn) {
 724     case SDRAM0_CFGADDR:
 725         sdram->addr = val;
 726         break;
 727     case SDRAM0_CFGDATA:
 728         switch (sdram->addr) {
 729         case 0x00: /* SDRAM_BESR0 */
 730             sdram->besr0 &= ~val;
 731             break;
 732         case 0x08: /* SDRAM_BESR1 */
 733             sdram->besr1 &= ~val;
 734             break;
 735         case 0x10: /* SDRAM_BEAR */
 736             sdram->bear = val;
 737             break;
 738         case 0x20: /* SDRAM_CFG */
 739             val &= 0xFFE00000;
 740             if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
 741 #ifdef DEBUG_SDRAM
 742                 printf("%s: enable SDRAM controller\n", __func__);
 743 #endif
 744                 /* validate all RAM mappings */
 745                 sdram_map_bcr(sdram);
 746                 sdram->status &= ~0x80000000;
 747             } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
 748 #ifdef DEBUG_SDRAM
 749                 printf("%s: disable SDRAM controller\n", __func__);
 750 #endif
 751                 /* invalidate all RAM mappings */
 752                 sdram_unmap_bcr(sdram);
 753                 sdram->status |= 0x80000000;
 754             }
 755             if (!(sdram->cfg & 0x40000000) && (val & 0x40000000))
 756                 sdram->status |= 0x40000000;
 757             else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000))
 758                 sdram->status &= ~0x40000000;
 759             sdram->cfg = val;
 760             break;
 761         case 0x24: /* SDRAM_STATUS */
 762             /* Read-only register */
 763             break;
 764         case 0x30: /* SDRAM_RTR */
 765             sdram->rtr = val & 0x3FF80000;
 766             break;
 767         case 0x34: /* SDRAM_PMIT */
 768             sdram->pmit = (val & 0xF8000000) | 0x07C00000;
 769             break;
 770         case 0x40: /* SDRAM_B0CR */
 771             sdram_set_bcr(&sdram->bcr[0], val, sdram->cfg & 0x80000000);
 772             break;
 773         case 0x44: /* SDRAM_B1CR */
 774             sdram_set_bcr(&sdram->bcr[1], val, sdram->cfg & 0x80000000);
 775             break;
 776         case 0x48: /* SDRAM_B2CR */
 777             sdram_set_bcr(&sdram->bcr[2], val, sdram->cfg & 0x80000000);
 778             break;
 779         case 0x4C: /* SDRAM_B3CR */
 780             sdram_set_bcr(&sdram->bcr[3], val, sdram->cfg & 0x80000000);
 781             break;
 782         case 0x80: /* SDRAM_TR */
 783             sdram->tr = val & 0x018FC01F;
 784             break;
 785         case 0x94: /* SDRAM_ECCCFG */
 786             sdram->ecccfg = val & 0x00F00000;
 787             break;
 788         case 0x98: /* SDRAM_ECCESR */
 789             val &= 0xFFF0F000;
 790             if (sdram->eccesr == 0 && val != 0)
 791                 qemu_irq_raise(sdram->irq);
 792             else if (sdram->eccesr != 0 && val == 0)
 793                 qemu_irq_lower(sdram->irq);
 794             sdram->eccesr = val;
 795             break;
 796         default: /* Error */
 797             break;
 798         }
 799         break;
 800     }
 801 }
 802
 803 static void sdram_reset (void *opaque)
 804 {
 805     ppc4xx_sdram_t *sdram;
 806
 807     sdram = opaque;
 808     sdram->addr = 0x00000000;
 809     sdram->bear = 0x00000000;
 810     sdram->besr0 = 0x00000000; /* No error */
 811     sdram->besr1 = 0x00000000; /* No error */
 812     sdram->cfg = 0x00000000;
 813     sdram->ecccfg = 0x00000000; /* No ECC */
 814     sdram->eccesr = 0x00000000; /* No error */
 815     sdram->pmit = 0x07C00000;
 816     sdram->rtr = 0x05F00000;
 817     sdram->tr = 0x00854009;
 818     /* We pre-initialize RAM banks */
 819     sdram->status = 0x00000000;
 820     sdram->cfg = 0x00800000;
 821     sdram_unmap_bcr(sdram);
 822 }
 823
 824 void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
 825                         target_phys_addr_t *ram_bases,
 826                         target_phys_addr_t *ram_sizes,
 827                         int do_init)
 828 {
 829     ppc4xx_sdram_t *sdram;
 830
 831     sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t));
 832     if (sdram != NULL) {
 833         sdram->irq = irq;
 834         sdram->nbanks = nbanks;
 835         memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t));
 836         memcpy(sdram->ram_bases, ram_bases,
 837                nbanks * sizeof(target_phys_addr_t));
 838         memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t));
 839         memcpy(sdram->ram_sizes, ram_sizes,
 840                nbanks * sizeof(target_phys_addr_t));
 841         sdram_reset(sdram);
 842         qemu_register_reset(&sdram_reset, sdram);
 843         ppc_dcr_register(env, SDRAM0_CFGADDR,
 844                          sdram, &dcr_read_sdram, &dcr_write_sdram);
 845         ppc_dcr_register(env, SDRAM0_CFGDATA,
 846                          sdram, &dcr_read_sdram, &dcr_write_sdram);
 847         if (do_init)
 848             sdram_map_bcr(sdram);
 849     }
 850 }
 851
 852 /* Fill in consecutive SDRAM banks with 'ram_size' bytes of memory.
 853  *
 854  * sdram_bank_sizes[] must be 0-terminated.
 855  *
 856  * The 4xx SDRAM controller supports a small number of banks, and each bank
 857  * must be one of a small set of sizes. The number of banks and the supported
 858  * sizes varies by SoC. */
 859 ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
 860                                target_phys_addr_t ram_bases[],
 861                                target_phys_addr_t ram_sizes[],
 862                                const unsigned int sdram_bank_sizes[])
 863 {
 864     ram_addr_t ram_end = 0;
 865     int i;
 866     int j;
 867
 868     for (i = 0; i < nr_banks; i++) {
 869         for (j = 0; sdram_bank_sizes[j] != 0; j++) {
 870             unsigned int bank_size = sdram_bank_sizes[j];
 871
 872             if (bank_size <= ram_size) {
 873                 ram_bases[i] = ram_end;
 874                 ram_sizes[i] = bank_size;
 875                 ram_end += bank_size;
 876                 ram_size -= bank_size;
 877                 break;
 878             }
 879         }
 880
 881         if (!ram_size) {
 882             /* No need to use the remaining banks. */
 883             break;
 884         }
 885     }
 886
 887     if (ram_size)
 888         printf("Truncating memory to %d MiB to fit SDRAM controller limits.\n",
 889                (int)(ram_end >> 20));
 890
 891     return ram_end;
 892 }