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Merge tag 'ui-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging
[qemu/kevin.git] / disas / hppa.c
blob2b58434966c3adfd9e96af8dbca04640612223e0
1 /* Disassembler for the PA-RISC. Somewhat derived from sparc-pinsn.c.
2 Copyright 1989, 1990, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2003,
3 2005 Free Software Foundation, Inc.
4
5 Contributed by the Center for Software Science at the
6 University of Utah (pa-gdb-bugs@cs.utah.edu).
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, see <http://www.gnu.org/licenses/>. */
20
21 #include "qemu/osdep.h"
22 #include "disas/dis-asm.h"
23
24 /* HP PA-RISC SOM object file format: definitions internal to BFD.
25 Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000,
26 2003 Free Software Foundation, Inc.
27
28 Contributed by the Center for Software Science at the
29 University of Utah (pa-gdb-bugs@cs.utah.edu).
30
31 This file is part of BFD, the Binary File Descriptor library.
32
33 This program is free software; you can redistribute it and/or modify
34 it under the terms of the GNU General Public License as published by
35 the Free Software Foundation; either version 2 of the License, or
36 (at your option) any later version.
37
38 This program is distributed in the hope that it will be useful,
39 but WITHOUT ANY WARRANTY; without even the implied warranty of
40 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
41 GNU General Public License for more details.
42
43 You should have received a copy of the GNU General Public License
44 along with this program; if not, see <http://www.gnu.org/licenses/>. */
45
46 #ifndef _LIBHPPA_H
47 #define _LIBHPPA_H
48
49 #define BYTES_IN_WORD 4
50 #define PA_PAGESIZE 0x1000
51
52 /* The PA instruction set variants. */
53 enum pa_arch {pa10 = 10, pa11 = 11, pa20 = 20, pa20w = 25};
54
55 /* HP PA-RISC relocation types */
56
57 enum hppa_reloc_field_selector_type
58 {
59 R_HPPA_FSEL = 0x0,
60 R_HPPA_LSSEL = 0x1,
61 R_HPPA_RSSEL = 0x2,
62 R_HPPA_LSEL = 0x3,
63 R_HPPA_RSEL = 0x4,
64 R_HPPA_LDSEL = 0x5,
65 R_HPPA_RDSEL = 0x6,
66 R_HPPA_LRSEL = 0x7,
67 R_HPPA_RRSEL = 0x8,
68 R_HPPA_NSEL = 0x9,
69 R_HPPA_NLSEL = 0xa,
70 R_HPPA_NLRSEL = 0xb,
71 R_HPPA_PSEL = 0xc,
72 R_HPPA_LPSEL = 0xd,
73 R_HPPA_RPSEL = 0xe,
74 R_HPPA_TSEL = 0xf,
75 R_HPPA_LTSEL = 0x10,
76 R_HPPA_RTSEL = 0x11,
77 R_HPPA_LTPSEL = 0x12,
78 R_HPPA_RTPSEL = 0x13
79 };
80
81 /* /usr/include/reloc.h defines these to constants. We want to use
82 them in enums, so #undef them before we start using them. We might
83 be able to fix this another way by simply managing not to include
84 /usr/include/reloc.h, but currently GDB picks up these defines
85 somewhere. */
86 #undef e_fsel
87 #undef e_lssel
88 #undef e_rssel
89 #undef e_lsel
90 #undef e_rsel
91 #undef e_ldsel
92 #undef e_rdsel
93 #undef e_lrsel
94 #undef e_rrsel
95 #undef e_nsel
96 #undef e_nlsel
97 #undef e_nlrsel
98 #undef e_psel
99 #undef e_lpsel
100 #undef e_rpsel
101 #undef e_tsel
102 #undef e_ltsel
103 #undef e_rtsel
104 #undef e_one
105 #undef e_two
106 #undef e_pcrel
107 #undef e_con
108 #undef e_plabel
109 #undef e_abs
110
111 /* for compatibility */
112 enum hppa_reloc_field_selector_type_alt
113 {
114 e_fsel = R_HPPA_FSEL,
115 e_lssel = R_HPPA_LSSEL,
116 e_rssel = R_HPPA_RSSEL,
117 e_lsel = R_HPPA_LSEL,
118 e_rsel = R_HPPA_RSEL,
119 e_ldsel = R_HPPA_LDSEL,
120 e_rdsel = R_HPPA_RDSEL,
121 e_lrsel = R_HPPA_LRSEL,
122 e_rrsel = R_HPPA_RRSEL,
123 e_nsel = R_HPPA_NSEL,
124 e_nlsel = R_HPPA_NLSEL,
125 e_nlrsel = R_HPPA_NLRSEL,
126 e_psel = R_HPPA_PSEL,
127 e_lpsel = R_HPPA_LPSEL,
128 e_rpsel = R_HPPA_RPSEL,
129 e_tsel = R_HPPA_TSEL,
130 e_ltsel = R_HPPA_LTSEL,
131 e_rtsel = R_HPPA_RTSEL,
132 e_ltpsel = R_HPPA_LTPSEL,
133 e_rtpsel = R_HPPA_RTPSEL
134 };
135
136 enum hppa_reloc_expr_type
137 {
138 R_HPPA_E_ONE = 0,
139 R_HPPA_E_TWO = 1,
140 R_HPPA_E_PCREL = 2,
141 R_HPPA_E_CON = 3,
142 R_HPPA_E_PLABEL = 7,
143 R_HPPA_E_ABS = 18
144 };
145
146 /* for compatibility */
147 enum hppa_reloc_expr_type_alt
148 {
149 e_one = R_HPPA_E_ONE,
150 e_two = R_HPPA_E_TWO,
151 e_pcrel = R_HPPA_E_PCREL,
152 e_con = R_HPPA_E_CON,
153 e_plabel = R_HPPA_E_PLABEL,
154 e_abs = R_HPPA_E_ABS
155 };
156
157
158 /* Relocations for function calls must be accompanied by parameter
159 relocation bits. These bits describe exactly where the caller has
160 placed the function's arguments and where it expects to find a return
161 value.
162
163 Both ELF and SOM encode this information within the addend field
164 of the call relocation. (Note this could break very badly if one
165 was to make a call like bl foo + 0x12345678).
166
167 The high order 10 bits contain parameter relocation information,
168 the low order 22 bits contain the constant offset. */
169
170 #define HPPA_R_ARG_RELOC(a) \
171 (((a) >> 22) & 0x3ff)
172 #define HPPA_R_CONSTANT(a) \
173 ((((bfd_signed_vma)(a)) << (BFD_ARCH_SIZE-22)) >> (BFD_ARCH_SIZE-22))
174 #define HPPA_R_ADDEND(r, c) \
175 (((r) << 22) + ((c) & 0x3fffff))
176
177
178 /* Some functions to manipulate PA instructions. */
179
180 /* Declare the functions with the unused attribute to avoid warnings. */
181 static inline int sign_extend (int, int) ATTRIBUTE_UNUSED;
182 static inline int low_sign_extend (int, int) ATTRIBUTE_UNUSED;
183 static inline int sign_unext (int, int) ATTRIBUTE_UNUSED;
184 static inline int low_sign_unext (int, int) ATTRIBUTE_UNUSED;
185 static inline int re_assemble_3 (int) ATTRIBUTE_UNUSED;
186 static inline int re_assemble_12 (int) ATTRIBUTE_UNUSED;
187 static inline int re_assemble_14 (int) ATTRIBUTE_UNUSED;
188 static inline int re_assemble_16 (int) ATTRIBUTE_UNUSED;
189 static inline int re_assemble_17 (int) ATTRIBUTE_UNUSED;
190 static inline int re_assemble_21 (int) ATTRIBUTE_UNUSED;
191 static inline int re_assemble_22 (int) ATTRIBUTE_UNUSED;
192 static inline bfd_signed_vma hppa_field_adjust
193 (bfd_vma, bfd_signed_vma, enum hppa_reloc_field_selector_type_alt)
194 ATTRIBUTE_UNUSED;
195 static inline int hppa_rebuild_insn (int, int, int) ATTRIBUTE_UNUSED;
196
197
198 /* The *sign_extend functions are used to assemble various bitfields
199 taken from an instruction and return the resulting immediate
200 value. */
201
202 static inline int
203 sign_extend (int x, int len)
204 {
205 int signbit = (1 << (len - 1));
206 int mask = (signbit << 1) - 1;
207 return ((x & mask) ^ signbit) - signbit;
208 }
209
210 static inline int
211 low_sign_extend (int x, int len)
212 {
213 return (x >> 1) - ((x & 1) << (len - 1));
214 }
215
216
217 /* The re_assemble_* functions prepare an immediate value for
218 insertion into an opcode. pa-risc uses all sorts of weird bitfields
219 in the instruction to hold the value. */
220
221 static inline int
222 sign_unext (int x, int len)
223 {
224 int len_ones;
225
226 len_ones = (1 << len) - 1;
227
228 return x & len_ones;
229 }
230
231 static inline int
232 low_sign_unext (int x, int len)
233 {
234 int temp;
235 int sign;
236
237 sign = (x >> (len-1)) & 1;
238
239 temp = sign_unext (x, len-1);
240
241 return (temp << 1) | sign;
242 }
243
244 static inline int
245 re_assemble_3 (int as3)
246 {
247 return (( (as3 & 4) << (13-2))
248 | ((as3 & 3) << (13+1)));
249 }
250
251 static inline int
252 re_assemble_12 (int as12)
253 {
254 return (( (as12 & 0x800) >> 11)
255 | ((as12 & 0x400) >> (10 - 2))
256 | ((as12 & 0x3ff) << (1 + 2)));
257 }
258
259 static inline int
260 re_assemble_14 (int as14)
261 {
262 return (( (as14 & 0x1fff) << 1)
263 | ((as14 & 0x2000) >> 13));
264 }
265
266 static inline int
267 re_assemble_16 (int as16)
268 {
269 int s, t;
270
271 /* Unusual 16-bit encoding, for wide mode only. */
272 t = (as16 << 1) & 0xffff;
273 s = (as16 & 0x8000);
274 return (t ^ s ^ (s >> 1)) | (s >> 15);
275 }
276
277 static inline int
278 re_assemble_17 (int as17)
279 {
280 return (( (as17 & 0x10000) >> 16)
281 | ((as17 & 0x0f800) << (16 - 11))
282 | ((as17 & 0x00400) >> (10 - 2))
283 | ((as17 & 0x003ff) << (1 + 2)));
284 }
285
286 static inline int
287 re_assemble_21 (int as21)
288 {
289 return (( (as21 & 0x100000) >> 20)
290 | ((as21 & 0x0ffe00) >> 8)
291 | ((as21 & 0x000180) << 7)
292 | ((as21 & 0x00007c) << 14)
293 | ((as21 & 0x000003) << 12));
294 }
295
296 static inline int
297 re_assemble_22 (int as22)
298 {
299 return (( (as22 & 0x200000) >> 21)
300 | ((as22 & 0x1f0000) << (21 - 16))
301 | ((as22 & 0x00f800) << (16 - 11))
302 | ((as22 & 0x000400) >> (10 - 2))
303 | ((as22 & 0x0003ff) << (1 + 2)));
304 }
305
306
307 /* Handle field selectors for PA instructions.
308 The L and R (and LS, RS etc.) selectors are used in pairs to form a
309 full 32 bit address. eg.
310
311 LDIL L'start,%r1 ; put left part into r1
312 LDW R'start(%r1),%r2 ; add r1 and right part to form address
313
314 This function returns sign extended values in all cases.
315 */
316
317 static inline bfd_signed_vma
318 hppa_field_adjust (bfd_vma sym_val,
319 bfd_signed_vma addend,
320 enum hppa_reloc_field_selector_type_alt r_field)
321 {
322 bfd_signed_vma value;
323
324 value = sym_val + addend;
325 switch (r_field)
326 {
327 case e_fsel:
328 /* F: No change. */
329 break;
330
331 case e_nsel:
332 /* N: null selector. I don't really understand what this is all
333 about, but HP's documentation says "this indicates that zero
334 bits are to be used for the displacement on the instruction.
335 This fixup is used to identify three-instruction sequences to
336 access data (for importing shared library data)." */
337 value = 0;
338 break;
339
340 case e_lsel:
341 case e_nlsel:
342 /* L: Select top 21 bits. */
343 value = value >> 11;
344 break;
345
346 case e_rsel:
347 /* R: Select bottom 11 bits. */
348 value = value & 0x7ff;
349 break;
350
351 case e_lssel:
352 /* LS: Round to nearest multiple of 2048 then select top 21 bits. */
353 value = value + 0x400;
354 value = value >> 11;
355 break;
356
357 case e_rssel:
358 /* RS: Select bottom 11 bits for LS.
359 We need to return a value such that 2048 * LS'x + RS'x == x.
360 ie. RS'x = x - ((x + 0x400) & -0x800)
361 this is just a sign extension from bit 21. */
362 value = ((value & 0x7ff) ^ 0x400) - 0x400;
363 break;
364
365 case e_ldsel:
366 /* LD: Round to next multiple of 2048 then select top 21 bits.
367 Yes, if we are already on a multiple of 2048, we go up to the
368 next one. RD in this case will be -2048. */
369 value = value + 0x800;
370 value = value >> 11;
371 break;
372
373 case e_rdsel:
374 /* RD: Set bits 0-20 to one. */
375 value = value | -0x800;
376 break;
377
378 case e_lrsel:
379 case e_nlrsel:
380 /* LR: L with rounding of the addend to nearest 8k. */
381 value = sym_val + ((addend + 0x1000) & -0x2000);
382 value = value >> 11;
383 break;
384
385 case e_rrsel:
386 /* RR: R with rounding of the addend to nearest 8k.
387 We need to return a value such that 2048 * LR'x + RR'x == x
388 ie. RR'x = s+a - (s + (((a + 0x1000) & -0x2000) & -0x800))
389 . = s+a - ((s & -0x800) + ((a + 0x1000) & -0x2000))
390 . = (s & 0x7ff) + a - ((a + 0x1000) & -0x2000) */
391 value = (sym_val & 0x7ff) + (((addend & 0x1fff) ^ 0x1000) - 0x1000);
392 break;
393
394 default:
395 abort ();
396 }
397 return value;
398 }
399
400 /* PA-RISC OPCODES */
401 #define get_opcode(insn) (((insn) >> 26) & 0x3f)
402
403 enum hppa_opcode_type
404 {
405 /* None of the opcodes in the first group generate relocs, so we
406 aren't too concerned about them. */
407 OP_SYSOP = 0x00,
408 OP_MEMMNG = 0x01,
409 OP_ALU = 0x02,
410 OP_NDXMEM = 0x03,
411 OP_SPOP = 0x04,
412 OP_DIAG = 0x05,
413 OP_FMPYADD = 0x06,
414 OP_UNDEF07 = 0x07,
415 OP_COPRW = 0x09,
416 OP_COPRDW = 0x0b,
417 OP_COPR = 0x0c,
418 OP_FLOAT = 0x0e,
419 OP_PRDSPEC = 0x0f,
420 OP_UNDEF15 = 0x15,
421 OP_UNDEF1d = 0x1d,
422 OP_FMPYSUB = 0x26,
423 OP_FPFUSED = 0x2e,
424 OP_SHEXDP0 = 0x34,
425 OP_SHEXDP1 = 0x35,
426 OP_SHEXDP2 = 0x36,
427 OP_UNDEF37 = 0x37,
428 OP_SHEXDP3 = 0x3c,
429 OP_SHEXDP4 = 0x3d,
430 OP_MULTMED = 0x3e,
431 OP_UNDEF3f = 0x3f,
432
433 OP_LDIL = 0x08,
434 OP_ADDIL = 0x0a,
435
436 OP_LDO = 0x0d,
437 OP_LDB = 0x10,
438 OP_LDH = 0x11,
439 OP_LDW = 0x12,
440 OP_LDWM = 0x13,
441 OP_STB = 0x18,
442 OP_STH = 0x19,
443 OP_STW = 0x1a,
444 OP_STWM = 0x1b,
445
446 OP_LDD = 0x14,
447 OP_STD = 0x1c,
448
449 OP_FLDW = 0x16,
450 OP_LDWL = 0x17,
451 OP_FSTW = 0x1e,
452 OP_STWL = 0x1f,
453
454 OP_COMBT = 0x20,
455 OP_COMIBT = 0x21,
456 OP_COMBF = 0x22,
457 OP_COMIBF = 0x23,
458 OP_CMPBDT = 0x27,
459 OP_ADDBT = 0x28,
460 OP_ADDIBT = 0x29,
461 OP_ADDBF = 0x2a,
462 OP_ADDIBF = 0x2b,
463 OP_CMPBDF = 0x2f,
464 OP_BVB = 0x30,
465 OP_BB = 0x31,
466 OP_MOVB = 0x32,
467 OP_MOVIB = 0x33,
468 OP_CMPIBD = 0x3b,
469
470 OP_COMICLR = 0x24,
471 OP_SUBI = 0x25,
472 OP_ADDIT = 0x2c,
473 OP_ADDI = 0x2d,
474
475 OP_BE = 0x38,
476 OP_BLE = 0x39,
477 OP_BL = 0x3a
478 };
479
480
481 /* Insert VALUE into INSN using R_FORMAT to determine exactly what
482 bits to change. */
483
484 static inline int
485 hppa_rebuild_insn (int insn, int value, int r_format)
486 {
487 switch (r_format)
488 {
489 case 11:
490 return (insn & ~ 0x7ff) | low_sign_unext (value, 11);
491
492 case 12:
493 return (insn & ~ 0x1ffd) | re_assemble_12 (value);
494
495
496 case 10:
497 return (insn & ~ 0x3ff1) | re_assemble_14 (value & -8);
498
499 case -11:
500 return (insn & ~ 0x3ff9) | re_assemble_14 (value & -4);
501
502 case 14:
503 return (insn & ~ 0x3fff) | re_assemble_14 (value);
504
505
506 case -10:
507 return (insn & ~ 0xfff1) | re_assemble_16 (value & -8);
508
509 case -16:
510 return (insn & ~ 0xfff9) | re_assemble_16 (value & -4);
511
512 case 16:
513 return (insn & ~ 0xffff) | re_assemble_16 (value);
514
515
516 case 17:
517 return (insn & ~ 0x1f1ffd) | re_assemble_17 (value);
518
519 case 21:
520 return (insn & ~ 0x1fffff) | re_assemble_21 (value);
521
522 case 22:
523 return (insn & ~ 0x3ff1ffd) | re_assemble_22 (value);
524
525 case 32:
526 return value;
527
528 default:
529 abort ();
530 }
531 return insn;
532 }
533
534 #endif /* _LIBHPPA_H */
535 /* Table of opcodes for the PA-RISC.
536 Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000,
537 2001, 2002, 2003, 2004, 2005
538 Free Software Foundation, Inc.
539
540 Contributed by the Center for Software Science at the
541 University of Utah (pa-gdb-bugs@cs.utah.edu).
542
543 This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
544
545 GAS/GDB is free software; you can redistribute it and/or modify
546 it under the terms of the GNU General Public License as published by
547 the Free Software Foundation; either version 1, or (at your option)
548 any later version.
549
550 GAS/GDB is distributed in the hope that it will be useful,
551 but WITHOUT ANY WARRANTY; without even the implied warranty of
552 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
553 GNU General Public License for more details.
554
555 You should have received a copy of the GNU General Public License
556 along with GAS or GDB; see the file COPYING.
557 If not, see <http://www.gnu.org/licenses/>. */
558
559 #if !defined(__STDC__) && !defined(const)
560 #define const
561 #endif
562
563 /*
564 * Structure of an opcode table entry.
565 */
566
567 /* There are two kinds of delay slot nullification: normal which is
568 * controlled by the nullification bit, and conditional, which depends
569 * on the direction of the branch and its success or failure.
570 *
571 * NONE is unfortunately #defined in the hiux system include files.
572 * #undef it away.
573 */
574 #undef NONE
575 struct pa_opcode
576 {
577 const char *name;
578 unsigned long int match; /* Bits that must be set... */
579 unsigned long int mask; /* ... in these bits. */
580 const char *args;
581 enum pa_arch arch;
582 char flags;
583 };
584
585 /* Enables strict matching. Opcodes with match errors are skipped
586 when this bit is set. */
587 #define FLAG_STRICT 0x1
588
589 /*
590 All hppa opcodes are 32 bits.
591
592 The match component is a mask saying which bits must match a
593 particular opcode in order for an instruction to be an instance
594 of that opcode.
595
596 The args component is a string containing one character for each operand of
597 the instruction. Characters used as a prefix allow any second character to
598 be used without conflicting with the main operand characters.
599
600 Bit positions in this description follow HP usage of lsb = 31,
601 "at" is lsb of field.
602
603 In the args field, the following characters must match exactly:
604
605 '+,() '
606
607 In the args field, the following characters are unused:
608
609 ' " - / 34 678 :; '
610 '@ C M [\] '
611 '` e g } '
612
613 Here are all the characters:
614
615 ' !"#$%&'()*+-,./0123456789:;<=>?'
616 '@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_'
617 '`abcdefghijklmnopqrstuvwxyz{|}~ '
618
619 Kinds of operands:
620 x integer register field at 15.
621 b integer register field at 10.
622 t integer register field at 31.
623 a integer register field at 10 and 15 (for PERMH)
624 5 5 bit immediate at 15.
625 s 2 bit space specifier at 17.
626 S 3 bit space specifier at 18.
627 V 5 bit immediate value at 31
628 i 11 bit immediate value at 31
629 j 14 bit immediate value at 31
630 k 21 bit immediate value at 31
631 l 16 bit immediate value at 31 (wide mode only, unusual encoding).
632 n nullification for branch instructions
633 N nullification for spop and copr instructions
634 w 12 bit branch displacement
635 W 17 bit branch displacement (PC relative)
636 X 22 bit branch displacement (PC relative)
637 z 17 bit branch displacement (just a number, not an address)
638
639 Also these:
640
641 . 2 bit shift amount at 25
642 * 4 bit shift amount at 25
643 p 5 bit shift count at 26 (to support the SHD instruction) encoded as
644 31-p
645 ~ 6 bit shift count at 20,22:26 encoded as 63-~.
646 P 5 bit bit position at 26
647 q 6 bit bit position at 20,22:26
648 T 5 bit field length at 31 (encoded as 32-T)
649 % 6 bit field length at 23,27:31 (variable extract/deposit)
650 | 6 bit field length at 19,27:31 (fixed extract/deposit)
651 A 13 bit immediate at 18 (to support the BREAK instruction)
652 ^ like b, but describes a control register
653 9 like b, but describes a diagnose register
654 ! sar (cr11) register
655 D 26 bit immediate at 31 (to support the DIAG instruction)
656 $ 9 bit immediate at 28 (to support POPBTS)
657
658 v 3 bit Special Function Unit identifier at 25
659 O 20 bit Special Function Unit operation split between 15 bits at 20
660 and 5 bits at 31
661 o 15 bit Special Function Unit operation at 20
662 2 22 bit Special Function Unit operation split between 17 bits at 20
663 and 5 bits at 31
664 1 15 bit Special Function Unit operation split between 10 bits at 20
665 and 5 bits at 31
666 0 10 bit Special Function Unit operation split between 5 bits at 20
667 and 5 bits at 31
668 u 3 bit coprocessor unit identifier at 25
669 F Source Floating Point Operand Format Completer encoded 2 bits at 20
670 I Source Floating Point Operand Format Completer encoded 1 bits at 20
671 (for 0xe format FP instructions)
672 G Destination Floating Point Operand Format Completer encoded 2 bits at 18
673 H Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub'
674 (very similar to 'F')
675
676 r 5 bit immediate value at 31 (for the break instruction)
677 (very similar to V above, except the value is unsigned instead of
678 low_sign_ext)
679 R 5 bit immediate value at 15 (for the ssm, rsm, probei instructions)
680 (same as r above, except the value is in a different location)
681 U 10 bit immediate value at 15 (for SSM, RSM on pa2.0)
682 Q 5 bit immediate value at 10 (a bit position specified in
683 the bb instruction. It's the same as r above, except the
684 value is in a different location)
685 B 5 bit immediate value at 10 (a bit position specified in
686 the bb instruction. Similar to Q, but 64 bit handling is
687 different.
688 Z %r1 -- implicit target of addil instruction.
689 L ,%r2 completer for new syntax branch
690 { Source format completer for fcnv
691 _ Destination format completer for fcnv
692 h cbit for fcmp
693 = gfx tests for ftest
694 d 14 bit offset for single precision FP long load/store.
695 # 14 bit offset for double precision FP load long/store.
696 J Yet another 14 bit offset for load/store with ma,mb completers.
697 K Yet another 14 bit offset for load/store with ma,mb completers.
698 y 16 bit offset for word aligned load/store (PA2.0 wide).
699 & 16 bit offset for dword aligned load/store (PA2.0 wide).
700 < 16 bit offset for load/store with ma,mb completers (PA2.0 wide).
701 > 16 bit offset for load/store with ma,mb completers (PA2.0 wide).
702 Y %sr0,%r31 -- implicit target of be,l instruction.
703 @ implicit immediate value of 0
704
705 Completer operands all have 'c' as the prefix:
706
707 cx indexed load and store completer.
708 cX indexed load and store completer. Like cx, but emits a space
709 after in disassembler.
710 cm short load and store completer.
711 cM short load and store completer. Like cm, but emits a space
712 after in disassembler.
713 cq long load and store completer (like cm, but inserted into a
714 different location in the target instruction).
715 cs store bytes short completer.
716 cA store bytes short completer. Like cs, but emits a space
717 after in disassembler.
718 ce long load/store completer for LDW/STW with a different encoding
719 than the others
720 cc load cache control hint
721 cd load and clear cache control hint
722 cC store cache control hint
723 co ordered access
724
725 cp branch link and push completer
726 cP branch pop completer
727 cl branch link completer
728 cg branch gate completer
729
730 cw read/write completer for PROBE
731 cW wide completer for MFCTL
732 cL local processor completer for cache control
733 cZ System Control Completer (to support LPA, LHA, etc.)
734
735 ci correction completer for DCOR
736 ca add completer
737 cy 32 bit add carry completer
738 cY 64 bit add carry completer
739 cv signed overflow trap completer
740 ct trap on condition completer for ADDI, SUB
741 cT trap on condition completer for UADDCM
742 cb 32 bit borrow completer for SUB
743 cB 64 bit borrow completer for SUB
744
745 ch left/right half completer
746 cH signed/unsigned saturation completer
747 cS signed/unsigned completer at 21
748 cz zero/sign extension completer.
749 c* permutation completer
750
751 Condition operands all have '?' as the prefix:
752
753 ?f Floating point compare conditions (encoded as 5 bits at 31)
754
755 ?a add conditions
756 ?A 64 bit add conditions
757 ?@ add branch conditions followed by nullify
758 ?d non-negated add branch conditions
759 ?D negated add branch conditions
760 ?w wide mode non-negated add branch conditions
761 ?W wide mode negated add branch conditions
762
763 ?s compare/subtract conditions
764 ?S 64 bit compare/subtract conditions
765 ?t non-negated compare and branch conditions
766 ?n 32 bit compare and branch conditions followed by nullify
767 ?N 64 bit compare and branch conditions followed by nullify
768 ?Q 64 bit compare and branch conditions for CMPIB instruction
769
770 ?l logical conditions
771 ?L 64 bit logical conditions
772
773 ?b branch on bit conditions
774 ?B 64 bit branch on bit conditions
775
776 ?x shift/extract/deposit conditions
777 ?X 64 bit shift/extract/deposit conditions
778 ?y shift/extract/deposit conditions followed by nullify for conditional
779 branches
780
781 ?u unit conditions
782 ?U 64 bit unit conditions
783
784 Floating point registers all have 'f' as a prefix:
785
786 ft target register at 31
787 fT target register with L/R halves at 31
788 fa operand 1 register at 10
789 fA operand 1 register with L/R halves at 10
790 fX Same as fA, except prints a space before register during disasm
791 fb operand 2 register at 15
792 fB operand 2 register with L/R halves at 15
793 fC operand 3 register with L/R halves at 16:18,21:23
794 fe Like fT, but encoding is different.
795 fE Same as fe, except prints a space before register during disasm.
796 fx target register at 15 (only for PA 2.0 long format FLDD/FSTD).
797
798 Float registers for fmpyadd and fmpysub:
799
800 fi mult operand 1 register at 10
801 fj mult operand 2 register at 15
802 fk mult target register at 20
803 fl add/sub operand register at 25
804 fm add/sub target register at 31
805
806 */
807
808
809 #if 0
810 /* List of characters not to put a space after. Note that
811 "," is included, as the "spopN" operations use literal
812 commas in their completer sections. */
813 static const char *const completer_chars = ",CcY<>?!@+&U~FfGHINnOoZMadu|/=0123%e$m}";
814 #endif
815
816 /* The order of the opcodes in this table is significant:
817
818 * The assembler requires that all instances of the same mnemonic be
819 consecutive. If they aren't, the assembler will bomb at runtime.
820
821 * Immediate fields use pa_get_absolute_expression to parse the
822 string. It will generate a "bad expression" error if passed
823 a register name. Thus, register index variants of an opcode
824 need to precede immediate variants.
825
826 * The disassembler does not care about the order of the opcodes
827 except in cases where implicit addressing is used.
828
829 Here are the rules for ordering the opcodes of a mnemonic:
830
831 1) Opcodes with FLAG_STRICT should precede opcodes without
832 FLAG_STRICT.
833
834 2) Opcodes with FLAG_STRICT should be ordered as follows:
835 register index opcodes, short immediate opcodes, and finally
836 long immediate opcodes. When both pa10 and pa11 variants
837 of the same opcode are available, the pa10 opcode should
838 come first for correct architectural promotion.
839
840 3) When implicit addressing is available for an opcode, the
841 implicit opcode should precede the explicit opcode.
842
843 4) Opcodes without FLAG_STRICT should be ordered as follows:
844 register index opcodes, long immediate opcodes, and finally
845 short immediate opcodes. */
846
847 static const struct pa_opcode pa_opcodes[] =
848 {
849
850 /* Pseudo-instructions. */
851
852 { "ldi", 0x34000000, 0xffe00000, "l,x", pa20w, 0},/* ldo val(r0),r */
853 { "ldi", 0x34000000, 0xffe0c000, "j,x", pa10, 0},/* ldo val(r0),r */
854
855 { "cmpib", 0xec000000, 0xfc000000, "?Qn5,b,w", pa20, FLAG_STRICT},
856 { "cmpib", 0x84000000, 0xf4000000, "?nn5,b,w", pa10, FLAG_STRICT},
857 { "comib", 0x84000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/
858 /* This entry is for the disassembler only. It will never be used by
859 assembler. */
860 { "comib", 0x8c000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/
861 { "cmpb", 0x9c000000, 0xdc000000, "?Nnx,b,w", pa20, FLAG_STRICT},
862 { "cmpb", 0x80000000, 0xf4000000, "?nnx,b,w", pa10, FLAG_STRICT},
863 { "comb", 0x80000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */
864 /* This entry is for the disassembler only. It will never be used by
865 assembler. */
866 { "comb", 0x88000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */
867 { "addb", 0xa0000000, 0xf4000000, "?Wnx,b,w", pa20w, FLAG_STRICT},
868 { "addb", 0xa0000000, 0xfc000000, "?@nx,b,w", pa10, 0}, /* addb{tf} */
869 /* This entry is for the disassembler only. It will never be used by
870 assembler. */
871 { "addb", 0xa8000000, 0xfc000000, "?@nx,b,w", pa10, 0},
872 { "addib", 0xa4000000, 0xf4000000, "?Wn5,b,w", pa20w, FLAG_STRICT},
873 { "addib", 0xa4000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/
874 /* This entry is for the disassembler only. It will never be used by
875 assembler. */
876 { "addib", 0xac000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/
877 { "nop", 0x08000240, 0xffffffff, "", pa10, 0}, /* or 0,0,0 */
878 { "copy", 0x08000240, 0xffe0ffe0, "x,t", pa10, 0}, /* or r,0,t */
879 { "mtsar", 0x01601840, 0xffe0ffff, "x", pa10, 0}, /* mtctl r,cr11 */
880
881 /* Loads and Stores for integer registers. */
882
883 { "ldd", 0x0c0000c0, 0xfc00d3c0, "cxccx(b),t", pa20, FLAG_STRICT},
884 { "ldd", 0x0c0000c0, 0xfc0013c0, "cxccx(s,b),t", pa20, FLAG_STRICT},
885 { "ldd", 0x0c0010e0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
886 { "ldd", 0x0c0010e0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},
887 { "ldd", 0x0c0010c0, 0xfc00d3c0, "cmcc5(b),t", pa20, FLAG_STRICT},
888 { "ldd", 0x0c0010c0, 0xfc0013c0, "cmcc5(s,b),t", pa20, FLAG_STRICT},
889 { "ldd", 0x50000000, 0xfc000002, "cq&(b),x", pa20w, FLAG_STRICT},
890 { "ldd", 0x50000000, 0xfc00c002, "cq#(b),x", pa20, FLAG_STRICT},
891 { "ldd", 0x50000000, 0xfc000002, "cq#(s,b),x", pa20, FLAG_STRICT},
892 { "ldw", 0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
893 { "ldw", 0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
894 { "ldw", 0x0c000080, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
895 { "ldw", 0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
896 { "ldw", 0x0c0010a0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
897 { "ldw", 0x0c0010a0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},
898 { "ldw", 0x0c001080, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
899 { "ldw", 0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
900 { "ldw", 0x0c001080, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
901 { "ldw", 0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
902 { "ldw", 0x4c000000, 0xfc000000, "ce<(b),x", pa20w, FLAG_STRICT},
903 { "ldw", 0x5c000004, 0xfc000006, "ce>(b),x", pa20w, FLAG_STRICT},
904 { "ldw", 0x48000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT},
905 { "ldw", 0x5c000004, 0xfc00c006, "ceK(b),x", pa20, FLAG_STRICT},
906 { "ldw", 0x5c000004, 0xfc000006, "ceK(s,b),x", pa20, FLAG_STRICT},
907 { "ldw", 0x4c000000, 0xfc00c000, "ceJ(b),x", pa10, FLAG_STRICT},
908 { "ldw", 0x4c000000, 0xfc000000, "ceJ(s,b),x", pa10, FLAG_STRICT},
909 { "ldw", 0x48000000, 0xfc00c000, "j(b),x", pa10, 0},
910 { "ldw", 0x48000000, 0xfc000000, "j(s,b),x", pa10, 0},
911 { "ldh", 0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
912 { "ldh", 0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
913 { "ldh", 0x0c000040, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
914 { "ldh", 0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
915 { "ldh", 0x0c001060, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
916 { "ldh", 0x0c001060, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},
917 { "ldh", 0x0c001040, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
918 { "ldh", 0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
919 { "ldh", 0x0c001040, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
920 { "ldh", 0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
921 { "ldh", 0x44000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT},
922 { "ldh", 0x44000000, 0xfc00c000, "j(b),x", pa10, 0},
923 { "ldh", 0x44000000, 0xfc000000, "j(s,b),x", pa10, 0},
924 { "ldb", 0x0c000000, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
925 { "ldb", 0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
926 { "ldb", 0x0c000000, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
927 { "ldb", 0x0c000000, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
928 { "ldb", 0x0c001020, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
929 { "ldb", 0x0c001020, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT},
930 { "ldb", 0x0c001000, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
931 { "ldb", 0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
932 { "ldb", 0x0c001000, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
933 { "ldb", 0x0c001000, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
934 { "ldb", 0x40000000, 0xfc000000, "l(b),x", pa20w, FLAG_STRICT},
935 { "ldb", 0x40000000, 0xfc00c000, "j(b),x", pa10, 0},
936 { "ldb", 0x40000000, 0xfc000000, "j(s,b),x", pa10, 0},
937 { "std", 0x0c0012e0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
938 { "std", 0x0c0012e0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},
939 { "std", 0x0c0012c0, 0xfc00d3c0, "cmcCx,V(b)", pa20, FLAG_STRICT},
940 { "std", 0x0c0012c0, 0xfc0013c0, "cmcCx,V(s,b)", pa20, FLAG_STRICT},
941 { "std", 0x70000000, 0xfc000002, "cqx,&(b)", pa20w, FLAG_STRICT},
942 { "std", 0x70000000, 0xfc00c002, "cqx,#(b)", pa20, FLAG_STRICT},
943 { "std", 0x70000000, 0xfc000002, "cqx,#(s,b)", pa20, FLAG_STRICT},
944 { "stw", 0x0c0012a0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
945 { "stw", 0x0c0012a0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},
946 { "stw", 0x0c001280, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
947 { "stw", 0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},
948 { "stw", 0x0c001280, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
949 { "stw", 0x0c001280, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
950 { "stw", 0x6c000000, 0xfc000000, "cex,<(b)", pa20w, FLAG_STRICT},
951 { "stw", 0x7c000004, 0xfc000006, "cex,>(b)", pa20w, FLAG_STRICT},
952 { "stw", 0x68000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT},
953 { "stw", 0x7c000004, 0xfc00c006, "cex,K(b)", pa20, FLAG_STRICT},
954 { "stw", 0x7c000004, 0xfc000006, "cex,K(s,b)", pa20, FLAG_STRICT},
955 { "stw", 0x6c000000, 0xfc00c000, "cex,J(b)", pa10, FLAG_STRICT},
956 { "stw", 0x6c000000, 0xfc000000, "cex,J(s,b)", pa10, FLAG_STRICT},
957 { "stw", 0x68000000, 0xfc00c000, "x,j(b)", pa10, 0},
958 { "stw", 0x68000000, 0xfc000000, "x,j(s,b)", pa10, 0},
959 { "sth", 0x0c001260, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
960 { "sth", 0x0c001260, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},
961 { "sth", 0x0c001240, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
962 { "sth", 0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},
963 { "sth", 0x0c001240, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
964 { "sth", 0x0c001240, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
965 { "sth", 0x64000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT},
966 { "sth", 0x64000000, 0xfc00c000, "x,j(b)", pa10, 0},
967 { "sth", 0x64000000, 0xfc000000, "x,j(s,b)", pa10, 0},
968 { "stb", 0x0c001220, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
969 { "stb", 0x0c001220, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT},
970 { "stb", 0x0c001200, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
971 { "stb", 0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},
972 { "stb", 0x0c001200, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
973 { "stb", 0x0c001200, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
974 { "stb", 0x60000000, 0xfc000000, "x,l(b)", pa20w, FLAG_STRICT},
975 { "stb", 0x60000000, 0xfc00c000, "x,j(b)", pa10, 0},
976 { "stb", 0x60000000, 0xfc000000, "x,j(s,b)", pa10, 0},
977 { "ldwm", 0x4c000000, 0xfc00c000, "j(b),x", pa10, 0},
978 { "ldwm", 0x4c000000, 0xfc000000, "j(s,b),x", pa10, 0},
979 { "stwm", 0x6c000000, 0xfc00c000, "x,j(b)", pa10, 0},
980 { "stwm", 0x6c000000, 0xfc000000, "x,j(s,b)", pa10, 0},
981 { "ldwx", 0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
982 { "ldwx", 0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
983 { "ldwx", 0x0c000080, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
984 { "ldwx", 0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
985 { "ldwx", 0x0c000080, 0xfc00dfc0, "cXx(b),t", pa10, 0},
986 { "ldwx", 0x0c000080, 0xfc001fc0, "cXx(s,b),t", pa10, 0},
987 { "ldhx", 0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
988 { "ldhx", 0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
989 { "ldhx", 0x0c000040, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
990 { "ldhx", 0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
991 { "ldhx", 0x0c000040, 0xfc00dfc0, "cXx(b),t", pa10, 0},
992 { "ldhx", 0x0c000040, 0xfc001fc0, "cXx(s,b),t", pa10, 0},
993 { "ldbx", 0x0c000000, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
994 { "ldbx", 0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
995 { "ldbx", 0x0c000000, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
996 { "ldbx", 0x0c000000, 0xfc0013c0, "cxccx(s,b),t", pa11, FLAG_STRICT},
997 { "ldbx", 0x0c000000, 0xfc00dfc0, "cXx(b),t", pa10, 0},
998 { "ldbx", 0x0c000000, 0xfc001fc0, "cXx(s,b),t", pa10, 0},
999 { "ldwa", 0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
1000 { "ldwa", 0x0c000180, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
1001 { "ldwa", 0x0c0011a0, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
1002 { "ldwa", 0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
1003 { "ldwa", 0x0c001180, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
1004 { "ldcw", 0x0c0001c0, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
1005 { "ldcw", 0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
1006 { "ldcw", 0x0c0001c0, 0xfc00d3c0, "cxcdx(b),t", pa11, FLAG_STRICT},
1007 { "ldcw", 0x0c0001c0, 0xfc0013c0, "cxcdx(s,b),t", pa11, FLAG_STRICT},
1008 { "ldcw", 0x0c0011c0, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
1009 { "ldcw", 0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
1010 { "ldcw", 0x0c0011c0, 0xfc00d3c0, "cmcd5(b),t", pa11, FLAG_STRICT},
1011 { "ldcw", 0x0c0011c0, 0xfc0013c0, "cmcd5(s,b),t", pa11, FLAG_STRICT},
1012 { "stwa", 0x0c0013a0, 0xfc00d3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
1013 { "stwa", 0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
1014 { "stwa", 0x0c001380, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
1015 { "stby", 0x0c001300, 0xfc00dfc0, "cAx,V(b)", pa10, FLAG_STRICT},
1016 { "stby", 0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, FLAG_STRICT},
1017 { "stby", 0x0c001300, 0xfc00d3c0, "cscCx,V(b)", pa11, FLAG_STRICT},
1018 { "stby", 0x0c001300, 0xfc0013c0, "cscCx,V(s,b)", pa11, FLAG_STRICT},
1019 { "ldda", 0x0c000100, 0xfc00d3c0, "cxccx(b),t", pa20, FLAG_STRICT},
1020 { "ldda", 0x0c001120, 0xfc1ff3e0, "cocc@(b),t", pa20, FLAG_STRICT},
1021 { "ldda", 0x0c001100, 0xfc00d3c0, "cmcc5(b),t", pa20, FLAG_STRICT},
1022 { "ldcd", 0x0c000140, 0xfc00d3c0, "cxcdx(b),t", pa20, FLAG_STRICT},
1023 { "ldcd", 0x0c000140, 0xfc0013c0, "cxcdx(s,b),t", pa20, FLAG_STRICT},
1024 { "ldcd", 0x0c001140, 0xfc00d3c0, "cmcd5(b),t", pa20, FLAG_STRICT},
1025 { "ldcd", 0x0c001140, 0xfc0013c0, "cmcd5(s,b),t", pa20, FLAG_STRICT},
1026 { "stda", 0x0c0013e0, 0xfc00f3ff, "cocCx,@(b)", pa20, FLAG_STRICT},
1027 { "stda", 0x0c0013c0, 0xfc00d3c0, "cmcCx,V(b)", pa20, FLAG_STRICT},
1028 { "ldwax", 0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
1029 { "ldwax", 0x0c000180, 0xfc00d3c0, "cxccx(b),t", pa11, FLAG_STRICT},
1030 { "ldwax", 0x0c000180, 0xfc00dfc0, "cXx(b),t", pa10, 0},
1031 { "ldcwx", 0x0c0001c0, 0xfc00dfc0, "cXx(b),t", pa10, FLAG_STRICT},
1032 { "ldcwx", 0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, FLAG_STRICT},
1033 { "ldcwx", 0x0c0001c0, 0xfc00d3c0, "cxcdx(b),t", pa11, FLAG_STRICT},
1034 { "ldcwx", 0x0c0001c0, 0xfc0013c0, "cxcdx(s,b),t", pa11, FLAG_STRICT},
1035 { "ldcwx", 0x0c0001c0, 0xfc00dfc0, "cXx(b),t", pa10, 0},
1036 { "ldcwx", 0x0c0001c0, 0xfc001fc0, "cXx(s,b),t", pa10, 0},
1037 { "ldws", 0x0c001080, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
1038 { "ldws", 0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
1039 { "ldws", 0x0c001080, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
1040 { "ldws", 0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
1041 { "ldws", 0x0c001080, 0xfc00dfc0, "cM5(b),t", pa10, 0},
1042 { "ldws", 0x0c001080, 0xfc001fc0, "cM5(s,b),t", pa10, 0},
1043 { "ldhs", 0x0c001040, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
1044 { "ldhs", 0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
1045 { "ldhs", 0x0c001040, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
1046 { "ldhs", 0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
1047 { "ldhs", 0x0c001040, 0xfc00dfc0, "cM5(b),t", pa10, 0},
1048 { "ldhs", 0x0c001040, 0xfc001fc0, "cM5(s,b),t", pa10, 0},
1049 { "ldbs", 0x0c001000, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
1050 { "ldbs", 0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
1051 { "ldbs", 0x0c001000, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
1052 { "ldbs", 0x0c001000, 0xfc0013c0, "cmcc5(s,b),t", pa11, FLAG_STRICT},
1053 { "ldbs", 0x0c001000, 0xfc00dfc0, "cM5(b),t", pa10, 0},
1054 { "ldbs", 0x0c001000, 0xfc001fc0, "cM5(s,b),t", pa10, 0},
1055 { "ldwas", 0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
1056 { "ldwas", 0x0c001180, 0xfc00d3c0, "cmcc5(b),t", pa11, FLAG_STRICT},
1057 { "ldwas", 0x0c001180, 0xfc00dfc0, "cM5(b),t", pa10, 0},
1058 { "ldcws", 0x0c0011c0, 0xfc00dfc0, "cM5(b),t", pa10, FLAG_STRICT},
1059 { "ldcws", 0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, FLAG_STRICT},
1060 { "ldcws", 0x0c0011c0, 0xfc00d3c0, "cmcd5(b),t", pa11, FLAG_STRICT},
1061 { "ldcws", 0x0c0011c0, 0xfc0013c0, "cmcd5(s,b),t", pa11, FLAG_STRICT},
1062 { "ldcws", 0x0c0011c0, 0xfc00dfc0, "cM5(b),t", pa10, 0},
1063 { "ldcws", 0x0c0011c0, 0xfc001fc0, "cM5(s,b),t", pa10, 0},
1064 { "stws", 0x0c001280, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
1065 { "stws", 0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},
1066 { "stws", 0x0c001280, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
1067 { "stws", 0x0c001280, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
1068 { "stws", 0x0c001280, 0xfc00dfc0, "cMx,V(b)", pa10, 0},
1069 { "stws", 0x0c001280, 0xfc001fc0, "cMx,V(s,b)", pa10, 0},
1070 { "sths", 0x0c001240, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
1071 { "sths", 0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},
1072 { "sths", 0x0c001240, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
1073 { "sths", 0x0c001240, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
1074 { "sths", 0x0c001240, 0xfc00dfc0, "cMx,V(b)", pa10, 0},
1075 { "sths", 0x0c001240, 0xfc001fc0, "cMx,V(s,b)", pa10, 0},
1076 { "stbs", 0x0c001200, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
1077 { "stbs", 0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, FLAG_STRICT},
1078 { "stbs", 0x0c001200, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
1079 { "stbs", 0x0c001200, 0xfc0013c0, "cmcCx,V(s,b)", pa11, FLAG_STRICT},
1080 { "stbs", 0x0c001200, 0xfc00dfc0, "cMx,V(b)", pa10, 0},
1081 { "stbs", 0x0c001200, 0xfc001fc0, "cMx,V(s,b)", pa10, 0},
1082 { "stwas", 0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, FLAG_STRICT},
1083 { "stwas", 0x0c001380, 0xfc00d3c0, "cmcCx,V(b)", pa11, FLAG_STRICT},
1084 { "stwas", 0x0c001380, 0xfc00dfc0, "cMx,V(b)", pa10, 0},
1085 { "stdby", 0x0c001340, 0xfc00d3c0, "cscCx,V(b)", pa20, FLAG_STRICT},
1086 { "stdby", 0x0c001340, 0xfc0013c0, "cscCx,V(s,b)", pa20, FLAG_STRICT},
1087 { "stbys", 0x0c001300, 0xfc00dfc0, "cAx,V(b)", pa10, FLAG_STRICT},
1088 { "stbys", 0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, FLAG_STRICT},
1089 { "stbys", 0x0c001300, 0xfc00d3c0, "cscCx,V(b)", pa11, FLAG_STRICT},
1090 { "stbys", 0x0c001300, 0xfc0013c0, "cscCx,V(s,b)", pa11, FLAG_STRICT},
1091 { "stbys", 0x0c001300, 0xfc00dfc0, "cAx,V(b)", pa10, 0},
1092 { "stbys", 0x0c001300, 0xfc001fc0, "cAx,V(s,b)", pa10, 0},
1093
1094 /* Immediate instructions. */
1095 { "ldo", 0x34000000, 0xfc000000, "l(b),x", pa20w, 0},
1096 { "ldo", 0x34000000, 0xfc00c000, "j(b),x", pa10, 0},
1097 { "ldil", 0x20000000, 0xfc000000, "k,b", pa10, 0},
1098 { "addil", 0x28000000, 0xfc000000, "k,b,Z", pa10, 0},
1099 { "addil", 0x28000000, 0xfc000000, "k,b", pa10, 0},
1100
1101 /* Branching instructions. */
1102 { "b", 0xe8008000, 0xfc00e000, "cpnXL", pa20, FLAG_STRICT},
1103 { "b", 0xe800a000, 0xfc00e000, "clnXL", pa20, FLAG_STRICT},
1104 { "b", 0xe8000000, 0xfc00e000, "clnW,b", pa10, FLAG_STRICT},
1105 { "b", 0xe8002000, 0xfc00e000, "cgnW,b", pa10, FLAG_STRICT},
1106 { "b", 0xe8000000, 0xffe0e000, "nW", pa10, 0}, /* b,l foo,r0 */
1107 { "bl", 0xe8000000, 0xfc00e000, "nW,b", pa10, 0},
1108 { "gate", 0xe8002000, 0xfc00e000, "nW,b", pa10, 0},
1109 { "blr", 0xe8004000, 0xfc00e001, "nx,b", pa10, 0},
1110 { "bv", 0xe800c000, 0xfc00fffd, "nx(b)", pa10, 0},
1111 { "bv", 0xe800c000, 0xfc00fffd, "n(b)", pa10, 0},
1112 { "bve", 0xe800f001, 0xfc1ffffd, "cpn(b)L", pa20, FLAG_STRICT},
1113 { "bve", 0xe800f000, 0xfc1ffffd, "cln(b)L", pa20, FLAG_STRICT},
1114 { "bve", 0xe800d001, 0xfc1ffffd, "cPn(b)", pa20, FLAG_STRICT},
1115 { "bve", 0xe800d000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT},
1116 { "be", 0xe4000000, 0xfc000000, "clnz(S,b),Y", pa10, FLAG_STRICT},
1117 { "be", 0xe4000000, 0xfc000000, "clnz(b),Y", pa10, FLAG_STRICT},
1118 { "be", 0xe0000000, 0xfc000000, "nz(S,b)", pa10, 0},
1119 { "be", 0xe0000000, 0xfc000000, "nz(b)", pa10, 0},
1120 { "ble", 0xe4000000, 0xfc000000, "nz(S,b)", pa10, 0},
1121 { "movb", 0xc8000000, 0xfc000000, "?ynx,b,w", pa10, 0},
1122 { "movib", 0xcc000000, 0xfc000000, "?yn5,b,w", pa10, 0},
1123 { "combt", 0x80000000, 0xfc000000, "?tnx,b,w", pa10, 0},
1124 { "combf", 0x88000000, 0xfc000000, "?tnx,b,w", pa10, 0},
1125 { "comibt", 0x84000000, 0xfc000000, "?tn5,b,w", pa10, 0},
1126 { "comibf", 0x8c000000, 0xfc000000, "?tn5,b,w", pa10, 0},
1127 { "addbt", 0xa0000000, 0xfc000000, "?dnx,b,w", pa10, 0},
1128 { "addbf", 0xa8000000, 0xfc000000, "?dnx,b,w", pa10, 0},
1129 { "addibt", 0xa4000000, 0xfc000000, "?dn5,b,w", pa10, 0},
1130 { "addibf", 0xac000000, 0xfc000000, "?dn5,b,w", pa10, 0},
1131 { "bb", 0xc0004000, 0xffe06000, "?bnx,!,w", pa10, FLAG_STRICT},
1132 { "bb", 0xc0006000, 0xffe06000, "?Bnx,!,w", pa20, FLAG_STRICT},
1133 { "bb", 0xc4004000, 0xfc006000, "?bnx,Q,w", pa10, FLAG_STRICT},
1134 { "bb", 0xc4004000, 0xfc004000, "?Bnx,B,w", pa20, FLAG_STRICT},
1135 { "bvb", 0xc0004000, 0xffe04000, "?bnx,w", pa10, 0},
1136 { "clrbts", 0xe8004005, 0xffffffff, "", pa20, FLAG_STRICT},
1137 { "popbts", 0xe8004005, 0xfffff007, "$", pa20, FLAG_STRICT},
1138 { "pushnom", 0xe8004001, 0xffffffff, "", pa20, FLAG_STRICT},
1139 { "pushbts", 0xe8004001, 0xffe0ffff, "x", pa20, FLAG_STRICT},
1140
1141 /* Computation Instructions. */
1142
1143 { "cmpclr", 0x080008a0, 0xfc000fe0, "?Sx,b,t", pa20, FLAG_STRICT},
1144 { "cmpclr", 0x08000880, 0xfc000fe0, "?sx,b,t", pa10, FLAG_STRICT},
1145 { "comclr", 0x08000880, 0xfc000fe0, "?sx,b,t", pa10, 0},
1146 { "or", 0x08000260, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
1147 { "or", 0x08000240, 0xfc000fe0, "?lx,b,t", pa10, 0},
1148 { "xor", 0x080002a0, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
1149 { "xor", 0x08000280, 0xfc000fe0, "?lx,b,t", pa10, 0},
1150 { "and", 0x08000220, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
1151 { "and", 0x08000200, 0xfc000fe0, "?lx,b,t", pa10, 0},
1152 { "andcm", 0x08000020, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
1153 { "andcm", 0x08000000, 0xfc000fe0, "?lx,b,t", pa10, 0},
1154 { "uxor", 0x080003a0, 0xfc000fe0, "?Ux,b,t", pa20, FLAG_STRICT},
1155 { "uxor", 0x08000380, 0xfc000fe0, "?ux,b,t", pa10, 0},
1156 { "uaddcm", 0x080009a0, 0xfc000fa0, "cT?Ux,b,t", pa20, FLAG_STRICT},
1157 { "uaddcm", 0x08000980, 0xfc000fa0, "cT?ux,b,t", pa10, FLAG_STRICT},
1158 { "uaddcm", 0x08000980, 0xfc000fe0, "?ux,b,t", pa10, 0},
1159 { "uaddcmt", 0x080009c0, 0xfc000fe0, "?ux,b,t", pa10, 0},
1160 { "dcor", 0x08000ba0, 0xfc1f0fa0, "ci?Ub,t", pa20, FLAG_STRICT},
1161 { "dcor", 0x08000b80, 0xfc1f0fa0, "ci?ub,t", pa10, FLAG_STRICT},
1162 { "dcor", 0x08000b80, 0xfc1f0fe0, "?ub,t", pa10, 0},
1163 { "idcor", 0x08000bc0, 0xfc1f0fe0, "?ub,t", pa10, 0},
1164 { "addi", 0xb0000000, 0xfc000000, "ct?ai,b,x", pa10, FLAG_STRICT},
1165 { "addi", 0xb4000000, 0xfc000000, "cv?ai,b,x", pa10, FLAG_STRICT},
1166 { "addi", 0xb4000000, 0xfc000800, "?ai,b,x", pa10, 0},
1167 { "addio", 0xb4000800, 0xfc000800, "?ai,b,x", pa10, 0},
1168 { "addit", 0xb0000000, 0xfc000800, "?ai,b,x", pa10, 0},
1169 { "addito", 0xb0000800, 0xfc000800, "?ai,b,x", pa10, 0},
1170 { "add", 0x08000720, 0xfc0007e0, "cY?Ax,b,t", pa20, FLAG_STRICT},
1171 { "add", 0x08000700, 0xfc0007e0, "cy?ax,b,t", pa10, FLAG_STRICT},
1172 { "add", 0x08000220, 0xfc0003e0, "ca?Ax,b,t", pa20, FLAG_STRICT},
1173 { "add", 0x08000200, 0xfc0003e0, "ca?ax,b,t", pa10, FLAG_STRICT},
1174 { "add", 0x08000600, 0xfc000fe0, "?ax,b,t", pa10, 0},
1175 { "addl", 0x08000a00, 0xfc000fe0, "?ax,b,t", pa10, 0},
1176 { "addo", 0x08000e00, 0xfc000fe0, "?ax,b,t", pa10, 0},
1177 { "addc", 0x08000700, 0xfc000fe0, "?ax,b,t", pa10, 0},
1178 { "addco", 0x08000f00, 0xfc000fe0, "?ax,b,t", pa10, 0},
1179 { "sub", 0x080004e0, 0xfc0007e0, "ct?Sx,b,t", pa20, FLAG_STRICT},
1180 { "sub", 0x080004c0, 0xfc0007e0, "ct?sx,b,t", pa10, FLAG_STRICT},
1181 { "sub", 0x08000520, 0xfc0007e0, "cB?Sx,b,t", pa20, FLAG_STRICT},
1182 { "sub", 0x08000500, 0xfc0007e0, "cb?sx,b,t", pa10, FLAG_STRICT},
1183 { "sub", 0x08000420, 0xfc0007e0, "cv?Sx,b,t", pa20, FLAG_STRICT},
1184 { "sub", 0x08000400, 0xfc0007e0, "cv?sx,b,t", pa10, FLAG_STRICT},
1185 { "sub", 0x08000400, 0xfc000fe0, "?sx,b,t", pa10, 0},
1186 { "subo", 0x08000c00, 0xfc000fe0, "?sx,b,t", pa10, 0},
1187 { "subb", 0x08000500, 0xfc000fe0, "?sx,b,t", pa10, 0},
1188 { "subbo", 0x08000d00, 0xfc000fe0, "?sx,b,t", pa10, 0},
1189 { "subt", 0x080004c0, 0xfc000fe0, "?sx,b,t", pa10, 0},
1190 { "subto", 0x08000cc0, 0xfc000fe0, "?sx,b,t", pa10, 0},
1191 { "ds", 0x08000440, 0xfc000fe0, "?sx,b,t", pa10, 0},
1192 { "subi", 0x94000000, 0xfc000000, "cv?si,b,x", pa10, FLAG_STRICT},
1193 { "subi", 0x94000000, 0xfc000800, "?si,b,x", pa10, 0},
1194 { "subio", 0x94000800, 0xfc000800, "?si,b,x", pa10, 0},
1195 { "cmpiclr", 0x90000800, 0xfc000800, "?Si,b,x", pa20, FLAG_STRICT},
1196 { "cmpiclr", 0x90000000, 0xfc000800, "?si,b,x", pa10, FLAG_STRICT},
1197 { "comiclr", 0x90000000, 0xfc000800, "?si,b,x", pa10, 0},
1198 { "shladd", 0x08000220, 0xfc000320, "ca?Ax,.,b,t", pa20, FLAG_STRICT},
1199 { "shladd", 0x08000200, 0xfc000320, "ca?ax,.,b,t", pa10, FLAG_STRICT},
1200 { "sh1add", 0x08000640, 0xfc000fe0, "?ax,b,t", pa10, 0},
1201 { "sh1addl", 0x08000a40, 0xfc000fe0, "?ax,b,t", pa10, 0},
1202 { "sh1addo", 0x08000e40, 0xfc000fe0, "?ax,b,t", pa10, 0},
1203 { "sh2add", 0x08000680, 0xfc000fe0, "?ax,b,t", pa10, 0},
1204 { "sh2addl", 0x08000a80, 0xfc000fe0, "?ax,b,t", pa10, 0},
1205 { "sh2addo", 0x08000e80, 0xfc000fe0, "?ax,b,t", pa10, 0},
1206 { "sh3add", 0x080006c0, 0xfc000fe0, "?ax,b,t", pa10, 0},
1207 { "sh3addl", 0x08000ac0, 0xfc000fe0, "?ax,b,t", pa10, 0},
1208 { "sh3addo", 0x08000ec0, 0xfc000fe0, "?ax,b,t", pa10, 0},
1209
1210 /* Subword Operation Instructions. */
1211
1212 { "hadd", 0x08000300, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT},
1213 { "havg", 0x080002c0, 0xfc00ffe0, "x,b,t", pa20, FLAG_STRICT},
1214 { "hshl", 0xf8008800, 0xffe0fc20, "x,*,t", pa20, FLAG_STRICT},
1215 { "hshladd", 0x08000700, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT},
1216 { "hshr", 0xf800c800, 0xfc1ff820, "cSb,*,t", pa20, FLAG_STRICT},
1217 { "hshradd", 0x08000500, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT},
1218 { "hsub", 0x08000100, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT},
1219 { "mixh", 0xf8008400, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT},
1220 { "mixw", 0xf8008000, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT},
1221 { "permh", 0xf8000000, 0xfc009020, "c*a,t", pa20, FLAG_STRICT},
1222
1223
1224 /* Extract and Deposit Instructions. */
1225
1226 { "shrpd", 0xd0000200, 0xfc001fe0, "?Xx,b,!,t", pa20, FLAG_STRICT},
1227 { "shrpd", 0xd0000400, 0xfc001400, "?Xx,b,~,t", pa20, FLAG_STRICT},
1228 { "shrpw", 0xd0000000, 0xfc001fe0, "?xx,b,!,t", pa10, FLAG_STRICT},
1229 { "shrpw", 0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10, FLAG_STRICT},
1230 { "vshd", 0xd0000000, 0xfc001fe0, "?xx,b,t", pa10, 0},
1231 { "shd", 0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10, 0},
1232 { "extrd", 0xd0001200, 0xfc001ae0, "cS?Xb,!,%,x", pa20, FLAG_STRICT},
1233 { "extrd", 0xd8000000, 0xfc000000, "cS?Xb,q,|,x", pa20, FLAG_STRICT},
1234 { "extrw", 0xd0001000, 0xfc001be0, "cS?xb,!,T,x", pa10, FLAG_STRICT},
1235 { "extrw", 0xd0001800, 0xfc001800, "cS?xb,P,T,x", pa10, FLAG_STRICT},
1236 { "vextru", 0xd0001000, 0xfc001fe0, "?xb,T,x", pa10, 0},
1237 { "vextrs", 0xd0001400, 0xfc001fe0, "?xb,T,x", pa10, 0},
1238 { "extru", 0xd0001800, 0xfc001c00, "?xb,P,T,x", pa10, 0},
1239 { "extrs", 0xd0001c00, 0xfc001c00, "?xb,P,T,x", pa10, 0},
1240 { "depd", 0xd4000200, 0xfc001ae0, "cz?Xx,!,%,b", pa20, FLAG_STRICT},
1241 { "depd", 0xf0000000, 0xfc000000, "cz?Xx,~,|,b", pa20, FLAG_STRICT},
1242 { "depdi", 0xd4001200, 0xfc001ae0, "cz?X5,!,%,b", pa20, FLAG_STRICT},
1243 { "depdi", 0xf4000000, 0xfc000000, "cz?X5,~,|,b", pa20, FLAG_STRICT},
1244 { "depw", 0xd4000000, 0xfc001be0, "cz?xx,!,T,b", pa10, FLAG_STRICT},
1245 { "depw", 0xd4000800, 0xfc001800, "cz?xx,p,T,b", pa10, FLAG_STRICT},
1246 { "depwi", 0xd4001000, 0xfc001be0, "cz?x5,!,T,b", pa10, FLAG_STRICT},
1247 { "depwi", 0xd4001800, 0xfc001800, "cz?x5,p,T,b", pa10, FLAG_STRICT},
1248 { "zvdep", 0xd4000000, 0xfc001fe0, "?xx,T,b", pa10, 0},
1249 { "vdep", 0xd4000400, 0xfc001fe0, "?xx,T,b", pa10, 0},
1250 { "zdep", 0xd4000800, 0xfc001c00, "?xx,p,T,b", pa10, 0},
1251 { "dep", 0xd4000c00, 0xfc001c00, "?xx,p,T,b", pa10, 0},
1252 { "zvdepi", 0xd4001000, 0xfc001fe0, "?x5,T,b", pa10, 0},
1253 { "vdepi", 0xd4001400, 0xfc001fe0, "?x5,T,b", pa10, 0},
1254 { "zdepi", 0xd4001800, 0xfc001c00, "?x5,p,T,b", pa10, 0},
1255 { "depi", 0xd4001c00, 0xfc001c00, "?x5,p,T,b", pa10, 0},
1256
1257 /* System Control Instructions. */
1258
1259 { "break", 0x00000000, 0xfc001fe0, "r,A", pa10, 0},
1260 { "rfi", 0x00000c00, 0xffffff1f, "cr", pa10, FLAG_STRICT},
1261 { "rfi", 0x00000c00, 0xffffffff, "", pa10, 0},
1262 { "rfir", 0x00000ca0, 0xffffffff, "", pa11, 0},
1263 { "ssm", 0x00000d60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT},
1264 { "ssm", 0x00000d60, 0xffe0ffe0, "R,t", pa10, 0},
1265 { "rsm", 0x00000e60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT},
1266 { "rsm", 0x00000e60, 0xffe0ffe0, "R,t", pa10, 0},
1267 { "mtsm", 0x00001860, 0xffe0ffff, "x", pa10, 0},
1268 { "ldsid", 0x000010a0, 0xfc1fffe0, "(b),t", pa10, 0},
1269 { "ldsid", 0x000010a0, 0xfc1f3fe0, "(s,b),t", pa10, 0},
1270 { "mtsp", 0x00001820, 0xffe01fff, "x,S", pa10, 0},
1271 { "mtctl", 0x00001840, 0xfc00ffff, "x,^", pa10, 0},
1272 { "mtsarcm", 0x016018C0, 0xffe0ffff, "x", pa20, FLAG_STRICT},
1273 { "mfia", 0x000014A0, 0xffffffe0, "t", pa20, FLAG_STRICT},
1274 { "mfsp", 0x000004a0, 0xffff1fe0, "S,t", pa10, 0},
1275 { "mfctl", 0x016048a0, 0xffffffe0, "cW!,t", pa20, FLAG_STRICT},
1276 { "mfctl", 0x000008a0, 0xfc1fffe0, "^,t", pa10, 0},
1277 { "sync", 0x00000400, 0xffffffff, "", pa10, 0},
1278 { "syncdma", 0x00100400, 0xffffffff, "", pa10, 0},
1279 { "probe", 0x04001180, 0xfc00ffa0, "cw(b),x,t", pa10, FLAG_STRICT},
1280 { "probe", 0x04001180, 0xfc003fa0, "cw(s,b),x,t", pa10, FLAG_STRICT},
1281 { "probei", 0x04003180, 0xfc00ffa0, "cw(b),R,t", pa10, FLAG_STRICT},
1282 { "probei", 0x04003180, 0xfc003fa0, "cw(s,b),R,t", pa10, FLAG_STRICT},
1283 { "prober", 0x04001180, 0xfc00ffe0, "(b),x,t", pa10, 0},
1284 { "prober", 0x04001180, 0xfc003fe0, "(s,b),x,t", pa10, 0},
1285 { "proberi", 0x04003180, 0xfc00ffe0, "(b),R,t", pa10, 0},
1286 { "proberi", 0x04003180, 0xfc003fe0, "(s,b),R,t", pa10, 0},
1287 { "probew", 0x040011c0, 0xfc00ffe0, "(b),x,t", pa10, 0},
1288 { "probew", 0x040011c0, 0xfc003fe0, "(s,b),x,t", pa10, 0},
1289 { "probewi", 0x040031c0, 0xfc00ffe0, "(b),R,t", pa10, 0},
1290 { "probewi", 0x040031c0, 0xfc003fe0, "(s,b),R,t", pa10, 0},
1291 { "lpa", 0x04001340, 0xfc00ffc0, "cZx(b),t", pa10, 0},
1292 { "lpa", 0x04001340, 0xfc003fc0, "cZx(s,b),t", pa10, 0},
1293 { "lci", 0x04001300, 0xfc00ffe0, "x(b),t", pa11, 0},
1294 { "lci", 0x04001300, 0xfc003fe0, "x(s,b),t", pa11, 0},
1295 { "pdtlb", 0x04001600, 0xfc00ffdf, "cLcZx(b)", pa20, FLAG_STRICT},
1296 { "pdtlb", 0x04001600, 0xfc003fdf, "cLcZx(s,b)", pa20, FLAG_STRICT},
1297 { "pdtlb", 0x04001600, 0xfc1fffdf, "cLcZ@(b)", pa20, FLAG_STRICT},
1298 { "pdtlb", 0x04001600, 0xfc1f3fdf, "cLcZ@(s,b)", pa20, FLAG_STRICT},
1299 { "pdtlb", 0x04001200, 0xfc00ffdf, "cZx(b)", pa10, 0},
1300 { "pdtlb", 0x04001200, 0xfc003fdf, "cZx(s,b)", pa10, 0},
1301 { "pitlb", 0x04000600, 0xfc001fdf, "cLcZx(S,b)", pa20, FLAG_STRICT},
1302 { "pitlb", 0x04000600, 0xfc1f1fdf, "cLcZ@(S,b)", pa20, FLAG_STRICT},
1303 { "pitlb", 0x04000200, 0xfc001fdf, "cZx(S,b)", pa10, 0},
1304 { "pdtlbe", 0x04001240, 0xfc00ffdf, "cZx(b)", pa10, 0},
1305 { "pdtlbe", 0x04001240, 0xfc003fdf, "cZx(s,b)", pa10, 0},
1306 { "pitlbe", 0x04000240, 0xfc001fdf, "cZx(S,b)", pa10, 0},
1307 { "idtlba", 0x04001040, 0xfc00ffff, "x,(b)", pa10, 0},
1308 { "idtlba", 0x04001040, 0xfc003fff, "x,(s,b)", pa10, 0},
1309 { "iitlba", 0x04000040, 0xfc001fff, "x,(S,b)", pa10, 0},
1310 { "idtlbp", 0x04001000, 0xfc00ffff, "x,(b)", pa10, 0},
1311 { "idtlbp", 0x04001000, 0xfc003fff, "x,(s,b)", pa10, 0},
1312 { "iitlbp", 0x04000000, 0xfc001fff, "x,(S,b)", pa10, 0},
1313 { "pdc", 0x04001380, 0xfc00ffdf, "cZx(b)", pa10, 0},
1314 { "pdc", 0x04001380, 0xfc003fdf, "cZx(s,b)", pa10, 0},
1315 { "fdc", 0x04001280, 0xfc00ffdf, "cZx(b)", pa10, FLAG_STRICT},
1316 { "fdc", 0x04001280, 0xfc003fdf, "cZx(s,b)", pa10, FLAG_STRICT},
1317 { "fdc", 0x04003280, 0xfc00ffff, "5(b)", pa20, FLAG_STRICT},
1318 { "fdc", 0x04003280, 0xfc003fff, "5(s,b)", pa20, FLAG_STRICT},
1319 { "fdc", 0x04001280, 0xfc00ffdf, "cZx(b)", pa10, 0},
1320 { "fdc", 0x04001280, 0xfc003fdf, "cZx(s,b)", pa10, 0},
1321 { "fic", 0x040013c0, 0xfc00dfdf, "cZx(b)", pa20, FLAG_STRICT},
1322 { "fic", 0x04000280, 0xfc001fdf, "cZx(S,b)", pa10, 0},
1323 { "fdce", 0x040012c0, 0xfc00ffdf, "cZx(b)", pa10, 0},
1324 { "fdce", 0x040012c0, 0xfc003fdf, "cZx(s,b)", pa10, 0},
1325 { "fice", 0x040002c0, 0xfc001fdf, "cZx(S,b)", pa10, 0},
1326 { "idtlbt", 0x04001800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT},
1327 { "iitlbt", 0x04000800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT},
1328
1329 /* completely undocumented, but used by ODE, HP-UX and Linux: */
1330 { "mfcpu_pcxu", 0x140008a0, 0xfc9fffe0, "9,t", pa20, 0}, /* PCXU: mfdiag */
1331 { "mtcpu_pcxu", 0x14001840, 0xfc00ffff, "x,9", pa20, 0},
1332
1333 /* These may be specific to certain versions of the PA. Joel claimed
1334 they were 72000 (7200?) specific. However, I'm almost certain the
1335 mtcpu/mfcpu were undocumented, but available in the older 700 machines. */
1336 { "mfcpu_c", 0x14000600, 0xfc00ffff, "9,x", pa10, 0}, /* PCXL: for dr0 and dr8 only */
1337 { "mfcpu_t", 0x14001400, 0xfc9fffe0, "9,t", pa10, 0}, /* PCXL: all dr except dr0 and dr8 */
1338 { "mtcpu_pcxl", 0x14000240, 0xfc00ffff, "x,9", pa11, 0}, /* PCXL: mtcpu for dr0 and dr8 */
1339 { "mtcpu", 0x14001600, 0xfc00ffff, "x,^", pa10, 0},
1340 { "mfcpu", 0x14001A00, 0xfc00ffff, "^,x", pa10, 0},
1341 { "tocen", 0x14403600, 0xffffffff, "", pa10, 0},
1342 { "tocdis", 0x14401620, 0xffffffff, "", pa10, 0},
1343 { "shdwgr", 0x14402600, 0xffffffff, "", pa10, 0},
1344 { "grshdw", 0x14400620, 0xffffffff, "", pa10, 0},
1345
1346 /* instead of showing D only, show all other registers too */
1347 { "diag", 0x14000000, 0xfc000000, "D x,9,t", pa10, 0},
1348
1349 /* gfw and gfr are not in the HP PA 1.1 manual, but they are in either
1350 the Timex FPU or the Mustang ERS (not sure which) manual. */
1351 { "gfw", 0x04001680, 0xfc00ffdf, "cZx(b)", pa11, 0},
1352 { "gfw", 0x04001680, 0xfc003fdf, "cZx(s,b)", pa11, 0},
1353 { "gfr", 0x04001a80, 0xfc00ffdf, "cZx(b)", pa11, 0},
1354 { "gfr", 0x04001a80, 0xfc003fdf, "cZx(s,b)", pa11, 0},
1355
1356 /* Floating Point Coprocessor Instructions. */
1357
1358 { "fldw", 0x24000000, 0xfc00df80, "cXx(b),fT", pa10, FLAG_STRICT},
1359 { "fldw", 0x24000000, 0xfc001f80, "cXx(s,b),fT", pa10, FLAG_STRICT},
1360 { "fldw", 0x24000000, 0xfc00d380, "cxccx(b),fT", pa11, FLAG_STRICT},
1361 { "fldw", 0x24000000, 0xfc001380, "cxccx(s,b),fT", pa11, FLAG_STRICT},
1362 { "fldw", 0x24001020, 0xfc1ff3a0, "cocc@(b),fT", pa20, FLAG_STRICT},
1363 { "fldw", 0x24001020, 0xfc1f33a0, "cocc@(s,b),fT", pa20, FLAG_STRICT},
1364 { "fldw", 0x24001000, 0xfc00df80, "cM5(b),fT", pa10, FLAG_STRICT},
1365 { "fldw", 0x24001000, 0xfc001f80, "cM5(s,b),fT", pa10, FLAG_STRICT},
1366 { "fldw", 0x24001000, 0xfc00d380, "cmcc5(b),fT", pa11, FLAG_STRICT},
1367 { "fldw", 0x24001000, 0xfc001380, "cmcc5(s,b),fT", pa11, FLAG_STRICT},
1368 { "fldw", 0x5c000000, 0xfc000004, "y(b),fe", pa20w, FLAG_STRICT},
1369 { "fldw", 0x58000000, 0xfc000000, "cJy(b),fe", pa20w, FLAG_STRICT},
1370 { "fldw", 0x5c000000, 0xfc00c004, "d(b),fe", pa20, FLAG_STRICT},
1371 { "fldw", 0x5c000000, 0xfc000004, "d(s,b),fe", pa20, FLAG_STRICT},
1372 { "fldw", 0x58000000, 0xfc00c000, "cJd(b),fe", pa20, FLAG_STRICT},
1373 { "fldw", 0x58000000, 0xfc000000, "cJd(s,b),fe", pa20, FLAG_STRICT},
1374 { "fldd", 0x2c000000, 0xfc00dfc0, "cXx(b),ft", pa10, FLAG_STRICT},
1375 { "fldd", 0x2c000000, 0xfc001fc0, "cXx(s,b),ft", pa10, FLAG_STRICT},
1376 { "fldd", 0x2c000000, 0xfc00d3c0, "cxccx(b),ft", pa11, FLAG_STRICT},
1377 { "fldd", 0x2c000000, 0xfc0013c0, "cxccx(s,b),ft", pa11, FLAG_STRICT},
1378 { "fldd", 0x2c001020, 0xfc1ff3e0, "cocc@(b),ft", pa20, FLAG_STRICT},
1379 { "fldd", 0x2c001020, 0xfc1f33e0, "cocc@(s,b),ft", pa20, FLAG_STRICT},
1380 { "fldd", 0x2c001000, 0xfc00dfc0, "cM5(b),ft", pa10, FLAG_STRICT},
1381 { "fldd", 0x2c001000, 0xfc001fc0, "cM5(s,b),ft", pa10, FLAG_STRICT},
1382 { "fldd", 0x2c001000, 0xfc00d3c0, "cmcc5(b),ft", pa11, FLAG_STRICT},
1383 { "fldd", 0x2c001000, 0xfc0013c0, "cmcc5(s,b),ft", pa11, FLAG_STRICT},
1384 { "fldd", 0x50000002, 0xfc000002, "cq&(b),fx", pa20w, FLAG_STRICT},
1385 { "fldd", 0x50000002, 0xfc00c002, "cq#(b),fx", pa20, FLAG_STRICT},
1386 { "fldd", 0x50000002, 0xfc000002, "cq#(s,b),fx", pa20, FLAG_STRICT},
1387 { "fstw", 0x24000200, 0xfc00df80, "cXfT,x(b)", pa10, FLAG_STRICT},
1388 { "fstw", 0x24000200, 0xfc001f80, "cXfT,x(s,b)", pa10, FLAG_STRICT},
1389 { "fstw", 0x24000200, 0xfc00d380, "cxcCfT,x(b)", pa11, FLAG_STRICT},
1390 { "fstw", 0x24000200, 0xfc001380, "cxcCfT,x(s,b)", pa11, FLAG_STRICT},
1391 { "fstw", 0x24001220, 0xfc1ff3a0, "cocCfT,@(b)", pa20, FLAG_STRICT},
1392 { "fstw", 0x24001220, 0xfc1f33a0, "cocCfT,@(s,b)", pa20, FLAG_STRICT},
1393 { "fstw", 0x24001200, 0xfc00df80, "cMfT,5(b)", pa10, FLAG_STRICT},
1394 { "fstw", 0x24001200, 0xfc001f80, "cMfT,5(s,b)", pa10, FLAG_STRICT},
1395 { "fstw", 0x24001200, 0xfc00df80, "cMfT,5(b)", pa10, FLAG_STRICT},
1396 { "fstw", 0x24001200, 0xfc001f80, "cMfT,5(s,b)", pa10, FLAG_STRICT},
1397 { "fstw", 0x7c000000, 0xfc000004, "fE,y(b)", pa20w, FLAG_STRICT},
1398 { "fstw", 0x78000000, 0xfc000000, "cJfE,y(b)", pa20w, FLAG_STRICT},
1399 { "fstw", 0x7c000000, 0xfc00c004, "fE,d(b)", pa20, FLAG_STRICT},
1400 { "fstw", 0x7c000000, 0xfc000004, "fE,d(s,b)", pa20, FLAG_STRICT},
1401 { "fstw", 0x78000000, 0xfc00c000, "cJfE,d(b)", pa20, FLAG_STRICT},
1402 { "fstw", 0x78000000, 0xfc000000, "cJfE,d(s,b)", pa20, FLAG_STRICT},
1403 { "fstd", 0x2c000200, 0xfc00dfc0, "cXft,x(b)", pa10, FLAG_STRICT},
1404 { "fstd", 0x2c000200, 0xfc001fc0, "cXft,x(s,b)", pa10, FLAG_STRICT},
1405 { "fstd", 0x2c000200, 0xfc00d3c0, "cxcCft,x(b)", pa11, FLAG_STRICT},
1406 { "fstd", 0x2c000200, 0xfc0013c0, "cxcCft,x(s,b)", pa11, FLAG_STRICT},
1407 { "fstd", 0x2c001220, 0xfc1ff3e0, "cocCft,@(b)", pa20, FLAG_STRICT},
1408 { "fstd", 0x2c001220, 0xfc1f33e0, "cocCft,@(s,b)", pa20, FLAG_STRICT},
1409 { "fstd", 0x2c001200, 0xfc00dfc0, "cMft,5(b)", pa10, FLAG_STRICT},
1410 { "fstd", 0x2c001200, 0xfc001fc0, "cMft,5(s,b)", pa10, FLAG_STRICT},
1411 { "fstd", 0x2c001200, 0xfc00d3c0, "cmcCft,5(b)", pa11, FLAG_STRICT},
1412 { "fstd", 0x2c001200, 0xfc0013c0, "cmcCft,5(s,b)", pa11, FLAG_STRICT},
1413 { "fstd", 0x70000002, 0xfc000002, "cqfx,&(b)", pa20w, FLAG_STRICT},
1414 { "fstd", 0x70000002, 0xfc00c002, "cqfx,#(b)", pa20, FLAG_STRICT},
1415 { "fstd", 0x70000002, 0xfc000002, "cqfx,#(s,b)", pa20, FLAG_STRICT},
1416 { "fldwx", 0x24000000, 0xfc00df80, "cXx(b),fT", pa10, FLAG_STRICT},
1417 { "fldwx", 0x24000000, 0xfc001f80, "cXx(s,b),fT", pa10, FLAG_STRICT},
1418 { "fldwx", 0x24000000, 0xfc00d380, "cxccx(b),fT", pa11, FLAG_STRICT},
1419 { "fldwx", 0x24000000, 0xfc001380, "cxccx(s,b),fT", pa11, FLAG_STRICT},
1420 { "fldwx", 0x24000000, 0xfc00df80, "cXx(b),fT", pa10, 0},
1421 { "fldwx", 0x24000000, 0xfc001f80, "cXx(s,b),fT", pa10, 0},
1422 { "flddx", 0x2c000000, 0xfc00dfc0, "cXx(b),ft", pa10, FLAG_STRICT},
1423 { "flddx", 0x2c000000, 0xfc001fc0, "cXx(s,b),ft", pa10, FLAG_STRICT},
1424 { "flddx", 0x2c000000, 0xfc00d3c0, "cxccx(b),ft", pa11, FLAG_STRICT},
1425 { "flddx", 0x2c000000, 0xfc0013c0, "cxccx(s,b),ft", pa11, FLAG_STRICT},
1426 { "flddx", 0x2c000000, 0xfc00dfc0, "cXx(b),ft", pa10, 0},
1427 { "flddx", 0x2c000000, 0xfc001fc0, "cXx(s,b),ft", pa10, 0},
1428 { "fstwx", 0x24000200, 0xfc00df80, "cxfT,x(b)", pa10, FLAG_STRICT},
1429 { "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10, FLAG_STRICT},
1430 { "fstwx", 0x24000200, 0xfc00d380, "cxcCfT,x(b)", pa11, FLAG_STRICT},
1431 { "fstwx", 0x24000200, 0xfc001380, "cxcCfT,x(s,b)", pa11, FLAG_STRICT},
1432 { "fstwx", 0x24000200, 0xfc00df80, "cxfT,x(b)", pa10, 0},
1433 { "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10, 0},
1434 { "fstdx", 0x2c000200, 0xfc00dfc0, "cxft,x(b)", pa10, FLAG_STRICT},
1435 { "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, FLAG_STRICT},
1436 { "fstdx", 0x2c000200, 0xfc00d3c0, "cxcCft,x(b)", pa11, FLAG_STRICT},
1437 { "fstdx", 0x2c000200, 0xfc0013c0, "cxcCft,x(s,b)", pa11, FLAG_STRICT},
1438 { "fstdx", 0x2c000200, 0xfc00dfc0, "cxft,x(b)", pa10, 0},
1439 { "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0},
1440 { "fstqx", 0x3c000200, 0xfc00dfc0, "cxft,x(b)", pa10, 0},
1441 { "fstqx", 0x3c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0},
1442 { "fldws", 0x24001000, 0xfc00df80, "cm5(b),fT", pa10, FLAG_STRICT},
1443 { "fldws", 0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10, FLAG_STRICT},
1444 { "fldws", 0x24001000, 0xfc00d380, "cmcc5(b),fT", pa11, FLAG_STRICT},
1445 { "fldws", 0x24001000, 0xfc001380, "cmcc5(s,b),fT", pa11, FLAG_STRICT},
1446 { "fldws", 0x24001000, 0xfc00df80, "cm5(b),fT", pa10, 0},
1447 { "fldws", 0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10, 0},
1448 { "fldds", 0x2c001000, 0xfc00dfc0, "cm5(b),ft", pa10, FLAG_STRICT},
1449 { "fldds", 0x2c001000, 0xfc001fc0, "cm5(s,b),ft", pa10, FLAG_STRICT},
1450 { "fldds", 0x2c001000, 0xfc00d3c0, "cmcc5(b),ft", pa11, FLAG_STRICT},
1451 { "fldds", 0x2c001000, 0xfc0013c0, "cmcc5(s,b),ft", pa11, FLAG_STRICT},
1452 { "fldds", 0x2c001000, 0xfc00dfc0, "cm5(b),ft", pa10, 0},
1453 { "fldds", 0x2c001000, 0xfc001fc0, "cm5(s,b),ft", pa10, 0},
1454 { "fstws", 0x24001200, 0xfc00df80, "cmfT,5(b)", pa10, FLAG_STRICT},
1455 { "fstws", 0x24001200, 0xfc001f80, "cmfT,5(s,b)", pa10, FLAG_STRICT},
1456 { "fstws", 0x24001200, 0xfc00d380, "cmcCfT,5(b)", pa11, FLAG_STRICT},
1457 { "fstws", 0x24001200, 0xfc001380, "cmcCfT,5(s,b)", pa11, FLAG_STRICT},
1458 { "fstws", 0x24001200, 0xfc00df80, "cmfT,5(b)", pa10, 0},
1459 { "fstws", 0x24001200, 0xfc001f80, "cmfT,5(s,b)", pa10, 0},
1460 { "fstds", 0x2c001200, 0xfc00dfc0, "cmft,5(b)", pa10, FLAG_STRICT},
1461 { "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, FLAG_STRICT},
1462 { "fstds", 0x2c001200, 0xfc00d3c0, "cmcCft,5(b)", pa11, FLAG_STRICT},
1463 { "fstds", 0x2c001200, 0xfc0013c0, "cmcCft,5(s,b)", pa11, FLAG_STRICT},
1464 { "fstds", 0x2c001200, 0xfc00dfc0, "cmft,5(b)", pa10, 0},
1465 { "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0},
1466 { "fstqs", 0x3c001200, 0xfc00dfc0, "cmft,5(b)", pa10, 0},
1467 { "fstqs", 0x3c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0},
1468 { "fadd", 0x30000600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
1469 { "fadd", 0x38000600, 0xfc00e720, "IfA,fB,fT", pa10, 0},
1470 { "fsub", 0x30002600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
1471 { "fsub", 0x38002600, 0xfc00e720, "IfA,fB,fT", pa10, 0},
1472 { "fmpy", 0x30004600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
1473 { "fmpy", 0x38004600, 0xfc00e720, "IfA,fB,fT", pa10, 0},
1474 { "fdiv", 0x30006600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
1475 { "fdiv", 0x38006600, 0xfc00e720, "IfA,fB,fT", pa10, 0},
1476 { "fsqrt", 0x30008000, 0xfc1fe7e0, "Ffa,fT", pa10, 0},
1477 { "fsqrt", 0x38008000, 0xfc1fe720, "FfA,fT", pa10, 0},
1478 { "fabs", 0x30006000, 0xfc1fe7e0, "Ffa,fT", pa10, 0},
1479 { "fabs", 0x38006000, 0xfc1fe720, "FfA,fT", pa10, 0},
1480 { "frem", 0x30008600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
1481 { "frem", 0x38008600, 0xfc00e720, "FfA,fB,fT", pa10, 0},
1482 { "frnd", 0x3000a000, 0xfc1fe7e0, "Ffa,fT", pa10, 0},
1483 { "frnd", 0x3800a000, 0xfc1fe720, "FfA,fT", pa10, 0},
1484 { "fcpy", 0x30004000, 0xfc1fe7e0, "Ffa,fT", pa10, 0},
1485 { "fcpy", 0x38004000, 0xfc1fe720, "FfA,fT", pa10, 0},
1486 { "fcnvff", 0x30000200, 0xfc1f87e0, "FGfa,fT", pa10, 0},
1487 { "fcnvff", 0x38000200, 0xfc1f8720, "FGfA,fT", pa10, 0},
1488 { "fcnvxf", 0x30008200, 0xfc1f87e0, "FGfa,fT", pa10, 0},
1489 { "fcnvxf", 0x38008200, 0xfc1f8720, "FGfA,fT", pa10, 0},
1490 { "fcnvfx", 0x30010200, 0xfc1f87e0, "FGfa,fT", pa10, 0},
1491 { "fcnvfx", 0x38010200, 0xfc1f8720, "FGfA,fT", pa10, 0},
1492 { "fcnvfxt", 0x30018200, 0xfc1f87e0, "FGfa,fT", pa10, 0},
1493 { "fcnvfxt", 0x38018200, 0xfc1f8720, "FGfA,fT", pa10, 0},
1494 { "fmpyfadd", 0xb8000000, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT},
1495 { "fmpynfadd", 0xb8000020, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT},
1496 { "fneg", 0x3000c000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT},
1497 { "fneg", 0x3800c000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT},
1498 { "fnegabs", 0x3000e000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT},
1499 { "fnegabs", 0x3800e000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT},
1500 { "fcnv", 0x30000200, 0xfc1c0720, "{_fa,fT", pa20, FLAG_STRICT},
1501 { "fcnv", 0x38000200, 0xfc1c0720, "FGfA,fT", pa20, FLAG_STRICT},
1502 { "fcmp", 0x30000400, 0xfc00e7e0, "F?ffa,fb", pa10, FLAG_STRICT},
1503 { "fcmp", 0x38000400, 0xfc00e720, "I?ffA,fB", pa10, FLAG_STRICT},
1504 { "fcmp", 0x30000400, 0xfc0007e0, "F?ffa,fb,h", pa20, FLAG_STRICT},
1505 { "fcmp", 0x38000400, 0xfc000720, "I?ffA,fB,h", pa20, FLAG_STRICT},
1506 { "fcmp", 0x30000400, 0xfc00e7e0, "F?ffa,fb", pa10, 0},
1507 { "fcmp", 0x38000400, 0xfc00e720, "I?ffA,fB", pa10, 0},
1508 { "xmpyu", 0x38004700, 0xfc00e720, "fX,fB,fT", pa11, 0},
1509 { "fmpyadd", 0x18000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11, 0},
1510 { "fmpysub", 0x98000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11, 0},
1511 { "ftest", 0x30002420, 0xffffffff, "", pa10, FLAG_STRICT},
1512 { "ftest", 0x30002420, 0xffffffe0, ",=", pa20, FLAG_STRICT},
1513 { "ftest", 0x30000420, 0xffff1fff, "m", pa20, FLAG_STRICT},
1514 { "fid", 0x30000000, 0xffffffff, "", pa11, 0},
1515
1516 /* Performance Monitor Instructions. */
1517
1518 { "pmdis", 0x30000280, 0xffffffdf, "N", pa20, FLAG_STRICT},
1519 { "pmenb", 0x30000680, 0xffffffff, "", pa20, FLAG_STRICT},
1520
1521 /* Assist Instructions. */
1522
1523 { "spop0", 0x10000000, 0xfc000600, "v,ON", pa10, 0},
1524 { "spop1", 0x10000200, 0xfc000600, "v,oNt", pa10, 0},
1525 { "spop2", 0x10000400, 0xfc000600, "v,1Nb", pa10, 0},
1526 { "spop3", 0x10000600, 0xfc000600, "v,0Nx,b", pa10, 0},
1527 { "copr", 0x30000000, 0xfc000000, "u,2N", pa10, 0},
1528 { "cldw", 0x24000000, 0xfc00de00, "ucXx(b),t", pa10, FLAG_STRICT},
1529 { "cldw", 0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT},
1530 { "cldw", 0x24000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT},
1531 { "cldw", 0x24000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT},
1532 { "cldw", 0x24001000, 0xfc00d200, "ucocc@(b),t", pa20, FLAG_STRICT},
1533 { "cldw", 0x24001000, 0xfc001200, "ucocc@(s,b),t", pa20, FLAG_STRICT},
1534 { "cldw", 0x24001000, 0xfc00de00, "ucM5(b),t", pa10, FLAG_STRICT},
1535 { "cldw", 0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT},
1536 { "cldw", 0x24001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT},
1537 { "cldw", 0x24001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT},
1538 { "cldd", 0x2c000000, 0xfc00de00, "ucXx(b),t", pa10, FLAG_STRICT},
1539 { "cldd", 0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT},
1540 { "cldd", 0x2c000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT},
1541 { "cldd", 0x2c000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT},
1542 { "cldd", 0x2c001000, 0xfc00d200, "ucocc@(b),t", pa20, FLAG_STRICT},
1543 { "cldd", 0x2c001000, 0xfc001200, "ucocc@(s,b),t", pa20, FLAG_STRICT},
1544 { "cldd", 0x2c001000, 0xfc00de00, "ucM5(b),t", pa10, FLAG_STRICT},
1545 { "cldd", 0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT},
1546 { "cldd", 0x2c001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT},
1547 { "cldd", 0x2c001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT},
1548 { "cstw", 0x24000200, 0xfc00de00, "ucXt,x(b)", pa10, FLAG_STRICT},
1549 { "cstw", 0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT},
1550 { "cstw", 0x24000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT},
1551 { "cstw", 0x24000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT},
1552 { "cstw", 0x24001200, 0xfc00d200, "ucocCt,@(b)", pa20, FLAG_STRICT},
1553 { "cstw", 0x24001200, 0xfc001200, "ucocCt,@(s,b)", pa20, FLAG_STRICT},
1554 { "cstw", 0x24001200, 0xfc00de00, "ucMt,5(b)", pa10, FLAG_STRICT},
1555 { "cstw", 0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT},
1556 { "cstw", 0x24001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT},
1557 { "cstw", 0x24001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT},
1558 { "cstd", 0x2c000200, 0xfc00de00, "ucXt,x(b)", pa10, FLAG_STRICT},
1559 { "cstd", 0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT},
1560 { "cstd", 0x2c000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT},
1561 { "cstd", 0x2c000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT},
1562 { "cstd", 0x2c001200, 0xfc00d200, "ucocCt,@(b)", pa20, FLAG_STRICT},
1563 { "cstd", 0x2c001200, 0xfc001200, "ucocCt,@(s,b)", pa20, FLAG_STRICT},
1564 { "cstd", 0x2c001200, 0xfc00de00, "ucMt,5(b)", pa10, FLAG_STRICT},
1565 { "cstd", 0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT},
1566 { "cstd", 0x2c001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT},
1567 { "cstd", 0x2c001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT},
1568 { "cldwx", 0x24000000, 0xfc00de00, "ucXx(b),t", pa10, FLAG_STRICT},
1569 { "cldwx", 0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT},
1570 { "cldwx", 0x24000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT},
1571 { "cldwx", 0x24000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT},
1572 { "cldwx", 0x24000000, 0xfc00de00, "ucXx(b),t", pa10, 0},
1573 { "cldwx", 0x24000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0},
1574 { "clddx", 0x2c000000, 0xfc00de00, "ucXx(b),t", pa10, FLAG_STRICT},
1575 { "clddx", 0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, FLAG_STRICT},
1576 { "clddx", 0x2c000000, 0xfc00d200, "ucxccx(b),t", pa11, FLAG_STRICT},
1577 { "clddx", 0x2c000000, 0xfc001200, "ucxccx(s,b),t", pa11, FLAG_STRICT},
1578 { "clddx", 0x2c000000, 0xfc00de00, "ucXx(b),t", pa10, 0},
1579 { "clddx", 0x2c000000, 0xfc001e00, "ucXx(s,b),t", pa10, 0},
1580 { "cstwx", 0x24000200, 0xfc00de00, "ucXt,x(b)", pa10, FLAG_STRICT},
1581 { "cstwx", 0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT},
1582 { "cstwx", 0x24000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT},
1583 { "cstwx", 0x24000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT},
1584 { "cstwx", 0x24000200, 0xfc00de00, "ucXt,x(b)", pa10, 0},
1585 { "cstwx", 0x24000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0},
1586 { "cstdx", 0x2c000200, 0xfc00de00, "ucXt,x(b)", pa10, FLAG_STRICT},
1587 { "cstdx", 0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, FLAG_STRICT},
1588 { "cstdx", 0x2c000200, 0xfc00d200, "ucxcCt,x(b)", pa11, FLAG_STRICT},
1589 { "cstdx", 0x2c000200, 0xfc001200, "ucxcCt,x(s,b)", pa11, FLAG_STRICT},
1590 { "cstdx", 0x2c000200, 0xfc00de00, "ucXt,x(b)", pa10, 0},
1591 { "cstdx", 0x2c000200, 0xfc001e00, "ucXt,x(s,b)", pa10, 0},
1592 { "cldws", 0x24001000, 0xfc00de00, "ucM5(b),t", pa10, FLAG_STRICT},
1593 { "cldws", 0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT},
1594 { "cldws", 0x24001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT},
1595 { "cldws", 0x24001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT},
1596 { "cldws", 0x24001000, 0xfc00de00, "ucM5(b),t", pa10, 0},
1597 { "cldws", 0x24001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0},
1598 { "cldds", 0x2c001000, 0xfc00de00, "ucM5(b),t", pa10, FLAG_STRICT},
1599 { "cldds", 0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, FLAG_STRICT},
1600 { "cldds", 0x2c001000, 0xfc00d200, "ucmcc5(b),t", pa11, FLAG_STRICT},
1601 { "cldds", 0x2c001000, 0xfc001200, "ucmcc5(s,b),t", pa11, FLAG_STRICT},
1602 { "cldds", 0x2c001000, 0xfc00de00, "ucM5(b),t", pa10, 0},
1603 { "cldds", 0x2c001000, 0xfc001e00, "ucM5(s,b),t", pa10, 0},
1604 { "cstws", 0x24001200, 0xfc00de00, "ucMt,5(b)", pa10, FLAG_STRICT},
1605 { "cstws", 0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT},
1606 { "cstws", 0x24001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT},
1607 { "cstws", 0x24001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT},
1608 { "cstws", 0x24001200, 0xfc00de00, "ucMt,5(b)", pa10, 0},
1609 { "cstws", 0x24001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0},
1610 { "cstds", 0x2c001200, 0xfc00de00, "ucMt,5(b)", pa10, FLAG_STRICT},
1611 { "cstds", 0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, FLAG_STRICT},
1612 { "cstds", 0x2c001200, 0xfc00d200, "ucmcCt,5(b)", pa11, FLAG_STRICT},
1613 { "cstds", 0x2c001200, 0xfc001200, "ucmcCt,5(s,b)", pa11, FLAG_STRICT},
1614 { "cstds", 0x2c001200, 0xfc00de00, "ucMt,5(b)", pa10, 0},
1615 { "cstds", 0x2c001200, 0xfc001e00, "ucMt,5(s,b)", pa10, 0},
1616
1617 /* More pseudo instructions which must follow the main table. */
1618 { "call", 0xe800f000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT},
1619 { "call", 0xe800a000, 0xffe0e000, "nW", pa10, FLAG_STRICT},
1620 { "ret", 0xe840d000, 0xfffffffd, "n", pa20, FLAG_STRICT},
1621
1622 /* Opcodes assigned to QEMU, used by SeaBIOS firmware and Linux kernel */
1623 { "HALT QEMU", 0xfffdead0, 0xfffffffd, "n", pa10, FLAG_STRICT},
1624 { "RESET QEMU", 0xfffdead1, 0xfffffffd, "n", pa10, FLAG_STRICT},
1625 { "RESTORE SHR",0xfffdead2, 0xfffffffd, "n", pa10, FLAG_STRICT},
1626 };
1627
1628 #define NUMOPCODES ((sizeof pa_opcodes)/(sizeof pa_opcodes[0]))
1629
1630 /* SKV 12/18/92. Added some denotations for various operands. */
1631
1632 #define PA_IMM11_AT_31 'i'
1633 #define PA_IMM14_AT_31 'j'
1634 #define PA_IMM21_AT_31 'k'
1635 #define PA_DISP12 'w'
1636 #define PA_DISP17 'W'
1637
1638 #define N_HPPA_OPERAND_FORMATS 5
1639
1640 /* Integer register names, indexed by the numbers which appear in the
1641 opcodes. */
1642 static const char *const reg_names[] =
1643 {
1644 "flags", "r1", "rp", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
1645 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19",
1646 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "dp", "ret0", "ret1",
1647 "sp", "r31"
1648 };
1649
1650 /* Floating point register names, indexed by the numbers which appear in the
1651 opcodes. */
1652 static const char *const fp_reg_names[] =
1653 {
1654 "fpsr", "fpe2", "fpe4", "fpe6",
1655 "fr4", "fr5", "fr6", "fr7", "fr8",
1656 "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
1657 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
1658 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31"
1659 };
1660
1661 typedef unsigned int CORE_ADDR;
1662
1663 /* Get at various relevant fields of an instruction word. */
1664
1665 #define MASK_5 0x1f
1666 #define MASK_10 0x3ff
1667 #define MASK_11 0x7ff
1668 #define MASK_14 0x3fff
1669 #define MASK_16 0xffff
1670 #define MASK_21 0x1fffff
1671
1672 /* These macros get bit fields using HP's numbering (MSB = 0). */
1673
1674 #define GET_FIELD(X, FROM, TO) \
1675 ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
1676
1677 #define GET_BIT(X, WHICH) \
1678 GET_FIELD (X, WHICH, WHICH)
1679
1680 /* Some of these have been converted to 2-d arrays because they
1681 consume less storage this way. If the maintenance becomes a
1682 problem, convert them back to const 1-d pointer arrays. */
1683 static const char *const control_reg[] =
1684 {
1685 "rctr", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1686 "pidr1", "pidr2", "ccr", "sar", "pidr3", "pidr4",
1687 "iva", "eiem", "itmr", "pcsq", "pcoq", "iir", "isr",
1688 "ior", "ipsw", "eirr", "tr0", "tr1", "tr2", "tr3",
1689 "tr4", "tr5", "tr6", "tr7"
1690 };
1691
1692 static const char *const compare_cond_names[] =
1693 {
1694 "", ",=", ",<", ",<=", ",<<", ",<<=", ",sv", ",od",
1695 ",tr", ",<>", ",>=", ",>", ",>>=", ",>>", ",nsv", ",ev"
1696 };
1697 static const char *const compare_cond_64_names[] =
1698 {
1699 "", ",*=", ",*<", ",*<=", ",*<<", ",*<<=", ",*sv", ",*od",
1700 ",*tr", ",*<>", ",*>=", ",*>", ",*>>=", ",*>>", ",*nsv", ",*ev"
1701 };
1702 static const char *const cmpib_cond_64_names[] =
1703 {
1704 ",*<<", ",*=", ",*<", ",*<=", ",*>>=", ",*<>", ",*>=", ",*>"
1705 };
1706 static const char *const add_cond_names[] =
1707 {
1708 "", ",=", ",<", ",<=", ",nuv", ",znv", ",sv", ",od",
1709 ",tr", ",<>", ",>=", ",>", ",uv", ",vnz", ",nsv", ",ev"
1710 };
1711 static const char *const add_cond_64_names[] =
1712 {
1713 "", ",*=", ",*<", ",*<=", ",*nuv", ",*znv", ",*sv", ",*od",
1714 ",*tr", ",*<>", ",*>=", ",*>", ",*uv", ",*vnz", ",*nsv", ",*ev"
1715 };
1716 static const char *const wide_add_cond_names[] =
1717 {
1718 "", ",=", ",<", ",<=", ",nuv", ",*=", ",*<", ",*<=",
1719 ",tr", ",<>", ",>=", ",>", ",uv", ",*<>", ",*>=", ",*>"
1720 };
1721 static const char *const logical_cond_names[] =
1722 {
1723 "", ",=", ",<", ",<=", 0, 0, 0, ",od",
1724 ",tr", ",<>", ",>=", ",>", 0, 0, 0, ",ev"};
1725 static const char *const logical_cond_64_names[] =
1726 {
1727 "", ",*=", ",*<", ",*<=", 0, 0, 0, ",*od",
1728 ",*tr", ",*<>", ",*>=", ",*>", 0, 0, 0, ",*ev"};
1729 static const char *const unit_cond_names[] =
1730 {
1731 "", ",swz", ",sbz", ",shz", ",sdc", ",swc", ",sbc", ",shc",
1732 ",tr", ",nwz", ",nbz", ",nhz", ",ndc", ",nwc", ",nbc", ",nhc"
1733 };
1734 static const char *const unit_cond_64_names[] =
1735 {
1736 "", ",*swz", ",*sbz", ",*shz", ",*sdc", ",*swc", ",*sbc", ",*shc",
1737 ",*tr", ",*nwz", ",*nbz", ",*nhz", ",*ndc", ",*nwc", ",*nbc", ",*nhc"
1738 };
1739 static const char *const shift_cond_names[] =
1740 {
1741 "", ",=", ",<", ",od", ",tr", ",<>", ",>=", ",ev"
1742 };
1743 static const char *const shift_cond_64_names[] =
1744 {
1745 "", ",*=", ",*<", ",*od", ",*tr", ",*<>", ",*>=", ",*ev"
1746 };
1747 static const char *const bb_cond_64_names[] =
1748 {
1749 ",*<", ",*>="
1750 };
1751 static const char *const index_compl_names[] = {"", ",m", ",s", ",sm"};
1752 static const char *const short_ldst_compl_names[] = {"", ",ma", "", ",mb"};
1753 static const char *const short_bytes_compl_names[] =
1754 {
1755 "", ",b,m", ",e", ",e,m"
1756 };
1757 static const char *const float_format_names[] = {",sgl", ",dbl", "", ",quad"};
1758 static const char *const fcnv_fixed_names[] = {",w", ",dw", "", ",qw"};
1759 static const char *const fcnv_ufixed_names[] = {",uw", ",udw", "", ",uqw"};
1760 static const char *const float_comp_names[] =
1761 {
1762 ",false?", ",false", ",?", ",!<=>", ",=", ",=t", ",?=", ",!<>",
1763 ",!?>=", ",<", ",?<", ",!>=", ",!?>", ",<=", ",?<=", ",!>",
1764 ",!?<=", ",>", ",?>", ",!<=", ",!?<", ",>=", ",?>=", ",!<",
1765 ",!?=", ",<>", ",!=", ",!=t", ",!?", ",<=>", ",true?", ",true"
1766 };
1767 static const char *const signed_unsigned_names[] = {",u", ",s"};
1768 static const char *const mix_half_names[] = {",l", ",r"};
1769 static const char *const saturation_names[] = {",us", ",ss", 0, ""};
1770 static const char *const read_write_names[] = {",r", ",w"};
1771 static const char *const add_compl_names[] = { 0, "", ",l", ",tsv" };
1772
1773 /* For a bunch of different instructions form an index into a
1774 completer name table. */
1775 #define GET_COMPL(insn) (GET_FIELD (insn, 26, 26) | \
1776 GET_FIELD (insn, 18, 18) << 1)
1777
1778 #define GET_COND(insn) (GET_FIELD ((insn), 16, 18) + \
1779 (GET_FIELD ((insn), 19, 19) ? 8 : 0))
1780
1781 /* Utility function to print registers. Put these first, so gcc's function
1782 inlining can do its stuff. */
1783
1784 #define fputs_filtered(STR,F) (*info->fprintf_func) (info->stream, "%s", STR)
1785
1786 static void
1787 fput_reg (unsigned reg, disassemble_info *info)
1788 {
1789 (*info->fprintf_func) (info->stream, "%s", reg ? reg_names[reg] : "r0");
1790 }
1791
1792 static void
1793 fput_fp_reg (unsigned reg, disassemble_info *info)
1794 {
1795 (*info->fprintf_func) (info->stream, "%s", reg ? fp_reg_names[reg] : "fr0");
1796 }
1797
1798 static void
1799 fput_fp_reg_r (unsigned reg, disassemble_info *info)
1800 {
1801 /* Special case floating point exception registers. */
1802 if (reg < 4)
1803 (*info->fprintf_func) (info->stream, "fpe%d", reg * 2 + 1);
1804 else
1805 (*info->fprintf_func) (info->stream, "%sR", fp_reg_names[reg]);
1806 }
1807
1808 static void
1809 fput_creg (unsigned reg, disassemble_info *info)
1810 {
1811 (*info->fprintf_func) (info->stream, "%s", control_reg[reg]);
1812 }
1813
1814 static void
1815 fput_dreg (unsigned reg, disassemble_info *info)
1816 {
1817 (*info->fprintf_func) (info->stream, "dr%d", reg);
1818 }
1819
1820 /* Print constants with sign. */
1821
1822 static void
1823 fput_const (unsigned num, disassemble_info *info)
1824 {
1825 if ((int) num < 0)
1826 (*info->fprintf_func) (info->stream, "-%x", - (int) num);
1827 else
1828 (*info->fprintf_func) (info->stream, "%x", num);
1829 }
1830
1831 /* Routines to extract various sized constants out of hppa
1832 instructions. */
1833
1834 /* Extract a 3-bit space register number from a be, ble, mtsp or mfsp. */
1835 static int
1836 extract_3 (unsigned word)
1837 {
1838 return GET_FIELD (word, 18, 18) << 2 | GET_FIELD (word, 16, 17);
1839 }
1840
1841 static int
1842 extract_5_load (unsigned word)
1843 {
1844 return low_sign_extend (word >> 16 & MASK_5, 5);
1845 }
1846
1847 /* Extract the immediate field from a st{bhw}s instruction. */
1848
1849 static int
1850 extract_5_store (unsigned word)
1851 {
1852 return low_sign_extend (word & MASK_5, 5);
1853 }
1854
1855 /* Extract the immediate field from a break instruction. */
1856
1857 static unsigned
1858 extract_5r_store (unsigned word)
1859 {
1860 return (word & MASK_5);
1861 }
1862
1863 /* Extract the immediate field from a {sr}sm instruction. */
1864
1865 static unsigned
1866 extract_5R_store (unsigned word)
1867 {
1868 return (word >> 16 & MASK_5);
1869 }
1870
1871 /* Extract the 10 bit immediate field from a {sr}sm instruction. */
1872
1873 static unsigned
1874 extract_10U_store (unsigned word)
1875 {
1876 return (word >> 16 & MASK_10);
1877 }
1878
1879 /* Extract the immediate field from a bb instruction. */
1880
1881 static unsigned
1882 extract_5Q_store (unsigned word)
1883 {
1884 return (word >> 21 & MASK_5);
1885 }
1886
1887 /* Extract an 11 bit immediate field. */
1888
1889 static int
1890 extract_11 (unsigned word)
1891 {
1892 return low_sign_extend (word & MASK_11, 11);
1893 }
1894
1895 /* Extract a 14 bit immediate field. */
1896
1897 static int
1898 extract_14 (unsigned word)
1899 {
1900 return low_sign_extend (word & MASK_14, 14);
1901 }
1902
1903 /* Extract a 16 bit immediate field (PA2.0 wide only). */
1904
1905 static int
1906 extract_16 (unsigned word)
1907 {
1908 int m15, m0, m1;
1909
1910 m0 = GET_BIT (word, 16);
1911 m1 = GET_BIT (word, 17);
1912 m15 = GET_BIT (word, 31);
1913 word = (word >> 1) & 0x1fff;
1914 word = word | (m15 << 15) | ((m15 ^ m0) << 14) | ((m15 ^ m1) << 13);
1915 return sign_extend (word, 16);
1916 }
1917
1918 /* Extract a 21 bit constant. */
1919
1920 static int
1921 extract_21 (unsigned word)
1922 {
1923 int val;
1924
1925 word &= MASK_21;
1926 word <<= 11;
1927 val = GET_FIELD (word, 20, 20);
1928 val <<= 11;
1929 val |= GET_FIELD (word, 9, 19);
1930 val <<= 2;
1931 val |= GET_FIELD (word, 5, 6);
1932 val <<= 5;
1933 val |= GET_FIELD (word, 0, 4);
1934 val <<= 2;
1935 val |= GET_FIELD (word, 7, 8);
1936 return sign_extend (val, 21) << 11;
1937 }
1938
1939 /* Extract a 12 bit constant from branch instructions. */
1940
1941 static int
1942 extract_12 (unsigned word)
1943 {
1944 return sign_extend (GET_FIELD (word, 19, 28)
1945 | GET_FIELD (word, 29, 29) << 10
1946 | (word & 0x1) << 11, 12) << 2;
1947 }
1948
1949 /* Extract a 17 bit constant from branch instructions, returning the
1950 19 bit signed value. */
1951
1952 static int
1953 extract_17 (unsigned word)
1954 {
1955 return sign_extend (GET_FIELD (word, 19, 28)
1956 | GET_FIELD (word, 29, 29) << 10
1957 | GET_FIELD (word, 11, 15) << 11
1958 | (word & 0x1) << 16, 17) << 2;
1959 }
1960
1961 static int
1962 extract_22 (unsigned word)
1963 {
1964 return sign_extend (GET_FIELD (word, 19, 28)
1965 | GET_FIELD (word, 29, 29) << 10
1966 | GET_FIELD (word, 11, 15) << 11
1967 | GET_FIELD (word, 6, 10) << 16
1968 | (word & 0x1) << 21, 22) << 2;
1969 }
1970
1971 /* Print one instruction. */
1972
1973 int
1974 print_insn_hppa (bfd_vma memaddr, disassemble_info *info)
1975 {
1976 bfd_byte buffer[4];
1977 unsigned int insn, i;
1978
1979 {
1980 int status =
1981 (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
1982 if (status != 0)
1983 {
1984 (*info->memory_error_func) (status, memaddr, info);
1985 return -1;
1986 }
1987 }
1988
1989 insn = bfd_getb32 (buffer);
1990
1991 if (info->show_opcodes) {
1992 info->fprintf_func(info->stream, " %02x %02x %02x %02x ",
1993 (insn >> 24) & 0xff, (insn >> 16) & 0xff,
1994 (insn >> 8) & 0xff, insn & 0xff);
1995 }
1996
1997 for (i = 0; i < NUMOPCODES; ++i)
1998 {
1999 const struct pa_opcode *opcode = &pa_opcodes[i];
2000
2001 if ((insn & opcode->mask) == opcode->match)
2002 {
2003 const char *s;
2004 #ifndef BFD64
2005 if (opcode->arch == pa20w)
2006 continue;
2007 #endif
2008 (*info->fprintf_func) (info->stream, "%s", opcode->name);
2009
2010 if (!strchr ("cfCY?-+nHNZFIuv{", opcode->args[0]))
2011 (*info->fprintf_func) (info->stream, " ");
2012 for (s = opcode->args; *s != '\0'; ++s)
2013 {
2014 switch (*s)
2015 {
2016 case 'x':
2017 fput_reg (GET_FIELD (insn, 11, 15), info);
2018 break;
2019 case 'a':
2020 case 'b':
2021 fput_reg (GET_FIELD (insn, 6, 10), info);
2022 break;
2023 case '^':
2024 fput_creg (GET_FIELD (insn, 6, 10), info);
2025 break;
2026 case '9':
2027 fput_dreg (GET_FIELD (insn, 6, 10), info);
2028 break;
2029 case 't':
2030 fput_reg (GET_FIELD (insn, 27, 31), info);
2031 break;
2032
2033 /* Handle floating point registers. */
2034 case 'f':
2035 switch (*++s)
2036 {
2037 case 't':
2038 fput_fp_reg (GET_FIELD (insn, 27, 31), info);
2039 break;
2040 case 'T':
2041 if (GET_FIELD (insn, 25, 25))
2042 fput_fp_reg_r (GET_FIELD (insn, 27, 31), info);
2043 else
2044 fput_fp_reg (GET_FIELD (insn, 27, 31), info);
2045 break;
2046 case 'a':
2047 if (GET_FIELD (insn, 25, 25))
2048 fput_fp_reg_r (GET_FIELD (insn, 6, 10), info);
2049 else
2050 fput_fp_reg (GET_FIELD (insn, 6, 10), info);
2051 break;
2052
2053 /* 'fA' will not generate a space before the register
2054 name. Normally that is fine. Except that it
2055 causes problems with xmpyu which has no FP format
2056 completer. */
2057 case 'X':
2058 fputs_filtered (" ", info);
2059 /* FALLTHRU */
2060
2061 case 'A':
2062 if (GET_FIELD (insn, 24, 24))
2063 fput_fp_reg_r (GET_FIELD (insn, 6, 10), info);
2064 else
2065 fput_fp_reg (GET_FIELD (insn, 6, 10), info);
2066 break;
2067 case 'b':
2068 if (GET_FIELD (insn, 25, 25))
2069 fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
2070 else
2071 fput_fp_reg (GET_FIELD (insn, 11, 15), info);
2072 break;
2073 case 'B':
2074 if (GET_FIELD (insn, 19, 19))
2075 fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
2076 else
2077 fput_fp_reg (GET_FIELD (insn, 11, 15), info);
2078 break;
2079 case 'C':
2080 {
2081 int reg = GET_FIELD (insn, 21, 22);
2082 reg |= GET_FIELD (insn, 16, 18) << 2;
2083 if (GET_FIELD (insn, 23, 23) != 0)
2084 fput_fp_reg_r (reg, info);
2085 else
2086 fput_fp_reg (reg, info);
2087 break;
2088 }
2089 case 'i':
2090 {
2091 int reg = GET_FIELD (insn, 6, 10);
2092
2093 reg |= (GET_FIELD (insn, 26, 26) << 4);
2094 fput_fp_reg (reg, info);
2095 break;
2096 }
2097 case 'j':
2098 {
2099 int reg = GET_FIELD (insn, 11, 15);
2100
2101 reg |= (GET_FIELD (insn, 26, 26) << 4);
2102 fput_fp_reg (reg, info);
2103 break;
2104 }
2105 case 'k':
2106 {
2107 int reg = GET_FIELD (insn, 27, 31);
2108
2109 reg |= (GET_FIELD (insn, 26, 26) << 4);
2110 fput_fp_reg (reg, info);
2111 break;
2112 }
2113 case 'l':
2114 {
2115 int reg = GET_FIELD (insn, 21, 25);
2116
2117 reg |= (GET_FIELD (insn, 26, 26) << 4);
2118 fput_fp_reg (reg, info);
2119 break;
2120 }
2121 case 'm':
2122 {
2123 int reg = GET_FIELD (insn, 16, 20);
2124
2125 reg |= (GET_FIELD (insn, 26, 26) << 4);
2126 fput_fp_reg (reg, info);
2127 break;
2128 }
2129
2130 /* 'fe' will not generate a space before the register
2131 name. Normally that is fine. Except that it
2132 causes problems with fstw fe,y(b) which has no FP
2133 format completer. */
2134 case 'E':
2135 fputs_filtered (" ", info);
2136 /* FALLTHRU */
2137
2138 case 'e':
2139 if (GET_FIELD (insn, 30, 30))
2140 fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
2141 else
2142 fput_fp_reg (GET_FIELD (insn, 11, 15), info);
2143 break;
2144 case 'x':
2145 fput_fp_reg (GET_FIELD (insn, 11, 15), info);
2146 break;
2147 }
2148 break;
2149
2150 case '5':
2151 fput_const (extract_5_load (insn), info);
2152 break;
2153 case 's':
2154 {
2155 int space = GET_FIELD (insn, 16, 17);
2156 /* Zero means implicit addressing, not use of sr0. */
2157 if (space != 0)
2158 (*info->fprintf_func) (info->stream, "sr%d", space);
2159 }
2160 break;
2161
2162 case 'S':
2163 (*info->fprintf_func) (info->stream, "sr%d",
2164 extract_3 (insn));
2165 break;
2166
2167 /* Handle completers. */
2168 case 'c':
2169 switch (*++s)
2170 {
2171 case 'x':
2172 (*info->fprintf_func)
2173 (info->stream, "%s",
2174 index_compl_names[GET_COMPL (insn)]);
2175 break;
2176 case 'X':
2177 (*info->fprintf_func)
2178 (info->stream, "%s ",
2179 index_compl_names[GET_COMPL (insn)]);
2180 break;
2181 case 'm':
2182 (*info->fprintf_func)
2183 (info->stream, "%s",
2184 short_ldst_compl_names[GET_COMPL (insn)]);
2185 break;
2186 case 'M':
2187 (*info->fprintf_func)
2188 (info->stream, "%s ",
2189 short_ldst_compl_names[GET_COMPL (insn)]);
2190 break;
2191 case 'A':
2192 (*info->fprintf_func)
2193 (info->stream, "%s ",
2194 short_bytes_compl_names[GET_COMPL (insn)]);
2195 break;
2196 case 's':
2197 (*info->fprintf_func)
2198 (info->stream, "%s",
2199 short_bytes_compl_names[GET_COMPL (insn)]);
2200 break;
2201 case 'c':
2202 case 'C':
2203 switch (GET_FIELD (insn, 20, 21))
2204 {
2205 case 1:
2206 (*info->fprintf_func) (info->stream, ",bc ");
2207 break;
2208 case 2:
2209 (*info->fprintf_func) (info->stream, ",sl ");
2210 break;
2211 default:
2212 (*info->fprintf_func) (info->stream, " ");
2213 }
2214 break;
2215 case 'd':
2216 switch (GET_FIELD (insn, 20, 21))
2217 {
2218 case 1:
2219 (*info->fprintf_func) (info->stream, ",co ");
2220 break;
2221 default:
2222 (*info->fprintf_func) (info->stream, " ");
2223 }
2224 break;
2225 case 'o':
2226 (*info->fprintf_func) (info->stream, ",o");
2227 break;
2228 case 'g':
2229 (*info->fprintf_func) (info->stream, ",gate");
2230 break;
2231 case 'p':
2232 (*info->fprintf_func) (info->stream, ",l,push");
2233 break;
2234 case 'P':
2235 (*info->fprintf_func) (info->stream, ",pop");
2236 break;
2237 case 'l':
2238 case 'L':
2239 (*info->fprintf_func) (info->stream, ",l");
2240 break;
2241 case 'w':
2242 (*info->fprintf_func)
2243 (info->stream, "%s ",
2244 read_write_names[GET_FIELD (insn, 25, 25)]);
2245 break;
2246 case 'W':
2247 (*info->fprintf_func) (info->stream, ",w ");
2248 break;
2249 case 'r':
2250 if (GET_FIELD (insn, 23, 26) == 5)
2251 (*info->fprintf_func) (info->stream, ",r");
2252 break;
2253 case 'Z':
2254 if (GET_FIELD (insn, 26, 26))
2255 (*info->fprintf_func) (info->stream, ",m ");
2256 else
2257 (*info->fprintf_func) (info->stream, " ");
2258 break;
2259 case 'i':
2260 if (GET_FIELD (insn, 25, 25))
2261 (*info->fprintf_func) (info->stream, ",i");
2262 break;
2263 case 'z':
2264 if (!GET_FIELD (insn, 21, 21))
2265 (*info->fprintf_func) (info->stream, ",z");
2266 break;
2267 case 'a':
2268 (*info->fprintf_func)
2269 (info->stream, "%s",
2270 add_compl_names[GET_FIELD (insn, 20, 21)]);
2271 break;
2272 case 'Y':
2273 (*info->fprintf_func)
2274 (info->stream, ",dc%s",
2275 add_compl_names[GET_FIELD (insn, 20, 21)]);
2276 break;
2277 case 'y':
2278 (*info->fprintf_func)
2279 (info->stream, ",c%s",
2280 add_compl_names[GET_FIELD (insn, 20, 21)]);
2281 break;
2282 case 'v':
2283 if (GET_FIELD (insn, 20, 20))
2284 (*info->fprintf_func) (info->stream, ",tsv");
2285 break;
2286 case 't':
2287 (*info->fprintf_func) (info->stream, ",tc");
2288 if (GET_FIELD (insn, 20, 20))
2289 (*info->fprintf_func) (info->stream, ",tsv");
2290 break;
2291 case 'B':
2292 (*info->fprintf_func) (info->stream, ",db");
2293 if (GET_FIELD (insn, 20, 20))
2294 (*info->fprintf_func) (info->stream, ",tsv");
2295 break;
2296 case 'b':
2297 (*info->fprintf_func) (info->stream, ",b");
2298 if (GET_FIELD (insn, 20, 20))
2299 (*info->fprintf_func) (info->stream, ",tsv");
2300 break;
2301 case 'T':
2302 if (GET_FIELD (insn, 25, 25))
2303 (*info->fprintf_func) (info->stream, ",tc");
2304 break;
2305 case 'S':
2306 /* EXTRD/W has a following condition. */
2307 if (*(s + 1) == '?')
2308 (*info->fprintf_func)
2309 (info->stream, "%s",
2310 signed_unsigned_names[GET_FIELD (insn, 21, 21)]);
2311 else
2312 (*info->fprintf_func)
2313 (info->stream, "%s ",
2314 signed_unsigned_names[GET_FIELD (insn, 21, 21)]);
2315 break;
2316 case 'h':
2317 (*info->fprintf_func)
2318 (info->stream, "%s",
2319 mix_half_names[GET_FIELD (insn, 17, 17)]);
2320 break;
2321 case 'H':
2322 (*info->fprintf_func)
2323 (info->stream, "%s ",
2324 saturation_names[GET_FIELD (insn, 24, 25)]);
2325 break;
2326 case '*':
2327 (*info->fprintf_func)
2328 (info->stream, ",%d%d%d%d ",
2329 GET_FIELD (insn, 17, 18), GET_FIELD (insn, 20, 21),
2330 GET_FIELD (insn, 22, 23), GET_FIELD (insn, 24, 25));
2331 break;
2332
2333 case 'q':
2334 {
2335 int m, a;
2336
2337 m = GET_FIELD (insn, 28, 28);
2338 a = GET_FIELD (insn, 29, 29);
2339
2340 if (m && !a)
2341 fputs_filtered (",ma ", info);
2342 else if (m && a)
2343 fputs_filtered (",mb ", info);
2344 else
2345 fputs_filtered (" ", info);
2346 break;
2347 }
2348
2349 case 'J':
2350 {
2351 int opc = GET_FIELD (insn, 0, 5);
2352
2353 if (opc == 0x16 || opc == 0x1e)
2354 {
2355 if (GET_FIELD (insn, 29, 29) == 0)
2356 fputs_filtered (",ma ", info);
2357 else
2358 fputs_filtered (",mb ", info);
2359 }
2360 else
2361 fputs_filtered (" ", info);
2362 break;
2363 }
2364
2365 case 'e':
2366 {
2367 int opc = GET_FIELD (insn, 0, 5);
2368
2369 if (opc == 0x13 || opc == 0x1b)
2370 {
2371 if (GET_FIELD (insn, 18, 18) == 1)
2372 fputs_filtered (",mb ", info);
2373 else
2374 fputs_filtered (",ma ", info);
2375 }
2376 else if (opc == 0x17 || opc == 0x1f)
2377 {
2378 if (GET_FIELD (insn, 31, 31) == 1)
2379 fputs_filtered (",ma ", info);
2380 else
2381 fputs_filtered (",mb ", info);
2382 }
2383 else
2384 fputs_filtered (" ", info);
2385
2386 break;
2387 }
2388 }
2389 break;
2390
2391 /* Handle conditions. */
2392 case '?':
2393 {
2394 s++;
2395 switch (*s)
2396 {
2397 case 'f':
2398 (*info->fprintf_func)
2399 (info->stream, "%s ",
2400 float_comp_names[GET_FIELD (insn, 27, 31)]);
2401 break;
2402
2403 /* These four conditions are for the set of instructions
2404 which distinguish true/false conditions by opcode
2405 rather than by the 'f' bit (sigh): comb, comib,
2406 addb, addib. */
2407 case 't':
2408 fputs_filtered
2409 (compare_cond_names[GET_FIELD (insn, 16, 18)], info);
2410 break;
2411 case 'n':
2412 fputs_filtered
2413 (compare_cond_names[GET_FIELD (insn, 16, 18)
2414 + GET_FIELD (insn, 4, 4) * 8],
2415 info);
2416 break;
2417 case 'N':
2418 fputs_filtered
2419 (compare_cond_64_names[GET_FIELD (insn, 16, 18)
2420 + GET_FIELD (insn, 2, 2) * 8],
2421 info);
2422 break;
2423 case 'Q':
2424 fputs_filtered
2425 (cmpib_cond_64_names[GET_FIELD (insn, 16, 18)],
2426 info);
2427 break;
2428 case '@':
2429 fputs_filtered
2430 (add_cond_names[GET_FIELD (insn, 16, 18)
2431 + GET_FIELD (insn, 4, 4) * 8],
2432 info);
2433 break;
2434 case 's':
2435 (*info->fprintf_func)
2436 (info->stream, "%s ",
2437 compare_cond_names[GET_COND (insn)]);
2438 break;
2439 case 'S':
2440 (*info->fprintf_func)
2441 (info->stream, "%s ",
2442 compare_cond_64_names[GET_COND (insn)]);
2443 break;
2444 case 'a':
2445 (*info->fprintf_func)
2446 (info->stream, "%s ",
2447 add_cond_names[GET_COND (insn)]);
2448 break;
2449 case 'A':
2450 (*info->fprintf_func)
2451 (info->stream, "%s ",
2452 add_cond_64_names[GET_COND (insn)]);
2453 break;
2454 case 'd':
2455 (*info->fprintf_func)
2456 (info->stream, "%s",
2457 add_cond_names[GET_FIELD (insn, 16, 18)]);
2458 break;
2459
2460 case 'W':
2461 (*info->fprintf_func)
2462 (info->stream, "%s",
2463 wide_add_cond_names[GET_FIELD (insn, 16, 18) +
2464 GET_FIELD (insn, 4, 4) * 8]);
2465 break;
2466
2467 case 'l':
2468 (*info->fprintf_func)
2469 (info->stream, "%s ",
2470 logical_cond_names[GET_COND (insn)]);
2471 break;
2472 case 'L':
2473 (*info->fprintf_func)
2474 (info->stream, "%s ",
2475 logical_cond_64_names[GET_COND (insn)]);
2476 break;
2477 case 'u':
2478 (*info->fprintf_func)
2479 (info->stream, "%s ",
2480 unit_cond_names[GET_COND (insn)]);
2481 break;
2482 case 'U':
2483 (*info->fprintf_func)
2484 (info->stream, "%s ",
2485 unit_cond_64_names[GET_COND (insn)]);
2486 break;
2487 case 'y':
2488 case 'x':
2489 case 'b':
2490 (*info->fprintf_func)
2491 (info->stream, "%s",
2492 shift_cond_names[GET_FIELD (insn, 16, 18)]);
2493
2494 /* If the next character in args is 'n', it will handle
2495 putting out the space. */
2496 if (s[1] != 'n')
2497 (*info->fprintf_func) (info->stream, " ");
2498 break;
2499 case 'X':
2500 (*info->fprintf_func)
2501 (info->stream, "%s ",
2502 shift_cond_64_names[GET_FIELD (insn, 16, 18)]);
2503 break;
2504 case 'B':
2505 (*info->fprintf_func)
2506 (info->stream, "%s",
2507 bb_cond_64_names[GET_FIELD (insn, 16, 16)]);
2508
2509 /* If the next character in args is 'n', it will handle
2510 putting out the space. */
2511 if (s[1] != 'n')
2512 (*info->fprintf_func) (info->stream, " ");
2513 break;
2514 }
2515 break;
2516 }
2517
2518 case 'V':
2519 fput_const (extract_5_store (insn), info);
2520 break;
2521 case 'r':
2522 fput_const (extract_5r_store (insn), info);
2523 break;
2524 case 'R':
2525 fput_const (extract_5R_store (insn), info);
2526 break;
2527 case 'U':
2528 fput_const (extract_10U_store (insn), info);
2529 break;
2530 case 'B':
2531 case 'Q':
2532 fput_const (extract_5Q_store (insn), info);
2533 break;
2534 case 'i':
2535 fput_const (extract_11 (insn), info);
2536 break;
2537 case 'j':
2538 fput_const (extract_14 (insn), info);
2539 break;
2540 case 'k':
2541 fputs_filtered ("L%", info);
2542 fput_const (extract_21 (insn), info);
2543 break;
2544 case '<':
2545 case 'l':
2546 /* 16-bit long disp., PA2.0 wide only. */
2547 fput_const (extract_16 (insn), info);
2548 break;
2549 case 'n':
2550 if (insn & 0x2)
2551 (*info->fprintf_func) (info->stream, ",n ");
2552 else
2553 (*info->fprintf_func) (info->stream, " ");
2554 break;
2555 case 'N':
2556 if ((insn & 0x20) && s[1])
2557 (*info->fprintf_func) (info->stream, ",n ");
2558 else if (insn & 0x20)
2559 (*info->fprintf_func) (info->stream, ",n");
2560 else if (s[1])
2561 (*info->fprintf_func) (info->stream, " ");
2562 break;
2563 case 'w':
2564 (*info->print_address_func)
2565 (memaddr + 8 + extract_12 (insn), info);
2566 break;
2567 case 'W':
2568 /* 17 bit PC-relative branch. */
2569 (*info->print_address_func)
2570 ((memaddr + 8 + extract_17 (insn)), info);
2571 break;
2572 case 'z':
2573 /* 17 bit displacement. This is an offset from a register
2574 so it gets disasssembled as just a number, not any sort
2575 of address. */
2576 fput_const (extract_17 (insn), info);
2577 break;
2578
2579 case 'Z':
2580 /* addil %r1 implicit output. */
2581 fputs_filtered ("r1", info);
2582 break;
2583
2584 case 'Y':
2585 /* be,l %sr0,%r31 implicit output. */
2586 fputs_filtered ("sr0,r31", info);
2587 break;
2588
2589 case '@':
2590 (*info->fprintf_func) (info->stream, "0");
2591 break;
2592
2593 case '.':
2594 (*info->fprintf_func) (info->stream, "%d",
2595 GET_FIELD (insn, 24, 25));
2596 break;
2597 case '*':
2598 (*info->fprintf_func) (info->stream, "%d",
2599 GET_FIELD (insn, 22, 25));
2600 break;
2601 case '!':
2602 fputs_filtered ("sar", info);
2603 break;
2604 case 'p':
2605 (*info->fprintf_func) (info->stream, "%d",
2606 31 - GET_FIELD (insn, 22, 26));
2607 break;
2608 case '~':
2609 {
2610 int num;
2611 num = GET_FIELD (insn, 20, 20) << 5;
2612 num |= GET_FIELD (insn, 22, 26);
2613 (*info->fprintf_func) (info->stream, "%d", 63 - num);
2614 break;
2615 }
2616 case 'P':
2617 (*info->fprintf_func) (info->stream, "%d",
2618 GET_FIELD (insn, 22, 26));
2619 break;
2620 case 'q':
2621 {
2622 int num;
2623 num = GET_FIELD (insn, 20, 20) << 5;
2624 num |= GET_FIELD (insn, 22, 26);
2625 (*info->fprintf_func) (info->stream, "%d", num);
2626 break;
2627 }
2628 case 'T':
2629 (*info->fprintf_func) (info->stream, "%d",
2630 32 - GET_FIELD (insn, 27, 31));
2631 break;
2632 case '%':
2633 {
2634 int num;
2635 num = (GET_FIELD (insn, 23, 23) + 1) * 32;
2636 num -= GET_FIELD (insn, 27, 31);
2637 (*info->fprintf_func) (info->stream, "%d", num);
2638 break;
2639 }
2640 case '|':
2641 {
2642 int num;
2643 num = (GET_FIELD (insn, 19, 19) + 1) * 32;
2644 num -= GET_FIELD (insn, 27, 31);
2645 (*info->fprintf_func) (info->stream, "%d", num);
2646 break;
2647 }
2648 case '$':
2649 fput_const (GET_FIELD (insn, 20, 28), info);
2650 break;
2651 case 'A':
2652 fput_const (GET_FIELD (insn, 6, 18), info);
2653 break;
2654 case 'D':
2655 fput_const (GET_FIELD (insn, 6, 31), info);
2656 break;
2657 case 'v':
2658 (*info->fprintf_func) (info->stream, ",%d",
2659 GET_FIELD (insn, 23, 25));
2660 break;
2661 case 'O':
2662 fput_const ((GET_FIELD (insn, 6,20) << 5 |
2663 GET_FIELD (insn, 27, 31)), info);
2664 break;
2665 case 'o':
2666 fput_const (GET_FIELD (insn, 6, 20), info);
2667 break;
2668 case '2':
2669 fput_const ((GET_FIELD (insn, 6, 22) << 5 |
2670 GET_FIELD (insn, 27, 31)), info);
2671 break;
2672 case '1':
2673 fput_const ((GET_FIELD (insn, 11, 20) << 5 |
2674 GET_FIELD (insn, 27, 31)), info);
2675 break;
2676 case '0':
2677 fput_const ((GET_FIELD (insn, 16, 20) << 5 |
2678 GET_FIELD (insn, 27, 31)), info);
2679 break;
2680 case 'u':
2681 (*info->fprintf_func) (info->stream, ",%d",
2682 GET_FIELD (insn, 23, 25));
2683 break;
2684 case 'F':
2685 /* If no destination completer and not before a completer
2686 for fcmp, need a space here. */
2687 if (s[1] == 'G' || s[1] == '?')
2688 fputs_filtered
2689 (float_format_names[GET_FIELD (insn, 19, 20)], info);
2690 else
2691 (*info->fprintf_func)
2692 (info->stream, "%s ",
2693 float_format_names[GET_FIELD (insn, 19, 20)]);
2694 break;
2695 case 'G':
2696 (*info->fprintf_func)
2697 (info->stream, "%s ",
2698 float_format_names[GET_FIELD (insn, 17, 18)]);
2699 break;
2700 case 'H':
2701 if (GET_FIELD (insn, 26, 26) == 1)
2702 (*info->fprintf_func) (info->stream, "%s ",
2703 float_format_names[0]);
2704 else
2705 (*info->fprintf_func) (info->stream, "%s ",
2706 float_format_names[1]);
2707 break;
2708 case 'I':
2709 /* If no destination completer and not before a completer
2710 for fcmp, need a space here. */
2711 if (s[1] == '?')
2712 fputs_filtered
2713 (float_format_names[GET_FIELD (insn, 20, 20)], info);
2714 else
2715 (*info->fprintf_func)
2716 (info->stream, "%s ",
2717 float_format_names[GET_FIELD (insn, 20, 20)]);
2718 break;
2719
2720 case 'J':
2721 fput_const (extract_14 (insn), info);
2722 break;
2723
2724 case '#':
2725 {
2726 int sign = GET_FIELD (insn, 31, 31);
2727 int imm10 = GET_FIELD (insn, 18, 27);
2728 int disp;
2729
2730 if (sign)
2731 disp = (-1 << 10) | imm10;
2732 else
2733 disp = imm10;
2734
2735 disp <<= 3;
2736 fput_const (disp, info);
2737 break;
2738 }
2739 case 'K':
2740 case 'd':
2741 {
2742 int sign = GET_FIELD (insn, 31, 31);
2743 int imm11 = GET_FIELD (insn, 18, 28);
2744 int disp;
2745
2746 if (sign)
2747 disp = (-1 << 11) | imm11;
2748 else
2749 disp = imm11;
2750
2751 disp <<= 2;
2752 fput_const (disp, info);
2753 break;
2754 }
2755
2756 case '>':
2757 case 'y':
2758 {
2759 /* 16-bit long disp., PA2.0 wide only. */
2760 int disp = extract_16 (insn);
2761 disp &= ~3;
2762 fput_const (disp, info);
2763 break;
2764 }
2765
2766 case '&':
2767 {
2768 /* 16-bit long disp., PA2.0 wide only. */
2769 int disp = extract_16 (insn);
2770 disp &= ~7;
2771 fput_const (disp, info);
2772 break;
2773 }
2774
2775 case '_':
2776 break; /* Dealt with by '{' */
2777
2778 case '{':
2779 {
2780 int sub = GET_FIELD (insn, 14, 16);
2781 int df = GET_FIELD (insn, 17, 18);
2782 int sf = GET_FIELD (insn, 19, 20);
2783 const char * const * source = float_format_names;
2784 const char * const * dest = float_format_names;
2785 const char *t = "";
2786
2787 if (sub == 4)
2788 {
2789 fputs_filtered (",UND ", info);
2790 break;
2791 }
2792 if ((sub & 3) == 3)
2793 t = ",t";
2794 if ((sub & 3) == 1)
2795 source = sub & 4 ? fcnv_ufixed_names : fcnv_fixed_names;
2796 if (sub & 2)
2797 dest = sub & 4 ? fcnv_ufixed_names : fcnv_fixed_names;
2798
2799 (*info->fprintf_func) (info->stream, "%s%s%s ",
2800 t, source[sf], dest[df]);
2801 break;
2802 }
2803
2804 case 'm':
2805 {
2806 int y = GET_FIELD (insn, 16, 18);
2807
2808 if (y != 1)
2809 fput_const ((y ^ 1) - 1, info);
2810 }
2811 break;
2812
2813 case 'h':
2814 {
2815 int cbit;
2816
2817 cbit = GET_FIELD (insn, 16, 18);
2818
2819 if (cbit > 0)
2820 (*info->fprintf_func) (info->stream, ",%d", cbit - 1);
2821 break;
2822 }
2823
2824 case '=':
2825 {
2826 int cond = GET_FIELD (insn, 27, 31);
2827
2828 switch (cond)
2829 {
2830 case 0: fputs_filtered (" ", info); break;
2831 case 1: fputs_filtered ("acc ", info); break;
2832 case 2: fputs_filtered ("rej ", info); break;
2833 case 5: fputs_filtered ("acc8 ", info); break;
2834 case 6: fputs_filtered ("rej8 ", info); break;
2835 case 9: fputs_filtered ("acc6 ", info); break;
2836 case 13: fputs_filtered ("acc4 ", info); break;
2837 case 17: fputs_filtered ("acc2 ", info); break;
2838 default: break;
2839 }
2840 break;
2841 }
2842
2843 case 'X':
2844 (*info->print_address_func)
2845 (memaddr + 8 + extract_22 (insn), info);
2846 break;
2847 case 'L':
2848 fputs_filtered (",rp", info);
2849 break;
2850 default:
2851 (*info->fprintf_func) (info->stream, "%c", *s);
2852 break;
2853 }
2854 }
2855 return sizeof (insn);
2856 }
2857 }
2858 info->fprintf_func(info->stream, "<unknown>");
2859 return sizeof (insn);
2860 }
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