target-mips/mips-defs.h

   1 #if !defined (__QEMU_MIPS_DEFS_H__)
   2 #define __QEMU_MIPS_DEFS_H__
   3
   4 /* If we want to use host float regs... */
   5 //#define USE_HOST_FLOAT_REGS
   6
   7 /* Real pages are variable size... */
   8 #define TARGET_PAGE_BITS 12
   9 #define MIPS_TLB_MAX 128
  10
  11 #if defined(TARGET_MIPS64)
  12 #define TARGET_LONG_BITS 64
  13 #define TARGET_PHYS_ADDR_SPACE_BITS 36
  14 #define TARGET_VIRT_ADDR_SPACE_BITS 42
  15 #else
  16 #define TARGET_LONG_BITS 32
  17 #define TARGET_PHYS_ADDR_SPACE_BITS 36
  18 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  19 #endif
  20
  21 /* Masks used to mark instructions to indicate which ISA level they
  22    were introduced in. */
  23 #define         ISA_MIPS1       0x00000001
  24 #define         ISA_MIPS2       0x00000002
  25 #define         ISA_MIPS3       0x00000004
  26 #define         ISA_MIPS4       0x00000008
  27 #define         ISA_MIPS5       0x00000010
  28 #define         ISA_MIPS32      0x00000020
  29 #define         ISA_MIPS32R2    0x00000040
  30 #define         ISA_MIPS64      0x00000080
  31 #define         ISA_MIPS64R2    0x00000100
  32
  33 /* MIPS ASEs. */
  34 #define         ASE_MIPS16      0x00001000
  35 #define         ASE_MIPS3D      0x00002000
  36 #define         ASE_MDMX        0x00004000
  37 #define         ASE_DSP         0x00008000
  38 #define         ASE_DSPR2       0x00010000
  39 #define         ASE_MT          0x00020000
  40 #define         ASE_SMARTMIPS   0x00040000
  41 #define         ASE_MICROMIPS   0x00080000
  42
  43 /* Chip specific instructions. */
  44 #define         INSN_LOONGSON2E  0x20000000
  45 #define         INSN_LOONGSON2F  0x40000000
  46 #define         INSN_VR54XX     0x80000000
  47
  48 /* MIPS CPU defines. */
  49 #define         CPU_MIPS1       (ISA_MIPS1)
  50 #define         CPU_MIPS2       (CPU_MIPS1 | ISA_MIPS2)
  51 #define         CPU_MIPS3       (CPU_MIPS2 | ISA_MIPS3)
  52 #define         CPU_MIPS4       (CPU_MIPS3 | ISA_MIPS4)
  53 #define         CPU_VR54XX      (CPU_MIPS4 | INSN_VR54XX)
  54 #define         CPU_LOONGSON2E  (CPU_MIPS3 | INSN_LOONGSON2E)
  55 #define         CPU_LOONGSON2F  (CPU_MIPS3 | INSN_LOONGSON2F)
  56
  57 #define         CPU_MIPS5       (CPU_MIPS4 | ISA_MIPS5)
  58
  59 /* MIPS Technologies "Release 1" */
  60 #define         CPU_MIPS32      (CPU_MIPS2 | ISA_MIPS32)
  61 #define         CPU_MIPS64      (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64)
  62
  63 /* MIPS Technologies "Release 2" */
  64 #define         CPU_MIPS32R2    (CPU_MIPS32 | ISA_MIPS32R2)
  65 #define         CPU_MIPS64R2    (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
  66
  67 /* Strictly follow the architecture standard:
  68    - Disallow "special" instruction handling for PMON/SPIM.
  69    Note that we still maintain Count/Compare to match the host clock. */
  70 //#define MIPS_STRICT_STANDARD 1
  71
  72 #endif /* !defined (__QEMU_MIPS_DEFS_H__) */