lsi: Fix value overflow in request tag processing
[qemu/mdroth.git] / hw / pci.h
blobf6e6c5f4194f9298559dbb4fee39935b041320c8
1 #ifndef QEMU_PCI_H
2 #define QEMU_PCI_H
4 #include "qemu-common.h"
5 #include "qobject.h"
7 #include "qdev.h"
9 /* PCI includes legacy ISA access. */
10 #include "isa.h"
12 /* PCI bus */
14 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
15 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
16 #define PCI_FUNC(devfn) ((devfn) & 0x07)
18 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
19 #include "pci_ids.h"
21 /* QEMU-specific Vendor and Device ID definitions */
23 /* IBM (0x1014) */
24 #define PCI_DEVICE_ID_IBM_440GX 0x027f
25 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
27 /* Hitachi (0x1054) */
28 #define PCI_VENDOR_ID_HITACHI 0x1054
29 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
31 /* Apple (0x106b) */
32 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010
33 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
34 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
35 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
36 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
38 /* Realtek (0x10ec) */
39 #define PCI_DEVICE_ID_REALTEK_8029 0x8029
41 /* Xilinx (0x10ee) */
42 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
44 /* Marvell (0x11ab) */
45 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
47 /* QEMU/Bochs VGA (0x1234) */
48 #define PCI_VENDOR_ID_QEMU 0x1234
49 #define PCI_DEVICE_ID_QEMU_VGA 0x1111
51 /* VMWare (0x15ad) */
52 #define PCI_VENDOR_ID_VMWARE 0x15ad
53 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
54 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
55 #define PCI_DEVICE_ID_VMWARE_NET 0x0720
56 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
57 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
59 /* Intel (0x8086) */
60 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209
61 #define PCI_DEVICE_ID_INTEL_82557 0x1229
63 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
64 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
65 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
66 #define PCI_SUBDEVICE_ID_QEMU 0x1100
68 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000
69 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
70 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
71 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
73 #define FMT_PCIBUS PRIx64
75 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
76 uint32_t address, uint32_t data, int len);
77 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
78 uint32_t address, int len);
79 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
80 pcibus_t addr, pcibus_t size, int type);
81 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
83 typedef struct PCIIORegion {
84 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
85 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
86 pcibus_t size;
87 pcibus_t filtered_size;
88 uint8_t type;
89 PCIMapIORegionFunc *map_func;
90 } PCIIORegion;
92 #define PCI_ROM_SLOT 6
93 #define PCI_NUM_REGIONS 7
95 #include "pci_regs.h"
97 /* PCI HEADER_TYPE */
98 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
100 #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
101 PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \
102 PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK)
104 #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
106 /* Bits in the PCI Command Register (PCI 2.3 spec) */
107 #define PCI_COMMAND_RESERVED 0xf800
109 #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
111 /* Size of the standard PCI config header */
112 #define PCI_CONFIG_HEADER_SIZE 0x40
113 /* Size of the standard PCI config space */
114 #define PCI_CONFIG_SPACE_SIZE 0x100
115 /* Size of the standart PCIe config space: 4KB */
116 #define PCIE_CONFIG_SPACE_SIZE 0x1000
118 #define PCI_NUM_PINS 4 /* A-D */
120 /* Bits in cap_present field. */
121 enum {
122 QEMU_PCI_CAP_MSIX = 0x1,
123 QEMU_PCI_CAP_EXPRESS = 0x2,
126 struct PCIDevice {
127 DeviceState qdev;
128 /* PCI config space */
129 uint8_t *config;
131 /* Used to enable config checks on load. Note that writeable bits are
132 * never checked even if set in cmask. */
133 uint8_t *cmask;
135 /* Used to implement R/W bytes */
136 uint8_t *wmask;
138 /* Used to allocate config space for capabilities. */
139 uint8_t *used;
141 /* the following fields are read only */
142 PCIBus *bus;
143 uint32_t devfn;
144 char name[64];
145 PCIIORegion io_regions[PCI_NUM_REGIONS];
147 /* do not access the following fields */
148 PCIConfigReadFunc *config_read;
149 PCIConfigWriteFunc *config_write;
151 /* IRQ objects for the INTA-INTD pins. */
152 qemu_irq *irq;
154 /* Current IRQ levels. Used internally by the generic PCI code. */
155 uint8_t irq_state;
157 /* Capability bits */
158 uint32_t cap_present;
160 /* Offset of MSI-X capability in config space */
161 uint8_t msix_cap;
163 /* MSI-X entries */
164 int msix_entries_nr;
166 /* Space to store MSIX table */
167 uint8_t *msix_table_page;
168 /* MMIO index used to map MSIX table and pending bit entries. */
169 int msix_mmio_index;
170 /* Reference-count for entries actually in use by driver. */
171 unsigned *msix_entry_used;
172 /* Region including the MSI-X table */
173 uint32_t msix_bar_size;
174 /* Version id needed for VMState */
175 int32_t version_id;
177 /* Location of option rom */
178 char *romfile;
179 ram_addr_t rom_offset;
180 uint32_t rom_bar;
183 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
184 int instance_size, int devfn,
185 PCIConfigReadFunc *config_read,
186 PCIConfigWriteFunc *config_write);
188 void pci_register_bar(PCIDevice *pci_dev, int region_num,
189 pcibus_t size, int type,
190 PCIMapIORegionFunc *map_func);
192 int pci_add_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
193 int pci_add_capability_at_offset(PCIDevice *pci_dev, uint8_t cap_id,
194 uint8_t cap_offset, uint8_t cap_size);
196 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
198 void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size);
200 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
203 uint32_t pci_default_read_config(PCIDevice *d,
204 uint32_t address, int len);
205 void pci_default_write_config(PCIDevice *d,
206 uint32_t address, uint32_t val, int len);
207 void pci_device_save(PCIDevice *s, QEMUFile *f);
208 int pci_device_load(PCIDevice *s, QEMUFile *f);
210 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
211 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
212 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev, int state);
213 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
214 const char *name, int devfn_min);
215 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min);
216 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
217 void *irq_opaque, int nirq);
218 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
219 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
220 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
221 void *irq_opaque, int devfn_min, int nirq);
223 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base);
225 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
226 const char *default_devaddr);
227 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
228 const char *default_devaddr);
229 int pci_bus_num(PCIBus *s);
230 void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
231 PCIBus *pci_find_root_bus(int domain);
232 PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
233 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function);
234 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
236 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
237 unsigned *slotp);
239 void do_pci_info_print(Monitor *mon, const QObject *data);
240 void do_pci_info(Monitor *mon, QObject **ret_data);
241 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
242 pci_map_irq_fn map_irq, const char *name);
243 PCIDevice *pci_bridge_get_device(PCIBus *bus);
245 static inline void
246 pci_set_byte(uint8_t *config, uint8_t val)
248 *config = val;
251 static inline uint8_t
252 pci_get_byte(const uint8_t *config)
254 return *config;
257 static inline void
258 pci_set_word(uint8_t *config, uint16_t val)
260 cpu_to_le16wu((uint16_t *)config, val);
263 static inline uint16_t
264 pci_get_word(const uint8_t *config)
266 return le16_to_cpupu((const uint16_t *)config);
269 static inline void
270 pci_set_long(uint8_t *config, uint32_t val)
272 cpu_to_le32wu((uint32_t *)config, val);
275 static inline uint32_t
276 pci_get_long(const uint8_t *config)
278 return le32_to_cpupu((const uint32_t *)config);
281 static inline void
282 pci_set_quad(uint8_t *config, uint64_t val)
284 cpu_to_le64w((uint64_t *)config, val);
287 static inline uint64_t
288 pci_get_quad(const uint8_t *config)
290 return le64_to_cpup((const uint64_t *)config);
293 static inline void
294 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
296 pci_set_word(&pci_config[PCI_VENDOR_ID], val);
299 static inline void
300 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
302 pci_set_word(&pci_config[PCI_DEVICE_ID], val);
305 static inline void
306 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
308 pci_set_byte(&pci_config[PCI_REVISION_ID], val);
311 static inline void
312 pci_config_set_class(uint8_t *pci_config, uint16_t val)
314 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
317 static inline void
318 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
320 pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
323 static inline void
324 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
326 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
329 typedef int (*pci_qdev_initfn)(PCIDevice *dev);
330 typedef struct {
331 DeviceInfo qdev;
332 pci_qdev_initfn init;
333 PCIUnregisterFunc *exit;
334 PCIConfigReadFunc *config_read;
335 PCIConfigWriteFunc *config_write;
337 /* pci config header type */
338 uint8_t header_type;
340 /* pcie stuff */
341 int is_express; /* is this device pci express? */
343 /* rom bar */
344 const char *romfile;
345 } PCIDeviceInfo;
347 void pci_qdev_register(PCIDeviceInfo *info);
348 void pci_qdev_register_many(PCIDeviceInfo *info);
350 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
351 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
353 static inline int pci_is_express(PCIDevice *d)
355 return d->cap_present & QEMU_PCI_CAP_EXPRESS;
358 static inline uint32_t pci_config_size(PCIDevice *d)
360 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
363 /* These are not pci specific. Should move into a separate header.
364 * Only pci.c uses them, so keep them here for now.
367 /* Get last byte of a range from offset + length.
368 * Undefined for ranges that wrap around 0. */
369 static inline uint64_t range_get_last(uint64_t offset, uint64_t len)
371 return offset + len - 1;
374 /* Check whether a given range covers a given byte. */
375 static inline int range_covers_byte(uint64_t offset, uint64_t len,
376 uint64_t byte)
378 return offset <= byte && byte <= range_get_last(offset, len);
381 /* Check whether 2 given ranges overlap.
382 * Undefined if ranges that wrap around 0. */
383 static inline int ranges_overlap(uint64_t first1, uint64_t len1,
384 uint64_t first2, uint64_t len2)
386 uint64_t last1 = range_get_last(first1, len1);
387 uint64_t last2 = range_get_last(first2, len2);
389 return !(last2 < first1 || last1 < first2);
392 #endif