hw/versatile_pci.c

   1 /*
   2  * ARM Versatile/PB PCI host controller
   3  *
   4  * Copyright (c) 2006-2009 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licenced under the LGPL.
   8  */
   9
  10 #include "sysbus.h"
  11 #include "pci.h"
  12 #include "pci_host.h"
  13
  14 typedef struct {
  15     SysBusDevice busdev;
  16     qemu_irq irq[4];
  17     int realview;
  18     int mem_config;
  19 } PCIVPBState;
  20
  21 static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr)
  22 {
  23     return addr & 0xffffff;
  24 }
  25
  26 static void pci_vpb_config_writeb (void *opaque, target_phys_addr_t addr,
  27                                    uint32_t val)
  28 {
  29     pci_data_write(opaque, vpb_pci_config_addr (addr), val, 1);
  30 }
  31
  32 static void pci_vpb_config_writew (void *opaque, target_phys_addr_t addr,
  33                                    uint32_t val)
  34 {
  35     pci_data_write(opaque, vpb_pci_config_addr (addr), val, 2);
  36 }
  37
  38 static void pci_vpb_config_writel (void *opaque, target_phys_addr_t addr,
  39                                    uint32_t val)
  40 {
  41     pci_data_write(opaque, vpb_pci_config_addr (addr), val, 4);
  42 }
  43
  44 static uint32_t pci_vpb_config_readb (void *opaque, target_phys_addr_t addr)
  45 {
  46     uint32_t val;
  47     val = pci_data_read(opaque, vpb_pci_config_addr (addr), 1);
  48     return val;
  49 }
  50
  51 static uint32_t pci_vpb_config_readw (void *opaque, target_phys_addr_t addr)
  52 {
  53     uint32_t val;
  54     val = pci_data_read(opaque, vpb_pci_config_addr (addr), 2);
  55     return val;
  56 }
  57
  58 static uint32_t pci_vpb_config_readl (void *opaque, target_phys_addr_t addr)
  59 {
  60     uint32_t val;
  61     val = pci_data_read(opaque, vpb_pci_config_addr (addr), 4);
  62     return val;
  63 }
  64
  65 static CPUWriteMemoryFunc * const pci_vpb_config_write[] = {
  66     &pci_vpb_config_writeb,
  67     &pci_vpb_config_writew,
  68     &pci_vpb_config_writel,
  69 };
  70
  71 static CPUReadMemoryFunc * const pci_vpb_config_read[] = {
  72     &pci_vpb_config_readb,
  73     &pci_vpb_config_readw,
  74     &pci_vpb_config_readl,
  75 };
  76
  77 static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
  78 {
  79     return irq_num;
  80 }
  81
  82 static void pci_vpb_set_irq(void *opaque, int irq_num, int level)
  83 {
  84     qemu_irq *pic = opaque;
  85
  86     qemu_set_irq(pic[irq_num], level);
  87 }
  88
  89 static void pci_vpb_map(SysBusDevice *dev, target_phys_addr_t base)
  90 {
  91     PCIVPBState *s = (PCIVPBState *)dev;
  92     /* Selfconfig area.  */
  93     cpu_register_physical_memory(base + 0x01000000, 0x1000000, s->mem_config);
  94     /* Normal config area.  */
  95     cpu_register_physical_memory(base + 0x02000000, 0x1000000, s->mem_config);
  96
  97     if (s->realview) {
  98         /* IO memory area.  */
  99         isa_mmio_init(base + 0x03000000, 0x00100000);
 100     }
 101 }
 102
 103 static int pci_vpb_init(SysBusDevice *dev)
 104 {
 105     PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev);
 106     PCIBus *bus;
 107     int i;
 108
 109     for (i = 0; i < 4; i++) {
 110         sysbus_init_irq(dev, &s->irq[i]);
 111     }
 112     bus = pci_register_bus(&dev->qdev, "pci",
 113                            pci_vpb_set_irq, pci_vpb_map_irq, s->irq,
 114                            PCI_DEVFN(11, 0), 4);
 115
 116     /* ??? Register memory space.  */
 117
 118     s->mem_config = cpu_register_io_memory(pci_vpb_config_read,
 119                                            pci_vpb_config_write, bus,
 120                                            DEVICE_LITTLE_ENDIAN);
 121     sysbus_init_mmio_cb(dev, 0x04000000, pci_vpb_map);
 122
 123     pci_create_simple(bus, -1, "versatile_pci_host");
 124     return 0;
 125 }
 126
 127 static int pci_realview_init(SysBusDevice *dev)
 128 {
 129     PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev);
 130     s->realview = 1;
 131     return pci_vpb_init(dev);
 132 }
 133
 134 static int versatile_pci_host_init(PCIDevice *d)
 135 {
 136     pci_set_word(d->config + PCI_STATUS,
 137                  PCI_STATUS_66MHZ | PCI_STATUS_DEVSEL_MEDIUM);
 138     pci_set_byte(d->config + PCI_LATENCY_TIMER, 0x10);
 139     return 0;
 140 }
 141
 142 static PCIDeviceInfo versatile_pci_host_info = {
 143     .qdev.name = "versatile_pci_host",
 144     .qdev.size = sizeof(PCIDevice),
 145     .init      = versatile_pci_host_init,
 146     .vendor_id = PCI_VENDOR_ID_XILINX,
 147     /* Both boards have the same device ID.  Oh well.  */
 148     .device_id = PCI_DEVICE_ID_XILINX_XC2VP30,
 149     .class_id  = PCI_CLASS_PROCESSOR_CO,
 150 };
 151
 152 static void versatile_pci_register_devices(void)
 153 {
 154     sysbus_register_dev("versatile_pci", sizeof(PCIVPBState), pci_vpb_init);
 155     sysbus_register_dev("realview_pci", sizeof(PCIVPBState),
 156                         pci_realview_init);
 157     pci_qdev_register(&versatile_pci_host_info);
 158 }
 159
 160 device_init(versatile_pci_register_devices)