target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21 #include <linux/kvm_para.h>
  22
  23 #include "qemu-common.h"
  24 #include "sysemu.h"
  25 #include "kvm.h"
  26 #include "cpu.h"
  27 #include "gdbstub.h"
  28 #include "host-utils.h"
  29 #include "hw/pc.h"
  30 #include "hw/apic.h"
  31 #include "ioport.h"
  32
  33 //#define DEBUG_KVM
  34
  35 #ifdef DEBUG_KVM
  36 #define DPRINTF(fmt, ...) \
  37     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  38 #else
  39 #define DPRINTF(fmt, ...) \
  40     do { } while (0)
  41 #endif
  42
  43 #define MSR_KVM_WALL_CLOCK  0x11
  44 #define MSR_KVM_SYSTEM_TIME 0x12
  45
  46 #ifndef BUS_MCEERR_AR
  47 #define BUS_MCEERR_AR 4
  48 #endif
  49 #ifndef BUS_MCEERR_AO
  50 #define BUS_MCEERR_AO 5
  51 #endif
  52
  53 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  54     KVM_CAP_INFO(SET_TSS_ADDR),
  55     KVM_CAP_INFO(EXT_CPUID),
  56     KVM_CAP_INFO(MP_STATE),
  57     KVM_CAP_LAST_INFO
  58 };
  59
  60 static bool has_msr_star;
  61 static bool has_msr_hsave_pa;
  62 static bool has_msr_async_pf_en;
  63 static int lm_capable_kernel;
  64
  65 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  66 {
  67     struct kvm_cpuid2 *cpuid;
  68     int r, size;
  69
  70     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  71     cpuid = (struct kvm_cpuid2 *)g_malloc0(size);
  72     cpuid->nent = max;
  73     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  74     if (r == 0 && cpuid->nent >= max) {
  75         r = -E2BIG;
  76     }
  77     if (r < 0) {
  78         if (r == -E2BIG) {
  79             g_free(cpuid);
  80             return NULL;
  81         } else {
  82             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  83                     strerror(-r));
  84             exit(1);
  85         }
  86     }
  87     return cpuid;
  88 }
  89
  90 struct kvm_para_features {
  91     int cap;
  92     int feature;
  93 } para_features[] = {
  94     { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
  95     { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
  96     { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
  97     { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
  98     { -1, -1 }
  99 };
 100
 101 static int get_para_features(KVMState *s)
 102 {
 103     int i, features = 0;
 104
 105     for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 106         if (kvm_check_extension(s, para_features[i].cap)) {
 107             features |= (1 << para_features[i].feature);
 108         }
 109     }
 110
 111     return features;
 112 }
 113
 114
 115 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
 116                                       uint32_t index, int reg)
 117 {
 118     struct kvm_cpuid2 *cpuid;
 119     int i, max;
 120     uint32_t ret = 0;
 121     uint32_t cpuid_1_edx;
 122     int has_kvm_features = 0;
 123
 124     max = 1;
 125     while ((cpuid = try_get_cpuid(s, max)) == NULL) {
 126         max *= 2;
 127     }
 128
 129     for (i = 0; i < cpuid->nent; ++i) {
 130         if (cpuid->entries[i].function == function &&
 131             cpuid->entries[i].index == index) {
 132             if (cpuid->entries[i].function == KVM_CPUID_FEATURES) {
 133                 has_kvm_features = 1;
 134             }
 135             switch (reg) {
 136             case R_EAX:
 137                 ret = cpuid->entries[i].eax;
 138                 break;
 139             case R_EBX:
 140                 ret = cpuid->entries[i].ebx;
 141                 break;
 142             case R_ECX:
 143                 ret = cpuid->entries[i].ecx;
 144                 break;
 145             case R_EDX:
 146                 ret = cpuid->entries[i].edx;
 147                 switch (function) {
 148                 case 1:
 149                     /* KVM before 2.6.30 misreports the following features */
 150                     ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 151                     break;
 152                 case 0x80000001:
 153                     /* On Intel, kvm returns cpuid according to the Intel spec,
 154                      * so add missing bits according to the AMD spec:
 155                      */
 156                     cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 157                     ret |= cpuid_1_edx & 0x183f7ff;
 158                     break;
 159                 }
 160                 break;
 161             }
 162         }
 163     }
 164
 165     g_free(cpuid);
 166
 167     /* fallback for older kernels */
 168     if (!has_kvm_features && (function == KVM_CPUID_FEATURES)) {
 169         ret = get_para_features(s);
 170     }
 171
 172     return ret;
 173 }
 174
 175 typedef struct HWPoisonPage {
 176     ram_addr_t ram_addr;
 177     QLIST_ENTRY(HWPoisonPage) list;
 178 } HWPoisonPage;
 179
 180 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
 181     QLIST_HEAD_INITIALIZER(hwpoison_page_list);
 182
 183 static void kvm_unpoison_all(void *param)
 184 {
 185     HWPoisonPage *page, *next_page;
 186
 187     QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
 188         QLIST_REMOVE(page, list);
 189         qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
 190         g_free(page);
 191     }
 192 }
 193
 194 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
 195 {
 196     HWPoisonPage *page;
 197
 198     QLIST_FOREACH(page, &hwpoison_page_list, list) {
 199         if (page->ram_addr == ram_addr) {
 200             return;
 201         }
 202     }
 203     page = g_malloc(sizeof(HWPoisonPage));
 204     page->ram_addr = ram_addr;
 205     QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
 206 }
 207
 208 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 209                                      int *max_banks)
 210 {
 211     int r;
 212
 213     r = kvm_check_extension(s, KVM_CAP_MCE);
 214     if (r > 0) {
 215         *max_banks = r;
 216         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 217     }
 218     return -ENOSYS;
 219 }
 220
 221 static void kvm_mce_inject(CPUState *env, target_phys_addr_t paddr, int code)
 222 {
 223     uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
 224                       MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
 225     uint64_t mcg_status = MCG_STATUS_MCIP;
 226
 227     if (code == BUS_MCEERR_AR) {
 228         status |= MCI_STATUS_AR | 0x134;
 229         mcg_status |= MCG_STATUS_EIPV;
 230     } else {
 231         status |= 0xc0;
 232         mcg_status |= MCG_STATUS_RIPV;
 233     }
 234     cpu_x86_inject_mce(NULL, env, 9, status, mcg_status, paddr,
 235                        (MCM_ADDR_PHYS << 6) | 0xc,
 236                        cpu_x86_support_mca_broadcast(env) ?
 237                        MCE_INJECT_BROADCAST : 0);
 238 }
 239
 240 static void hardware_memory_error(void)
 241 {
 242     fprintf(stderr, "Hardware memory error!\n");
 243     exit(1);
 244 }
 245
 246 int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr)
 247 {
 248     ram_addr_t ram_addr;
 249     target_phys_addr_t paddr;
 250
 251     if ((env->mcg_cap & MCG_SER_P) && addr
 252         && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
 253         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 254             !kvm_physical_memory_addr_from_ram(env->kvm_state, ram_addr,
 255                                                &paddr)) {
 256             fprintf(stderr, "Hardware memory error for memory used by "
 257                     "QEMU itself instead of guest system!\n");
 258             /* Hope we are lucky for AO MCE */
 259             if (code == BUS_MCEERR_AO) {
 260                 return 0;
 261             } else {
 262                 hardware_memory_error();
 263             }
 264         }
 265         kvm_hwpoison_page_add(ram_addr);
 266         kvm_mce_inject(env, paddr, code);
 267     } else {
 268         if (code == BUS_MCEERR_AO) {
 269             return 0;
 270         } else if (code == BUS_MCEERR_AR) {
 271             hardware_memory_error();
 272         } else {
 273             return 1;
 274         }
 275     }
 276     return 0;
 277 }
 278
 279 int kvm_arch_on_sigbus(int code, void *addr)
 280 {
 281     if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
 282         ram_addr_t ram_addr;
 283         target_phys_addr_t paddr;
 284
 285         /* Hope we are lucky for AO MCE */
 286         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 287             !kvm_physical_memory_addr_from_ram(first_cpu->kvm_state, ram_addr,
 288                                                &paddr)) {
 289             fprintf(stderr, "Hardware memory error for memory used by "
 290                     "QEMU itself instead of guest system!: %p\n", addr);
 291             return 0;
 292         }
 293         kvm_hwpoison_page_add(ram_addr);
 294         kvm_mce_inject(first_cpu, paddr, code);
 295     } else {
 296         if (code == BUS_MCEERR_AO) {
 297             return 0;
 298         } else if (code == BUS_MCEERR_AR) {
 299             hardware_memory_error();
 300         } else {
 301             return 1;
 302         }
 303     }
 304     return 0;
 305 }
 306
 307 static int kvm_inject_mce_oldstyle(CPUState *env)
 308 {
 309     if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
 310         unsigned int bank, bank_num = env->mcg_cap & 0xff;
 311         struct kvm_x86_mce mce;
 312
 313         env->exception_injected = -1;
 314
 315         /*
 316          * There must be at least one bank in use if an MCE is pending.
 317          * Find it and use its values for the event injection.
 318          */
 319         for (bank = 0; bank < bank_num; bank++) {
 320             if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
 321                 break;
 322             }
 323         }
 324         assert(bank < bank_num);
 325
 326         mce.bank = bank;
 327         mce.status = env->mce_banks[bank * 4 + 1];
 328         mce.mcg_status = env->mcg_status;
 329         mce.addr = env->mce_banks[bank * 4 + 2];
 330         mce.misc = env->mce_banks[bank * 4 + 3];
 331
 332         return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, &mce);
 333     }
 334     return 0;
 335 }
 336
 337 static void cpu_update_state(void *opaque, int running, int reason)
 338 {
 339     CPUState *env = opaque;
 340
 341     if (running) {
 342         env->tsc_valid = false;
 343     }
 344 }
 345
 346 int kvm_arch_init_vcpu(CPUState *env)
 347 {
 348     struct {
 349         struct kvm_cpuid2 cpuid;
 350         struct kvm_cpuid_entry2 entries[100];
 351     } __attribute__((packed)) cpuid_data;
 352     KVMState *s = env->kvm_state;
 353     uint32_t limit, i, j, cpuid_i;
 354     uint32_t unused;
 355     struct kvm_cpuid_entry2 *c;
 356     uint32_t signature[3];
 357     int r;
 358
 359     env->cpuid_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 360
 361     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 362     env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
 363     env->cpuid_ext_features |= i;
 364
 365     env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(s, 0x80000001,
 366                                                              0, R_EDX);
 367     env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(s, 0x80000001,
 368                                                              0, R_ECX);
 369     env->cpuid_svm_features  &= kvm_arch_get_supported_cpuid(s, 0x8000000A,
 370                                                              0, R_EDX);
 371
 372     cpuid_i = 0;
 373
 374     /* Paravirtualization CPUIDs */
 375     memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 376     c = &cpuid_data.entries[cpuid_i++];
 377     memset(c, 0, sizeof(*c));
 378     c->function = KVM_CPUID_SIGNATURE;
 379     c->eax = 0;
 380     c->ebx = signature[0];
 381     c->ecx = signature[1];
 382     c->edx = signature[2];
 383
 384     c = &cpuid_data.entries[cpuid_i++];
 385     memset(c, 0, sizeof(*c));
 386     c->function = KVM_CPUID_FEATURES;
 387     c->eax = env->cpuid_kvm_features &
 388         kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
 389
 390     has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
 391
 392     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 393
 394     for (i = 0; i <= limit; i++) {
 395         c = &cpuid_data.entries[cpuid_i++];
 396
 397         switch (i) {
 398         case 2: {
 399             /* Keep reading function 2 till all the input is received */
 400             int times;
 401
 402             c->function = i;
 403             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 404                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 405             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 406             times = c->eax & 0xff;
 407
 408             for (j = 1; j < times; ++j) {
 409                 c = &cpuid_data.entries[cpuid_i++];
 410                 c->function = i;
 411                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 412                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 413             }
 414             break;
 415         }
 416         case 4:
 417         case 0xb:
 418         case 0xd:
 419             for (j = 0; ; j++) {
 420                 if (i == 0xd && j == 64) {
 421                     break;
 422                 }
 423                 c->function = i;
 424                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 425                 c->index = j;
 426                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 427
 428                 if (i == 4 && c->eax == 0) {
 429                     break;
 430                 }
 431                 if (i == 0xb && !(c->ecx & 0xff00)) {
 432                     break;
 433                 }
 434                 if (i == 0xd && c->eax == 0) {
 435                     continue;
 436                 }
 437                 c = &cpuid_data.entries[cpuid_i++];
 438             }
 439             break;
 440         default:
 441             c->function = i;
 442             c->flags = 0;
 443             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 444             break;
 445         }
 446     }
 447     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 448
 449     for (i = 0x80000000; i <= limit; i++) {
 450         c = &cpuid_data.entries[cpuid_i++];
 451
 452         c->function = i;
 453         c->flags = 0;
 454         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 455     }
 456
 457     /* Call Centaur's CPUID instructions they are supported. */
 458     if (env->cpuid_xlevel2 > 0) {
 459         env->cpuid_ext4_features &=
 460             kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
 461         cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
 462
 463         for (i = 0xC0000000; i <= limit; i++) {
 464             c = &cpuid_data.entries[cpuid_i++];
 465
 466             c->function = i;
 467             c->flags = 0;
 468             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 469         }
 470     }
 471
 472     cpuid_data.cpuid.nent = cpuid_i;
 473
 474     if (((env->cpuid_version >> 8)&0xF) >= 6
 475         && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
 476         && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
 477         uint64_t mcg_cap;
 478         int banks;
 479         int ret;
 480
 481         ret = kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks);
 482         if (ret < 0) {
 483             fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
 484             return ret;
 485         }
 486
 487         if (banks > MCE_BANKS_DEF) {
 488             banks = MCE_BANKS_DEF;
 489         }
 490         mcg_cap &= MCE_CAP_DEF;
 491         mcg_cap |= banks;
 492         ret = kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, &mcg_cap);
 493         if (ret < 0) {
 494             fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
 495             return ret;
 496         }
 497
 498         env->mcg_cap = mcg_cap;
 499     }
 500
 501     qemu_add_vm_change_state_handler(cpu_update_state, env);
 502
 503     r = kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 504     if (r)
 505             return r;
 506
 507     r = kvm_check_extension(env->kvm_state, KVM_CAP_TSC_CONTROL);
 508     if (r && env->tsc_khz) {
 509         r = kvm_vcpu_ioctl(env, KVM_SET_TSC_KHZ, env->tsc_khz);
 510         if (r < 0) {
 511             fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
 512             return r;
 513         }
 514     }
 515
 516     return 0;
 517 }
 518
 519 void kvm_arch_reset_vcpu(CPUState *env)
 520 {
 521     env->exception_injected = -1;
 522     env->interrupt_injected = -1;
 523     env->xcr0 = 1;
 524     if (kvm_irqchip_in_kernel()) {
 525         env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE :
 526                                           KVM_MP_STATE_UNINITIALIZED;
 527     } else {
 528         env->mp_state = KVM_MP_STATE_RUNNABLE;
 529     }
 530 }
 531
 532 static int kvm_get_supported_msrs(KVMState *s)
 533 {
 534     static int kvm_supported_msrs;
 535     int ret = 0;
 536
 537     /* first time */
 538     if (kvm_supported_msrs == 0) {
 539         struct kvm_msr_list msr_list, *kvm_msr_list;
 540
 541         kvm_supported_msrs = -1;
 542
 543         /* Obtain MSR list from KVM.  These are the MSRs that we must
 544          * save/restore */
 545         msr_list.nmsrs = 0;
 546         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
 547         if (ret < 0 && ret != -E2BIG) {
 548             return ret;
 549         }
 550         /* Old kernel modules had a bug and could write beyond the provided
 551            memory. Allocate at least a safe amount of 1K. */
 552         kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
 553                                               msr_list.nmsrs *
 554                                               sizeof(msr_list.indices[0])));
 555
 556         kvm_msr_list->nmsrs = msr_list.nmsrs;
 557         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 558         if (ret >= 0) {
 559             int i;
 560
 561             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 562                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 563                     has_msr_star = true;
 564                     continue;
 565                 }
 566                 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
 567                     has_msr_hsave_pa = true;
 568                     continue;
 569                 }
 570             }
 571         }
 572
 573         g_free(kvm_msr_list);
 574     }
 575
 576     return ret;
 577 }
 578
 579 int kvm_arch_init(KVMState *s)
 580 {
 581     uint64_t identity_base = 0xfffbc000;
 582     int ret;
 583     struct utsname utsname;
 584
 585     ret = kvm_get_supported_msrs(s);
 586     if (ret < 0) {
 587         return ret;
 588     }
 589
 590     uname(&utsname);
 591     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
 592
 593     /*
 594      * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
 595      * In order to use vm86 mode, an EPT identity map and a TSS  are needed.
 596      * Since these must be part of guest physical memory, we need to allocate
 597      * them, both by setting their start addresses in the kernel and by
 598      * creating a corresponding e820 entry. We need 4 pages before the BIOS.
 599      *
 600      * Older KVM versions may not support setting the identity map base. In
 601      * that case we need to stick with the default, i.e. a 256K maximum BIOS
 602      * size.
 603      */
 604     if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 605         /* Allows up to 16M BIOSes. */
 606         identity_base = 0xfeffc000;
 607
 608         ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
 609         if (ret < 0) {
 610             return ret;
 611         }
 612     }
 613
 614     /* Set TSS base one page after EPT identity map. */
 615     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
 616     if (ret < 0) {
 617         return ret;
 618     }
 619
 620     /* Tell fw_cfg to notify the BIOS to reserve the range. */
 621     ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
 622     if (ret < 0) {
 623         fprintf(stderr, "e820_add_entry() table is full\n");
 624         return ret;
 625     }
 626     qemu_register_reset(kvm_unpoison_all, NULL);
 627
 628     return 0;
 629 }
 630
 631 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 632 {
 633     lhs->selector = rhs->selector;
 634     lhs->base = rhs->base;
 635     lhs->limit = rhs->limit;
 636     lhs->type = 3;
 637     lhs->present = 1;
 638     lhs->dpl = 3;
 639     lhs->db = 0;
 640     lhs->s = 1;
 641     lhs->l = 0;
 642     lhs->g = 0;
 643     lhs->avl = 0;
 644     lhs->unusable = 0;
 645 }
 646
 647 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 648 {
 649     unsigned flags = rhs->flags;
 650     lhs->selector = rhs->selector;
 651     lhs->base = rhs->base;
 652     lhs->limit = rhs->limit;
 653     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 654     lhs->present = (flags & DESC_P_MASK) != 0;
 655     lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
 656     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 657     lhs->s = (flags & DESC_S_MASK) != 0;
 658     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 659     lhs->g = (flags & DESC_G_MASK) != 0;
 660     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 661     lhs->unusable = 0;
 662 }
 663
 664 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 665 {
 666     lhs->selector = rhs->selector;
 667     lhs->base = rhs->base;
 668     lhs->limit = rhs->limit;
 669     lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
 670                  (rhs->present * DESC_P_MASK) |
 671                  (rhs->dpl << DESC_DPL_SHIFT) |
 672                  (rhs->db << DESC_B_SHIFT) |
 673                  (rhs->s * DESC_S_MASK) |
 674                  (rhs->l << DESC_L_SHIFT) |
 675                  (rhs->g * DESC_G_MASK) |
 676                  (rhs->avl * DESC_AVL_MASK);
 677 }
 678
 679 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 680 {
 681     if (set) {
 682         *kvm_reg = *qemu_reg;
 683     } else {
 684         *qemu_reg = *kvm_reg;
 685     }
 686 }
 687
 688 static int kvm_getput_regs(CPUState *env, int set)
 689 {
 690     struct kvm_regs regs;
 691     int ret = 0;
 692
 693     if (!set) {
 694         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 695         if (ret < 0) {
 696             return ret;
 697         }
 698     }
 699
 700     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 701     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 702     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 703     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 704     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 705     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 706     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 707     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 708 #ifdef TARGET_X86_64
 709     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 710     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 711     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 712     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 713     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 714     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 715     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 716     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 717 #endif
 718
 719     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 720     kvm_getput_reg(&regs.rip, &env->eip, set);
 721
 722     if (set) {
 723         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 724     }
 725
 726     return ret;
 727 }
 728
 729 static int kvm_put_fpu(CPUState *env)
 730 {
 731     struct kvm_fpu fpu;
 732     int i;
 733
 734     memset(&fpu, 0, sizeof fpu);
 735     fpu.fsw = env->fpus & ~(7 << 11);
 736     fpu.fsw |= (env->fpstt & 7) << 11;
 737     fpu.fcw = env->fpuc;
 738     fpu.last_opcode = env->fpop;
 739     fpu.last_ip = env->fpip;
 740     fpu.last_dp = env->fpdp;
 741     for (i = 0; i < 8; ++i) {
 742         fpu.ftwx |= (!env->fptags[i]) << i;
 743     }
 744     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 745     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 746     fpu.mxcsr = env->mxcsr;
 747
 748     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 749 }
 750
 751 #define XSAVE_CWD_RIP     2
 752 #define XSAVE_CWD_RDP     4
 753 #define XSAVE_MXCSR       6
 754 #define XSAVE_ST_SPACE    8
 755 #define XSAVE_XMM_SPACE   40
 756 #define XSAVE_XSTATE_BV   128
 757 #define XSAVE_YMMH_SPACE  144
 758
 759 static int kvm_put_xsave(CPUState *env)
 760 {
 761     int i, r;
 762     struct kvm_xsave* xsave;
 763     uint16_t cwd, swd, twd;
 764
 765     if (!kvm_has_xsave()) {
 766         return kvm_put_fpu(env);
 767     }
 768
 769     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 770     memset(xsave, 0, sizeof(struct kvm_xsave));
 771     cwd = swd = twd = 0;
 772     swd = env->fpus & ~(7 << 11);
 773     swd |= (env->fpstt & 7) << 11;
 774     cwd = env->fpuc;
 775     for (i = 0; i < 8; ++i) {
 776         twd |= (!env->fptags[i]) << i;
 777     }
 778     xsave->region[0] = (uint32_t)(swd << 16) + cwd;
 779     xsave->region[1] = (uint32_t)(env->fpop << 16) + twd;
 780     memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
 781     memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
 782     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 783             sizeof env->fpregs);
 784     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 785             sizeof env->xmm_regs);
 786     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 787     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 788     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 789             sizeof env->ymmh_regs);
 790     r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
 791     g_free(xsave);
 792     return r;
 793 }
 794
 795 static int kvm_put_xcrs(CPUState *env)
 796 {
 797     struct kvm_xcrs xcrs;
 798
 799     if (!kvm_has_xcrs()) {
 800         return 0;
 801     }
 802
 803     xcrs.nr_xcrs = 1;
 804     xcrs.flags = 0;
 805     xcrs.xcrs[0].xcr = 0;
 806     xcrs.xcrs[0].value = env->xcr0;
 807     return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
 808 }
 809
 810 static int kvm_put_sregs(CPUState *env)
 811 {
 812     struct kvm_sregs sregs;
 813
 814     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 815     if (env->interrupt_injected >= 0) {
 816         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 817                 (uint64_t)1 << (env->interrupt_injected % 64);
 818     }
 819
 820     if ((env->eflags & VM_MASK)) {
 821         set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 822         set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 823         set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 824         set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 825         set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 826         set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 827     } else {
 828         set_seg(&sregs.cs, &env->segs[R_CS]);
 829         set_seg(&sregs.ds, &env->segs[R_DS]);
 830         set_seg(&sregs.es, &env->segs[R_ES]);
 831         set_seg(&sregs.fs, &env->segs[R_FS]);
 832         set_seg(&sregs.gs, &env->segs[R_GS]);
 833         set_seg(&sregs.ss, &env->segs[R_SS]);
 834     }
 835
 836     set_seg(&sregs.tr, &env->tr);
 837     set_seg(&sregs.ldt, &env->ldt);
 838
 839     sregs.idt.limit = env->idt.limit;
 840     sregs.idt.base = env->idt.base;
 841     sregs.gdt.limit = env->gdt.limit;
 842     sregs.gdt.base = env->gdt.base;
 843
 844     sregs.cr0 = env->cr[0];
 845     sregs.cr2 = env->cr[2];
 846     sregs.cr3 = env->cr[3];
 847     sregs.cr4 = env->cr[4];
 848
 849     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
 850     sregs.apic_base = cpu_get_apic_base(env->apic_state);
 851
 852     sregs.efer = env->efer;
 853
 854     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 855 }
 856
 857 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 858                               uint32_t index, uint64_t value)
 859 {
 860     entry->index = index;
 861     entry->data = value;
 862 }
 863
 864 static int kvm_put_msrs(CPUState *env, int level)
 865 {
 866     struct {
 867         struct kvm_msrs info;
 868         struct kvm_msr_entry entries[100];
 869     } msr_data;
 870     struct kvm_msr_entry *msrs = msr_data.entries;
 871     int n = 0;
 872
 873     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 874     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 875     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 876     kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
 877     if (has_msr_star) {
 878         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 879     }
 880     if (has_msr_hsave_pa) {
 881         kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 882     }
 883 #ifdef TARGET_X86_64
 884     if (lm_capable_kernel) {
 885         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 886         kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 887         kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 888         kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 889     }
 890 #endif
 891     if (level == KVM_PUT_FULL_STATE) {
 892         /*
 893          * KVM is yet unable to synchronize TSC values of multiple VCPUs on
 894          * writeback. Until this is fixed, we only write the offset to SMP
 895          * guests after migration, desynchronizing the VCPUs, but avoiding
 896          * huge jump-backs that would occur without any writeback at all.
 897          */
 898         if (smp_cpus == 1 || env->tsc != 0) {
 899             kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 900         }
 901     }
 902     /*
 903      * The following paravirtual MSRs have side effects on the guest or are
 904      * too heavy for normal writeback. Limit them to reset or full state
 905      * updates.
 906      */
 907     if (level >= KVM_PUT_RESET_STATE) {
 908         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
 909                           env->system_time_msr);
 910         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
 911         if (has_msr_async_pf_en) {
 912             kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
 913                               env->async_pf_en_msr);
 914         }
 915     }
 916     if (env->mcg_cap) {
 917         int i;
 918
 919         kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
 920         kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
 921         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
 922             kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
 923         }
 924     }
 925
 926     msr_data.info.nmsrs = n;
 927
 928     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 929
 930 }
 931
 932
 933 static int kvm_get_fpu(CPUState *env)
 934 {
 935     struct kvm_fpu fpu;
 936     int i, ret;
 937
 938     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 939     if (ret < 0) {
 940         return ret;
 941     }
 942
 943     env->fpstt = (fpu.fsw >> 11) & 7;
 944     env->fpus = fpu.fsw;
 945     env->fpuc = fpu.fcw;
 946     env->fpop = fpu.last_opcode;
 947     env->fpip = fpu.last_ip;
 948     env->fpdp = fpu.last_dp;
 949     for (i = 0; i < 8; ++i) {
 950         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 951     }
 952     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 953     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 954     env->mxcsr = fpu.mxcsr;
 955
 956     return 0;
 957 }
 958
 959 static int kvm_get_xsave(CPUState *env)
 960 {
 961     struct kvm_xsave* xsave;
 962     int ret, i;
 963     uint16_t cwd, swd, twd;
 964
 965     if (!kvm_has_xsave()) {
 966         return kvm_get_fpu(env);
 967     }
 968
 969     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 970     ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
 971     if (ret < 0) {
 972         g_free(xsave);
 973         return ret;
 974     }
 975
 976     cwd = (uint16_t)xsave->region[0];
 977     swd = (uint16_t)(xsave->region[0] >> 16);
 978     twd = (uint16_t)xsave->region[1];
 979     env->fpop = (uint16_t)(xsave->region[1] >> 16);
 980     env->fpstt = (swd >> 11) & 7;
 981     env->fpus = swd;
 982     env->fpuc = cwd;
 983     for (i = 0; i < 8; ++i) {
 984         env->fptags[i] = !((twd >> i) & 1);
 985     }
 986     memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
 987     memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
 988     env->mxcsr = xsave->region[XSAVE_MXCSR];
 989     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
 990             sizeof env->fpregs);
 991     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
 992             sizeof env->xmm_regs);
 993     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
 994     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
 995             sizeof env->ymmh_regs);
 996     g_free(xsave);
 997     return 0;
 998 }
 999
1000 static int kvm_get_xcrs(CPUState *env)
1001 {
1002     int i, ret;
1003     struct kvm_xcrs xcrs;
1004
1005     if (!kvm_has_xcrs()) {
1006         return 0;
1007     }
1008
1009     ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
1010     if (ret < 0) {
1011         return ret;
1012     }
1013
1014     for (i = 0; i < xcrs.nr_xcrs; i++) {
1015         /* Only support xcr0 now */
1016         if (xcrs.xcrs[0].xcr == 0) {
1017             env->xcr0 = xcrs.xcrs[0].value;
1018             break;
1019         }
1020     }
1021     return 0;
1022 }
1023
1024 static int kvm_get_sregs(CPUState *env)
1025 {
1026     struct kvm_sregs sregs;
1027     uint32_t hflags;
1028     int bit, i, ret;
1029
1030     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
1031     if (ret < 0) {
1032         return ret;
1033     }
1034
1035     /* There can only be one pending IRQ set in the bitmap at a time, so try
1036        to find it and save its number instead (-1 for none). */
1037     env->interrupt_injected = -1;
1038     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1039         if (sregs.interrupt_bitmap[i]) {
1040             bit = ctz64(sregs.interrupt_bitmap[i]);
1041             env->interrupt_injected = i * 64 + bit;
1042             break;
1043         }
1044     }
1045
1046     get_seg(&env->segs[R_CS], &sregs.cs);
1047     get_seg(&env->segs[R_DS], &sregs.ds);
1048     get_seg(&env->segs[R_ES], &sregs.es);
1049     get_seg(&env->segs[R_FS], &sregs.fs);
1050     get_seg(&env->segs[R_GS], &sregs.gs);
1051     get_seg(&env->segs[R_SS], &sregs.ss);
1052
1053     get_seg(&env->tr, &sregs.tr);
1054     get_seg(&env->ldt, &sregs.ldt);
1055
1056     env->idt.limit = sregs.idt.limit;
1057     env->idt.base = sregs.idt.base;
1058     env->gdt.limit = sregs.gdt.limit;
1059     env->gdt.base = sregs.gdt.base;
1060
1061     env->cr[0] = sregs.cr0;
1062     env->cr[2] = sregs.cr2;
1063     env->cr[3] = sregs.cr3;
1064     env->cr[4] = sregs.cr4;
1065
1066     cpu_set_apic_base(env->apic_state, sregs.apic_base);
1067
1068     env->efer = sregs.efer;
1069     //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
1070
1071 #define HFLAG_COPY_MASK \
1072     ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1073        HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1074        HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1075        HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1076
1077     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1078     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1079     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1080                 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1081     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1082     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1083                 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1084
1085     if (env->efer & MSR_EFER_LMA) {
1086         hflags |= HF_LMA_MASK;
1087     }
1088
1089     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1090         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1091     } else {
1092         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1093                     (DESC_B_SHIFT - HF_CS32_SHIFT);
1094         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1095                     (DESC_B_SHIFT - HF_SS32_SHIFT);
1096         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1097             !(hflags & HF_CS32_MASK)) {
1098             hflags |= HF_ADDSEG_MASK;
1099         } else {
1100             hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1101                         env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1102         }
1103     }
1104     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1105
1106     return 0;
1107 }
1108
1109 static int kvm_get_msrs(CPUState *env)
1110 {
1111     struct {
1112         struct kvm_msrs info;
1113         struct kvm_msr_entry entries[100];
1114     } msr_data;
1115     struct kvm_msr_entry *msrs = msr_data.entries;
1116     int ret, i, n;
1117
1118     n = 0;
1119     msrs[n++].index = MSR_IA32_SYSENTER_CS;
1120     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1121     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1122     msrs[n++].index = MSR_PAT;
1123     if (has_msr_star) {
1124         msrs[n++].index = MSR_STAR;
1125     }
1126     if (has_msr_hsave_pa) {
1127         msrs[n++].index = MSR_VM_HSAVE_PA;
1128     }
1129
1130     if (!env->tsc_valid) {
1131         msrs[n++].index = MSR_IA32_TSC;
1132         env->tsc_valid = !vm_running;
1133     }
1134
1135 #ifdef TARGET_X86_64
1136     if (lm_capable_kernel) {
1137         msrs[n++].index = MSR_CSTAR;
1138         msrs[n++].index = MSR_KERNELGSBASE;
1139         msrs[n++].index = MSR_FMASK;
1140         msrs[n++].index = MSR_LSTAR;
1141     }
1142 #endif
1143     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1144     msrs[n++].index = MSR_KVM_WALL_CLOCK;
1145     if (has_msr_async_pf_en) {
1146         msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1147     }
1148
1149     if (env->mcg_cap) {
1150         msrs[n++].index = MSR_MCG_STATUS;
1151         msrs[n++].index = MSR_MCG_CTL;
1152         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1153             msrs[n++].index = MSR_MC0_CTL + i;
1154         }
1155     }
1156
1157     msr_data.info.nmsrs = n;
1158     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
1159     if (ret < 0) {
1160         return ret;
1161     }
1162
1163     for (i = 0; i < ret; i++) {
1164         switch (msrs[i].index) {
1165         case MSR_IA32_SYSENTER_CS:
1166             env->sysenter_cs = msrs[i].data;
1167             break;
1168         case MSR_IA32_SYSENTER_ESP:
1169             env->sysenter_esp = msrs[i].data;
1170             break;
1171         case MSR_IA32_SYSENTER_EIP:
1172             env->sysenter_eip = msrs[i].data;
1173             break;
1174         case MSR_PAT:
1175             env->pat = msrs[i].data;
1176             break;
1177         case MSR_STAR:
1178             env->star = msrs[i].data;
1179             break;
1180 #ifdef TARGET_X86_64
1181         case MSR_CSTAR:
1182             env->cstar = msrs[i].data;
1183             break;
1184         case MSR_KERNELGSBASE:
1185             env->kernelgsbase = msrs[i].data;
1186             break;
1187         case MSR_FMASK:
1188             env->fmask = msrs[i].data;
1189             break;
1190         case MSR_LSTAR:
1191             env->lstar = msrs[i].data;
1192             break;
1193 #endif
1194         case MSR_IA32_TSC:
1195             env->tsc = msrs[i].data;
1196             break;
1197         case MSR_VM_HSAVE_PA:
1198             env->vm_hsave = msrs[i].data;
1199             break;
1200         case MSR_KVM_SYSTEM_TIME:
1201             env->system_time_msr = msrs[i].data;
1202             break;
1203         case MSR_KVM_WALL_CLOCK:
1204             env->wall_clock_msr = msrs[i].data;
1205             break;
1206         case MSR_MCG_STATUS:
1207             env->mcg_status = msrs[i].data;
1208             break;
1209         case MSR_MCG_CTL:
1210             env->mcg_ctl = msrs[i].data;
1211             break;
1212         default:
1213             if (msrs[i].index >= MSR_MC0_CTL &&
1214                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1215                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1216             }
1217             break;
1218         case MSR_KVM_ASYNC_PF_EN:
1219             env->async_pf_en_msr = msrs[i].data;
1220             break;
1221         }
1222     }
1223
1224     return 0;
1225 }
1226
1227 static int kvm_put_mp_state(CPUState *env)
1228 {
1229     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1230
1231     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
1232 }
1233
1234 static int kvm_get_mp_state(CPUState *env)
1235 {
1236     struct kvm_mp_state mp_state;
1237     int ret;
1238
1239     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
1240     if (ret < 0) {
1241         return ret;
1242     }
1243     env->mp_state = mp_state.mp_state;
1244     if (kvm_irqchip_in_kernel()) {
1245         env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1246     }
1247     return 0;
1248 }
1249
1250 static int kvm_put_vcpu_events(CPUState *env, int level)
1251 {
1252     struct kvm_vcpu_events events;
1253
1254     if (!kvm_has_vcpu_events()) {
1255         return 0;
1256     }
1257
1258     events.exception.injected = (env->exception_injected >= 0);
1259     events.exception.nr = env->exception_injected;
1260     events.exception.has_error_code = env->has_error_code;
1261     events.exception.error_code = env->error_code;
1262
1263     events.interrupt.injected = (env->interrupt_injected >= 0);
1264     events.interrupt.nr = env->interrupt_injected;
1265     events.interrupt.soft = env->soft_interrupt;
1266
1267     events.nmi.injected = env->nmi_injected;
1268     events.nmi.pending = env->nmi_pending;
1269     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1270
1271     events.sipi_vector = env->sipi_vector;
1272
1273     events.flags = 0;
1274     if (level >= KVM_PUT_RESET_STATE) {
1275         events.flags |=
1276             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1277     }
1278
1279     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
1280 }
1281
1282 static int kvm_get_vcpu_events(CPUState *env)
1283 {
1284     struct kvm_vcpu_events events;
1285     int ret;
1286
1287     if (!kvm_has_vcpu_events()) {
1288         return 0;
1289     }
1290
1291     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1292     if (ret < 0) {
1293        return ret;
1294     }
1295     env->exception_injected =
1296        events.exception.injected ? events.exception.nr : -1;
1297     env->has_error_code = events.exception.has_error_code;
1298     env->error_code = events.exception.error_code;
1299
1300     env->interrupt_injected =
1301         events.interrupt.injected ? events.interrupt.nr : -1;
1302     env->soft_interrupt = events.interrupt.soft;
1303
1304     env->nmi_injected = events.nmi.injected;
1305     env->nmi_pending = events.nmi.pending;
1306     if (events.nmi.masked) {
1307         env->hflags2 |= HF2_NMI_MASK;
1308     } else {
1309         env->hflags2 &= ~HF2_NMI_MASK;
1310     }
1311
1312     env->sipi_vector = events.sipi_vector;
1313
1314     return 0;
1315 }
1316
1317 static int kvm_guest_debug_workarounds(CPUState *env)
1318 {
1319     int ret = 0;
1320     unsigned long reinject_trap = 0;
1321
1322     if (!kvm_has_vcpu_events()) {
1323         if (env->exception_injected == 1) {
1324             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1325         } else if (env->exception_injected == 3) {
1326             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1327         }
1328         env->exception_injected = -1;
1329     }
1330
1331     /*
1332      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1333      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1334      * by updating the debug state once again if single-stepping is on.
1335      * Another reason to call kvm_update_guest_debug here is a pending debug
1336      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1337      * reinject them via SET_GUEST_DEBUG.
1338      */
1339     if (reinject_trap ||
1340         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1341         ret = kvm_update_guest_debug(env, reinject_trap);
1342     }
1343     return ret;
1344 }
1345
1346 static int kvm_put_debugregs(CPUState *env)
1347 {
1348     struct kvm_debugregs dbgregs;
1349     int i;
1350
1351     if (!kvm_has_debugregs()) {
1352         return 0;
1353     }
1354
1355     for (i = 0; i < 4; i++) {
1356         dbgregs.db[i] = env->dr[i];
1357     }
1358     dbgregs.dr6 = env->dr[6];
1359     dbgregs.dr7 = env->dr[7];
1360     dbgregs.flags = 0;
1361
1362     return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1363 }
1364
1365 static int kvm_get_debugregs(CPUState *env)
1366 {
1367     struct kvm_debugregs dbgregs;
1368     int i, ret;
1369
1370     if (!kvm_has_debugregs()) {
1371         return 0;
1372     }
1373
1374     ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1375     if (ret < 0) {
1376         return ret;
1377     }
1378     for (i = 0; i < 4; i++) {
1379         env->dr[i] = dbgregs.db[i];
1380     }
1381     env->dr[4] = env->dr[6] = dbgregs.dr6;
1382     env->dr[5] = env->dr[7] = dbgregs.dr7;
1383
1384     return 0;
1385 }
1386
1387 int kvm_arch_put_registers(CPUState *env, int level)
1388 {
1389     int ret;
1390
1391     assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1392
1393     ret = kvm_getput_regs(env, 1);
1394     if (ret < 0) {
1395         return ret;
1396     }
1397     ret = kvm_put_xsave(env);
1398     if (ret < 0) {
1399         return ret;
1400     }
1401     ret = kvm_put_xcrs(env);
1402     if (ret < 0) {
1403         return ret;
1404     }
1405     ret = kvm_put_sregs(env);
1406     if (ret < 0) {
1407         return ret;
1408     }
1409     /* must be before kvm_put_msrs */
1410     ret = kvm_inject_mce_oldstyle(env);
1411     if (ret < 0) {
1412         return ret;
1413     }
1414     ret = kvm_put_msrs(env, level);
1415     if (ret < 0) {
1416         return ret;
1417     }
1418     if (level >= KVM_PUT_RESET_STATE) {
1419         ret = kvm_put_mp_state(env);
1420         if (ret < 0) {
1421             return ret;
1422         }
1423     }
1424     ret = kvm_put_vcpu_events(env, level);
1425     if (ret < 0) {
1426         return ret;
1427     }
1428     ret = kvm_put_debugregs(env);
1429     if (ret < 0) {
1430         return ret;
1431     }
1432     /* must be last */
1433     ret = kvm_guest_debug_workarounds(env);
1434     if (ret < 0) {
1435         return ret;
1436     }
1437     return 0;
1438 }
1439
1440 int kvm_arch_get_registers(CPUState *env)
1441 {
1442     int ret;
1443
1444     assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1445
1446     ret = kvm_getput_regs(env, 0);
1447     if (ret < 0) {
1448         return ret;
1449     }
1450     ret = kvm_get_xsave(env);
1451     if (ret < 0) {
1452         return ret;
1453     }
1454     ret = kvm_get_xcrs(env);
1455     if (ret < 0) {
1456         return ret;
1457     }
1458     ret = kvm_get_sregs(env);
1459     if (ret < 0) {
1460         return ret;
1461     }
1462     ret = kvm_get_msrs(env);
1463     if (ret < 0) {
1464         return ret;
1465     }
1466     ret = kvm_get_mp_state(env);
1467     if (ret < 0) {
1468         return ret;
1469     }
1470     ret = kvm_get_vcpu_events(env);
1471     if (ret < 0) {
1472         return ret;
1473     }
1474     ret = kvm_get_debugregs(env);
1475     if (ret < 0) {
1476         return ret;
1477     }
1478     return 0;
1479 }
1480
1481 void kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1482 {
1483     int ret;
1484
1485     /* Inject NMI */
1486     if (env->interrupt_request & CPU_INTERRUPT_NMI) {
1487         env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1488         DPRINTF("injected NMI\n");
1489         ret = kvm_vcpu_ioctl(env, KVM_NMI);
1490         if (ret < 0) {
1491             fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
1492                     strerror(-ret));
1493         }
1494     }
1495
1496     if (!kvm_irqchip_in_kernel()) {
1497         /* Force the VCPU out of its inner loop to process the INIT request */
1498         if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1499             env->exit_request = 1;
1500         }
1501
1502         /* Try to inject an interrupt if the guest can accept it */
1503         if (run->ready_for_interrupt_injection &&
1504             (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1505             (env->eflags & IF_MASK)) {
1506             int irq;
1507
1508             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1509             irq = cpu_get_pic_interrupt(env);
1510             if (irq >= 0) {
1511                 struct kvm_interrupt intr;
1512
1513                 intr.irq = irq;
1514                 DPRINTF("injected interrupt %d\n", irq);
1515                 ret = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1516                 if (ret < 0) {
1517                     fprintf(stderr,
1518                             "KVM: injection failed, interrupt lost (%s)\n",
1519                             strerror(-ret));
1520                 }
1521             }
1522         }
1523
1524         /* If we have an interrupt but the guest is not ready to receive an
1525          * interrupt, request an interrupt window exit.  This will
1526          * cause a return to userspace as soon as the guest is ready to
1527          * receive interrupts. */
1528         if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
1529             run->request_interrupt_window = 1;
1530         } else {
1531             run->request_interrupt_window = 0;
1532         }
1533
1534         DPRINTF("setting tpr\n");
1535         run->cr8 = cpu_get_apic_tpr(env->apic_state);
1536     }
1537 }
1538
1539 void kvm_arch_post_run(CPUState *env, struct kvm_run *run)
1540 {
1541     if (run->if_flag) {
1542         env->eflags |= IF_MASK;
1543     } else {
1544         env->eflags &= ~IF_MASK;
1545     }
1546     cpu_set_apic_tpr(env->apic_state, run->cr8);
1547     cpu_set_apic_base(env->apic_state, run->apic_base);
1548 }
1549
1550 int kvm_arch_process_async_events(CPUState *env)
1551 {
1552     if (env->interrupt_request & CPU_INTERRUPT_MCE) {
1553         /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
1554         assert(env->mcg_cap);
1555
1556         env->interrupt_request &= ~CPU_INTERRUPT_MCE;
1557
1558         kvm_cpu_synchronize_state(env);
1559
1560         if (env->exception_injected == EXCP08_DBLE) {
1561             /* this means triple fault */
1562             qemu_system_reset_request();
1563             env->exit_request = 1;
1564             return 0;
1565         }
1566         env->exception_injected = EXCP12_MCHK;
1567         env->has_error_code = 0;
1568
1569         env->halted = 0;
1570         if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
1571             env->mp_state = KVM_MP_STATE_RUNNABLE;
1572         }
1573     }
1574
1575     if (kvm_irqchip_in_kernel()) {
1576         return 0;
1577     }
1578
1579     if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1580          (env->eflags & IF_MASK)) ||
1581         (env->interrupt_request & CPU_INTERRUPT_NMI)) {
1582         env->halted = 0;
1583     }
1584     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1585         kvm_cpu_synchronize_state(env);
1586         do_cpu_init(env);
1587     }
1588     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1589         kvm_cpu_synchronize_state(env);
1590         do_cpu_sipi(env);
1591     }
1592
1593     return env->halted;
1594 }
1595
1596 static int kvm_handle_halt(CPUState *env)
1597 {
1598     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1599           (env->eflags & IF_MASK)) &&
1600         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1601         env->halted = 1;
1602         return EXCP_HLT;
1603     }
1604
1605     return 0;
1606 }
1607
1608 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1609 {
1610     static const uint8_t int3 = 0xcc;
1611
1612     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1613         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
1614         return -EINVAL;
1615     }
1616     return 0;
1617 }
1618
1619 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1620 {
1621     uint8_t int3;
1622
1623     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1624         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
1625         return -EINVAL;
1626     }
1627     return 0;
1628 }
1629
1630 static struct {
1631     target_ulong addr;
1632     int len;
1633     int type;
1634 } hw_breakpoint[4];
1635
1636 static int nb_hw_breakpoint;
1637
1638 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1639 {
1640     int n;
1641
1642     for (n = 0; n < nb_hw_breakpoint; n++) {
1643         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1644             (hw_breakpoint[n].len == len || len == -1)) {
1645             return n;
1646         }
1647     }
1648     return -1;
1649 }
1650
1651 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1652                                   target_ulong len, int type)
1653 {
1654     switch (type) {
1655     case GDB_BREAKPOINT_HW:
1656         len = 1;
1657         break;
1658     case GDB_WATCHPOINT_WRITE:
1659     case GDB_WATCHPOINT_ACCESS:
1660         switch (len) {
1661         case 1:
1662             break;
1663         case 2:
1664         case 4:
1665         case 8:
1666             if (addr & (len - 1)) {
1667                 return -EINVAL;
1668             }
1669             break;
1670         default:
1671             return -EINVAL;
1672         }
1673         break;
1674     default:
1675         return -ENOSYS;
1676     }
1677
1678     if (nb_hw_breakpoint == 4) {
1679         return -ENOBUFS;
1680     }
1681     if (find_hw_breakpoint(addr, len, type) >= 0) {
1682         return -EEXIST;
1683     }
1684     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1685     hw_breakpoint[nb_hw_breakpoint].len = len;
1686     hw_breakpoint[nb_hw_breakpoint].type = type;
1687     nb_hw_breakpoint++;
1688
1689     return 0;
1690 }
1691
1692 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1693                                   target_ulong len, int type)
1694 {
1695     int n;
1696
1697     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1698     if (n < 0) {
1699         return -ENOENT;
1700     }
1701     nb_hw_breakpoint--;
1702     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1703
1704     return 0;
1705 }
1706
1707 void kvm_arch_remove_all_hw_breakpoints(void)
1708 {
1709     nb_hw_breakpoint = 0;
1710 }
1711
1712 static CPUWatchpoint hw_watchpoint;
1713
1714 static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info)
1715 {
1716     int ret = 0;
1717     int n;
1718
1719     if (arch_info->exception == 1) {
1720         if (arch_info->dr6 & (1 << 14)) {
1721             if (cpu_single_env->singlestep_enabled) {
1722                 ret = EXCP_DEBUG;
1723             }
1724         } else {
1725             for (n = 0; n < 4; n++) {
1726                 if (arch_info->dr6 & (1 << n)) {
1727                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1728                     case 0x0:
1729                         ret = EXCP_DEBUG;
1730                         break;
1731                     case 0x1:
1732                         ret = EXCP_DEBUG;
1733                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1734                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1735                         hw_watchpoint.flags = BP_MEM_WRITE;
1736                         break;
1737                     case 0x3:
1738                         ret = EXCP_DEBUG;
1739                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1740                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1741                         hw_watchpoint.flags = BP_MEM_ACCESS;
1742                         break;
1743                     }
1744                 }
1745             }
1746         }
1747     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) {
1748         ret = EXCP_DEBUG;
1749     }
1750     if (ret == 0) {
1751         cpu_synchronize_state(cpu_single_env);
1752         assert(cpu_single_env->exception_injected == -1);
1753
1754         /* pass to guest */
1755         cpu_single_env->exception_injected = arch_info->exception;
1756         cpu_single_env->has_error_code = 0;
1757     }
1758
1759     return ret;
1760 }
1761
1762 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1763 {
1764     const uint8_t type_code[] = {
1765         [GDB_BREAKPOINT_HW] = 0x0,
1766         [GDB_WATCHPOINT_WRITE] = 0x1,
1767         [GDB_WATCHPOINT_ACCESS] = 0x3
1768     };
1769     const uint8_t len_code[] = {
1770         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1771     };
1772     int n;
1773
1774     if (kvm_sw_breakpoints_active(env)) {
1775         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1776     }
1777     if (nb_hw_breakpoint > 0) {
1778         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1779         dbg->arch.debugreg[7] = 0x0600;
1780         for (n = 0; n < nb_hw_breakpoint; n++) {
1781             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1782             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1783                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1784                 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
1785         }
1786     }
1787 }
1788
1789 static bool host_supports_vmx(void)
1790 {
1791     uint32_t ecx, unused;
1792
1793     host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
1794     return ecx & CPUID_EXT_VMX;
1795 }
1796
1797 #define VMX_INVALID_GUEST_STATE 0x80000021
1798
1799 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
1800 {
1801     uint64_t code;
1802     int ret;
1803
1804     switch (run->exit_reason) {
1805     case KVM_EXIT_HLT:
1806         DPRINTF("handle_hlt\n");
1807         ret = kvm_handle_halt(env);
1808         break;
1809     case KVM_EXIT_SET_TPR:
1810         ret = 0;
1811         break;
1812     case KVM_EXIT_FAIL_ENTRY:
1813         code = run->fail_entry.hardware_entry_failure_reason;
1814         fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
1815                 code);
1816         if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
1817             fprintf(stderr,
1818                     "\nIf you're runnning a guest on an Intel machine without "
1819                         "unrestricted mode\n"
1820                     "support, the failure can be most likely due to the guest "
1821                         "entering an invalid\n"
1822                     "state for Intel VT. For example, the guest maybe running "
1823                         "in big real mode\n"
1824                     "which is not supported on less recent Intel processors."
1825                         "\n\n");
1826         }
1827         ret = -1;
1828         break;
1829     case KVM_EXIT_EXCEPTION:
1830         fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
1831                 run->ex.exception, run->ex.error_code);
1832         ret = -1;
1833         break;
1834     case KVM_EXIT_DEBUG:
1835         DPRINTF("kvm_exit_debug\n");
1836         ret = kvm_handle_debug(&run->debug.arch);
1837         break;
1838     default:
1839         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
1840         ret = -1;
1841         break;
1842     }
1843
1844     return ret;
1845 }
1846
1847 bool kvm_arch_stop_on_emulation_error(CPUState *env)
1848 {
1849     return !(env->cr[0] & CR0_PE_MASK) ||
1850            ((env->segs[R_CS].selector  & 3) != 3);
1851 }