hw/i8259.c

   1 /*
   2  * QEMU 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "isa.h"
  27 #include "monitor.h"
  28 #include "qemu-timer.h"
  29
  30 /* debug PIC */
  31 //#define DEBUG_PIC
  32
  33 //#define DEBUG_IRQ_LATENCY
  34 //#define DEBUG_IRQ_COUNT
  35
  36 typedef struct PicState {
  37     uint8_t last_irr; /* edge detection */
  38     uint8_t irr; /* interrupt request register */
  39     uint8_t imr; /* interrupt mask register */
  40     uint8_t isr; /* interrupt service register */
  41     uint8_t priority_add; /* highest irq priority */
  42     uint8_t irq_base;
  43     uint8_t read_reg_select;
  44     uint8_t poll;
  45     uint8_t special_mask;
  46     uint8_t init_state;
  47     uint8_t auto_eoi;
  48     uint8_t rotate_on_auto_eoi;
  49     uint8_t special_fully_nested_mode;
  50     uint8_t init4; /* true if 4 byte init */
  51     uint8_t single_mode; /* true if slave pic is not initialized */
  52     uint8_t elcr; /* PIIX edge/trigger selection*/
  53     uint8_t elcr_mask;
  54     PicState2 *pics_state;
  55 } PicState;
  56
  57 struct PicState2 {
  58     /* 0 is master pic, 1 is slave pic */
  59     /* XXX: better separation between the two pics */
  60     PicState pics[2];
  61     qemu_irq parent_irq;
  62     void *irq_request_opaque;
  63 };
  64
  65 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
  66 static int irq_level[16];
  67 #endif
  68 #ifdef DEBUG_IRQ_COUNT
  69 static uint64_t irq_count[16];
  70 #endif
  71
  72 /* set irq level. If an edge is detected, then the IRR is set to 1 */
  73 static inline void pic_set_irq1(PicState *s, int irq, int level)
  74 {
  75     int mask;
  76     mask = 1 << irq;
  77     if (s->elcr & mask) {
  78         /* level triggered */
  79         if (level) {
  80             s->irr |= mask;
  81             s->last_irr |= mask;
  82         } else {
  83             s->irr &= ~mask;
  84             s->last_irr &= ~mask;
  85         }
  86     } else {
  87         /* edge triggered */
  88         if (level) {
  89             if ((s->last_irr & mask) == 0)
  90                 s->irr |= mask;
  91             s->last_irr |= mask;
  92         } else {
  93             s->last_irr &= ~mask;
  94         }
  95     }
  96 }
  97
  98 /* return the highest priority found in mask (highest = smallest
  99    number). Return 8 if no irq */
 100 static inline int get_priority(PicState *s, int mask)
 101 {
 102     int priority;
 103     if (mask == 0)
 104         return 8;
 105     priority = 0;
 106     while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
 107         priority++;
 108     return priority;
 109 }
 110
 111 /* return the pic wanted interrupt. return -1 if none */
 112 static int pic_get_irq(PicState *s)
 113 {
 114     int mask, cur_priority, priority;
 115
 116     mask = s->irr & ~s->imr;
 117     priority = get_priority(s, mask);
 118     if (priority == 8)
 119         return -1;
 120     /* compute current priority. If special fully nested mode on the
 121        master, the IRQ coming from the slave is not taken into account
 122        for the priority computation. */
 123     mask = s->isr;
 124     if (s->special_mask)
 125         mask &= ~s->imr;
 126     if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
 127         mask &= ~(1 << 2);
 128     cur_priority = get_priority(s, mask);
 129     if (priority < cur_priority) {
 130         /* higher priority found: an irq should be generated */
 131         return (priority + s->priority_add) & 7;
 132     } else {
 133         return -1;
 134     }
 135 }
 136
 137 /* raise irq to CPU if necessary. must be called every time the active
 138    irq may change */
 139 /* XXX: should not export it, but it is needed for an APIC kludge */
 140 void pic_update_irq(PicState2 *s)
 141 {
 142     int irq2, irq;
 143
 144     /* first look at slave pic */
 145     irq2 = pic_get_irq(&s->pics[1]);
 146     if (irq2 >= 0) {
 147         /* if irq request by slave pic, signal master PIC */
 148         pic_set_irq1(&s->pics[0], 2, 1);
 149         pic_set_irq1(&s->pics[0], 2, 0);
 150     }
 151     /* look at requested irq */
 152     irq = pic_get_irq(&s->pics[0]);
 153     if (irq >= 0) {
 154 #if defined(DEBUG_PIC)
 155         {
 156             int i;
 157             for(i = 0; i < 2; i++) {
 158                 printf("pic%d: imr=%x irr=%x padd=%d\n",
 159                        i, s->pics[i].imr, s->pics[i].irr,
 160                        s->pics[i].priority_add);
 161
 162             }
 163         }
 164         printf("pic: cpu_interrupt\n");
 165 #endif
 166         qemu_irq_raise(s->parent_irq);
 167     }
 168
 169 /* all targets should do this rather than acking the IRQ in the cpu */
 170 #if defined(TARGET_MIPS) || defined(TARGET_PPC) || defined(TARGET_ALPHA)
 171     else {
 172         qemu_irq_lower(s->parent_irq);
 173     }
 174 #endif
 175 }
 176
 177 #ifdef DEBUG_IRQ_LATENCY
 178 int64_t irq_time[16];
 179 #endif
 180
 181 static void i8259_set_irq(void *opaque, int irq, int level)
 182 {
 183     PicState2 *s = opaque;
 184
 185 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
 186     if (level != irq_level[irq]) {
 187 #if defined(DEBUG_PIC)
 188         printf("i8259_set_irq: irq=%d level=%d\n", irq, level);
 189 #endif
 190         irq_level[irq] = level;
 191 #ifdef DEBUG_IRQ_COUNT
 192         if (level == 1)
 193             irq_count[irq]++;
 194 #endif
 195     }
 196 #endif
 197 #ifdef DEBUG_IRQ_LATENCY
 198     if (level) {
 199         irq_time[irq] = qemu_get_clock(vm_clock);
 200     }
 201 #endif
 202     pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
 203     pic_update_irq(s);
 204 }
 205
 206 /* acknowledge interrupt 'irq' */
 207 static inline void pic_intack(PicState *s, int irq)
 208 {
 209     if (s->auto_eoi) {
 210         if (s->rotate_on_auto_eoi)
 211             s->priority_add = (irq + 1) & 7;
 212     } else {
 213         s->isr |= (1 << irq);
 214     }
 215     /* We don't clear a level sensitive interrupt here */
 216     if (!(s->elcr & (1 << irq)))
 217         s->irr &= ~(1 << irq);
 218 }
 219
 220 int pic_read_irq(PicState2 *s)
 221 {
 222     int irq, irq2, intno;
 223
 224     irq = pic_get_irq(&s->pics[0]);
 225     if (irq >= 0) {
 226         pic_intack(&s->pics[0], irq);
 227         if (irq == 2) {
 228             irq2 = pic_get_irq(&s->pics[1]);
 229             if (irq2 >= 0) {
 230                 pic_intack(&s->pics[1], irq2);
 231             } else {
 232                 /* spurious IRQ on slave controller */
 233                 irq2 = 7;
 234             }
 235             intno = s->pics[1].irq_base + irq2;
 236             irq = irq2 + 8;
 237         } else {
 238             intno = s->pics[0].irq_base + irq;
 239         }
 240     } else {
 241         /* spurious IRQ on host controller */
 242         irq = 7;
 243         intno = s->pics[0].irq_base + irq;
 244     }
 245     pic_update_irq(s);
 246
 247 #ifdef DEBUG_IRQ_LATENCY
 248     printf("IRQ%d latency=%0.3fus\n",
 249            irq,
 250            (double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec);
 251 #endif
 252 #if defined(DEBUG_PIC)
 253     printf("pic_interrupt: irq=%d\n", irq);
 254 #endif
 255     return intno;
 256 }
 257
 258 static void pic_reset(void *opaque)
 259 {
 260     PicState *s = opaque;
 261
 262     s->last_irr = 0;
 263     s->irr = 0;
 264     s->imr = 0;
 265     s->isr = 0;
 266     s->priority_add = 0;
 267     s->irq_base = 0;
 268     s->read_reg_select = 0;
 269     s->poll = 0;
 270     s->special_mask = 0;
 271     s->init_state = 0;
 272     s->auto_eoi = 0;
 273     s->rotate_on_auto_eoi = 0;
 274     s->special_fully_nested_mode = 0;
 275     s->init4 = 0;
 276     s->single_mode = 0;
 277     /* Note: ELCR is not reset */
 278 }
 279
 280 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 281 {
 282     PicState *s = opaque;
 283     int priority, cmd, irq;
 284
 285 #ifdef DEBUG_PIC
 286     printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
 287 #endif
 288     addr &= 1;
 289     if (addr == 0) {
 290         if (val & 0x10) {
 291             /* init */
 292             pic_reset(s);
 293             /* deassert a pending interrupt */
 294             qemu_irq_lower(s->pics_state->parent_irq);
 295             s->init_state = 1;
 296             s->init4 = val & 1;
 297             s->single_mode = val & 2;
 298             if (val & 0x08)
 299                 hw_error("level sensitive irq not supported");
 300         } else if (val & 0x08) {
 301             if (val & 0x04)
 302                 s->poll = 1;
 303             if (val & 0x02)
 304                 s->read_reg_select = val & 1;
 305             if (val & 0x40)
 306                 s->special_mask = (val >> 5) & 1;
 307         } else {
 308             cmd = val >> 5;
 309             switch(cmd) {
 310             case 0:
 311             case 4:
 312                 s->rotate_on_auto_eoi = cmd >> 2;
 313                 break;
 314             case 1: /* end of interrupt */
 315             case 5:
 316                 priority = get_priority(s, s->isr);
 317                 if (priority != 8) {
 318                     irq = (priority + s->priority_add) & 7;
 319                     s->isr &= ~(1 << irq);
 320                     if (cmd == 5)
 321                         s->priority_add = (irq + 1) & 7;
 322                     pic_update_irq(s->pics_state);
 323                 }
 324                 break;
 325             case 3:
 326                 irq = val & 7;
 327                 s->isr &= ~(1 << irq);
 328                 pic_update_irq(s->pics_state);
 329                 break;
 330             case 6:
 331                 s->priority_add = (val + 1) & 7;
 332                 pic_update_irq(s->pics_state);
 333                 break;
 334             case 7:
 335                 irq = val & 7;
 336                 s->isr &= ~(1 << irq);
 337                 s->priority_add = (irq + 1) & 7;
 338                 pic_update_irq(s->pics_state);
 339                 break;
 340             default:
 341                 /* no operation */
 342                 break;
 343             }
 344         }
 345     } else {
 346         switch(s->init_state) {
 347         case 0:
 348             /* normal mode */
 349             s->imr = val;
 350             pic_update_irq(s->pics_state);
 351             break;
 352         case 1:
 353             s->irq_base = val & 0xf8;
 354             s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2;
 355             break;
 356         case 2:
 357             if (s->init4) {
 358                 s->init_state = 3;
 359             } else {
 360                 s->init_state = 0;
 361             }
 362             break;
 363         case 3:
 364             s->special_fully_nested_mode = (val >> 4) & 1;
 365             s->auto_eoi = (val >> 1) & 1;
 366             s->init_state = 0;
 367             break;
 368         }
 369     }
 370 }
 371
 372 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
 373 {
 374     int ret;
 375
 376     ret = pic_get_irq(s);
 377     if (ret >= 0) {
 378         if (addr1 >> 7) {
 379             s->pics_state->pics[0].isr &= ~(1 << 2);
 380             s->pics_state->pics[0].irr &= ~(1 << 2);
 381         }
 382         s->irr &= ~(1 << ret);
 383         s->isr &= ~(1 << ret);
 384         if (addr1 >> 7 || ret != 2)
 385             pic_update_irq(s->pics_state);
 386     } else {
 387         ret = 0x07;
 388         pic_update_irq(s->pics_state);
 389     }
 390
 391     return ret;
 392 }
 393
 394 static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
 395 {
 396     PicState *s = opaque;
 397     unsigned int addr;
 398     int ret;
 399
 400     addr = addr1;
 401     addr &= 1;
 402     if (s->poll) {
 403         ret = pic_poll_read(s, addr1);
 404         s->poll = 0;
 405     } else {
 406         if (addr == 0) {
 407             if (s->read_reg_select)
 408                 ret = s->isr;
 409             else
 410                 ret = s->irr;
 411         } else {
 412             ret = s->imr;
 413         }
 414     }
 415 #ifdef DEBUG_PIC
 416     printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
 417 #endif
 418     return ret;
 419 }
 420
 421 /* memory mapped interrupt status */
 422 /* XXX: may be the same than pic_read_irq() */
 423 uint32_t pic_intack_read(PicState2 *s)
 424 {
 425     int ret;
 426
 427     ret = pic_poll_read(&s->pics[0], 0x00);
 428     if (ret == 2)
 429         ret = pic_poll_read(&s->pics[1], 0x80) + 8;
 430     /* Prepare for ISR read */
 431     s->pics[0].read_reg_select = 1;
 432
 433     return ret;
 434 }
 435
 436 static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 437 {
 438     PicState *s = opaque;
 439     s->elcr = val & s->elcr_mask;
 440 }
 441
 442 static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
 443 {
 444     PicState *s = opaque;
 445     return s->elcr;
 446 }
 447
 448 static void pic_save(QEMUFile *f, void *opaque)
 449 {
 450     PicState *s = opaque;
 451
 452     qemu_put_8s(f, &s->last_irr);
 453     qemu_put_8s(f, &s->irr);
 454     qemu_put_8s(f, &s->imr);
 455     qemu_put_8s(f, &s->isr);
 456     qemu_put_8s(f, &s->priority_add);
 457     qemu_put_8s(f, &s->irq_base);
 458     qemu_put_8s(f, &s->read_reg_select);
 459     qemu_put_8s(f, &s->poll);
 460     qemu_put_8s(f, &s->special_mask);
 461     qemu_put_8s(f, &s->init_state);
 462     qemu_put_8s(f, &s->auto_eoi);
 463     qemu_put_8s(f, &s->rotate_on_auto_eoi);
 464     qemu_put_8s(f, &s->special_fully_nested_mode);
 465     qemu_put_8s(f, &s->init4);
 466     qemu_put_8s(f, &s->single_mode);
 467     qemu_put_8s(f, &s->elcr);
 468 }
 469
 470 static int pic_load(QEMUFile *f, void *opaque, int version_id)
 471 {
 472     PicState *s = opaque;
 473
 474     if (version_id != 1)
 475         return -EINVAL;
 476
 477     qemu_get_8s(f, &s->last_irr);
 478     qemu_get_8s(f, &s->irr);
 479     qemu_get_8s(f, &s->imr);
 480     qemu_get_8s(f, &s->isr);
 481     qemu_get_8s(f, &s->priority_add);
 482     qemu_get_8s(f, &s->irq_base);
 483     qemu_get_8s(f, &s->read_reg_select);
 484     qemu_get_8s(f, &s->poll);
 485     qemu_get_8s(f, &s->special_mask);
 486     qemu_get_8s(f, &s->init_state);
 487     qemu_get_8s(f, &s->auto_eoi);
 488     qemu_get_8s(f, &s->rotate_on_auto_eoi);
 489     qemu_get_8s(f, &s->special_fully_nested_mode);
 490     qemu_get_8s(f, &s->init4);
 491     qemu_get_8s(f, &s->single_mode);
 492     qemu_get_8s(f, &s->elcr);
 493     return 0;
 494 }
 495
 496 /* XXX: add generic master/slave system */
 497 static void pic_init1(int io_addr, int elcr_addr, PicState *s)
 498 {
 499     register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
 500     register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
 501     if (elcr_addr >= 0) {
 502         register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
 503         register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
 504     }
 505     register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
 506     qemu_register_reset(pic_reset, s);
 507 }
 508
 509 void pic_info(Monitor *mon)
 510 {
 511     int i;
 512     PicState *s;
 513
 514     if (!isa_pic)
 515         return;
 516
 517     for(i=0;i<2;i++) {
 518         s = &isa_pic->pics[i];
 519         monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
 520                        "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
 521                        i, s->irr, s->imr, s->isr, s->priority_add,
 522                        s->irq_base, s->read_reg_select, s->elcr,
 523                        s->special_fully_nested_mode);
 524     }
 525 }
 526
 527 void irq_info(Monitor *mon)
 528 {
 529 #ifndef DEBUG_IRQ_COUNT
 530     monitor_printf(mon, "irq statistic code not compiled.\n");
 531 #else
 532     int i;
 533     int64_t count;
 534
 535     monitor_printf(mon, "IRQ statistics:\n");
 536     for (i = 0; i < 16; i++) {
 537         count = irq_count[i];
 538         if (count > 0)
 539             monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
 540     }
 541 #endif
 542 }
 543
 544 qemu_irq *i8259_init(qemu_irq parent_irq)
 545 {
 546     PicState2 *s;
 547
 548     s = qemu_mallocz(sizeof(PicState2));
 549     pic_init1(0x20, 0x4d0, &s->pics[0]);
 550     pic_init1(0xa0, 0x4d1, &s->pics[1]);
 551     s->pics[0].elcr_mask = 0xf8;
 552     s->pics[1].elcr_mask = 0xde;
 553     s->parent_irq = parent_irq;
 554     s->pics[0].pics_state = s;
 555     s->pics[1].pics_state = s;
 556     isa_pic = s;
 557     return qemu_allocate_irqs(i8259_set_irq, s, 16);
 558 }