hw/sun4c_intctl.c

   1 /*
   2  * QEMU Sparc Sun4c interrupt controller emulation
   3  *
   4  * Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "sun4m.h"
  27 #include "monitor.h"
  28 #include "sysbus.h"
  29
  30 //#define DEBUG_IRQ_COUNT
  31 //#define DEBUG_IRQ
  32
  33 #ifdef DEBUG_IRQ
  34 #define DPRINTF(fmt, ...)                                       \
  35     do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0)
  36 #else
  37 #define DPRINTF(fmt, ...)
  38 #endif
  39
  40 /*
  41  * Registers of interrupt controller in sun4c.
  42  *
  43  */
  44
  45 #define MAX_PILS 16
  46
  47 typedef struct Sun4c_INTCTLState {
  48     SysBusDevice busdev;
  49 #ifdef DEBUG_IRQ_COUNT
  50     uint64_t irq_count;
  51 #endif
  52     qemu_irq cpu_irqs[MAX_PILS];
  53     const uint32_t *intbit_to_level;
  54     uint32_t pil_out;
  55     uint8_t reg;
  56     uint8_t pending;
  57 } Sun4c_INTCTLState;
  58
  59 #define INTCTL_SIZE 1
  60
  61 static void sun4c_check_interrupts(void *opaque);
  62
  63 static uint32_t sun4c_intctl_mem_readb(void *opaque, target_phys_addr_t addr)
  64 {
  65     Sun4c_INTCTLState *s = opaque;
  66     uint32_t ret;
  67
  68     ret = s->reg;
  69     DPRINTF("read reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
  70
  71     return ret;
  72 }
  73
  74 static void sun4c_intctl_mem_writeb(void *opaque, target_phys_addr_t addr,
  75                                     uint32_t val)
  76 {
  77     Sun4c_INTCTLState *s = opaque;
  78
  79     DPRINTF("write reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
  80     val &= 0xbf;
  81     s->reg = val;
  82     sun4c_check_interrupts(s);
  83 }
  84
  85 static CPUReadMemoryFunc * const sun4c_intctl_mem_read[3] = {
  86     sun4c_intctl_mem_readb,
  87     NULL,
  88     NULL,
  89 };
  90
  91 static CPUWriteMemoryFunc * const sun4c_intctl_mem_write[3] = {
  92     sun4c_intctl_mem_writeb,
  93     NULL,
  94     NULL,
  95 };
  96
  97 void sun4c_pic_info(Monitor *mon, void *opaque)
  98 {
  99     Sun4c_INTCTLState *s = opaque;
 100
 101     monitor_printf(mon, "master: pending 0x%2.2x, enabled 0x%2.2x\n",
 102                    s->pending, s->reg);
 103 }
 104
 105 void sun4c_irq_info(Monitor *mon, void *opaque)
 106 {
 107 #ifndef DEBUG_IRQ_COUNT
 108     monitor_printf(mon, "irq statistic code not compiled.\n");
 109 #else
 110     Sun4c_INTCTLState *s = opaque;
 111     int64_t count;
 112
 113     monitor_printf(mon, "IRQ statistics:\n");
 114     count = s->irq_count;
 115     if (count > 0)
 116         monitor_printf(mon, " %" PRId64 "\n", count);
 117 #endif
 118 }
 119
 120 static const uint32_t intbit_to_level[] = { 0, 1, 4, 6, 8, 10, 0, 14, };
 121
 122 static void sun4c_check_interrupts(void *opaque)
 123 {
 124     Sun4c_INTCTLState *s = opaque;
 125     uint32_t pil_pending;
 126     unsigned int i;
 127
 128     pil_pending = 0;
 129     if (s->pending && !(s->reg & 0x80000000)) {
 130         for (i = 0; i < 8; i++) {
 131             if (s->pending & (1 << i))
 132                 pil_pending |= 1 << intbit_to_level[i];
 133         }
 134     }
 135
 136     for (i = 0; i < MAX_PILS; i++) {
 137         if (pil_pending & (1 << i)) {
 138             if (!(s->pil_out & (1 << i)))
 139                 qemu_irq_raise(s->cpu_irqs[i]);
 140         } else {
 141             if (s->pil_out & (1 << i))
 142                 qemu_irq_lower(s->cpu_irqs[i]);
 143         }
 144     }
 145     s->pil_out = pil_pending;
 146 }
 147
 148 /*
 149  * "irq" here is the bit number in the system interrupt register
 150  */
 151 static void sun4c_set_irq(void *opaque, int irq, int level)
 152 {
 153     Sun4c_INTCTLState *s = opaque;
 154     uint32_t mask = 1 << irq;
 155     uint32_t pil = intbit_to_level[irq];
 156
 157     DPRINTF("Set irq %d -> pil %d level %d\n", irq, pil,
 158             level);
 159     if (pil > 0) {
 160         if (level) {
 161 #ifdef DEBUG_IRQ_COUNT
 162             s->irq_count++;
 163 #endif
 164             s->pending |= mask;
 165         } else {
 166             s->pending &= ~mask;
 167         }
 168         sun4c_check_interrupts(s);
 169     }
 170 }
 171
 172 static void sun4c_intctl_save(QEMUFile *f, void *opaque)
 173 {
 174     Sun4c_INTCTLState *s = opaque;
 175
 176     qemu_put_8s(f, &s->reg);
 177     qemu_put_8s(f, &s->pending);
 178 }
 179
 180 static int sun4c_intctl_load(QEMUFile *f, void *opaque, int version_id)
 181 {
 182     Sun4c_INTCTLState *s = opaque;
 183
 184     if (version_id != 1)
 185         return -EINVAL;
 186
 187     qemu_get_8s(f, &s->reg);
 188     qemu_get_8s(f, &s->pending);
 189
 190     return 0;
 191 }
 192
 193 static void sun4c_intctl_reset(void *opaque)
 194 {
 195     Sun4c_INTCTLState *s = opaque;
 196
 197     s->reg = 1;
 198     s->pending = 0;
 199 }
 200
 201 static void sun4c_intctl_init1(SysBusDevice *dev)
 202 {
 203     Sun4c_INTCTLState *s = FROM_SYSBUS(Sun4c_INTCTLState, dev);
 204     int io_memory;
 205     unsigned int i;
 206
 207     io_memory = cpu_register_io_memory(sun4c_intctl_mem_read,
 208                                        sun4c_intctl_mem_write, s);
 209     sysbus_init_mmio(dev, INTCTL_SIZE, io_memory);
 210     qdev_init_gpio_in(&dev->qdev, sun4c_set_irq, 8);
 211
 212     for (i = 0; i < MAX_PILS; i++) {
 213         sysbus_init_irq(dev, &s->cpu_irqs[i]);
 214     }
 215     register_savevm("sun4c_intctl", -1, 1, sun4c_intctl_save,
 216                     sun4c_intctl_load, s);
 217     qemu_register_reset(sun4c_intctl_reset, s);
 218     sun4c_intctl_reset(s);
 219 }
 220
 221 static SysBusDeviceInfo sun4c_intctl_info = {
 222     .init = sun4c_intctl_init1,
 223     .qdev.name  = "sun4c_intctl",
 224     .qdev.size  = sizeof(Sun4c_INTCTLState),
 225 };
 226
 227 static void sun4c_intctl_register_devices(void)
 228 {
 229     sysbus_register_withprop(&sun4c_intctl_info);
 230 }
 231
 232 device_init(sun4c_intctl_register_devices)