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tcg/ppc64: Fix loading of 32bit constants
[qemu/mdroth.git] / alpha-dis.c
blob970da5bfe60f68ee93e96bc659471bd73a3f304d
1 /* alpha-dis.c -- Disassemble Alpha AXP instructions
2 Copyright 1996, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
3 Contributed by Richard Henderson <rth@tamu.edu>,
4 patterned after the PPC opcode handling written by Ian Lance Taylor.
5
6 This file is part of GDB, GAS, and the GNU binutils.
7
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 2, or (at your option) any later version.
12
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, see
20 <http://www.gnu.org/licenses/>. */
21
22 #include <stdio.h>
23 #include "dis-asm.h"
24
25 /* The opcode table is an array of struct alpha_opcode. */
26
27 struct alpha_opcode
28 {
29 /* The opcode name. */
30 const char *name;
31
32 /* The opcode itself. Those bits which will be filled in with
33 operands are zeroes. */
34 unsigned opcode;
35
36 /* The opcode mask. This is used by the disassembler. This is a
37 mask containing ones indicating those bits which must match the
38 opcode field, and zeroes indicating those bits which need not
39 match (and are presumably filled in by operands). */
40 unsigned mask;
41
42 /* One bit flags for the opcode. These are primarily used to
43 indicate specific processors and environments support the
44 instructions. The defined values are listed below. */
45 unsigned flags;
46
47 /* An array of operand codes. Each code is an index into the
48 operand table. They appear in the order which the operands must
49 appear in assembly code, and are terminated by a zero. */
50 unsigned char operands[4];
51 };
52
53 /* The table itself is sorted by major opcode number, and is otherwise
54 in the order in which the disassembler should consider
55 instructions. */
56 extern const struct alpha_opcode alpha_opcodes[];
57 extern const unsigned alpha_num_opcodes;
58
59 /* Values defined for the flags field of a struct alpha_opcode. */
60
61 /* CPU Availability */
62 #define AXP_OPCODE_BASE 0x0001 /* Base architecture -- all cpus. */
63 #define AXP_OPCODE_EV4 0x0002 /* EV4 specific PALcode insns. */
64 #define AXP_OPCODE_EV5 0x0004 /* EV5 specific PALcode insns. */
65 #define AXP_OPCODE_EV6 0x0008 /* EV6 specific PALcode insns. */
66 #define AXP_OPCODE_BWX 0x0100 /* Byte/word extension (amask bit 0). */
67 #define AXP_OPCODE_CIX 0x0200 /* "Count" extension (amask bit 1). */
68 #define AXP_OPCODE_MAX 0x0400 /* Multimedia extension (amask bit 8). */
69
70 #define AXP_OPCODE_NOPAL (~(AXP_OPCODE_EV4|AXP_OPCODE_EV5|AXP_OPCODE_EV6))
71
72 /* A macro to extract the major opcode from an instruction. */
73 #define AXP_OP(i) (((i) >> 26) & 0x3F)
74
75 /* The total number of major opcodes. */
76 #define AXP_NOPS 0x40
77
78 \f
79 /* The operands table is an array of struct alpha_operand. */
80
81 struct alpha_operand
82 {
83 /* The number of bits in the operand. */
84 unsigned int bits : 5;
85
86 /* How far the operand is left shifted in the instruction. */
87 unsigned int shift : 5;
88
89 /* The default relocation type for this operand. */
90 signed int default_reloc : 16;
91
92 /* One bit syntax flags. */
93 unsigned int flags : 16;
94
95 /* Insertion function. This is used by the assembler. To insert an
96 operand value into an instruction, check this field.
97
98 If it is NULL, execute
99 i |= (op & ((1 << o->bits) - 1)) << o->shift;
100 (i is the instruction which we are filling in, o is a pointer to
101 this structure, and op is the opcode value; this assumes twos
102 complement arithmetic).
103
104 If this field is not NULL, then simply call it with the
105 instruction and the operand value. It will return the new value
106 of the instruction. If the ERRMSG argument is not NULL, then if
107 the operand value is illegal, *ERRMSG will be set to a warning
108 string (the operand will be inserted in any case). If the
109 operand value is legal, *ERRMSG will be unchanged (most operands
110 can accept any value). */
111 unsigned (*insert) (unsigned instruction, int op,
112 const char **errmsg);
113
114 /* Extraction function. This is used by the disassembler. To
115 extract this operand type from an instruction, check this field.
116
117 If it is NULL, compute
118 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
119 if ((o->flags & AXP_OPERAND_SIGNED) != 0
120 && (op & (1 << (o->bits - 1))) != 0)
121 op -= 1 << o->bits;
122 (i is the instruction, o is a pointer to this structure, and op
123 is the result; this assumes twos complement arithmetic).
124
125 If this field is not NULL, then simply call it with the
126 instruction value. It will return the value of the operand. If
127 the INVALID argument is not NULL, *INVALID will be set to
128 non-zero if this operand type can not actually be extracted from
129 this operand (i.e., the instruction does not match). If the
130 operand is valid, *INVALID will not be changed. */
131 int (*extract) (unsigned instruction, int *invalid);
132 };
133
134 /* Elements in the table are retrieved by indexing with values from
135 the operands field of the alpha_opcodes table. */
136
137 extern const struct alpha_operand alpha_operands[];
138 extern const unsigned alpha_num_operands;
139
140 /* Values defined for the flags field of a struct alpha_operand. */
141
142 /* Mask for selecting the type for typecheck purposes */
143 #define AXP_OPERAND_TYPECHECK_MASK \
144 (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA | AXP_OPERAND_IR | \
145 AXP_OPERAND_FPR | AXP_OPERAND_RELATIVE | AXP_OPERAND_SIGNED | \
146 AXP_OPERAND_UNSIGNED)
147
148 /* This operand does not actually exist in the assembler input. This
149 is used to support extended mnemonics, for which two operands fields
150 are identical. The assembler should call the insert function with
151 any op value. The disassembler should call the extract function,
152 ignore the return value, and check the value placed in the invalid
153 argument. */
154 #define AXP_OPERAND_FAKE 01
155
156 /* The operand should be wrapped in parentheses rather than separated
157 from the previous by a comma. This is used for the load and store
158 instructions which want their operands to look like "Ra,disp(Rb)". */
159 #define AXP_OPERAND_PARENS 02
160
161 /* Used in combination with PARENS, this suppresses the suppression of
162 the comma. This is used for "jmp Ra,(Rb),hint". */
163 #define AXP_OPERAND_COMMA 04
164
165 /* This operand names an integer register. */
166 #define AXP_OPERAND_IR 010
167
168 /* This operand names a floating point register. */
169 #define AXP_OPERAND_FPR 020
170
171 /* This operand is a relative branch displacement. The disassembler
172 prints these symbolically if possible. */
173 #define AXP_OPERAND_RELATIVE 040
174
175 /* This operand takes signed values. */
176 #define AXP_OPERAND_SIGNED 0100
177
178 /* This operand takes unsigned values. This exists primarily so that
179 a flags value of 0 can be treated as end-of-arguments. */
180 #define AXP_OPERAND_UNSIGNED 0200
181
182 /* Suppress overflow detection on this field. This is used for hints. */
183 #define AXP_OPERAND_NOOVERFLOW 0400
184
185 /* Mask for optional argument default value. */
186 #define AXP_OPERAND_OPTIONAL_MASK 07000
187
188 /* This operand defaults to zero. This is used for jump hints. */
189 #define AXP_OPERAND_DEFAULT_ZERO 01000
190
191 /* This operand should default to the first (real) operand and is used
192 in conjunction with AXP_OPERAND_OPTIONAL. This allows
193 "and $0,3,$0" to be written as "and $0,3", etc. I don't like
194 it, but it's what DEC does. */
195 #define AXP_OPERAND_DEFAULT_FIRST 02000
196
197 /* Similarly, this operand should default to the second (real) operand.
198 This allows "negl $0" instead of "negl $0,$0". */
199 #define AXP_OPERAND_DEFAULT_SECOND 04000
200
201 \f
202 /* Register common names */
203
204 #define AXP_REG_V0 0
205 #define AXP_REG_T0 1
206 #define AXP_REG_T1 2
207 #define AXP_REG_T2 3
208 #define AXP_REG_T3 4
209 #define AXP_REG_T4 5
210 #define AXP_REG_T5 6
211 #define AXP_REG_T6 7
212 #define AXP_REG_T7 8
213 #define AXP_REG_S0 9
214 #define AXP_REG_S1 10
215 #define AXP_REG_S2 11
216 #define AXP_REG_S3 12
217 #define AXP_REG_S4 13
218 #define AXP_REG_S5 14
219 #define AXP_REG_FP 15
220 #define AXP_REG_A0 16
221 #define AXP_REG_A1 17
222 #define AXP_REG_A2 18
223 #define AXP_REG_A3 19
224 #define AXP_REG_A4 20
225 #define AXP_REG_A5 21
226 #define AXP_REG_T8 22
227 #define AXP_REG_T9 23
228 #define AXP_REG_T10 24
229 #define AXP_REG_T11 25
230 #define AXP_REG_RA 26
231 #define AXP_REG_PV 27
232 #define AXP_REG_T12 27
233 #define AXP_REG_AT 28
234 #define AXP_REG_GP 29
235 #define AXP_REG_SP 30
236 #define AXP_REG_ZERO 31
237
238 #define bfd_mach_alpha_ev4 0x10
239 #define bfd_mach_alpha_ev5 0x20
240 #define bfd_mach_alpha_ev6 0x30
241
242 enum bfd_reloc_code_real {
243 BFD_RELOC_23_PCREL_S2,
244 BFD_RELOC_ALPHA_HINT
245 };
246
247 /* This file holds the Alpha AXP opcode table. The opcode table includes
248 almost all of the extended instruction mnemonics. This permits the
249 disassembler to use them, and simplifies the assembler logic, at the
250 cost of increasing the table size. The table is strictly constant
251 data, so the compiler should be able to put it in the text segment.
252
253 This file also holds the operand table. All knowledge about inserting
254 and extracting operands from instructions is kept in this file.
255
256 The information for the base instruction set was compiled from the
257 _Alpha Architecture Handbook_, Digital Order Number EC-QD2KB-TE,
258 version 2.
259
260 The information for the post-ev5 architecture extensions BWX, CIX and
261 MAX came from version 3 of this same document, which is also available
262 on-line at http://ftp.digital.com/pub/Digital/info/semiconductor
263 /literature/alphahb2.pdf
264
265 The information for the EV4 PALcode instructions was compiled from
266 _DECchip 21064 and DECchip 21064A Alpha AXP Microprocessors Hardware
267 Reference Manual_, Digital Order Number EC-Q9ZUA-TE, preliminary
268 revision dated June 1994.
269
270 The information for the EV5 PALcode instructions was compiled from
271 _Alpha 21164 Microprocessor Hardware Reference Manual_, Digital
272 Order Number EC-QAEQB-TE, preliminary revision dated April 1995. */
273 \f
274 /* Local insertion and extraction functions */
275
276 static unsigned insert_rba (unsigned, int, const char **);
277 static unsigned insert_rca (unsigned, int, const char **);
278 static unsigned insert_za (unsigned, int, const char **);
279 static unsigned insert_zb (unsigned, int, const char **);
280 static unsigned insert_zc (unsigned, int, const char **);
281 static unsigned insert_bdisp (unsigned, int, const char **);
282 static unsigned insert_jhint (unsigned, int, const char **);
283 static unsigned insert_ev6hwjhint (unsigned, int, const char **);
284
285 static int extract_rba (unsigned, int *);
286 static int extract_rca (unsigned, int *);
287 static int extract_za (unsigned, int *);
288 static int extract_zb (unsigned, int *);
289 static int extract_zc (unsigned, int *);
290 static int extract_bdisp (unsigned, int *);
291 static int extract_jhint (unsigned, int *);
292 static int extract_ev6hwjhint (unsigned, int *);
293
294 \f
295 /* The operands table */
296
297 const struct alpha_operand alpha_operands[] =
298 {
299 /* The fields are bits, shift, insert, extract, flags */
300 /* The zero index is used to indicate end-of-list */
301 #define UNUSED 0
302 { 0, 0, 0, 0, 0, 0 },
303
304 /* The plain integer register fields */
305 #define RA (UNUSED + 1)
306 { 5, 21, 0, AXP_OPERAND_IR, 0, 0 },
307 #define RB (RA + 1)
308 { 5, 16, 0, AXP_OPERAND_IR, 0, 0 },
309 #define RC (RB + 1)
310 { 5, 0, 0, AXP_OPERAND_IR, 0, 0 },
311
312 /* The plain fp register fields */
313 #define FA (RC + 1)
314 { 5, 21, 0, AXP_OPERAND_FPR, 0, 0 },
315 #define FB (FA + 1)
316 { 5, 16, 0, AXP_OPERAND_FPR, 0, 0 },
317 #define FC (FB + 1)
318 { 5, 0, 0, AXP_OPERAND_FPR, 0, 0 },
319
320 /* The integer registers when they are ZERO */
321 #define ZA (FC + 1)
322 { 5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za },
323 #define ZB (ZA + 1)
324 { 5, 16, 0, AXP_OPERAND_FAKE, insert_zb, extract_zb },
325 #define ZC (ZB + 1)
326 { 5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc },
327
328 /* The RB field when it needs parentheses */
329 #define PRB (ZC + 1)
330 { 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS, 0, 0 },
331
332 /* The RB field when it needs parentheses _and_ a preceding comma */
333 #define CPRB (PRB + 1)
334 { 5, 16, 0,
335 AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA, 0, 0 },
336
337 /* The RB field when it must be the same as the RA field */
338 #define RBA (CPRB + 1)
339 { 5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba },
340
341 /* The RC field when it must be the same as the RB field */
342 #define RCA (RBA + 1)
343 { 5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca },
344
345 /* The RC field when it can *default* to RA */
346 #define DRC1 (RCA + 1)
347 { 5, 0, 0,
348 AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
349
350 /* The RC field when it can *default* to RB */
351 #define DRC2 (DRC1 + 1)
352 { 5, 0, 0,
353 AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
354
355 /* The FC field when it can *default* to RA */
356 #define DFC1 (DRC2 + 1)
357 { 5, 0, 0,
358 AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
359
360 /* The FC field when it can *default* to RB */
361 #define DFC2 (DFC1 + 1)
362 { 5, 0, 0,
363 AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
364
365 /* The unsigned 8-bit literal of Operate format insns */
366 #define LIT (DFC2 + 1)
367 { 8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0 },
368
369 /* The signed 16-bit displacement of Memory format insns. From here
370 we can't tell what relocation should be used, so don't use a default. */
371 #define MDISP (LIT + 1)
372 { 16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0 },
373
374 /* The signed "23-bit" aligned displacement of Branch format insns */
375 #define BDISP (MDISP + 1)
376 { 21, 0, BFD_RELOC_23_PCREL_S2,
377 AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp },
378
379 /* The 26-bit PALcode function */
380 #define PALFN (BDISP + 1)
381 { 26, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0 },
382
383 /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint */
384 #define JMPHINT (PALFN + 1)
385 { 14, 0, BFD_RELOC_ALPHA_HINT,
386 AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
387 insert_jhint, extract_jhint },
388
389 /* The optional hint to RET/JSR_COROUTINE */
390 #define RETHINT (JMPHINT + 1)
391 { 14, 0, -RETHINT,
392 AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO, 0, 0 },
393
394 /* The 12-bit displacement for the ev[46] hw_{ld,st} (pal1b/pal1f) insns */
395 #define EV4HWDISP (RETHINT + 1)
396 #define EV6HWDISP (EV4HWDISP)
397 { 12, 0, -EV4HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
398
399 /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns */
400 #define EV4HWINDEX (EV4HWDISP + 1)
401 { 5, 0, -EV4HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
402
403 /* The 8-bit index for the oddly unqualified hw_m[tf]pr insns
404 that occur in DEC PALcode. */
405 #define EV4EXTHWINDEX (EV4HWINDEX + 1)
406 { 8, 0, -EV4EXTHWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
407
408 /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns */
409 #define EV5HWDISP (EV4EXTHWINDEX + 1)
410 { 10, 0, -EV5HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
411
412 /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns */
413 #define EV5HWINDEX (EV5HWDISP + 1)
414 { 16, 0, -EV5HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
415
416 /* The 16-bit combined index/scoreboard mask for the ev6
417 hw_m[ft]pr (pal19/pal1d) insns */
418 #define EV6HWINDEX (EV5HWINDEX + 1)
419 { 16, 0, -EV6HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
420
421 /* The 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn */
422 #define EV6HWJMPHINT (EV6HWINDEX+ 1)
423 { 8, 0, -EV6HWJMPHINT,
424 AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
425 insert_ev6hwjhint, extract_ev6hwjhint }
426 };
427
428 const unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands);
429
430 /* The RB field when it is the same as the RA field in the same insn.
431 This operand is marked fake. The insertion function just copies
432 the RA field into the RB field, and the extraction function just
433 checks that the fields are the same. */
434
435 /*ARGSUSED*/
436 static unsigned
437 insert_rba(unsigned insn, int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED)
438 {
439 return insn | (((insn >> 21) & 0x1f) << 16);
440 }
441
442 static int
443 extract_rba(unsigned insn, int *invalid)
444 {
445 if (invalid != (int *) NULL
446 && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
447 *invalid = 1;
448 return 0;
449 }
450
451
452 /* The same for the RC field */
453
454 /*ARGSUSED*/
455 static unsigned
456 insert_rca(unsigned insn, int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED)
457 {
458 return insn | ((insn >> 21) & 0x1f);
459 }
460
461 static int
462 extract_rca(unsigned insn, int *invalid)
463 {
464 if (invalid != (int *) NULL
465 && ((insn >> 21) & 0x1f) != (insn & 0x1f))
466 *invalid = 1;
467 return 0;
468 }
469
470
471 /* Fake arguments in which the registers must be set to ZERO */
472
473 /*ARGSUSED*/
474 static unsigned
475 insert_za(unsigned insn, int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED)
476 {
477 return insn | (31 << 21);
478 }
479
480 static int
481 extract_za(unsigned insn, int *invalid)
482 {
483 if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31)
484 *invalid = 1;
485 return 0;
486 }
487
488 /*ARGSUSED*/
489 static unsigned
490 insert_zb(unsigned insn, int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED)
491 {
492 return insn | (31 << 16);
493 }
494
495 static int
496 extract_zb(unsigned insn, int *invalid)
497 {
498 if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31)
499 *invalid = 1;
500 return 0;
501 }
502
503 /*ARGSUSED*/
504 static unsigned
505 insert_zc(unsigned insn, int value ATTRIBUTE_UNUSED, const char **errmsg ATTRIBUTE_UNUSED)
506 {
507 return insn | 31;
508 }
509
510 static int
511 extract_zc(unsigned insn, int *invalid)
512 {
513 if (invalid != (int *) NULL && (insn & 0x1f) != 31)
514 *invalid = 1;
515 return 0;
516 }
517
518
519 /* The displacement field of a Branch format insn. */
520
521 static unsigned
522 insert_bdisp(unsigned insn, int value, const char **errmsg)
523 {
524 if (errmsg != (const char **)NULL && (value & 3))
525 *errmsg = _("branch operand unaligned");
526 return insn | ((value / 4) & 0x1FFFFF);
527 }
528
529 /*ARGSUSED*/
530 static int
531 extract_bdisp(unsigned insn, int *invalid ATTRIBUTE_UNUSED)
532 {
533 return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000);
534 }
535
536
537 /* The hint field of a JMP/JSR insn. */
538
539 static unsigned
540 insert_jhint(unsigned insn, int value, const char **errmsg)
541 {
542 if (errmsg != (const char **)NULL && (value & 3))
543 *errmsg = _("jump hint unaligned");
544 return insn | ((value / 4) & 0x3FFF);
545 }
546
547 /*ARGSUSED*/
548 static int
549 extract_jhint(unsigned insn, int *invalid ATTRIBUTE_UNUSED)
550 {
551 return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000);
552 }
553
554 /* The hint field of an EV6 HW_JMP/JSR insn. */
555
556 static unsigned
557 insert_ev6hwjhint(unsigned insn, int value, const char **errmsg)
558 {
559 if (errmsg != (const char **)NULL && (value & 3))
560 *errmsg = _("jump hint unaligned");
561 return insn | ((value / 4) & 0x1FFF);
562 }
563
564 /*ARGSUSED*/
565 static int
566 extract_ev6hwjhint(unsigned insn, int *invalid ATTRIBUTE_UNUSED)
567 {
568 return 4 * (((insn & 0x1FFF) ^ 0x1000) - 0x1000);
569 }
570
571 \f
572 /* Macros used to form opcodes */
573
574 /* The main opcode */
575 #define OP(x) (((x) & 0x3F) << 26)
576 #define OP_MASK 0xFC000000
577
578 /* Branch format instructions */
579 #define BRA_(oo) OP(oo)
580 #define BRA_MASK OP_MASK
581 #define BRA(oo) BRA_(oo), BRA_MASK
582
583 /* Floating point format instructions */
584 #define FP_(oo,fff) (OP(oo) | (((fff) & 0x7FF) << 5))
585 #define FP_MASK (OP_MASK | 0xFFE0)
586 #define FP(oo,fff) FP_(oo,fff), FP_MASK
587
588 /* Memory format instructions */
589 #define MEM_(oo) OP(oo)
590 #define MEM_MASK OP_MASK
591 #define MEM(oo) MEM_(oo), MEM_MASK
592
593 /* Memory/Func Code format instructions */
594 #define MFC_(oo,ffff) (OP(oo) | ((ffff) & 0xFFFF))
595 #define MFC_MASK (OP_MASK | 0xFFFF)
596 #define MFC(oo,ffff) MFC_(oo,ffff), MFC_MASK
597
598 /* Memory/Branch format instructions */
599 #define MBR_(oo,h) (OP(oo) | (((h) & 3) << 14))
600 #define MBR_MASK (OP_MASK | 0xC000)
601 #define MBR(oo,h) MBR_(oo,h), MBR_MASK
602
603 /* Operate format instructions. The OPRL variant specifies a
604 literal second argument. */
605 #define OPR_(oo,ff) (OP(oo) | (((ff) & 0x7F) << 5))
606 #define OPRL_(oo,ff) (OPR_((oo),(ff)) | 0x1000)
607 #define OPR_MASK (OP_MASK | 0x1FE0)
608 #define OPR(oo,ff) OPR_(oo,ff), OPR_MASK
609 #define OPRL(oo,ff) OPRL_(oo,ff), OPR_MASK
610
611 /* Generic PALcode format instructions */
612 #define PCD_(oo) OP(oo)
613 #define PCD_MASK OP_MASK
614 #define PCD(oo) PCD_(oo), PCD_MASK
615
616 /* Specific PALcode instructions */
617 #define SPCD_(oo,ffff) (OP(oo) | ((ffff) & 0x3FFFFFF))
618 #define SPCD_MASK 0xFFFFFFFF
619 #define SPCD(oo,ffff) SPCD_(oo,ffff), SPCD_MASK
620
621 /* Hardware memory (hw_{ld,st}) instructions */
622 #define EV4HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12))
623 #define EV4HWMEM_MASK (OP_MASK | 0xF000)
624 #define EV4HWMEM(oo,f) EV4HWMEM_(oo,f), EV4HWMEM_MASK
625
626 #define EV5HWMEM_(oo,f) (OP(oo) | (((f) & 0x3F) << 10))
627 #define EV5HWMEM_MASK (OP_MASK | 0xF800)
628 #define EV5HWMEM(oo,f) EV5HWMEM_(oo,f), EV5HWMEM_MASK
629
630 #define EV6HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12))
631 #define EV6HWMEM_MASK (OP_MASK | 0xF000)
632 #define EV6HWMEM(oo,f) EV6HWMEM_(oo,f), EV6HWMEM_MASK
633
634 #define EV6HWMBR_(oo,h) (OP(oo) | (((h) & 7) << 13))
635 #define EV6HWMBR_MASK (OP_MASK | 0xE000)
636 #define EV6HWMBR(oo,h) EV6HWMBR_(oo,h), EV6HWMBR_MASK
637
638 /* Abbreviations for instruction subsets. */
639 #define BASE AXP_OPCODE_BASE
640 #define EV4 AXP_OPCODE_EV4
641 #define EV5 AXP_OPCODE_EV5
642 #define EV6 AXP_OPCODE_EV6
643 #define BWX AXP_OPCODE_BWX
644 #define CIX AXP_OPCODE_CIX
645 #define MAX AXP_OPCODE_MAX
646
647 /* Common combinations of arguments */
648 #define ARG_NONE { 0 }
649 #define ARG_BRA { RA, BDISP }
650 #define ARG_FBRA { FA, BDISP }
651 #define ARG_FP { FA, FB, DFC1 }
652 #define ARG_FPZ1 { ZA, FB, DFC1 }
653 #define ARG_MEM { RA, MDISP, PRB }
654 #define ARG_FMEM { FA, MDISP, PRB }
655 #define ARG_OPR { RA, RB, DRC1 }
656 #define ARG_OPRL { RA, LIT, DRC1 }
657 #define ARG_OPRZ1 { ZA, RB, DRC1 }
658 #define ARG_OPRLZ1 { ZA, LIT, RC }
659 #define ARG_PCD { PALFN }
660 #define ARG_EV4HWMEM { RA, EV4HWDISP, PRB }
661 #define ARG_EV4HWMPR { RA, RBA, EV4HWINDEX }
662 #define ARG_EV5HWMEM { RA, EV5HWDISP, PRB }
663 #define ARG_EV6HWMEM { RA, EV6HWDISP, PRB }
664 \f
665 /* The opcode table.
666
667 The format of the opcode table is:
668
669 NAME OPCODE MASK { OPERANDS }
670
671 NAME is the name of the instruction.
672
673 OPCODE is the instruction opcode.
674
675 MASK is the opcode mask; this is used to tell the disassembler
676 which bits in the actual opcode must match OPCODE.
677
678 OPERANDS is the list of operands.
679
680 The preceding macros merge the text of the OPCODE and MASK fields.
681
682 The disassembler reads the table in order and prints the first
683 instruction which matches, so this table is sorted to put more
684 specific instructions before more general instructions.
685
686 Otherwise, it is sorted by major opcode and minor function code.
687
688 There are three classes of not-really-instructions in this table:
689
690 ALIAS is another name for another instruction. Some of
691 these come from the Architecture Handbook, some
692 come from the original gas opcode tables. In all
693 cases, the functionality of the opcode is unchanged.
694
695 PSEUDO a stylized code form endorsed by Chapter A.4 of the
696 Architecture Handbook.
697
698 EXTRA a stylized code form found in the original gas tables.
699
700 And two annotations:
701
702 EV56 BUT opcodes that are officially introduced as of the ev56,
703 but with defined results on previous implementations.
704
705 EV56 UNA opcodes that were introduced as of the ev56 with
706 presumably undefined results on previous implementations
707 that were not assigned to a particular extension.
708 */
709
710 const struct alpha_opcode alpha_opcodes[] = {
711 { "halt", SPCD(0x00,0x0000), BASE, ARG_NONE },
712 { "draina", SPCD(0x00,0x0002), BASE, ARG_NONE },
713 { "bpt", SPCD(0x00,0x0080), BASE, ARG_NONE },
714 { "bugchk", SPCD(0x00,0x0081), BASE, ARG_NONE },
715 { "callsys", SPCD(0x00,0x0083), BASE, ARG_NONE },
716 { "chmk", SPCD(0x00,0x0083), BASE, ARG_NONE },
717 { "imb", SPCD(0x00,0x0086), BASE, ARG_NONE },
718 { "rduniq", SPCD(0x00,0x009e), BASE, ARG_NONE },
719 { "wruniq", SPCD(0x00,0x009f), BASE, ARG_NONE },
720 { "gentrap", SPCD(0x00,0x00aa), BASE, ARG_NONE },
721 { "call_pal", PCD(0x00), BASE, ARG_PCD },
722 { "pal", PCD(0x00), BASE, ARG_PCD }, /* alias */
723
724 { "lda", MEM(0x08), BASE, { RA, MDISP, ZB } }, /* pseudo */
725 { "lda", MEM(0x08), BASE, ARG_MEM },
726 { "ldah", MEM(0x09), BASE, { RA, MDISP, ZB } }, /* pseudo */
727 { "ldah", MEM(0x09), BASE, ARG_MEM },
728 { "ldbu", MEM(0x0A), BWX, ARG_MEM },
729 { "unop", MEM_(0x0B) | (30 << 16),
730 MEM_MASK, BASE, { ZA } }, /* pseudo */
731 { "ldq_u", MEM(0x0B), BASE, ARG_MEM },
732 { "ldwu", MEM(0x0C), BWX, ARG_MEM },
733 { "stw", MEM(0x0D), BWX, ARG_MEM },
734 { "stb", MEM(0x0E), BWX, ARG_MEM },
735 { "stq_u", MEM(0x0F), BASE, ARG_MEM },
736
737 { "sextl", OPR(0x10,0x00), BASE, ARG_OPRZ1 }, /* pseudo */
738 { "sextl", OPRL(0x10,0x00), BASE, ARG_OPRLZ1 }, /* pseudo */
739 { "addl", OPR(0x10,0x00), BASE, ARG_OPR },
740 { "addl", OPRL(0x10,0x00), BASE, ARG_OPRL },
741 { "s4addl", OPR(0x10,0x02), BASE, ARG_OPR },
742 { "s4addl", OPRL(0x10,0x02), BASE, ARG_OPRL },
743 { "negl", OPR(0x10,0x09), BASE, ARG_OPRZ1 }, /* pseudo */
744 { "negl", OPRL(0x10,0x09), BASE, ARG_OPRLZ1 }, /* pseudo */
745 { "subl", OPR(0x10,0x09), BASE, ARG_OPR },
746 { "subl", OPRL(0x10,0x09), BASE, ARG_OPRL },
747 { "s4subl", OPR(0x10,0x0B), BASE, ARG_OPR },
748 { "s4subl", OPRL(0x10,0x0B), BASE, ARG_OPRL },
749 { "cmpbge", OPR(0x10,0x0F), BASE, ARG_OPR },
750 { "cmpbge", OPRL(0x10,0x0F), BASE, ARG_OPRL },
751 { "s8addl", OPR(0x10,0x12), BASE, ARG_OPR },
752 { "s8addl", OPRL(0x10,0x12), BASE, ARG_OPRL },
753 { "s8subl", OPR(0x10,0x1B), BASE, ARG_OPR },
754 { "s8subl", OPRL(0x10,0x1B), BASE, ARG_OPRL },
755 { "cmpult", OPR(0x10,0x1D), BASE, ARG_OPR },
756 { "cmpult", OPRL(0x10,0x1D), BASE, ARG_OPRL },
757 { "addq", OPR(0x10,0x20), BASE, ARG_OPR },
758 { "addq", OPRL(0x10,0x20), BASE, ARG_OPRL },
759 { "s4addq", OPR(0x10,0x22), BASE, ARG_OPR },
760 { "s4addq", OPRL(0x10,0x22), BASE, ARG_OPRL },
761 { "negq", OPR(0x10,0x29), BASE, ARG_OPRZ1 }, /* pseudo */
762 { "negq", OPRL(0x10,0x29), BASE, ARG_OPRLZ1 }, /* pseudo */
763 { "subq", OPR(0x10,0x29), BASE, ARG_OPR },
764 { "subq", OPRL(0x10,0x29), BASE, ARG_OPRL },
765 { "s4subq", OPR(0x10,0x2B), BASE, ARG_OPR },
766 { "s4subq", OPRL(0x10,0x2B), BASE, ARG_OPRL },
767 { "cmpeq", OPR(0x10,0x2D), BASE, ARG_OPR },
768 { "cmpeq", OPRL(0x10,0x2D), BASE, ARG_OPRL },
769 { "s8addq", OPR(0x10,0x32), BASE, ARG_OPR },
770 { "s8addq", OPRL(0x10,0x32), BASE, ARG_OPRL },
771 { "s8subq", OPR(0x10,0x3B), BASE, ARG_OPR },
772 { "s8subq", OPRL(0x10,0x3B), BASE, ARG_OPRL },
773 { "cmpule", OPR(0x10,0x3D), BASE, ARG_OPR },
774 { "cmpule", OPRL(0x10,0x3D), BASE, ARG_OPRL },
775 { "addl/v", OPR(0x10,0x40), BASE, ARG_OPR },
776 { "addl/v", OPRL(0x10,0x40), BASE, ARG_OPRL },
777 { "negl/v", OPR(0x10,0x49), BASE, ARG_OPRZ1 }, /* pseudo */
778 { "negl/v", OPRL(0x10,0x49), BASE, ARG_OPRLZ1 }, /* pseudo */
779 { "subl/v", OPR(0x10,0x49), BASE, ARG_OPR },
780 { "subl/v", OPRL(0x10,0x49), BASE, ARG_OPRL },
781 { "cmplt", OPR(0x10,0x4D), BASE, ARG_OPR },
782 { "cmplt", OPRL(0x10,0x4D), BASE, ARG_OPRL },
783 { "addq/v", OPR(0x10,0x60), BASE, ARG_OPR },
784 { "addq/v", OPRL(0x10,0x60), BASE, ARG_OPRL },
785 { "negq/v", OPR(0x10,0x69), BASE, ARG_OPRZ1 }, /* pseudo */
786 { "negq/v", OPRL(0x10,0x69), BASE, ARG_OPRLZ1 }, /* pseudo */
787 { "subq/v", OPR(0x10,0x69), BASE, ARG_OPR },
788 { "subq/v", OPRL(0x10,0x69), BASE, ARG_OPRL },
789 { "cmple", OPR(0x10,0x6D), BASE, ARG_OPR },
790 { "cmple", OPRL(0x10,0x6D), BASE, ARG_OPRL },
791
792 { "and", OPR(0x11,0x00), BASE, ARG_OPR },
793 { "and", OPRL(0x11,0x00), BASE, ARG_OPRL },
794 { "andnot", OPR(0x11,0x08), BASE, ARG_OPR }, /* alias */
795 { "andnot", OPRL(0x11,0x08), BASE, ARG_OPRL }, /* alias */
796 { "bic", OPR(0x11,0x08), BASE, ARG_OPR },
797 { "bic", OPRL(0x11,0x08), BASE, ARG_OPRL },
798 { "cmovlbs", OPR(0x11,0x14), BASE, ARG_OPR },
799 { "cmovlbs", OPRL(0x11,0x14), BASE, ARG_OPRL },
800 { "cmovlbc", OPR(0x11,0x16), BASE, ARG_OPR },
801 { "cmovlbc", OPRL(0x11,0x16), BASE, ARG_OPRL },
802 { "nop", OPR(0x11,0x20), BASE, { ZA, ZB, ZC } }, /* pseudo */
803 { "clr", OPR(0x11,0x20), BASE, { ZA, ZB, RC } }, /* pseudo */
804 { "mov", OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */
805 { "mov", OPR(0x11,0x20), BASE, { RA, RBA, RC } }, /* pseudo */
806 { "mov", OPRL(0x11,0x20), BASE, { ZA, LIT, RC } }, /* pseudo */
807 { "or", OPR(0x11,0x20), BASE, ARG_OPR }, /* alias */
808 { "or", OPRL(0x11,0x20), BASE, ARG_OPRL }, /* alias */
809 { "bis", OPR(0x11,0x20), BASE, ARG_OPR },
810 { "bis", OPRL(0x11,0x20), BASE, ARG_OPRL },
811 { "cmoveq", OPR(0x11,0x24), BASE, ARG_OPR },
812 { "cmoveq", OPRL(0x11,0x24), BASE, ARG_OPRL },
813 { "cmovne", OPR(0x11,0x26), BASE, ARG_OPR },
814 { "cmovne", OPRL(0x11,0x26), BASE, ARG_OPRL },
815 { "not", OPR(0x11,0x28), BASE, ARG_OPRZ1 }, /* pseudo */
816 { "not", OPRL(0x11,0x28), BASE, ARG_OPRLZ1 }, /* pseudo */
817 { "ornot", OPR(0x11,0x28), BASE, ARG_OPR },
818 { "ornot", OPRL(0x11,0x28), BASE, ARG_OPRL },
819 { "xor", OPR(0x11,0x40), BASE, ARG_OPR },
820 { "xor", OPRL(0x11,0x40), BASE, ARG_OPRL },
821 { "cmovlt", OPR(0x11,0x44), BASE, ARG_OPR },
822 { "cmovlt", OPRL(0x11,0x44), BASE, ARG_OPRL },
823 { "cmovge", OPR(0x11,0x46), BASE, ARG_OPR },
824 { "cmovge", OPRL(0x11,0x46), BASE, ARG_OPRL },
825 { "eqv", OPR(0x11,0x48), BASE, ARG_OPR },
826 { "eqv", OPRL(0x11,0x48), BASE, ARG_OPRL },
827 { "xornot", OPR(0x11,0x48), BASE, ARG_OPR }, /* alias */
828 { "xornot", OPRL(0x11,0x48), BASE, ARG_OPRL }, /* alias */
829 { "amask", OPR(0x11,0x61), BASE, ARG_OPRZ1 }, /* ev56 but */
830 { "amask", OPRL(0x11,0x61), BASE, ARG_OPRLZ1 }, /* ev56 but */
831 { "cmovle", OPR(0x11,0x64), BASE, ARG_OPR },
832 { "cmovle", OPRL(0x11,0x64), BASE, ARG_OPRL },
833 { "cmovgt", OPR(0x11,0x66), BASE, ARG_OPR },
834 { "cmovgt", OPRL(0x11,0x66), BASE, ARG_OPRL },
835 { "implver", OPRL_(0x11,0x6C)|(31<<21)|(1<<13),
836 0xFFFFFFE0, BASE, { RC } }, /* ev56 but */
837
838 { "mskbl", OPR(0x12,0x02), BASE, ARG_OPR },
839 { "mskbl", OPRL(0x12,0x02), BASE, ARG_OPRL },
840 { "extbl", OPR(0x12,0x06), BASE, ARG_OPR },
841 { "extbl", OPRL(0x12,0x06), BASE, ARG_OPRL },
842 { "insbl", OPR(0x12,0x0B), BASE, ARG_OPR },
843 { "insbl", OPRL(0x12,0x0B), BASE, ARG_OPRL },
844 { "mskwl", OPR(0x12,0x12), BASE, ARG_OPR },
845 { "mskwl", OPRL(0x12,0x12), BASE, ARG_OPRL },
846 { "extwl", OPR(0x12,0x16), BASE, ARG_OPR },
847 { "extwl", OPRL(0x12,0x16), BASE, ARG_OPRL },
848 { "inswl", OPR(0x12,0x1B), BASE, ARG_OPR },
849 { "inswl", OPRL(0x12,0x1B), BASE, ARG_OPRL },
850 { "mskll", OPR(0x12,0x22), BASE, ARG_OPR },
851 { "mskll", OPRL(0x12,0x22), BASE, ARG_OPRL },
852 { "extll", OPR(0x12,0x26), BASE, ARG_OPR },
853 { "extll", OPRL(0x12,0x26), BASE, ARG_OPRL },
854 { "insll", OPR(0x12,0x2B), BASE, ARG_OPR },
855 { "insll", OPRL(0x12,0x2B), BASE, ARG_OPRL },
856 { "zap", OPR(0x12,0x30), BASE, ARG_OPR },
857 { "zap", OPRL(0x12,0x30), BASE, ARG_OPRL },
858 { "zapnot", OPR(0x12,0x31), BASE, ARG_OPR },
859 { "zapnot", OPRL(0x12,0x31), BASE, ARG_OPRL },
860 { "mskql", OPR(0x12,0x32), BASE, ARG_OPR },
861 { "mskql", OPRL(0x12,0x32), BASE, ARG_OPRL },
862 { "srl", OPR(0x12,0x34), BASE, ARG_OPR },
863 { "srl", OPRL(0x12,0x34), BASE, ARG_OPRL },
864 { "extql", OPR(0x12,0x36), BASE, ARG_OPR },
865 { "extql", OPRL(0x12,0x36), BASE, ARG_OPRL },
866 { "sll", OPR(0x12,0x39), BASE, ARG_OPR },
867 { "sll", OPRL(0x12,0x39), BASE, ARG_OPRL },
868 { "insql", OPR(0x12,0x3B), BASE, ARG_OPR },
869 { "insql", OPRL(0x12,0x3B), BASE, ARG_OPRL },
870 { "sra", OPR(0x12,0x3C), BASE, ARG_OPR },
871 { "sra", OPRL(0x12,0x3C), BASE, ARG_OPRL },
872 { "mskwh", OPR(0x12,0x52), BASE, ARG_OPR },
873 { "mskwh", OPRL(0x12,0x52), BASE, ARG_OPRL },
874 { "inswh", OPR(0x12,0x57), BASE, ARG_OPR },
875 { "inswh", OPRL(0x12,0x57), BASE, ARG_OPRL },
876 { "extwh", OPR(0x12,0x5A), BASE, ARG_OPR },
877 { "extwh", OPRL(0x12,0x5A), BASE, ARG_OPRL },
878 { "msklh", OPR(0x12,0x62), BASE, ARG_OPR },
879 { "msklh", OPRL(0x12,0x62), BASE, ARG_OPRL },
880 { "inslh", OPR(0x12,0x67), BASE, ARG_OPR },
881 { "inslh", OPRL(0x12,0x67), BASE, ARG_OPRL },
882 { "extlh", OPR(0x12,0x6A), BASE, ARG_OPR },
883 { "extlh", OPRL(0x12,0x6A), BASE, ARG_OPRL },
884 { "mskqh", OPR(0x12,0x72), BASE, ARG_OPR },
885 { "mskqh", OPRL(0x12,0x72), BASE, ARG_OPRL },
886 { "insqh", OPR(0x12,0x77), BASE, ARG_OPR },
887 { "insqh", OPRL(0x12,0x77), BASE, ARG_OPRL },
888 { "extqh", OPR(0x12,0x7A), BASE, ARG_OPR },
889 { "extqh", OPRL(0x12,0x7A), BASE, ARG_OPRL },
890
891 { "mull", OPR(0x13,0x00), BASE, ARG_OPR },
892 { "mull", OPRL(0x13,0x00), BASE, ARG_OPRL },
893 { "mulq", OPR(0x13,0x20), BASE, ARG_OPR },
894 { "mulq", OPRL(0x13,0x20), BASE, ARG_OPRL },
895 { "umulh", OPR(0x13,0x30), BASE, ARG_OPR },
896 { "umulh", OPRL(0x13,0x30), BASE, ARG_OPRL },
897 { "mull/v", OPR(0x13,0x40), BASE, ARG_OPR },
898 { "mull/v", OPRL(0x13,0x40), BASE, ARG_OPRL },
899 { "mulq/v", OPR(0x13,0x60), BASE, ARG_OPR },
900 { "mulq/v", OPRL(0x13,0x60), BASE, ARG_OPRL },
901
902 { "itofs", FP(0x14,0x004), CIX, { RA, ZB, FC } },
903 { "sqrtf/c", FP(0x14,0x00A), CIX, ARG_FPZ1 },
904 { "sqrts/c", FP(0x14,0x00B), CIX, ARG_FPZ1 },
905 { "itoff", FP(0x14,0x014), CIX, { RA, ZB, FC } },
906 { "itoft", FP(0x14,0x024), CIX, { RA, ZB, FC } },
907 { "sqrtg/c", FP(0x14,0x02A), CIX, ARG_FPZ1 },
908 { "sqrtt/c", FP(0x14,0x02B), CIX, ARG_FPZ1 },
909 { "sqrts/m", FP(0x14,0x04B), CIX, ARG_FPZ1 },
910 { "sqrtt/m", FP(0x14,0x06B), CIX, ARG_FPZ1 },
911 { "sqrtf", FP(0x14,0x08A), CIX, ARG_FPZ1 },
912 { "sqrts", FP(0x14,0x08B), CIX, ARG_FPZ1 },
913 { "sqrtg", FP(0x14,0x0AA), CIX, ARG_FPZ1 },
914 { "sqrtt", FP(0x14,0x0AB), CIX, ARG_FPZ1 },
915 { "sqrts/d", FP(0x14,0x0CB), CIX, ARG_FPZ1 },
916 { "sqrtt/d", FP(0x14,0x0EB), CIX, ARG_FPZ1 },
917 { "sqrtf/uc", FP(0x14,0x10A), CIX, ARG_FPZ1 },
918 { "sqrts/uc", FP(0x14,0x10B), CIX, ARG_FPZ1 },
919 { "sqrtg/uc", FP(0x14,0x12A), CIX, ARG_FPZ1 },
920 { "sqrtt/uc", FP(0x14,0x12B), CIX, ARG_FPZ1 },
921 { "sqrts/um", FP(0x14,0x14B), CIX, ARG_FPZ1 },
922 { "sqrtt/um", FP(0x14,0x16B), CIX, ARG_FPZ1 },
923 { "sqrtf/u", FP(0x14,0x18A), CIX, ARG_FPZ1 },
924 { "sqrts/u", FP(0x14,0x18B), CIX, ARG_FPZ1 },
925 { "sqrtg/u", FP(0x14,0x1AA), CIX, ARG_FPZ1 },
926 { "sqrtt/u", FP(0x14,0x1AB), CIX, ARG_FPZ1 },
927 { "sqrts/ud", FP(0x14,0x1CB), CIX, ARG_FPZ1 },
928 { "sqrtt/ud", FP(0x14,0x1EB), CIX, ARG_FPZ1 },
929 { "sqrtf/sc", FP(0x14,0x40A), CIX, ARG_FPZ1 },
930 { "sqrtg/sc", FP(0x14,0x42A), CIX, ARG_FPZ1 },
931 { "sqrtf/s", FP(0x14,0x48A), CIX, ARG_FPZ1 },
932 { "sqrtg/s", FP(0x14,0x4AA), CIX, ARG_FPZ1 },
933 { "sqrtf/suc", FP(0x14,0x50A), CIX, ARG_FPZ1 },
934 { "sqrts/suc", FP(0x14,0x50B), CIX, ARG_FPZ1 },
935 { "sqrtg/suc", FP(0x14,0x52A), CIX, ARG_FPZ1 },
936 { "sqrtt/suc", FP(0x14,0x52B), CIX, ARG_FPZ1 },
937 { "sqrts/sum", FP(0x14,0x54B), CIX, ARG_FPZ1 },
938 { "sqrtt/sum", FP(0x14,0x56B), CIX, ARG_FPZ1 },
939 { "sqrtf/su", FP(0x14,0x58A), CIX, ARG_FPZ1 },
940 { "sqrts/su", FP(0x14,0x58B), CIX, ARG_FPZ1 },
941 { "sqrtg/su", FP(0x14,0x5AA), CIX, ARG_FPZ1 },
942 { "sqrtt/su", FP(0x14,0x5AB), CIX, ARG_FPZ1 },
943 { "sqrts/sud", FP(0x14,0x5CB), CIX, ARG_FPZ1 },
944 { "sqrtt/sud", FP(0x14,0x5EB), CIX, ARG_FPZ1 },
945 { "sqrts/suic", FP(0x14,0x70B), CIX, ARG_FPZ1 },
946 { "sqrtt/suic", FP(0x14,0x72B), CIX, ARG_FPZ1 },
947 { "sqrts/suim", FP(0x14,0x74B), CIX, ARG_FPZ1 },
948 { "sqrtt/suim", FP(0x14,0x76B), CIX, ARG_FPZ1 },
949 { "sqrts/sui", FP(0x14,0x78B), CIX, ARG_FPZ1 },
950 { "sqrtt/sui", FP(0x14,0x7AB), CIX, ARG_FPZ1 },
951 { "sqrts/suid", FP(0x14,0x7CB), CIX, ARG_FPZ1 },
952 { "sqrtt/suid", FP(0x14,0x7EB), CIX, ARG_FPZ1 },
953
954 { "addf/c", FP(0x15,0x000), BASE, ARG_FP },
955 { "subf/c", FP(0x15,0x001), BASE, ARG_FP },
956 { "mulf/c", FP(0x15,0x002), BASE, ARG_FP },
957 { "divf/c", FP(0x15,0x003), BASE, ARG_FP },
958 { "cvtdg/c", FP(0x15,0x01E), BASE, ARG_FPZ1 },
959 { "addg/c", FP(0x15,0x020), BASE, ARG_FP },
960 { "subg/c", FP(0x15,0x021), BASE, ARG_FP },
961 { "mulg/c", FP(0x15,0x022), BASE, ARG_FP },
962 { "divg/c", FP(0x15,0x023), BASE, ARG_FP },
963 { "cvtgf/c", FP(0x15,0x02C), BASE, ARG_FPZ1 },
964 { "cvtgd/c", FP(0x15,0x02D), BASE, ARG_FPZ1 },
965 { "cvtgq/c", FP(0x15,0x02F), BASE, ARG_FPZ1 },
966 { "cvtqf/c", FP(0x15,0x03C), BASE, ARG_FPZ1 },
967 { "cvtqg/c", FP(0x15,0x03E), BASE, ARG_FPZ1 },
968 { "addf", FP(0x15,0x080), BASE, ARG_FP },
969 { "negf", FP(0x15,0x081), BASE, ARG_FPZ1 }, /* pseudo */
970 { "subf", FP(0x15,0x081), BASE, ARG_FP },
971 { "mulf", FP(0x15,0x082), BASE, ARG_FP },
972 { "divf", FP(0x15,0x083), BASE, ARG_FP },
973 { "cvtdg", FP(0x15,0x09E), BASE, ARG_FPZ1 },
974 { "addg", FP(0x15,0x0A0), BASE, ARG_FP },
975 { "negg", FP(0x15,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */
976 { "subg", FP(0x15,0x0A1), BASE, ARG_FP },
977 { "mulg", FP(0x15,0x0A2), BASE, ARG_FP },
978 { "divg", FP(0x15,0x0A3), BASE, ARG_FP },
979 { "cmpgeq", FP(0x15,0x0A5), BASE, ARG_FP },
980 { "cmpglt", FP(0x15,0x0A6), BASE, ARG_FP },
981 { "cmpgle", FP(0x15,0x0A7), BASE, ARG_FP },
982 { "cvtgf", FP(0x15,0x0AC), BASE, ARG_FPZ1 },
983 { "cvtgd", FP(0x15,0x0AD), BASE, ARG_FPZ1 },
984 { "cvtgq", FP(0x15,0x0AF), BASE, ARG_FPZ1 },
985 { "cvtqf", FP(0x15,0x0BC), BASE, ARG_FPZ1 },
986 { "cvtqg", FP(0x15,0x0BE), BASE, ARG_FPZ1 },
987 { "addf/uc", FP(0x15,0x100), BASE, ARG_FP },
988 { "subf/uc", FP(0x15,0x101), BASE, ARG_FP },
989 { "mulf/uc", FP(0x15,0x102), BASE, ARG_FP },
990 { "divf/uc", FP(0x15,0x103), BASE, ARG_FP },
991 { "cvtdg/uc", FP(0x15,0x11E), BASE, ARG_FPZ1 },
992 { "addg/uc", FP(0x15,0x120), BASE, ARG_FP },
993 { "subg/uc", FP(0x15,0x121), BASE, ARG_FP },
994 { "mulg/uc", FP(0x15,0x122), BASE, ARG_FP },
995 { "divg/uc", FP(0x15,0x123), BASE, ARG_FP },
996 { "cvtgf/uc", FP(0x15,0x12C), BASE, ARG_FPZ1 },
997 { "cvtgd/uc", FP(0x15,0x12D), BASE, ARG_FPZ1 },
998 { "cvtgq/vc", FP(0x15,0x12F), BASE, ARG_FPZ1 },
999 { "addf/u", FP(0x15,0x180), BASE, ARG_FP },
1000 { "subf/u", FP(0x15,0x181), BASE, ARG_FP },
1001 { "mulf/u", FP(0x15,0x182), BASE, ARG_FP },
1002 { "divf/u", FP(0x15,0x183), BASE, ARG_FP },
1003 { "cvtdg/u", FP(0x15,0x19E), BASE, ARG_FPZ1 },
1004 { "addg/u", FP(0x15,0x1A0), BASE, ARG_FP },
1005 { "subg/u", FP(0x15,0x1A1), BASE, ARG_FP },
1006 { "mulg/u", FP(0x15,0x1A2), BASE, ARG_FP },
1007 { "divg/u", FP(0x15,0x1A3), BASE, ARG_FP },
1008 { "cvtgf/u", FP(0x15,0x1AC), BASE, ARG_FPZ1 },
1009 { "cvtgd/u", FP(0x15,0x1AD), BASE, ARG_FPZ1 },
1010 { "cvtgq/v", FP(0x15,0x1AF), BASE, ARG_FPZ1 },
1011 { "addf/sc", FP(0x15,0x400), BASE, ARG_FP },
1012 { "subf/sc", FP(0x15,0x401), BASE, ARG_FP },
1013 { "mulf/sc", FP(0x15,0x402), BASE, ARG_FP },
1014 { "divf/sc", FP(0x15,0x403), BASE, ARG_FP },
1015 { "cvtdg/sc", FP(0x15,0x41E), BASE, ARG_FPZ1 },
1016 { "addg/sc", FP(0x15,0x420), BASE, ARG_FP },
1017 { "subg/sc", FP(0x15,0x421), BASE, ARG_FP },
1018 { "mulg/sc", FP(0x15,0x422), BASE, ARG_FP },
1019 { "divg/sc", FP(0x15,0x423), BASE, ARG_FP },
1020 { "cvtgf/sc", FP(0x15,0x42C), BASE, ARG_FPZ1 },
1021 { "cvtgd/sc", FP(0x15,0x42D), BASE, ARG_FPZ1 },
1022 { "cvtgq/sc", FP(0x15,0x42F), BASE, ARG_FPZ1 },
1023 { "addf/s", FP(0x15,0x480), BASE, ARG_FP },
1024 { "negf/s", FP(0x15,0x481), BASE, ARG_FPZ1 }, /* pseudo */
1025 { "subf/s", FP(0x15,0x481), BASE, ARG_FP },
1026 { "mulf/s", FP(0x15,0x482), BASE, ARG_FP },
1027 { "divf/s", FP(0x15,0x483), BASE, ARG_FP },
1028 { "cvtdg/s", FP(0x15,0x49E), BASE, ARG_FPZ1 },
1029 { "addg/s", FP(0x15,0x4A0), BASE, ARG_FP },
1030 { "negg/s", FP(0x15,0x4A1), BASE, ARG_FPZ1 }, /* pseudo */
1031 { "subg/s", FP(0x15,0x4A1), BASE, ARG_FP },
1032 { "mulg/s", FP(0x15,0x4A2), BASE, ARG_FP },
1033 { "divg/s", FP(0x15,0x4A3), BASE, ARG_FP },
1034 { "cmpgeq/s", FP(0x15,0x4A5), BASE, ARG_FP },
1035 { "cmpglt/s", FP(0x15,0x4A6), BASE, ARG_FP },
1036 { "cmpgle/s", FP(0x15,0x4A7), BASE, ARG_FP },
1037 { "cvtgf/s", FP(0x15,0x4AC), BASE, ARG_FPZ1 },
1038 { "cvtgd/s", FP(0x15,0x4AD), BASE, ARG_FPZ1 },
1039 { "cvtgq/s", FP(0x15,0x4AF), BASE, ARG_FPZ1 },
1040 { "addf/suc", FP(0x15,0x500), BASE, ARG_FP },
1041 { "subf/suc", FP(0x15,0x501), BASE, ARG_FP },
1042 { "mulf/suc", FP(0x15,0x502), BASE, ARG_FP },
1043 { "divf/suc", FP(0x15,0x503), BASE, ARG_FP },
1044 { "cvtdg/suc", FP(0x15,0x51E), BASE, ARG_FPZ1 },
1045 { "addg/suc", FP(0x15,0x520), BASE, ARG_FP },
1046 { "subg/suc", FP(0x15,0x521), BASE, ARG_FP },
1047 { "mulg/suc", FP(0x15,0x522), BASE, ARG_FP },
1048 { "divg/suc", FP(0x15,0x523), BASE, ARG_FP },
1049 { "cvtgf/suc", FP(0x15,0x52C), BASE, ARG_FPZ1 },
1050 { "cvtgd/suc", FP(0x15,0x52D), BASE, ARG_FPZ1 },
1051 { "cvtgq/svc", FP(0x15,0x52F), BASE, ARG_FPZ1 },
1052 { "addf/su", FP(0x15,0x580), BASE, ARG_FP },
1053 { "subf/su", FP(0x15,0x581), BASE, ARG_FP },
1054 { "mulf/su", FP(0x15,0x582), BASE, ARG_FP },
1055 { "divf/su", FP(0x15,0x583), BASE, ARG_FP },
1056 { "cvtdg/su", FP(0x15,0x59E), BASE, ARG_FPZ1 },
1057 { "addg/su", FP(0x15,0x5A0), BASE, ARG_FP },
1058 { "subg/su", FP(0x15,0x5A1), BASE, ARG_FP },
1059 { "mulg/su", FP(0x15,0x5A2), BASE, ARG_FP },
1060 { "divg/su", FP(0x15,0x5A3), BASE, ARG_FP },
1061 { "cvtgf/su", FP(0x15,0x5AC), BASE, ARG_FPZ1 },
1062 { "cvtgd/su", FP(0x15,0x5AD), BASE, ARG_FPZ1 },
1063 { "cvtgq/sv", FP(0x15,0x5AF), BASE, ARG_FPZ1 },
1064
1065 { "adds/c", FP(0x16,0x000), BASE, ARG_FP },
1066 { "subs/c", FP(0x16,0x001), BASE, ARG_FP },
1067 { "muls/c", FP(0x16,0x002), BASE, ARG_FP },
1068 { "divs/c", FP(0x16,0x003), BASE, ARG_FP },
1069 { "addt/c", FP(0x16,0x020), BASE, ARG_FP },
1070 { "subt/c", FP(0x16,0x021), BASE, ARG_FP },
1071 { "mult/c", FP(0x16,0x022), BASE, ARG_FP },
1072 { "divt/c", FP(0x16,0x023), BASE, ARG_FP },
1073 { "cvtts/c", FP(0x16,0x02C), BASE, ARG_FPZ1 },
1074 { "cvttq/c", FP(0x16,0x02F), BASE, ARG_FPZ1 },
1075 { "cvtqs/c", FP(0x16,0x03C), BASE, ARG_FPZ1 },
1076 { "cvtqt/c", FP(0x16,0x03E), BASE, ARG_FPZ1 },
1077 { "adds/m", FP(0x16,0x040), BASE, ARG_FP },
1078 { "subs/m", FP(0x16,0x041), BASE, ARG_FP },
1079 { "muls/m", FP(0x16,0x042), BASE, ARG_FP },
1080 { "divs/m", FP(0x16,0x043), BASE, ARG_FP },
1081 { "addt/m", FP(0x16,0x060), BASE, ARG_FP },
1082 { "subt/m", FP(0x16,0x061), BASE, ARG_FP },
1083 { "mult/m", FP(0x16,0x062), BASE, ARG_FP },
1084 { "divt/m", FP(0x16,0x063), BASE, ARG_FP },
1085 { "cvtts/m", FP(0x16,0x06C), BASE, ARG_FPZ1 },
1086 { "cvttq/m", FP(0x16,0x06F), BASE, ARG_FPZ1 },
1087 { "cvtqs/m", FP(0x16,0x07C), BASE, ARG_FPZ1 },
1088 { "cvtqt/m", FP(0x16,0x07E), BASE, ARG_FPZ1 },
1089 { "adds", FP(0x16,0x080), BASE, ARG_FP },
1090 { "negs", FP(0x16,0x081), BASE, ARG_FPZ1 }, /* pseudo */
1091 { "subs", FP(0x16,0x081), BASE, ARG_FP },
1092 { "muls", FP(0x16,0x082), BASE, ARG_FP },
1093 { "divs", FP(0x16,0x083), BASE, ARG_FP },
1094 { "addt", FP(0x16,0x0A0), BASE, ARG_FP },
1095 { "negt", FP(0x16,0x0A1), BASE, ARG_FPZ1 }, /* pseudo */
1096 { "subt", FP(0x16,0x0A1), BASE, ARG_FP },
1097 { "mult", FP(0x16,0x0A2), BASE, ARG_FP },
1098 { "divt", FP(0x16,0x0A3), BASE, ARG_FP },
1099 { "cmptun", FP(0x16,0x0A4), BASE, ARG_FP },
1100 { "cmpteq", FP(0x16,0x0A5), BASE, ARG_FP },
1101 { "cmptlt", FP(0x16,0x0A6), BASE, ARG_FP },
1102 { "cmptle", FP(0x16,0x0A7), BASE, ARG_FP },
1103 { "cvtts", FP(0x16,0x0AC), BASE, ARG_FPZ1 },
1104 { "cvttq", FP(0x16,0x0AF), BASE, ARG_FPZ1 },
1105 { "cvtqs", FP(0x16,0x0BC), BASE, ARG_FPZ1 },
1106 { "cvtqt", FP(0x16,0x0BE), BASE, ARG_FPZ1 },
1107 { "adds/d", FP(0x16,0x0C0), BASE, ARG_FP },
1108 { "subs/d", FP(0x16,0x0C1), BASE, ARG_FP },
1109 { "muls/d", FP(0x16,0x0C2), BASE, ARG_FP },
1110 { "divs/d", FP(0x16,0x0C3), BASE, ARG_FP },
1111 { "addt/d", FP(0x16,0x0E0), BASE, ARG_FP },
1112 { "subt/d", FP(0x16,0x0E1), BASE, ARG_FP },
1113 { "mult/d", FP(0x16,0x0E2), BASE, ARG_FP },
1114 { "divt/d", FP(0x16,0x0E3), BASE, ARG_FP },
1115 { "cvtts/d", FP(0x16,0x0EC), BASE, ARG_FPZ1 },
1116 { "cvttq/d", FP(0x16,0x0EF), BASE, ARG_FPZ1 },
1117 { "cvtqs/d", FP(0x16,0x0FC), BASE, ARG_FPZ1 },
1118 { "cvtqt/d", FP(0x16,0x0FE), BASE, ARG_FPZ1 },
1119 { "adds/uc", FP(0x16,0x100), BASE, ARG_FP },
1120 { "subs/uc", FP(0x16,0x101), BASE, ARG_FP },
1121 { "muls/uc", FP(0x16,0x102), BASE, ARG_FP },
1122 { "divs/uc", FP(0x16,0x103), BASE, ARG_FP },
1123 { "addt/uc", FP(0x16,0x120), BASE, ARG_FP },
1124 { "subt/uc", FP(0x16,0x121), BASE, ARG_FP },
1125 { "mult/uc", FP(0x16,0x122), BASE, ARG_FP },
1126 { "divt/uc", FP(0x16,0x123), BASE, ARG_FP },
1127 { "cvtts/uc", FP(0x16,0x12C), BASE, ARG_FPZ1 },
1128 { "cvttq/vc", FP(0x16,0x12F), BASE, ARG_FPZ1 },
1129 { "adds/um", FP(0x16,0x140), BASE, ARG_FP },
1130 { "subs/um", FP(0x16,0x141), BASE, ARG_FP },
1131 { "muls/um", FP(0x16,0x142), BASE, ARG_FP },
1132 { "divs/um", FP(0x16,0x143), BASE, ARG_FP },
1133 { "addt/um", FP(0x16,0x160), BASE, ARG_FP },
1134 { "subt/um", FP(0x16,0x161), BASE, ARG_FP },
1135 { "mult/um", FP(0x16,0x162), BASE, ARG_FP },
1136 { "divt/um", FP(0x16,0x163), BASE, ARG_FP },
1137 { "cvtts/um", FP(0x16,0x16C), BASE, ARG_FPZ1 },
1138 { "cvttq/vm", FP(0x16,0x16F), BASE, ARG_FPZ1 },
1139 { "adds/u", FP(0x16,0x180), BASE, ARG_FP },
1140 { "subs/u", FP(0x16,0x181), BASE, ARG_FP },
1141 { "muls/u", FP(0x16,0x182), BASE, ARG_FP },
1142 { "divs/u", FP(0x16,0x183), BASE, ARG_FP },
1143 { "addt/u", FP(0x16,0x1A0), BASE, ARG_FP },
1144 { "subt/u", FP(0x16,0x1A1), BASE, ARG_FP },
1145 { "mult/u", FP(0x16,0x1A2), BASE, ARG_FP },
1146 { "divt/u", FP(0x16,0x1A3), BASE, ARG_FP },
1147 { "cvtts/u", FP(0x16,0x1AC), BASE, ARG_FPZ1 },
1148 { "cvttq/v", FP(0x16,0x1AF), BASE, ARG_FPZ1 },
1149 { "adds/ud", FP(0x16,0x1C0), BASE, ARG_FP },
1150 { "subs/ud", FP(0x16,0x1C1), BASE, ARG_FP },
1151 { "muls/ud", FP(0x16,0x1C2), BASE, ARG_FP },
1152 { "divs/ud", FP(0x16,0x1C3), BASE, ARG_FP },
1153 { "addt/ud", FP(0x16,0x1E0), BASE, ARG_FP },
1154 { "subt/ud", FP(0x16,0x1E1), BASE, ARG_FP },
1155 { "mult/ud", FP(0x16,0x1E2), BASE, ARG_FP },
1156 { "divt/ud", FP(0x16,0x1E3), BASE, ARG_FP },
1157 { "cvtts/ud", FP(0x16,0x1EC), BASE, ARG_FPZ1 },
1158 { "cvttq/vd", FP(0x16,0x1EF), BASE, ARG_FPZ1 },
1159 { "cvtst", FP(0x16,0x2AC), BASE, ARG_FPZ1 },
1160 { "adds/suc", FP(0x16,0x500), BASE, ARG_FP },
1161 { "subs/suc", FP(0x16,0x501), BASE, ARG_FP },
1162 { "muls/suc", FP(0x16,0x502), BASE, ARG_FP },
1163 { "divs/suc", FP(0x16,0x503), BASE, ARG_FP },
1164 { "addt/suc", FP(0x16,0x520), BASE, ARG_FP },
1165 { "subt/suc", FP(0x16,0x521), BASE, ARG_FP },
1166 { "mult/suc", FP(0x16,0x522), BASE, ARG_FP },
1167 { "divt/suc", FP(0x16,0x523), BASE, ARG_FP },
1168 { "cvtts/suc", FP(0x16,0x52C), BASE, ARG_FPZ1 },
1169 { "cvttq/svc", FP(0x16,0x52F), BASE, ARG_FPZ1 },
1170 { "adds/sum", FP(0x16,0x540), BASE, ARG_FP },
1171 { "subs/sum", FP(0x16,0x541), BASE, ARG_FP },
1172 { "muls/sum", FP(0x16,0x542), BASE, ARG_FP },
1173 { "divs/sum", FP(0x16,0x543), BASE, ARG_FP },
1174 { "addt/sum", FP(0x16,0x560), BASE, ARG_FP },
1175 { "subt/sum", FP(0x16,0x561), BASE, ARG_FP },
1176 { "mult/sum", FP(0x16,0x562), BASE, ARG_FP },
1177 { "divt/sum", FP(0x16,0x563), BASE, ARG_FP },
1178 { "cvtts/sum", FP(0x16,0x56C), BASE, ARG_FPZ1 },
1179 { "cvttq/svm", FP(0x16,0x56F), BASE, ARG_FPZ1 },
1180 { "adds/su", FP(0x16,0x580), BASE, ARG_FP },
1181 { "negs/su", FP(0x16,0x581), BASE, ARG_FPZ1 }, /* pseudo */
1182 { "subs/su", FP(0x16,0x581), BASE, ARG_FP },
1183 { "muls/su", FP(0x16,0x582), BASE, ARG_FP },
1184 { "divs/su", FP(0x16,0x583), BASE, ARG_FP },
1185 { "addt/su", FP(0x16,0x5A0), BASE, ARG_FP },
1186 { "negt/su", FP(0x16,0x5A1), BASE, ARG_FPZ1 }, /* pseudo */
1187 { "subt/su", FP(0x16,0x5A1), BASE, ARG_FP },
1188 { "mult/su", FP(0x16,0x5A2), BASE, ARG_FP },
1189 { "divt/su", FP(0x16,0x5A3), BASE, ARG_FP },
1190 { "cmptun/su", FP(0x16,0x5A4), BASE, ARG_FP },
1191 { "cmpteq/su", FP(0x16,0x5A5), BASE, ARG_FP },
1192 { "cmptlt/su", FP(0x16,0x5A6), BASE, ARG_FP },
1193 { "cmptle/su", FP(0x16,0x5A7), BASE, ARG_FP },
1194 { "cvtts/su", FP(0x16,0x5AC), BASE, ARG_FPZ1 },
1195 { "cvttq/sv", FP(0x16,0x5AF), BASE, ARG_FPZ1 },
1196 { "adds/sud", FP(0x16,0x5C0), BASE, ARG_FP },
1197 { "subs/sud", FP(0x16,0x5C1), BASE, ARG_FP },
1198 { "muls/sud", FP(0x16,0x5C2), BASE, ARG_FP },
1199 { "divs/sud", FP(0x16,0x5C3), BASE, ARG_FP },
1200 { "addt/sud", FP(0x16,0x5E0), BASE, ARG_FP },
1201 { "subt/sud", FP(0x16,0x5E1), BASE, ARG_FP },
1202 { "mult/sud", FP(0x16,0x5E2), BASE, ARG_FP },
1203 { "divt/sud", FP(0x16,0x5E3), BASE, ARG_FP },
1204 { "cvtts/sud", FP(0x16,0x5EC), BASE, ARG_FPZ1 },
1205 { "cvttq/svd", FP(0x16,0x5EF), BASE, ARG_FPZ1 },
1206 { "cvtst/s", FP(0x16,0x6AC), BASE, ARG_FPZ1 },
1207 { "adds/suic", FP(0x16,0x700), BASE, ARG_FP },
1208 { "subs/suic", FP(0x16,0x701), BASE, ARG_FP },
1209 { "muls/suic", FP(0x16,0x702), BASE, ARG_FP },
1210 { "divs/suic", FP(0x16,0x703), BASE, ARG_FP },
1211 { "addt/suic", FP(0x16,0x720), BASE, ARG_FP },
1212 { "subt/suic", FP(0x16,0x721), BASE, ARG_FP },
1213 { "mult/suic", FP(0x16,0x722), BASE, ARG_FP },
1214 { "divt/suic", FP(0x16,0x723), BASE, ARG_FP },
1215 { "cvtts/suic", FP(0x16,0x72C), BASE, ARG_FPZ1 },
1216 { "cvttq/svic", FP(0x16,0x72F), BASE, ARG_FPZ1 },
1217 { "cvtqs/suic", FP(0x16,0x73C), BASE, ARG_FPZ1 },
1218 { "cvtqt/suic", FP(0x16,0x73E), BASE, ARG_FPZ1 },
1219 { "adds/suim", FP(0x16,0x740), BASE, ARG_FP },
1220 { "subs/suim", FP(0x16,0x741), BASE, ARG_FP },
1221 { "muls/suim", FP(0x16,0x742), BASE, ARG_FP },
1222 { "divs/suim", FP(0x16,0x743), BASE, ARG_FP },
1223 { "addt/suim", FP(0x16,0x760), BASE, ARG_FP },
1224 { "subt/suim", FP(0x16,0x761), BASE, ARG_FP },
1225 { "mult/suim", FP(0x16,0x762), BASE, ARG_FP },
1226 { "divt/suim", FP(0x16,0x763), BASE, ARG_FP },
1227 { "cvtts/suim", FP(0x16,0x76C), BASE, ARG_FPZ1 },
1228 { "cvttq/svim", FP(0x16,0x76F), BASE, ARG_FPZ1 },
1229 { "cvtqs/suim", FP(0x16,0x77C), BASE, ARG_FPZ1 },
1230 { "cvtqt/suim", FP(0x16,0x77E), BASE, ARG_FPZ1 },
1231 { "adds/sui", FP(0x16,0x780), BASE, ARG_FP },
1232 { "negs/sui", FP(0x16,0x781), BASE, ARG_FPZ1 }, /* pseudo */
1233 { "subs/sui", FP(0x16,0x781), BASE, ARG_FP },
1234 { "muls/sui", FP(0x16,0x782), BASE, ARG_FP },
1235 { "divs/sui", FP(0x16,0x783), BASE, ARG_FP },
1236 { "addt/sui", FP(0x16,0x7A0), BASE, ARG_FP },
1237 { "negt/sui", FP(0x16,0x7A1), BASE, ARG_FPZ1 }, /* pseudo */
1238 { "subt/sui", FP(0x16,0x7A1), BASE, ARG_FP },
1239 { "mult/sui", FP(0x16,0x7A2), BASE, ARG_FP },
1240 { "divt/sui", FP(0x16,0x7A3), BASE, ARG_FP },
1241 { "cvtts/sui", FP(0x16,0x7AC), BASE, ARG_FPZ1 },
1242 { "cvttq/svi", FP(0x16,0x7AF), BASE, ARG_FPZ1 },
1243 { "cvtqs/sui", FP(0x16,0x7BC), BASE, ARG_FPZ1 },
1244 { "cvtqt/sui", FP(0x16,0x7BE), BASE, ARG_FPZ1 },
1245 { "adds/suid", FP(0x16,0x7C0), BASE, ARG_FP },
1246 { "subs/suid", FP(0x16,0x7C1), BASE, ARG_FP },
1247 { "muls/suid", FP(0x16,0x7C2), BASE, ARG_FP },
1248 { "divs/suid", FP(0x16,0x7C3), BASE, ARG_FP },
1249 { "addt/suid", FP(0x16,0x7E0), BASE, ARG_FP },
1250 { "subt/suid", FP(0x16,0x7E1), BASE, ARG_FP },
1251 { "mult/suid", FP(0x16,0x7E2), BASE, ARG_FP },
1252 { "divt/suid", FP(0x16,0x7E3), BASE, ARG_FP },
1253 { "cvtts/suid", FP(0x16,0x7EC), BASE, ARG_FPZ1 },
1254 { "cvttq/svid", FP(0x16,0x7EF), BASE, ARG_FPZ1 },
1255 { "cvtqs/suid", FP(0x16,0x7FC), BASE, ARG_FPZ1 },
1256 { "cvtqt/suid", FP(0x16,0x7FE), BASE, ARG_FPZ1 },
1257
1258 { "cvtlq", FP(0x17,0x010), BASE, ARG_FPZ1 },
1259 { "fnop", FP(0x17,0x020), BASE, { ZA, ZB, ZC } }, /* pseudo */
1260 { "fclr", FP(0x17,0x020), BASE, { ZA, ZB, FC } }, /* pseudo */
1261 { "fabs", FP(0x17,0x020), BASE, ARG_FPZ1 }, /* pseudo */
1262 { "fmov", FP(0x17,0x020), BASE, { FA, RBA, FC } }, /* pseudo */
1263 { "cpys", FP(0x17,0x020), BASE, ARG_FP },
1264 { "fneg", FP(0x17,0x021), BASE, { FA, RBA, FC } }, /* pseudo */
1265 { "cpysn", FP(0x17,0x021), BASE, ARG_FP },
1266 { "cpyse", FP(0x17,0x022), BASE, ARG_FP },
1267 { "mt_fpcr", FP(0x17,0x024), BASE, { FA, RBA, RCA } },
1268 { "mf_fpcr", FP(0x17,0x025), BASE, { FA, RBA, RCA } },
1269 { "fcmoveq", FP(0x17,0x02A), BASE, ARG_FP },
1270 { "fcmovne", FP(0x17,0x02B), BASE, ARG_FP },
1271 { "fcmovlt", FP(0x17,0x02C), BASE, ARG_FP },
1272 { "fcmovge", FP(0x17,0x02D), BASE, ARG_FP },
1273 { "fcmovle", FP(0x17,0x02E), BASE, ARG_FP },
1274 { "fcmovgt", FP(0x17,0x02F), BASE, ARG_FP },
1275 { "cvtql", FP(0x17,0x030), BASE, ARG_FPZ1 },
1276 { "cvtql/v", FP(0x17,0x130), BASE, ARG_FPZ1 },
1277 { "cvtql/sv", FP(0x17,0x530), BASE, ARG_FPZ1 },
1278
1279 { "trapb", MFC(0x18,0x0000), BASE, ARG_NONE },
1280 { "draint", MFC(0x18,0x0000), BASE, ARG_NONE }, /* alias */
1281 { "excb", MFC(0x18,0x0400), BASE, ARG_NONE },
1282 { "mb", MFC(0x18,0x4000), BASE, ARG_NONE },
1283 { "wmb", MFC(0x18,0x4400), BASE, ARG_NONE },
1284 { "fetch", MFC(0x18,0x8000), BASE, { ZA, PRB } },
1285 { "fetch_m", MFC(0x18,0xA000), BASE, { ZA, PRB } },
1286 { "rpcc", MFC(0x18,0xC000), BASE, { RA } },
1287 { "rc", MFC(0x18,0xE000), BASE, { RA } },
1288 { "ecb", MFC(0x18,0xE800), BASE, { ZA, PRB } }, /* ev56 una */
1289 { "rs", MFC(0x18,0xF000), BASE, { RA } },
1290 { "wh64", MFC(0x18,0xF800), BASE, { ZA, PRB } }, /* ev56 una */
1291 { "wh64en", MFC(0x18,0xFC00), BASE, { ZA, PRB } }, /* ev7 una */
1292
1293 { "hw_mfpr", OPR(0x19,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } },
1294 { "hw_mfpr", OP(0x19), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } },
1295 { "hw_mfpr", OP(0x19), OP_MASK, EV6, { RA, ZB, EV6HWINDEX } },
1296 { "hw_mfpr/i", OPR(0x19,0x01), EV4, ARG_EV4HWMPR },
1297 { "hw_mfpr/a", OPR(0x19,0x02), EV4, ARG_EV4HWMPR },
1298 { "hw_mfpr/ai", OPR(0x19,0x03), EV4, ARG_EV4HWMPR },
1299 { "hw_mfpr/p", OPR(0x19,0x04), EV4, ARG_EV4HWMPR },
1300 { "hw_mfpr/pi", OPR(0x19,0x05), EV4, ARG_EV4HWMPR },
1301 { "hw_mfpr/pa", OPR(0x19,0x06), EV4, ARG_EV4HWMPR },
1302 { "hw_mfpr/pai", OPR(0x19,0x07), EV4, ARG_EV4HWMPR },
1303 { "pal19", PCD(0x19), BASE, ARG_PCD },
1304
1305 { "jmp", MBR_(0x1A,0), MBR_MASK | 0x3FFF, /* pseudo */
1306 BASE, { ZA, CPRB } },
1307 { "jmp", MBR(0x1A,0), BASE, { RA, CPRB, JMPHINT } },
1308 { "jsr", MBR(0x1A,1), BASE, { RA, CPRB, JMPHINT } },
1309 { "ret", MBR_(0x1A,2) | (31 << 21) | (26 << 16) | 1,/* pseudo */
1310 0xFFFFFFFF, BASE, { 0 } },
1311 { "ret", MBR(0x1A,2), BASE, { RA, CPRB, RETHINT } },
1312 { "jcr", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, /* alias */
1313 { "jsr_coroutine", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } },
1314
1315 { "hw_ldl", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM },
1316 { "hw_ldl", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM },
1317 { "hw_ldl", EV6HWMEM(0x1B,0x8), EV6, ARG_EV6HWMEM },
1318 { "hw_ldl/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM },
1319 { "hw_ldl/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM },
1320 { "hw_ldl/a", EV6HWMEM(0x1B,0xC), EV6, ARG_EV6HWMEM },
1321 { "hw_ldl/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
1322 { "hw_ldl/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM },
1323 { "hw_ldl/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM },
1324 { "hw_ldl/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
1325 { "hw_ldl/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM },
1326 { "hw_ldl/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
1327 { "hw_ldl/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM },
1328 { "hw_ldl/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
1329 { "hw_ldl/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
1330 { "hw_ldl/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM },
1331 { "hw_ldl/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM },
1332 { "hw_ldl/p", EV6HWMEM(0x1B,0x0), EV6, ARG_EV6HWMEM },
1333 { "hw_ldl/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM },
1334 { "hw_ldl/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM },
1335 { "hw_ldl/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
1336 { "hw_ldl/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM },
1337 { "hw_ldl/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM },
1338 { "hw_ldl/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
1339 { "hw_ldl/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM },
1340 { "hw_ldl/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
1341 { "hw_ldl/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM },
1342 { "hw_ldl/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
1343 { "hw_ldl/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
1344 { "hw_ldl/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM },
1345 { "hw_ldl/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM },
1346 { "hw_ldl/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
1347 { "hw_ldl/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM },
1348 { "hw_ldl/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
1349 { "hw_ldl/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM },
1350 { "hw_ldl/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
1351 { "hw_ldl/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM },
1352 { "hw_ldl/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM },
1353 { "hw_ldl/v", EV6HWMEM(0x1B,0x4), EV6, ARG_EV6HWMEM },
1354 { "hw_ldl/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
1355 { "hw_ldl/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM },
1356 { "hw_ldl/w", EV6HWMEM(0x1B,0xA), EV6, ARG_EV6HWMEM },
1357 { "hw_ldl/wa", EV6HWMEM(0x1B,0xE), EV6, ARG_EV6HWMEM },
1358 { "hw_ldl/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
1359 { "hw_ldl/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM },
1360 { "hw_ldl/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
1361 { "hw_ldl_l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
1362 { "hw_ldl_l/a", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
1363 { "hw_ldl_l/av", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
1364 { "hw_ldl_l/aw", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
1365 { "hw_ldl_l/awv", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
1366 { "hw_ldl_l/p", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
1367 { "hw_ldl_l/p", EV6HWMEM(0x1B,0x2), EV6, ARG_EV6HWMEM },
1368 { "hw_ldl_l/pa", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
1369 { "hw_ldl_l/pav", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
1370 { "hw_ldl_l/paw", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
1371 { "hw_ldl_l/pawv", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
1372 { "hw_ldl_l/pv", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
1373 { "hw_ldl_l/pw", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
1374 { "hw_ldl_l/pwv", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
1375 { "hw_ldl_l/v", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
1376 { "hw_ldl_l/w", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
1377 { "hw_ldl_l/wv", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
1378 { "hw_ldq", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM },
1379 { "hw_ldq", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM },
1380 { "hw_ldq", EV6HWMEM(0x1B,0x9), EV6, ARG_EV6HWMEM },
1381 { "hw_ldq/a", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM },
1382 { "hw_ldq/a", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM },
1383 { "hw_ldq/a", EV6HWMEM(0x1B,0xD), EV6, ARG_EV6HWMEM },
1384 { "hw_ldq/al", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
1385 { "hw_ldq/ar", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM },
1386 { "hw_ldq/av", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM },
1387 { "hw_ldq/avl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
1388 { "hw_ldq/aw", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM },
1389 { "hw_ldq/awl", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
1390 { "hw_ldq/awv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM },
1391 { "hw_ldq/awvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
1392 { "hw_ldq/l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
1393 { "hw_ldq/p", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM },
1394 { "hw_ldq/p", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM },
1395 { "hw_ldq/p", EV6HWMEM(0x1B,0x1), EV6, ARG_EV6HWMEM },
1396 { "hw_ldq/pa", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM },
1397 { "hw_ldq/pa", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM },
1398 { "hw_ldq/pal", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
1399 { "hw_ldq/par", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM },
1400 { "hw_ldq/pav", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM },
1401 { "hw_ldq/pavl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
1402 { "hw_ldq/paw", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM },
1403 { "hw_ldq/pawl", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
1404 { "hw_ldq/pawv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM },
1405 { "hw_ldq/pawvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
1406 { "hw_ldq/pl", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
1407 { "hw_ldq/pr", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM },
1408 { "hw_ldq/pv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM },
1409 { "hw_ldq/pvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
1410 { "hw_ldq/pw", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM },
1411 { "hw_ldq/pwl", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
1412 { "hw_ldq/pwv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM },
1413 { "hw_ldq/pwvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
1414 { "hw_ldq/r", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM },
1415 { "hw_ldq/v", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM },
1416 { "hw_ldq/v", EV6HWMEM(0x1B,0x5), EV6, ARG_EV6HWMEM },
1417 { "hw_ldq/vl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
1418 { "hw_ldq/w", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM },
1419 { "hw_ldq/w", EV6HWMEM(0x1B,0xB), EV6, ARG_EV6HWMEM },
1420 { "hw_ldq/wa", EV6HWMEM(0x1B,0xF), EV6, ARG_EV6HWMEM },
1421 { "hw_ldq/wl", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
1422 { "hw_ldq/wv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM },
1423 { "hw_ldq/wvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
1424 { "hw_ldq_l", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
1425 { "hw_ldq_l/a", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
1426 { "hw_ldq_l/av", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
1427 { "hw_ldq_l/aw", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
1428 { "hw_ldq_l/awv", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
1429 { "hw_ldq_l/p", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
1430 { "hw_ldq_l/p", EV6HWMEM(0x1B,0x3), EV6, ARG_EV6HWMEM },
1431 { "hw_ldq_l/pa", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
1432 { "hw_ldq_l/pav", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
1433 { "hw_ldq_l/paw", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
1434 { "hw_ldq_l/pawv", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
1435 { "hw_ldq_l/pv", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
1436 { "hw_ldq_l/pw", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
1437 { "hw_ldq_l/pwv", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
1438 { "hw_ldq_l/v", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
1439 { "hw_ldq_l/w", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
1440 { "hw_ldq_l/wv", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
1441 { "hw_ld", EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM },
1442 { "hw_ld", EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM },
1443 { "hw_ld/a", EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM },
1444 { "hw_ld/a", EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM },
1445 { "hw_ld/al", EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
1446 { "hw_ld/aq", EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM },
1447 { "hw_ld/aq", EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM },
1448 { "hw_ld/aql", EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
1449 { "hw_ld/aqv", EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM },
1450 { "hw_ld/aqvl", EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
1451 { "hw_ld/ar", EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM },
1452 { "hw_ld/arq", EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM },
1453 { "hw_ld/av", EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM },
1454 { "hw_ld/avl", EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
1455 { "hw_ld/aw", EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM },
1456 { "hw_ld/awl", EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
1457 { "hw_ld/awq", EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM },
1458 { "hw_ld/awql", EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
1459 { "hw_ld/awqv", EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM },
1460 { "hw_ld/awqvl", EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
1461 { "hw_ld/awv", EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM },
1462 { "hw_ld/awvl", EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
1463 { "hw_ld/l", EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
1464 { "hw_ld/p", EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM },
1465 { "hw_ld/p", EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM },
1466 { "hw_ld/pa", EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM },
1467 { "hw_ld/pa", EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM },
1468 { "hw_ld/pal", EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
1469 { "hw_ld/paq", EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM },
1470 { "hw_ld/paq", EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM },
1471 { "hw_ld/paql", EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
1472 { "hw_ld/paqv", EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM },
1473 { "hw_ld/paqvl", EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
1474 { "hw_ld/par", EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM },
1475 { "hw_ld/parq", EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM },
1476 { "hw_ld/pav", EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM },
1477 { "hw_ld/pavl", EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
1478 { "hw_ld/paw", EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM },
1479 { "hw_ld/pawl", EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
1480 { "hw_ld/pawq", EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM },
1481 { "hw_ld/pawql", EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
1482 { "hw_ld/pawqv", EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM },
1483 { "hw_ld/pawqvl", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
1484 { "hw_ld/pawv", EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM },
1485 { "hw_ld/pawvl", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
1486 { "hw_ld/pl", EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
1487 { "hw_ld/pq", EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM },
1488 { "hw_ld/pq", EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM },
1489 { "hw_ld/pql", EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
1490 { "hw_ld/pqv", EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM },
1491 { "hw_ld/pqvl", EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
1492 { "hw_ld/pr", EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM },
1493 { "hw_ld/prq", EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM },
1494 { "hw_ld/pv", EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM },
1495 { "hw_ld/pvl", EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
1496 { "hw_ld/pw", EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM },
1497 { "hw_ld/pwl", EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
1498 { "hw_ld/pwq", EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM },
1499 { "hw_ld/pwql", EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
1500 { "hw_ld/pwqv", EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM },
1501 { "hw_ld/pwqvl", EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
1502 { "hw_ld/pwv", EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM },
1503 { "hw_ld/pwvl", EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
1504 { "hw_ld/q", EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM },
1505 { "hw_ld/q", EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM },
1506 { "hw_ld/ql", EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
1507 { "hw_ld/qv", EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM },
1508 { "hw_ld/qvl", EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
1509 { "hw_ld/r", EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM },
1510 { "hw_ld/rq", EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM },
1511 { "hw_ld/v", EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM },
1512 { "hw_ld/vl", EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
1513 { "hw_ld/w", EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM },
1514 { "hw_ld/wl", EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
1515 { "hw_ld/wq", EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM },
1516 { "hw_ld/wql", EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
1517 { "hw_ld/wqv", EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM },
1518 { "hw_ld/wqvl", EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
1519 { "hw_ld/wv", EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM },
1520 { "hw_ld/wvl", EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
1521 { "pal1b", PCD(0x1B), BASE, ARG_PCD },
1522
1523 { "sextb", OPR(0x1C, 0x00), BWX, ARG_OPRZ1 },
1524 { "sextw", OPR(0x1C, 0x01), BWX, ARG_OPRZ1 },
1525 { "ctpop", OPR(0x1C, 0x30), CIX, ARG_OPRZ1 },
1526 { "perr", OPR(0x1C, 0x31), MAX, ARG_OPR },
1527 { "ctlz", OPR(0x1C, 0x32), CIX, ARG_OPRZ1 },
1528 { "cttz", OPR(0x1C, 0x33), CIX, ARG_OPRZ1 },
1529 { "unpkbw", OPR(0x1C, 0x34), MAX, ARG_OPRZ1 },
1530 { "unpkbl", OPR(0x1C, 0x35), MAX, ARG_OPRZ1 },
1531 { "pkwb", OPR(0x1C, 0x36), MAX, ARG_OPRZ1 },
1532 { "pklb", OPR(0x1C, 0x37), MAX, ARG_OPRZ1 },
1533 { "minsb8", OPR(0x1C, 0x38), MAX, ARG_OPR },
1534 { "minsb8", OPRL(0x1C, 0x38), MAX, ARG_OPRL },
1535 { "minsw4", OPR(0x1C, 0x39), MAX, ARG_OPR },
1536 { "minsw4", OPRL(0x1C, 0x39), MAX, ARG_OPRL },
1537 { "minub8", OPR(0x1C, 0x3A), MAX, ARG_OPR },
1538 { "minub8", OPRL(0x1C, 0x3A), MAX, ARG_OPRL },
1539 { "minuw4", OPR(0x1C, 0x3B), MAX, ARG_OPR },
1540 { "minuw4", OPRL(0x1C, 0x3B), MAX, ARG_OPRL },
1541 { "maxub8", OPR(0x1C, 0x3C), MAX, ARG_OPR },
1542 { "maxub8", OPRL(0x1C, 0x3C), MAX, ARG_OPRL },
1543 { "maxuw4", OPR(0x1C, 0x3D), MAX, ARG_OPR },
1544 { "maxuw4", OPRL(0x1C, 0x3D), MAX, ARG_OPRL },
1545 { "maxsb8", OPR(0x1C, 0x3E), MAX, ARG_OPR },
1546 { "maxsb8", OPRL(0x1C, 0x3E), MAX, ARG_OPRL },
1547 { "maxsw4", OPR(0x1C, 0x3F), MAX, ARG_OPR },
1548 { "maxsw4", OPRL(0x1C, 0x3F), MAX, ARG_OPRL },
1549 { "ftoit", FP(0x1C, 0x70), CIX, { FA, ZB, RC } },
1550 { "ftois", FP(0x1C, 0x78), CIX, { FA, ZB, RC } },
1551
1552 { "hw_mtpr", OPR(0x1D,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } },
1553 { "hw_mtpr", OP(0x1D), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } },
1554 { "hw_mtpr", OP(0x1D), OP_MASK, EV6, { ZA, RB, EV6HWINDEX } },
1555 { "hw_mtpr/i", OPR(0x1D,0x01), EV4, ARG_EV4HWMPR },
1556 { "hw_mtpr/a", OPR(0x1D,0x02), EV4, ARG_EV4HWMPR },
1557 { "hw_mtpr/ai", OPR(0x1D,0x03), EV4, ARG_EV4HWMPR },
1558 { "hw_mtpr/p", OPR(0x1D,0x04), EV4, ARG_EV4HWMPR },
1559 { "hw_mtpr/pi", OPR(0x1D,0x05), EV4, ARG_EV4HWMPR },
1560 { "hw_mtpr/pa", OPR(0x1D,0x06), EV4, ARG_EV4HWMPR },
1561 { "hw_mtpr/pai", OPR(0x1D,0x07), EV4, ARG_EV4HWMPR },
1562 { "pal1d", PCD(0x1D), BASE, ARG_PCD },
1563
1564 { "hw_rei", SPCD(0x1E,0x3FF8000), EV4|EV5, ARG_NONE },
1565 { "hw_rei_stall", SPCD(0x1E,0x3FFC000), EV5, ARG_NONE },
1566 { "hw_jmp", EV6HWMBR(0x1E,0x0), EV6, { ZA, PRB, EV6HWJMPHINT } },
1567 { "hw_jsr", EV6HWMBR(0x1E,0x2), EV6, { ZA, PRB, EV6HWJMPHINT } },
1568 { "hw_ret", EV6HWMBR(0x1E,0x4), EV6, { ZA, PRB } },
1569 { "hw_jcr", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } },
1570 { "hw_coroutine", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, /* alias */
1571 { "hw_jmp/stall", EV6HWMBR(0x1E,0x1), EV6, { ZA, PRB, EV6HWJMPHINT } },
1572 { "hw_jsr/stall", EV6HWMBR(0x1E,0x3), EV6, { ZA, PRB, EV6HWJMPHINT } },
1573 { "hw_ret/stall", EV6HWMBR(0x1E,0x5), EV6, { ZA, PRB } },
1574 { "hw_jcr/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } },
1575 { "hw_coroutine/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, /* alias */
1576 { "pal1e", PCD(0x1E), BASE, ARG_PCD },
1577
1578 { "hw_stl", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM },
1579 { "hw_stl", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM },
1580 { "hw_stl", EV6HWMEM(0x1F,0x4), EV6, ARG_EV6HWMEM }, /* ??? 8 */
1581 { "hw_stl/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM },
1582 { "hw_stl/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM },
1583 { "hw_stl/a", EV6HWMEM(0x1F,0xC), EV6, ARG_EV6HWMEM },
1584 { "hw_stl/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
1585 { "hw_stl/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM },
1586 { "hw_stl/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM },
1587 { "hw_stl/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
1588 { "hw_stl/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
1589 { "hw_stl/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM },
1590 { "hw_stl/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM },
1591 { "hw_stl/p", EV6HWMEM(0x1F,0x0), EV6, ARG_EV6HWMEM },
1592 { "hw_stl/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM },
1593 { "hw_stl/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM },
1594 { "hw_stl/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
1595 { "hw_stl/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM },
1596 { "hw_stl/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
1597 { "hw_stl/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
1598 { "hw_stl/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM },
1599 { "hw_stl/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM },
1600 { "hw_stl/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
1601 { "hw_stl/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM },
1602 { "hw_stl/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM },
1603 { "hw_stl/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
1604 { "hw_stl_c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
1605 { "hw_stl_c/a", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
1606 { "hw_stl_c/av", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
1607 { "hw_stl_c/p", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
1608 { "hw_stl_c/p", EV6HWMEM(0x1F,0x2), EV6, ARG_EV6HWMEM },
1609 { "hw_stl_c/pa", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
1610 { "hw_stl_c/pav", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
1611 { "hw_stl_c/pv", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
1612 { "hw_stl_c/v", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
1613 { "hw_stq", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM },
1614 { "hw_stq", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM },
1615 { "hw_stq", EV6HWMEM(0x1F,0x5), EV6, ARG_EV6HWMEM }, /* ??? 9 */
1616 { "hw_stq/a", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM },
1617 { "hw_stq/a", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM },
1618 { "hw_stq/a", EV6HWMEM(0x1F,0xD), EV6, ARG_EV6HWMEM },
1619 { "hw_stq/ac", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
1620 { "hw_stq/ar", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM },
1621 { "hw_stq/av", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM },
1622 { "hw_stq/avc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
1623 { "hw_stq/c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
1624 { "hw_stq/p", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM },
1625 { "hw_stq/p", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM },
1626 { "hw_stq/p", EV6HWMEM(0x1F,0x1), EV6, ARG_EV6HWMEM },
1627 { "hw_stq/pa", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM },
1628 { "hw_stq/pa", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM },
1629 { "hw_stq/pac", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
1630 { "hw_stq/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM },
1631 { "hw_stq/par", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM },
1632 { "hw_stq/pav", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM },
1633 { "hw_stq/pavc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
1634 { "hw_stq/pc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
1635 { "hw_stq/pr", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM },
1636 { "hw_stq/pv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM },
1637 { "hw_stq/pvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
1638 { "hw_stq/r", EV4HWMEM(0x1F,0x3), EV4, ARG_EV4HWMEM },
1639 { "hw_stq/v", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM },
1640 { "hw_stq/vc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
1641 { "hw_stq_c", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
1642 { "hw_stq_c/a", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
1643 { "hw_stq_c/av", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
1644 { "hw_stq_c/p", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
1645 { "hw_stq_c/p", EV6HWMEM(0x1F,0x3), EV6, ARG_EV6HWMEM },
1646 { "hw_stq_c/pa", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
1647 { "hw_stq_c/pav", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
1648 { "hw_stq_c/pv", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
1649 { "hw_stq_c/v", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
1650 { "hw_st", EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM },
1651 { "hw_st", EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM },
1652 { "hw_st/a", EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM },
1653 { "hw_st/a", EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM },
1654 { "hw_st/ac", EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
1655 { "hw_st/aq", EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM },
1656 { "hw_st/aq", EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM },
1657 { "hw_st/aqc", EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
1658 { "hw_st/aqv", EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM },
1659 { "hw_st/aqvc", EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
1660 { "hw_st/ar", EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM },
1661 { "hw_st/arq", EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM },
1662 { "hw_st/av", EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM },
1663 { "hw_st/avc", EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
1664 { "hw_st/c", EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
1665 { "hw_st/p", EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM },
1666 { "hw_st/p", EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM },
1667 { "hw_st/pa", EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM },
1668 { "hw_st/pa", EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM },
1669 { "hw_st/pac", EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
1670 { "hw_st/paq", EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM },
1671 { "hw_st/paq", EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM },
1672 { "hw_st/paqc", EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
1673 { "hw_st/paqv", EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM },
1674 { "hw_st/paqvc", EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
1675 { "hw_st/par", EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM },
1676 { "hw_st/parq", EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM },
1677 { "hw_st/pav", EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM },
1678 { "hw_st/pavc", EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
1679 { "hw_st/pc", EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
1680 { "hw_st/pq", EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM },
1681 { "hw_st/pq", EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM },
1682 { "hw_st/pqc", EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
1683 { "hw_st/pqv", EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM },
1684 { "hw_st/pqvc", EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
1685 { "hw_st/pr", EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM },
1686 { "hw_st/prq", EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM },
1687 { "hw_st/pv", EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM },
1688 { "hw_st/pvc", EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
1689 { "hw_st/q", EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM },
1690 { "hw_st/q", EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM },
1691 { "hw_st/qc", EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
1692 { "hw_st/qv", EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM },
1693 { "hw_st/qvc", EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
1694 { "hw_st/r", EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM },
1695 { "hw_st/v", EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM },
1696 { "hw_st/vc", EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
1697 { "pal1f", PCD(0x1F), BASE, ARG_PCD },
1698
1699 { "ldf", MEM(0x20), BASE, ARG_FMEM },
1700 { "ldg", MEM(0x21), BASE, ARG_FMEM },
1701 { "lds", MEM(0x22), BASE, ARG_FMEM },
1702 { "ldt", MEM(0x23), BASE, ARG_FMEM },
1703 { "stf", MEM(0x24), BASE, ARG_FMEM },
1704 { "stg", MEM(0x25), BASE, ARG_FMEM },
1705 { "sts", MEM(0x26), BASE, ARG_FMEM },
1706 { "stt", MEM(0x27), BASE, ARG_FMEM },
1707
1708 { "ldl", MEM(0x28), BASE, ARG_MEM },
1709 { "ldq", MEM(0x29), BASE, ARG_MEM },
1710 { "ldl_l", MEM(0x2A), BASE, ARG_MEM },
1711 { "ldq_l", MEM(0x2B), BASE, ARG_MEM },
1712 { "stl", MEM(0x2C), BASE, ARG_MEM },
1713 { "stq", MEM(0x2D), BASE, ARG_MEM },
1714 { "stl_c", MEM(0x2E), BASE, ARG_MEM },
1715 { "stq_c", MEM(0x2F), BASE, ARG_MEM },
1716
1717 { "br", BRA(0x30), BASE, { ZA, BDISP } }, /* pseudo */
1718 { "br", BRA(0x30), BASE, ARG_BRA },
1719 { "fbeq", BRA(0x31), BASE, ARG_FBRA },
1720 { "fblt", BRA(0x32), BASE, ARG_FBRA },
1721 { "fble", BRA(0x33), BASE, ARG_FBRA },
1722 { "bsr", BRA(0x34), BASE, ARG_BRA },
1723 { "fbne", BRA(0x35), BASE, ARG_FBRA },
1724 { "fbge", BRA(0x36), BASE, ARG_FBRA },
1725 { "fbgt", BRA(0x37), BASE, ARG_FBRA },
1726 { "blbc", BRA(0x38), BASE, ARG_BRA },
1727 { "beq", BRA(0x39), BASE, ARG_BRA },
1728 { "blt", BRA(0x3A), BASE, ARG_BRA },
1729 { "ble", BRA(0x3B), BASE, ARG_BRA },
1730 { "blbs", BRA(0x3C), BASE, ARG_BRA },
1731 { "bne", BRA(0x3D), BASE, ARG_BRA },
1732 { "bge", BRA(0x3E), BASE, ARG_BRA },
1733 { "bgt", BRA(0x3F), BASE, ARG_BRA },
1734 };
1735
1736 const unsigned alpha_num_opcodes = sizeof(alpha_opcodes)/sizeof(*alpha_opcodes);
1737
1738 /* OSF register names. */
1739
1740 static const char * const osf_regnames[64] = {
1741 "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6",
1742 "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp",
1743 "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9",
1744 "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero",
1745 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
1746 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
1747 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
1748 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
1749 };
1750
1751 /* VMS register names. */
1752
1753 static const char * const vms_regnames[64] = {
1754 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
1755 "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15",
1756 "R16", "R17", "R18", "R19", "R20", "R21", "R22", "R23",
1757 "R24", "AI", "RA", "PV", "AT", "FP", "SP", "RZ",
1758 "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7",
1759 "F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15",
1760 "F16", "F17", "F18", "F19", "F20", "F21", "F22", "F23",
1761 "F24", "F25", "F26", "F27", "F28", "F29", "F30", "FZ"
1762 };
1763
1764 /* Disassemble Alpha instructions. */
1765
1766 int
1767 print_insn_alpha (bfd_vma memaddr, struct disassemble_info *info)
1768 {
1769 static const struct alpha_opcode *opcode_index[AXP_NOPS+1];
1770 const char * const * regnames;
1771 const struct alpha_opcode *opcode, *opcode_end;
1772 const unsigned char *opindex;
1773 unsigned insn, op, isa_mask;
1774 int need_comma;
1775
1776 /* Initialize the majorop table the first time through */
1777 if (!opcode_index[0])
1778 {
1779 opcode = alpha_opcodes;
1780 opcode_end = opcode + alpha_num_opcodes;
1781
1782 for (op = 0; op < AXP_NOPS; ++op)
1783 {
1784 opcode_index[op] = opcode;
1785 while (opcode < opcode_end && op == AXP_OP (opcode->opcode))
1786 ++opcode;
1787 }
1788 opcode_index[op] = opcode;
1789 }
1790
1791 if (info->flavour == bfd_target_evax_flavour)
1792 regnames = vms_regnames;
1793 else
1794 regnames = osf_regnames;
1795
1796 isa_mask = AXP_OPCODE_NOPAL;
1797 switch (info->mach)
1798 {
1799 case bfd_mach_alpha_ev4:
1800 isa_mask |= AXP_OPCODE_EV4;
1801 break;
1802 case bfd_mach_alpha_ev5:
1803 isa_mask |= AXP_OPCODE_EV5;
1804 break;
1805 case bfd_mach_alpha_ev6:
1806 isa_mask |= AXP_OPCODE_EV6;
1807 break;
1808 }
1809
1810 /* Read the insn into a host word */
1811 {
1812 bfd_byte buffer[4];
1813 int status = (*info->read_memory_func) (memaddr, buffer, 4, info);
1814 if (status != 0)
1815 {
1816 (*info->memory_error_func) (status, memaddr, info);
1817 return -1;
1818 }
1819 insn = bfd_getl32 (buffer);
1820 }
1821
1822 /* Get the major opcode of the instruction. */
1823 op = AXP_OP (insn);
1824
1825 /* Find the first match in the opcode table. */
1826 opcode_end = opcode_index[op + 1];
1827 for (opcode = opcode_index[op]; opcode < opcode_end; ++opcode)
1828 {
1829 if ((insn ^ opcode->opcode) & opcode->mask)
1830 continue;
1831
1832 if (!(opcode->flags & isa_mask))
1833 continue;
1834
1835 /* Make two passes over the operands. First see if any of them
1836 have extraction functions, and, if they do, make sure the
1837 instruction is valid. */
1838 {
1839 int invalid = 0;
1840 for (opindex = opcode->operands; *opindex != 0; opindex++)
1841 {
1842 const struct alpha_operand *operand = alpha_operands + *opindex;
1843 if (operand->extract)
1844 (*operand->extract) (insn, &invalid);
1845 }
1846 if (invalid)
1847 continue;
1848 }
1849
1850 /* The instruction is valid. */
1851 goto found;
1852 }
1853
1854 /* No instruction found */
1855 (*info->fprintf_func) (info->stream, ".long %#08x", insn);
1856
1857 return 4;
1858
1859 found:
1860 (*info->fprintf_func) (info->stream, "%s", opcode->name);
1861 if (opcode->operands[0] != 0)
1862 (*info->fprintf_func) (info->stream, "\t");
1863
1864 /* Now extract and print the operands. */
1865 need_comma = 0;
1866 for (opindex = opcode->operands; *opindex != 0; opindex++)
1867 {
1868 const struct alpha_operand *operand = alpha_operands + *opindex;
1869 int value;
1870
1871 /* Operands that are marked FAKE are simply ignored. We
1872 already made sure that the extract function considered
1873 the instruction to be valid. */
1874 if ((operand->flags & AXP_OPERAND_FAKE) != 0)
1875 continue;
1876
1877 /* Extract the value from the instruction. */
1878 if (operand->extract)
1879 value = (*operand->extract) (insn, (int *) NULL);
1880 else
1881 {
1882 value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
1883 if (operand->flags & AXP_OPERAND_SIGNED)
1884 {
1885 int signbit = 1 << (operand->bits - 1);
1886 value = (value ^ signbit) - signbit;
1887 }
1888 }
1889
1890 if (need_comma &&
1891 ((operand->flags & (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA))
1892 != AXP_OPERAND_PARENS))
1893 {
1894 (*info->fprintf_func) (info->stream, ",");
1895 }
1896 if (operand->flags & AXP_OPERAND_PARENS)
1897 (*info->fprintf_func) (info->stream, "(");
1898
1899 /* Print the operand as directed by the flags. */
1900 if (operand->flags & AXP_OPERAND_IR)
1901 (*info->fprintf_func) (info->stream, "%s", regnames[value]);
1902 else if (operand->flags & AXP_OPERAND_FPR)
1903 (*info->fprintf_func) (info->stream, "%s", regnames[value + 32]);
1904 else if (operand->flags & AXP_OPERAND_RELATIVE)
1905 (*info->print_address_func) (memaddr + 4 + value, info);
1906 else if (operand->flags & AXP_OPERAND_SIGNED)
1907 (*info->fprintf_func) (info->stream, "%d", value);
1908 else
1909 (*info->fprintf_func) (info->stream, "%#x", value);
1910
1911 if (operand->flags & AXP_OPERAND_PARENS)
1912 (*info->fprintf_func) (info->stream, ")");
1913 need_comma = 1;
1914 }
1915
1916 return 4;
1917 }
various patches