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tcg/ppc64: Fix loading of 32bit constants
[qemu/mdroth.git] / hw / vmware_vga.c
blobf3e3749e9cdd95af1685d37d7156ba97631ac11f
1 /*
2 * QEMU VMware-SVGA "chipset".
3 *
4 * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "loader.h"
26 #include "console.h"
27 #include "pci.h"
28 #include "vmware_vga.h"
29
30 #define VERBOSE
31 #undef DIRECT_VRAM
32 #define HW_RECT_ACCEL
33 #define HW_FILL_ACCEL
34 #define HW_MOUSE_ACCEL
35
36 # include "vga_int.h"
37
38 struct vmsvga_state_s {
39 VGACommonState vga;
40
41 int width;
42 int height;
43 int invalidated;
44 int depth;
45 int bypp;
46 int enable;
47 int config;
48 struct {
49 int id;
50 int x;
51 int y;
52 int on;
53 } cursor;
54
55 target_phys_addr_t vram_base;
56
57 int index;
58 int scratch_size;
59 uint32_t *scratch;
60 int new_width;
61 int new_height;
62 uint32_t guest;
63 uint32_t svgaid;
64 uint32_t wred;
65 uint32_t wgreen;
66 uint32_t wblue;
67 int syncing;
68 int fb_size;
69
70 union {
71 uint32_t *fifo;
72 struct __attribute__((__packed__)) {
73 uint32_t min;
74 uint32_t max;
75 uint32_t next_cmd;
76 uint32_t stop;
77 /* Add registers here when adding capabilities. */
78 uint32_t fifo[0];
79 } *cmd;
80 };
81
82 #define REDRAW_FIFO_LEN 512
83 struct vmsvga_rect_s {
84 int x, y, w, h;
85 } redraw_fifo[REDRAW_FIFO_LEN];
86 int redraw_fifo_first, redraw_fifo_last;
87 };
88
89 struct pci_vmsvga_state_s {
90 PCIDevice card;
91 struct vmsvga_state_s chip;
92 };
93
94 #define SVGA_MAGIC 0x900000UL
95 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
96 #define SVGA_ID_0 SVGA_MAKE_ID(0)
97 #define SVGA_ID_1 SVGA_MAKE_ID(1)
98 #define SVGA_ID_2 SVGA_MAKE_ID(2)
99
100 #define SVGA_LEGACY_BASE_PORT 0x4560
101 #define SVGA_INDEX_PORT 0x0
102 #define SVGA_VALUE_PORT 0x1
103 #define SVGA_BIOS_PORT 0x2
104
105 #define SVGA_VERSION_2
106
107 #ifdef SVGA_VERSION_2
108 # define SVGA_ID SVGA_ID_2
109 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
110 # define SVGA_IO_MUL 1
111 # define SVGA_FIFO_SIZE 0x10000
112 # define SVGA_MEM_BASE 0xe0000000
113 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
114 #else
115 # define SVGA_ID SVGA_ID_1
116 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
117 # define SVGA_IO_MUL 4
118 # define SVGA_FIFO_SIZE 0x10000
119 # define SVGA_MEM_BASE 0xe0000000
120 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
121 #endif
122
123 enum {
124 /* ID 0, 1 and 2 registers */
125 SVGA_REG_ID = 0,
126 SVGA_REG_ENABLE = 1,
127 SVGA_REG_WIDTH = 2,
128 SVGA_REG_HEIGHT = 3,
129 SVGA_REG_MAX_WIDTH = 4,
130 SVGA_REG_MAX_HEIGHT = 5,
131 SVGA_REG_DEPTH = 6,
132 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */
133 SVGA_REG_PSEUDOCOLOR = 8,
134 SVGA_REG_RED_MASK = 9,
135 SVGA_REG_GREEN_MASK = 10,
136 SVGA_REG_BLUE_MASK = 11,
137 SVGA_REG_BYTES_PER_LINE = 12,
138 SVGA_REG_FB_START = 13,
139 SVGA_REG_FB_OFFSET = 14,
140 SVGA_REG_VRAM_SIZE = 15,
141 SVGA_REG_FB_SIZE = 16,
142
143 /* ID 1 and 2 registers */
144 SVGA_REG_CAPABILITIES = 17,
145 SVGA_REG_MEM_START = 18, /* Memory for command FIFO */
146 SVGA_REG_MEM_SIZE = 19,
147 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
148 SVGA_REG_SYNC = 21, /* Write to force synchronization */
149 SVGA_REG_BUSY = 22, /* Read to check if sync is done */
150 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */
151 SVGA_REG_CURSOR_ID = 24, /* ID of cursor */
152 SVGA_REG_CURSOR_X = 25, /* Set cursor X position */
153 SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */
154 SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */
155 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */
156 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */
157 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */
158 SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */
159 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */
160
161 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
162 SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767,
163 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
164 };
165
166 #define SVGA_CAP_NONE 0
167 #define SVGA_CAP_RECT_FILL (1 << 0)
168 #define SVGA_CAP_RECT_COPY (1 << 1)
169 #define SVGA_CAP_RECT_PAT_FILL (1 << 2)
170 #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3)
171 #define SVGA_CAP_RASTER_OP (1 << 4)
172 #define SVGA_CAP_CURSOR (1 << 5)
173 #define SVGA_CAP_CURSOR_BYPASS (1 << 6)
174 #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7)
175 #define SVGA_CAP_8BIT_EMULATION (1 << 8)
176 #define SVGA_CAP_ALPHA_CURSOR (1 << 9)
177 #define SVGA_CAP_GLYPH (1 << 10)
178 #define SVGA_CAP_GLYPH_CLIPPING (1 << 11)
179 #define SVGA_CAP_OFFSCREEN_1 (1 << 12)
180 #define SVGA_CAP_ALPHA_BLEND (1 << 13)
181 #define SVGA_CAP_3D (1 << 14)
182 #define SVGA_CAP_EXTENDED_FIFO (1 << 15)
183 #define SVGA_CAP_MULTIMON (1 << 16)
184 #define SVGA_CAP_PITCHLOCK (1 << 17)
185
186 /*
187 * FIFO offsets (seen as an array of 32-bit words)
188 */
189 enum {
190 /*
191 * The original defined FIFO offsets
192 */
193 SVGA_FIFO_MIN = 0,
194 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
195 SVGA_FIFO_NEXT_CMD,
196 SVGA_FIFO_STOP,
197
198 /*
199 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
200 */
201 SVGA_FIFO_CAPABILITIES = 4,
202 SVGA_FIFO_FLAGS,
203 SVGA_FIFO_FENCE,
204 SVGA_FIFO_3D_HWVERSION,
205 SVGA_FIFO_PITCHLOCK,
206 };
207
208 #define SVGA_FIFO_CAP_NONE 0
209 #define SVGA_FIFO_CAP_FENCE (1 << 0)
210 #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1)
211 #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2)
212
213 #define SVGA_FIFO_FLAG_NONE 0
214 #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0)
215
216 /* These values can probably be changed arbitrarily. */
217 #define SVGA_SCRATCH_SIZE 0x8000
218 #define SVGA_MAX_WIDTH 2360
219 #define SVGA_MAX_HEIGHT 1770
220
221 #ifdef VERBOSE
222 # define GUEST_OS_BASE 0x5001
223 static const char *vmsvga_guest_id[] = {
224 [0x00] = "Dos",
225 [0x01] = "Windows 3.1",
226 [0x02] = "Windows 95",
227 [0x03] = "Windows 98",
228 [0x04] = "Windows ME",
229 [0x05] = "Windows NT",
230 [0x06] = "Windows 2000",
231 [0x07] = "Linux",
232 [0x08] = "OS/2",
233 [0x09] = "an unknown OS",
234 [0x0a] = "BSD",
235 [0x0b] = "Whistler",
236 [0x0c] = "an unknown OS",
237 [0x0d] = "an unknown OS",
238 [0x0e] = "an unknown OS",
239 [0x0f] = "an unknown OS",
240 [0x10] = "an unknown OS",
241 [0x11] = "an unknown OS",
242 [0x12] = "an unknown OS",
243 [0x13] = "an unknown OS",
244 [0x14] = "an unknown OS",
245 [0x15] = "Windows 2003",
246 };
247 #endif
248
249 enum {
250 SVGA_CMD_INVALID_CMD = 0,
251 SVGA_CMD_UPDATE = 1,
252 SVGA_CMD_RECT_FILL = 2,
253 SVGA_CMD_RECT_COPY = 3,
254 SVGA_CMD_DEFINE_BITMAP = 4,
255 SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
256 SVGA_CMD_DEFINE_PIXMAP = 6,
257 SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
258 SVGA_CMD_RECT_BITMAP_FILL = 8,
259 SVGA_CMD_RECT_PIXMAP_FILL = 9,
260 SVGA_CMD_RECT_BITMAP_COPY = 10,
261 SVGA_CMD_RECT_PIXMAP_COPY = 11,
262 SVGA_CMD_FREE_OBJECT = 12,
263 SVGA_CMD_RECT_ROP_FILL = 13,
264 SVGA_CMD_RECT_ROP_COPY = 14,
265 SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
266 SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
267 SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
268 SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
269 SVGA_CMD_DEFINE_CURSOR = 19,
270 SVGA_CMD_DISPLAY_CURSOR = 20,
271 SVGA_CMD_MOVE_CURSOR = 21,
272 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
273 SVGA_CMD_DRAW_GLYPH = 23,
274 SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
275 SVGA_CMD_UPDATE_VERBOSE = 25,
276 SVGA_CMD_SURFACE_FILL = 26,
277 SVGA_CMD_SURFACE_COPY = 27,
278 SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
279 SVGA_CMD_FRONT_ROP_FILL = 29,
280 SVGA_CMD_FENCE = 30,
281 };
282
283 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
284 enum {
285 SVGA_CURSOR_ON_HIDE = 0,
286 SVGA_CURSOR_ON_SHOW = 1,
287 SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
288 SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
289 };
290
291 static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
292 int x, int y, int w, int h)
293 {
294 #ifndef DIRECT_VRAM
295 int line;
296 int bypl;
297 int width;
298 int start;
299 uint8_t *src;
300 uint8_t *dst;
301
302 if (x + w > s->width) {
303 fprintf(stderr, "%s: update width too large x: %d, w: %d\n",
304 __FUNCTION__, x, w);
305 x = MIN(x, s->width);
306 w = s->width - x;
307 }
308
309 if (y + h > s->height) {
310 fprintf(stderr, "%s: update height too large y: %d, h: %d\n",
311 __FUNCTION__, y, h);
312 y = MIN(y, s->height);
313 h = s->height - y;
314 }
315
316 line = h;
317 bypl = s->bypp * s->width;
318 width = s->bypp * w;
319 start = s->bypp * x + bypl * y;
320 src = s->vga.vram_ptr + start;
321 dst = ds_get_data(s->vga.ds) + start;
322
323 for (; line > 0; line --, src += bypl, dst += bypl)
324 memcpy(dst, src, width);
325 #endif
326
327 dpy_update(s->vga.ds, x, y, w, h);
328 }
329
330 static inline void vmsvga_update_screen(struct vmsvga_state_s *s)
331 {
332 #ifndef DIRECT_VRAM
333 memcpy(ds_get_data(s->vga.ds), s->vga.vram_ptr, s->bypp * s->width * s->height);
334 #endif
335
336 dpy_update(s->vga.ds, 0, 0, s->width, s->height);
337 }
338
339 #ifdef DIRECT_VRAM
340 # define vmsvga_update_rect_delayed vmsvga_update_rect
341 #else
342 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
343 int x, int y, int w, int h)
344 {
345 struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last ++];
346 s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
347 rect->x = x;
348 rect->y = y;
349 rect->w = w;
350 rect->h = h;
351 }
352 #endif
353
354 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
355 {
356 struct vmsvga_rect_s *rect;
357 if (s->invalidated) {
358 s->redraw_fifo_first = s->redraw_fifo_last;
359 return;
360 }
361 /* Overlapping region updates can be optimised out here - if someone
362 * knows a smart algorithm to do that, please share. */
363 while (s->redraw_fifo_first != s->redraw_fifo_last) {
364 rect = &s->redraw_fifo[s->redraw_fifo_first ++];
365 s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
366 vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
367 }
368 }
369
370 #ifdef HW_RECT_ACCEL
371 static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
372 int x0, int y0, int x1, int y1, int w, int h)
373 {
374 # ifdef DIRECT_VRAM
375 uint8_t *vram = ds_get_data(s->ds);
376 # else
377 uint8_t *vram = s->vga.vram_ptr;
378 # endif
379 int bypl = s->bypp * s->width;
380 int width = s->bypp * w;
381 int line = h;
382 uint8_t *ptr[2];
383
384 # ifdef DIRECT_VRAM
385 if (s->ds->dpy_copy)
386 qemu_console_copy(s->ds, x0, y0, x1, y1, w, h);
387 else
388 # endif
389 {
390 if (y1 > y0) {
391 ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1);
392 ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1);
393 for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl)
394 memmove(ptr[1], ptr[0], width);
395 } else {
396 ptr[0] = vram + s->bypp * x0 + bypl * y0;
397 ptr[1] = vram + s->bypp * x1 + bypl * y1;
398 for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl)
399 memmove(ptr[1], ptr[0], width);
400 }
401 }
402
403 vmsvga_update_rect_delayed(s, x1, y1, w, h);
404 }
405 #endif
406
407 #ifdef HW_FILL_ACCEL
408 static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
409 uint32_t c, int x, int y, int w, int h)
410 {
411 # ifdef DIRECT_VRAM
412 uint8_t *vram = ds_get_data(s->ds);
413 # else
414 uint8_t *vram = s->vga.vram_ptr;
415 # endif
416 int bypp = s->bypp;
417 int bypl = bypp * s->width;
418 int width = bypp * w;
419 int line = h;
420 int column;
421 uint8_t *fst = vram + bypp * x + bypl * y;
422 uint8_t *dst;
423 uint8_t *src;
424 uint8_t col[4];
425
426 # ifdef DIRECT_VRAM
427 if (s->ds->dpy_fill)
428 s->ds->dpy_fill(s->ds, x, y, w, h, c);
429 else
430 # endif
431 {
432 col[0] = c;
433 col[1] = c >> 8;
434 col[2] = c >> 16;
435 col[3] = c >> 24;
436
437 if (line --) {
438 dst = fst;
439 src = col;
440 for (column = width; column > 0; column --) {
441 *(dst ++) = *(src ++);
442 if (src - col == bypp)
443 src = col;
444 }
445 dst = fst;
446 for (; line > 0; line --) {
447 dst += bypl;
448 memcpy(dst, fst, width);
449 }
450 }
451 }
452
453 vmsvga_update_rect_delayed(s, x, y, w, h);
454 }
455 #endif
456
457 struct vmsvga_cursor_definition_s {
458 int width;
459 int height;
460 int id;
461 int bpp;
462 int hot_x;
463 int hot_y;
464 uint32_t mask[1024];
465 uint32_t image[1024];
466 };
467
468 #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h))
469 #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h))
470
471 #ifdef HW_MOUSE_ACCEL
472 static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
473 struct vmsvga_cursor_definition_s *c)
474 {
475 int i;
476 for (i = SVGA_BITMAP_SIZE(c->width, c->height) - 1; i >= 0; i --)
477 c->mask[i] = ~c->mask[i];
478
479 if (s->vga.ds->cursor_define)
480 s->vga.ds->cursor_define(c->width, c->height, c->bpp, c->hot_x, c->hot_y,
481 (uint8_t *) c->image, (uint8_t *) c->mask);
482 }
483 #endif
484
485 #define CMD(f) le32_to_cpu(s->cmd->f)
486
487 static inline int vmsvga_fifo_empty(struct vmsvga_state_s *s)
488 {
489 if (!s->config || !s->enable)
490 return 1;
491 return (s->cmd->next_cmd == s->cmd->stop);
492 }
493
494 static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s)
495 {
496 uint32_t cmd = s->fifo[CMD(stop) >> 2];
497 s->cmd->stop = cpu_to_le32(CMD(stop) + 4);
498 if (CMD(stop) >= CMD(max))
499 s->cmd->stop = s->cmd->min;
500 return cmd;
501 }
502
503 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
504 {
505 return le32_to_cpu(vmsvga_fifo_read_raw(s));
506 }
507
508 static void vmsvga_fifo_run(struct vmsvga_state_s *s)
509 {
510 uint32_t cmd, colour;
511 int args = 0;
512 int x, y, dx, dy, width, height;
513 struct vmsvga_cursor_definition_s cursor;
514 while (!vmsvga_fifo_empty(s))
515 switch (cmd = vmsvga_fifo_read(s)) {
516 case SVGA_CMD_UPDATE:
517 case SVGA_CMD_UPDATE_VERBOSE:
518 x = vmsvga_fifo_read(s);
519 y = vmsvga_fifo_read(s);
520 width = vmsvga_fifo_read(s);
521 height = vmsvga_fifo_read(s);
522 vmsvga_update_rect_delayed(s, x, y, width, height);
523 break;
524
525 case SVGA_CMD_RECT_FILL:
526 colour = vmsvga_fifo_read(s);
527 x = vmsvga_fifo_read(s);
528 y = vmsvga_fifo_read(s);
529 width = vmsvga_fifo_read(s);
530 height = vmsvga_fifo_read(s);
531 #ifdef HW_FILL_ACCEL
532 vmsvga_fill_rect(s, colour, x, y, width, height);
533 break;
534 #else
535 goto badcmd;
536 #endif
537
538 case SVGA_CMD_RECT_COPY:
539 x = vmsvga_fifo_read(s);
540 y = vmsvga_fifo_read(s);
541 dx = vmsvga_fifo_read(s);
542 dy = vmsvga_fifo_read(s);
543 width = vmsvga_fifo_read(s);
544 height = vmsvga_fifo_read(s);
545 #ifdef HW_RECT_ACCEL
546 vmsvga_copy_rect(s, x, y, dx, dy, width, height);
547 break;
548 #else
549 goto badcmd;
550 #endif
551
552 case SVGA_CMD_DEFINE_CURSOR:
553 cursor.id = vmsvga_fifo_read(s);
554 cursor.hot_x = vmsvga_fifo_read(s);
555 cursor.hot_y = vmsvga_fifo_read(s);
556 cursor.width = x = vmsvga_fifo_read(s);
557 cursor.height = y = vmsvga_fifo_read(s);
558 vmsvga_fifo_read(s);
559 cursor.bpp = vmsvga_fifo_read(s);
560 for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args ++)
561 cursor.mask[args] = vmsvga_fifo_read_raw(s);
562 for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args ++)
563 cursor.image[args] = vmsvga_fifo_read_raw(s);
564 #ifdef HW_MOUSE_ACCEL
565 vmsvga_cursor_define(s, &cursor);
566 break;
567 #else
568 args = 0;
569 goto badcmd;
570 #endif
571
572 /*
573 * Other commands that we at least know the number of arguments
574 * for so we can avoid FIFO desync if driver uses them illegally.
575 */
576 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
577 vmsvga_fifo_read(s);
578 vmsvga_fifo_read(s);
579 vmsvga_fifo_read(s);
580 x = vmsvga_fifo_read(s);
581 y = vmsvga_fifo_read(s);
582 args = x * y;
583 goto badcmd;
584 case SVGA_CMD_RECT_ROP_FILL:
585 args = 6;
586 goto badcmd;
587 case SVGA_CMD_RECT_ROP_COPY:
588 args = 7;
589 goto badcmd;
590 case SVGA_CMD_DRAW_GLYPH_CLIPPED:
591 vmsvga_fifo_read(s);
592 vmsvga_fifo_read(s);
593 args = 7 + (vmsvga_fifo_read(s) >> 2);
594 goto badcmd;
595 case SVGA_CMD_SURFACE_ALPHA_BLEND:
596 args = 12;
597 goto badcmd;
598
599 /*
600 * Other commands that are not listed as depending on any
601 * CAPABILITIES bits, but are not described in the README either.
602 */
603 case SVGA_CMD_SURFACE_FILL:
604 case SVGA_CMD_SURFACE_COPY:
605 case SVGA_CMD_FRONT_ROP_FILL:
606 case SVGA_CMD_FENCE:
607 case SVGA_CMD_INVALID_CMD:
608 break; /* Nop */
609
610 default:
611 badcmd:
612 while (args --)
613 vmsvga_fifo_read(s);
614 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
615 __FUNCTION__, cmd);
616 break;
617 }
618
619 s->syncing = 0;
620 }
621
622 static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
623 {
624 struct vmsvga_state_s *s = opaque;
625 return s->index;
626 }
627
628 static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
629 {
630 struct vmsvga_state_s *s = opaque;
631 s->index = index;
632 }
633
634 static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
635 {
636 uint32_t caps;
637 struct vmsvga_state_s *s = opaque;
638 switch (s->index) {
639 case SVGA_REG_ID:
640 return s->svgaid;
641
642 case SVGA_REG_ENABLE:
643 return s->enable;
644
645 case SVGA_REG_WIDTH:
646 return s->width;
647
648 case SVGA_REG_HEIGHT:
649 return s->height;
650
651 case SVGA_REG_MAX_WIDTH:
652 return SVGA_MAX_WIDTH;
653
654 case SVGA_REG_MAX_HEIGHT:
655 return SVGA_MAX_HEIGHT;
656
657 case SVGA_REG_DEPTH:
658 return s->depth;
659
660 case SVGA_REG_BITS_PER_PIXEL:
661 return (s->depth + 7) & ~7;
662
663 case SVGA_REG_PSEUDOCOLOR:
664 return 0x0;
665
666 case SVGA_REG_RED_MASK:
667 return s->wred;
668 case SVGA_REG_GREEN_MASK:
669 return s->wgreen;
670 case SVGA_REG_BLUE_MASK:
671 return s->wblue;
672
673 case SVGA_REG_BYTES_PER_LINE:
674 return ((s->depth + 7) >> 3) * s->new_width;
675
676 case SVGA_REG_FB_START:
677 return s->vram_base;
678
679 case SVGA_REG_FB_OFFSET:
680 return 0x0;
681
682 case SVGA_REG_VRAM_SIZE:
683 return s->vga.vram_size - SVGA_FIFO_SIZE;
684
685 case SVGA_REG_FB_SIZE:
686 return s->fb_size;
687
688 case SVGA_REG_CAPABILITIES:
689 caps = SVGA_CAP_NONE;
690 #ifdef HW_RECT_ACCEL
691 caps |= SVGA_CAP_RECT_COPY;
692 #endif
693 #ifdef HW_FILL_ACCEL
694 caps |= SVGA_CAP_RECT_FILL;
695 #endif
696 #ifdef HW_MOUSE_ACCEL
697 if (s->vga.ds->mouse_set)
698 caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
699 SVGA_CAP_CURSOR_BYPASS;
700 #endif
701 return caps;
702
703 case SVGA_REG_MEM_START:
704 return s->vram_base + s->vga.vram_size - SVGA_FIFO_SIZE;
705
706 case SVGA_REG_MEM_SIZE:
707 return SVGA_FIFO_SIZE;
708
709 case SVGA_REG_CONFIG_DONE:
710 return s->config;
711
712 case SVGA_REG_SYNC:
713 case SVGA_REG_BUSY:
714 return s->syncing;
715
716 case SVGA_REG_GUEST_ID:
717 return s->guest;
718
719 case SVGA_REG_CURSOR_ID:
720 return s->cursor.id;
721
722 case SVGA_REG_CURSOR_X:
723 return s->cursor.x;
724
725 case SVGA_REG_CURSOR_Y:
726 return s->cursor.x;
727
728 case SVGA_REG_CURSOR_ON:
729 return s->cursor.on;
730
731 case SVGA_REG_HOST_BITS_PER_PIXEL:
732 return (s->depth + 7) & ~7;
733
734 case SVGA_REG_SCRATCH_SIZE:
735 return s->scratch_size;
736
737 case SVGA_REG_MEM_REGS:
738 case SVGA_REG_NUM_DISPLAYS:
739 case SVGA_REG_PITCHLOCK:
740 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
741 return 0;
742
743 default:
744 if (s->index >= SVGA_SCRATCH_BASE &&
745 s->index < SVGA_SCRATCH_BASE + s->scratch_size)
746 return s->scratch[s->index - SVGA_SCRATCH_BASE];
747 printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
748 }
749
750 return 0;
751 }
752
753 static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
754 {
755 struct vmsvga_state_s *s = opaque;
756 switch (s->index) {
757 case SVGA_REG_ID:
758 if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0)
759 s->svgaid = value;
760 break;
761
762 case SVGA_REG_ENABLE:
763 s->enable = value;
764 s->config &= !!value;
765 s->width = -1;
766 s->height = -1;
767 s->invalidated = 1;
768 s->vga.invalidate(&s->vga);
769 if (s->enable)
770 s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height;
771 break;
772
773 case SVGA_REG_WIDTH:
774 s->new_width = value;
775 s->invalidated = 1;
776 break;
777
778 case SVGA_REG_HEIGHT:
779 s->new_height = value;
780 s->invalidated = 1;
781 break;
782
783 case SVGA_REG_DEPTH:
784 case SVGA_REG_BITS_PER_PIXEL:
785 if (value != s->depth) {
786 printf("%s: Bad colour depth: %i bits\n", __FUNCTION__, value);
787 s->config = 0;
788 }
789 break;
790
791 case SVGA_REG_CONFIG_DONE:
792 if (value) {
793 s->fifo = (uint32_t *) &s->vga.vram_ptr[s->vga.vram_size - SVGA_FIFO_SIZE];
794 /* Check range and alignment. */
795 if ((CMD(min) | CMD(max) |
796 CMD(next_cmd) | CMD(stop)) & 3)
797 break;
798 if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo)
799 break;
800 if (CMD(max) > SVGA_FIFO_SIZE)
801 break;
802 if (CMD(max) < CMD(min) + 10 * 1024)
803 break;
804 }
805 s->config = !!value;
806 break;
807
808 case SVGA_REG_SYNC:
809 s->syncing = 1;
810 vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
811 break;
812
813 case SVGA_REG_GUEST_ID:
814 s->guest = value;
815 #ifdef VERBOSE
816 if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
817 ARRAY_SIZE(vmsvga_guest_id))
818 printf("%s: guest runs %s.\n", __FUNCTION__,
819 vmsvga_guest_id[value - GUEST_OS_BASE]);
820 #endif
821 break;
822
823 case SVGA_REG_CURSOR_ID:
824 s->cursor.id = value;
825 break;
826
827 case SVGA_REG_CURSOR_X:
828 s->cursor.x = value;
829 break;
830
831 case SVGA_REG_CURSOR_Y:
832 s->cursor.y = value;
833 break;
834
835 case SVGA_REG_CURSOR_ON:
836 s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
837 s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
838 #ifdef HW_MOUSE_ACCEL
839 if (s->vga.ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
840 s->vga.ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on);
841 #endif
842 break;
843
844 case SVGA_REG_MEM_REGS:
845 case SVGA_REG_NUM_DISPLAYS:
846 case SVGA_REG_PITCHLOCK:
847 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
848 break;
849
850 default:
851 if (s->index >= SVGA_SCRATCH_BASE &&
852 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
853 s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
854 break;
855 }
856 printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
857 }
858 }
859
860 static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
861 {
862 printf("%s: what are we supposed to return?\n", __FUNCTION__);
863 return 0xcafe;
864 }
865
866 static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
867 {
868 printf("%s: what are we supposed to do with (%08x)?\n",
869 __FUNCTION__, data);
870 }
871
872 static inline void vmsvga_size(struct vmsvga_state_s *s)
873 {
874 if (s->new_width != s->width || s->new_height != s->height) {
875 s->width = s->new_width;
876 s->height = s->new_height;
877 qemu_console_resize(s->vga.ds, s->width, s->height);
878 s->invalidated = 1;
879 }
880 }
881
882 static void vmsvga_update_display(void *opaque)
883 {
884 struct vmsvga_state_s *s = opaque;
885 if (!s->enable) {
886 s->vga.update(&s->vga);
887 return;
888 }
889
890 vmsvga_size(s);
891
892 vmsvga_fifo_run(s);
893 vmsvga_update_rect_flush(s);
894
895 /*
896 * Is it more efficient to look at vram VGA-dirty bits or wait
897 * for the driver to issue SVGA_CMD_UPDATE?
898 */
899 if (s->invalidated) {
900 s->invalidated = 0;
901 vmsvga_update_screen(s);
902 }
903 }
904
905 static void vmsvga_reset(struct vmsvga_state_s *s)
906 {
907 s->index = 0;
908 s->enable = 0;
909 s->config = 0;
910 s->width = -1;
911 s->height = -1;
912 s->svgaid = SVGA_ID;
913 s->depth = 24;
914 s->bypp = (s->depth + 7) >> 3;
915 s->cursor.on = 0;
916 s->redraw_fifo_first = 0;
917 s->redraw_fifo_last = 0;
918 switch (s->depth) {
919 case 8:
920 s->wred = 0x00000007;
921 s->wgreen = 0x00000038;
922 s->wblue = 0x000000c0;
923 break;
924 case 15:
925 s->wred = 0x0000001f;
926 s->wgreen = 0x000003e0;
927 s->wblue = 0x00007c00;
928 break;
929 case 16:
930 s->wred = 0x0000001f;
931 s->wgreen = 0x000007e0;
932 s->wblue = 0x0000f800;
933 break;
934 case 24:
935 s->wred = 0x00ff0000;
936 s->wgreen = 0x0000ff00;
937 s->wblue = 0x000000ff;
938 break;
939 case 32:
940 s->wred = 0x00ff0000;
941 s->wgreen = 0x0000ff00;
942 s->wblue = 0x000000ff;
943 break;
944 }
945 s->syncing = 0;
946 }
947
948 static void vmsvga_invalidate_display(void *opaque)
949 {
950 struct vmsvga_state_s *s = opaque;
951 if (!s->enable) {
952 s->vga.invalidate(&s->vga);
953 return;
954 }
955
956 s->invalidated = 1;
957 }
958
959 /* save the vga display in a PPM image even if no display is
960 available */
961 static void vmsvga_screen_dump(void *opaque, const char *filename)
962 {
963 struct vmsvga_state_s *s = opaque;
964 if (!s->enable) {
965 s->vga.screen_dump(&s->vga, filename);
966 return;
967 }
968
969 if (s->depth == 32) {
970 DisplaySurface *ds = qemu_create_displaysurface_from(s->width,
971 s->height, 32, ds_get_linesize(s->vga.ds), s->vga.vram_ptr);
972 ppm_save(filename, ds);
973 qemu_free(ds);
974 }
975 }
976
977 static void vmsvga_text_update(void *opaque, console_ch_t *chardata)
978 {
979 struct vmsvga_state_s *s = opaque;
980
981 if (s->vga.text_update)
982 s->vga.text_update(&s->vga, chardata);
983 }
984
985 #ifdef DIRECT_VRAM
986 static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr)
987 {
988 struct vmsvga_state_s *s = opaque;
989 if (addr < s->fb_size)
990 return *(uint8_t *) (ds_get_data(s->ds) + addr);
991 else
992 return *(uint8_t *) (s->vram_ptr + addr);
993 }
994
995 static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr)
996 {
997 struct vmsvga_state_s *s = opaque;
998 if (addr < s->fb_size)
999 return *(uint16_t *) (ds_get_data(s->ds) + addr);
1000 else
1001 return *(uint16_t *) (s->vram_ptr + addr);
1002 }
1003
1004 static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr)
1005 {
1006 struct vmsvga_state_s *s = opaque;
1007 if (addr < s->fb_size)
1008 return *(uint32_t *) (ds_get_data(s->ds) + addr);
1009 else
1010 return *(uint32_t *) (s->vram_ptr + addr);
1011 }
1012
1013 static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr,
1014 uint32_t value)
1015 {
1016 struct vmsvga_state_s *s = opaque;
1017 if (addr < s->fb_size)
1018 *(uint8_t *) (ds_get_data(s->ds) + addr) = value;
1019 else
1020 *(uint8_t *) (s->vram_ptr + addr) = value;
1021 }
1022
1023 static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr,
1024 uint32_t value)
1025 {
1026 struct vmsvga_state_s *s = opaque;
1027 if (addr < s->fb_size)
1028 *(uint16_t *) (ds_get_data(s->ds) + addr) = value;
1029 else
1030 *(uint16_t *) (s->vram_ptr + addr) = value;
1031 }
1032
1033 static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr,
1034 uint32_t value)
1035 {
1036 struct vmsvga_state_s *s = opaque;
1037 if (addr < s->fb_size)
1038 *(uint32_t *) (ds_get_data(s->ds) + addr) = value;
1039 else
1040 *(uint32_t *) (s->vram_ptr + addr) = value;
1041 }
1042
1043 static CPUReadMemoryFunc * const vmsvga_vram_read[] = {
1044 vmsvga_vram_readb,
1045 vmsvga_vram_readw,
1046 vmsvga_vram_readl,
1047 };
1048
1049 static CPUWriteMemoryFunc * const vmsvga_vram_write[] = {
1050 vmsvga_vram_writeb,
1051 vmsvga_vram_writew,
1052 vmsvga_vram_writel,
1053 };
1054 #endif
1055
1056 static int vmsvga_post_load(void *opaque, int version_id)
1057 {
1058 struct vmsvga_state_s *s = opaque;
1059
1060 s->invalidated = 1;
1061 if (s->config)
1062 s->fifo = (uint32_t *) &s->vga.vram_ptr[s->vga.vram_size - SVGA_FIFO_SIZE];
1063
1064 return 0;
1065 }
1066
1067 static const VMStateDescription vmstate_vmware_vga_internal = {
1068 .name = "vmware_vga_internal",
1069 .version_id = 0,
1070 .minimum_version_id = 0,
1071 .minimum_version_id_old = 0,
1072 .post_load = vmsvga_post_load,
1073 .fields = (VMStateField []) {
1074 VMSTATE_INT32_EQUAL(depth, struct vmsvga_state_s),
1075 VMSTATE_INT32(enable, struct vmsvga_state_s),
1076 VMSTATE_INT32(config, struct vmsvga_state_s),
1077 VMSTATE_INT32(cursor.id, struct vmsvga_state_s),
1078 VMSTATE_INT32(cursor.x, struct vmsvga_state_s),
1079 VMSTATE_INT32(cursor.y, struct vmsvga_state_s),
1080 VMSTATE_INT32(cursor.on, struct vmsvga_state_s),
1081 VMSTATE_INT32(index, struct vmsvga_state_s),
1082 VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s,
1083 scratch_size, 0, vmstate_info_uint32, uint32_t),
1084 VMSTATE_INT32(new_width, struct vmsvga_state_s),
1085 VMSTATE_INT32(new_height, struct vmsvga_state_s),
1086 VMSTATE_UINT32(guest, struct vmsvga_state_s),
1087 VMSTATE_UINT32(svgaid, struct vmsvga_state_s),
1088 VMSTATE_INT32(syncing, struct vmsvga_state_s),
1089 VMSTATE_INT32(fb_size, struct vmsvga_state_s),
1090 VMSTATE_END_OF_LIST()
1091 }
1092 };
1093
1094 static const VMStateDescription vmstate_vmware_vga = {
1095 .name = "vmware_vga",
1096 .version_id = 0,
1097 .minimum_version_id = 0,
1098 .minimum_version_id_old = 0,
1099 .fields = (VMStateField []) {
1100 VMSTATE_PCI_DEVICE(card, struct pci_vmsvga_state_s),
1101 VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0,
1102 vmstate_vmware_vga_internal, struct vmsvga_state_s),
1103 VMSTATE_END_OF_LIST()
1104 }
1105 };
1106
1107 static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size)
1108 {
1109 s->scratch_size = SVGA_SCRATCH_SIZE;
1110 s->scratch = qemu_malloc(s->scratch_size * 4);
1111
1112 vmsvga_reset(s);
1113
1114 vga_common_init(&s->vga, vga_ram_size);
1115 vga_init(&s->vga);
1116 vmstate_register(0, &vmstate_vga_common, &s->vga);
1117
1118 s->vga.ds = graphic_console_init(vmsvga_update_display,
1119 vmsvga_invalidate_display,
1120 vmsvga_screen_dump,
1121 vmsvga_text_update, s);
1122
1123 #ifdef CONFIG_BOCHS_VBE
1124 /* XXX: use optimized standard vga accesses */
1125 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
1126 vga_ram_size, s->vga.vram_offset);
1127 #endif
1128 rom_add_vga(VGABIOS_FILENAME);
1129 }
1130
1131 static void pci_vmsvga_map_ioport(PCIDevice *pci_dev, int region_num,
1132 pcibus_t addr, pcibus_t size, int type)
1133 {
1134 struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1135 struct vmsvga_state_s *s = &d->chip;
1136
1137 register_ioport_read(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1138 1, 4, vmsvga_index_read, s);
1139 register_ioport_write(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1140 1, 4, vmsvga_index_write, s);
1141 register_ioport_read(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1142 1, 4, vmsvga_value_read, s);
1143 register_ioport_write(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1144 1, 4, vmsvga_value_write, s);
1145 register_ioport_read(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1146 1, 4, vmsvga_bios_read, s);
1147 register_ioport_write(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1148 1, 4, vmsvga_bios_write, s);
1149 }
1150
1151 static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num,
1152 pcibus_t addr, pcibus_t size, int type)
1153 {
1154 struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1155 struct vmsvga_state_s *s = &d->chip;
1156 ram_addr_t iomemtype;
1157
1158 s->vram_base = addr;
1159 #ifdef DIRECT_VRAM
1160 iomemtype = cpu_register_io_memory(vmsvga_vram_read,
1161 vmsvga_vram_write, s);
1162 #else
1163 iomemtype = s->vga.vram_offset | IO_MEM_RAM;
1164 #endif
1165 cpu_register_physical_memory(s->vram_base, s->vga.vram_size,
1166 iomemtype);
1167 }
1168
1169 static int pci_vmsvga_initfn(PCIDevice *dev)
1170 {
1171 struct pci_vmsvga_state_s *s =
1172 DO_UPCAST(struct pci_vmsvga_state_s, card, dev);
1173
1174 pci_config_set_vendor_id(s->card.config, PCI_VENDOR_ID_VMWARE);
1175 pci_config_set_device_id(s->card.config, SVGA_PCI_DEVICE_ID);
1176 s->card.config[PCI_COMMAND] = 0x07; /* I/O + Memory */
1177 pci_config_set_class(s->card.config, PCI_CLASS_DISPLAY_VGA);
1178 s->card.config[0x0c] = 0x08; /* Cache line size */
1179 s->card.config[0x0d] = 0x40; /* Latency timer */
1180 s->card.config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL;
1181 s->card.config[0x2c] = PCI_VENDOR_ID_VMWARE & 0xff;
1182 s->card.config[0x2d] = PCI_VENDOR_ID_VMWARE >> 8;
1183 s->card.config[0x2e] = SVGA_PCI_DEVICE_ID & 0xff;
1184 s->card.config[0x2f] = SVGA_PCI_DEVICE_ID >> 8;
1185 s->card.config[0x3c] = 0xff; /* End */
1186
1187 pci_register_bar(&s->card, 0, 0x10,
1188 PCI_BASE_ADDRESS_SPACE_IO, pci_vmsvga_map_ioport);
1189 pci_register_bar(&s->card, 1, VGA_RAM_SIZE,
1190 PCI_BASE_ADDRESS_MEM_PREFETCH, pci_vmsvga_map_mem);
1191
1192 vmsvga_init(&s->chip, VGA_RAM_SIZE);
1193
1194 return 0;
1195 }
1196
1197 void pci_vmsvga_init(PCIBus *bus)
1198 {
1199 pci_create_simple(bus, -1, "vmware-svga");
1200 }
1201
1202 static PCIDeviceInfo vmsvga_info = {
1203 .qdev.name = "vmware-svga",
1204 .qdev.size = sizeof(struct pci_vmsvga_state_s),
1205 .qdev.vmsd = &vmstate_vmware_vga,
1206 .init = pci_vmsvga_initfn,
1207 };
1208
1209 static void vmsvga_register(void)
1210 {
1211 pci_qdev_register(&vmsvga_info);
1212 }
1213 device_init(vmsvga_register);
various patches