hw/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "apb_pci.h"
  27 #include "pc.h"
  28 #include "nvram.h"
  29 #include "fdc.h"
  30 #include "net.h"
  31 #include "qemu-timer.h"
  32 #include "sysemu.h"
  33 #include "boards.h"
  34 #include "firmware_abi.h"
  35 #include "fw_cfg.h"
  36 #include "sysbus.h"
  37 #include "ide.h"
  38 #include "loader.h"
  39 #include "elf.h"
  40
  41 //#define DEBUG_IRQ
  42 //#define DEBUG_EBUS
  43 //#define DEBUG_TIMER
  44
  45 #ifdef DEBUG_IRQ
  46 #define CPUIRQ_DPRINTF(fmt, ...)                                \
  47     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  48 #else
  49 #define CPUIRQ_DPRINTF(fmt, ...)
  50 #endif
  51
  52 #ifdef DEBUG_EBUS
  53 #define EBUS_DPRINTF(fmt, ...)                                  \
  54     do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0)
  55 #else
  56 #define EBUS_DPRINTF(fmt, ...)
  57 #endif
  58
  59 #ifdef DEBUG_TIMER
  60 #define TIMER_DPRINTF(fmt, ...)                                  \
  61     do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
  62 #else
  63 #define TIMER_DPRINTF(fmt, ...)
  64 #endif
  65
  66 #define KERNEL_LOAD_ADDR     0x00404000
  67 #define CMDLINE_ADDR         0x003ff000
  68 #define INITRD_LOAD_ADDR     0x00300000
  69 #define PROM_SIZE_MAX        (4 * 1024 * 1024)
  70 #define PROM_VADDR           0x000ffd00000ULL
  71 #define APB_SPECIAL_BASE     0x1fe00000000ULL
  72 #define APB_MEM_BASE         0x1ff00000000ULL
  73 #define VGA_BASE             (APB_MEM_BASE + 0x400000ULL)
  74 #define PROM_FILENAME        "openbios-sparc64"
  75 #define NVRAM_SIZE           0x2000
  76 #define MAX_IDE_BUS          2
  77 #define BIOS_CFG_IOPORT      0x510
  78 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
  79 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
  80 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
  81
  82 #define MAX_PILS 16
  83
  84 #define TICK_MAX             0x7fffffffffffffffULL
  85
  86 struct hwdef {
  87     const char * const default_cpu_model;
  88     uint16_t machine_id;
  89     uint64_t prom_addr;
  90     uint64_t console_serial_base;
  91 };
  92
  93 int DMA_get_channel_mode (int nchan)
  94 {
  95     return 0;
  96 }
  97 int DMA_read_memory (int nchan, void *buf, int pos, int size)
  98 {
  99     return 0;
 100 }
 101 int DMA_write_memory (int nchan, void *buf, int pos, int size)
 102 {
 103     return 0;
 104 }
 105 void DMA_hold_DREQ (int nchan) {}
 106 void DMA_release_DREQ (int nchan) {}
 107 void DMA_schedule(int nchan) {}
 108 void DMA_init (int high_page_enable) {}
 109 void DMA_register_channel (int nchan,
 110                            DMA_transfer_handler transfer_handler,
 111                            void *opaque)
 112 {
 113 }
 114
 115 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
 116 {
 117     fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 118     return 0;
 119 }
 120
 121 static int sun4u_NVRAM_set_params(M48t59State *nvram, uint16_t NVRAM_size,
 122                                   const char *arch, ram_addr_t RAM_size,
 123                                   const char *boot_devices,
 124                                   uint32_t kernel_image, uint32_t kernel_size,
 125                                   const char *cmdline,
 126                                   uint32_t initrd_image, uint32_t initrd_size,
 127                                   uint32_t NVRAM_image,
 128                                   int width, int height, int depth,
 129                                   const uint8_t *macaddr)
 130 {
 131     unsigned int i;
 132     uint32_t start, end;
 133     uint8_t image[0x1ff0];
 134     struct OpenBIOS_nvpart_v1 *part_header;
 135
 136     memset(image, '\0', sizeof(image));
 137
 138     start = 0;
 139
 140     // OpenBIOS nvram variables
 141     // Variable partition
 142     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 143     part_header->signature = OPENBIOS_PART_SYSTEM;
 144     pstrcpy(part_header->name, sizeof(part_header->name), "system");
 145
 146     end = start + sizeof(struct OpenBIOS_nvpart_v1);
 147     for (i = 0; i < nb_prom_envs; i++)
 148         end = OpenBIOS_set_var(image, end, prom_envs[i]);
 149
 150     // End marker
 151     image[end++] = '\0';
 152
 153     end = start + ((end - start + 15) & ~15);
 154     OpenBIOS_finish_partition(part_header, end - start);
 155
 156     // free partition
 157     start = end;
 158     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 159     part_header->signature = OPENBIOS_PART_FREE;
 160     pstrcpy(part_header->name, sizeof(part_header->name), "free");
 161
 162     end = 0x1fd0;
 163     OpenBIOS_finish_partition(part_header, end - start);
 164
 165     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 166
 167     for (i = 0; i < sizeof(image); i++)
 168         m48t59_write(nvram, i, image[i]);
 169
 170     return 0;
 171 }
 172 static unsigned long sun4u_load_kernel(const char *kernel_filename,
 173                                        const char *initrd_filename,
 174                                        ram_addr_t RAM_size, long *initrd_size)
 175 {
 176     int linux_boot;
 177     unsigned int i;
 178     long kernel_size;
 179     uint8_t *ptr;
 180
 181     linux_boot = (kernel_filename != NULL);
 182
 183     kernel_size = 0;
 184     if (linux_boot) {
 185         int bswap_needed;
 186
 187 #ifdef BSWAP_NEEDED
 188         bswap_needed = 1;
 189 #else
 190         bswap_needed = 0;
 191 #endif
 192         kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
 193                                NULL, NULL, 1, ELF_MACHINE, 0);
 194         if (kernel_size < 0)
 195             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 196                                     RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
 197                                     TARGET_PAGE_SIZE);
 198         if (kernel_size < 0)
 199             kernel_size = load_image_targphys(kernel_filename,
 200                                               KERNEL_LOAD_ADDR,
 201                                               RAM_size - KERNEL_LOAD_ADDR);
 202         if (kernel_size < 0) {
 203             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 204                     kernel_filename);
 205             exit(1);
 206         }
 207
 208         /* load initrd */
 209         *initrd_size = 0;
 210         if (initrd_filename) {
 211             *initrd_size = load_image_targphys(initrd_filename,
 212                                                INITRD_LOAD_ADDR,
 213                                                RAM_size - INITRD_LOAD_ADDR);
 214             if (*initrd_size < 0) {
 215                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 216                         initrd_filename);
 217                 exit(1);
 218             }
 219         }
 220         if (*initrd_size > 0) {
 221             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 222                 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
 223                 if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
 224                     stl_p(ptr + 24, INITRD_LOAD_ADDR + KERNEL_LOAD_ADDR - 0x4000);
 225                     stl_p(ptr + 28, *initrd_size);
 226                     break;
 227                 }
 228             }
 229         }
 230     }
 231     return kernel_size;
 232 }
 233
 234 void pic_info(Monitor *mon)
 235 {
 236 }
 237
 238 void irq_info(Monitor *mon)
 239 {
 240 }
 241
 242 void cpu_check_irqs(CPUState *env)
 243 {
 244     uint32_t pil = env->pil_in |
 245                   (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
 246
 247     /* check if TM or SM in SOFTINT are set
 248        setting these also causes interrupt 14 */
 249     if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
 250         pil |= 1 << 14;
 251     }
 252
 253     if (!pil) {
 254         if (env->interrupt_request & CPU_INTERRUPT_HARD) {
 255             CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
 256                            env->interrupt_index);
 257             env->interrupt_index = 0;
 258             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 259         }
 260         return;
 261     }
 262
 263     if (cpu_interrupts_enabled(env)) {
 264
 265         unsigned int i;
 266
 267         for (i = 15; i > env->psrpil; i--) {
 268             if (pil & (1 << i)) {
 269                 int old_interrupt = env->interrupt_index;
 270                 int new_interrupt = TT_EXTINT | i;
 271
 272                 if (env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt) {
 273                     CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
 274                                    "current %x >= pending %x\n",
 275                                    env->tl, cpu_tsptr(env)->tt, new_interrupt);
 276                 } else if (old_interrupt != new_interrupt) {
 277                     env->interrupt_index = new_interrupt;
 278                     CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
 279                                    old_interrupt, new_interrupt);
 280                     cpu_interrupt(env, CPU_INTERRUPT_HARD);
 281                 }
 282                 break;
 283             }
 284         }
 285     } else {
 286         CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
 287                        "current interrupt %x\n",
 288                        pil, env->pil_in, env->softint, env->interrupt_index);
 289     }
 290 }
 291
 292 static void cpu_kick_irq(CPUState *env)
 293 {
 294     env->halted = 0;
 295     cpu_check_irqs(env);
 296 }
 297
 298 static void cpu_set_irq(void *opaque, int irq, int level)
 299 {
 300     CPUState *env = opaque;
 301
 302     if (level) {
 303         CPUIRQ_DPRINTF("Raise CPU IRQ %d\n", irq);
 304         env->halted = 0;
 305         env->pil_in |= 1 << irq;
 306         cpu_check_irqs(env);
 307     } else {
 308         CPUIRQ_DPRINTF("Lower CPU IRQ %d\n", irq);
 309         env->pil_in &= ~(1 << irq);
 310         cpu_check_irqs(env);
 311     }
 312 }
 313
 314 typedef struct ResetData {
 315     CPUState *env;
 316     uint64_t prom_addr;
 317 } ResetData;
 318
 319 void cpu_put_timer(QEMUFile *f, CPUTimer *s)
 320 {
 321     qemu_put_be32s(f, &s->frequency);
 322     qemu_put_be32s(f, &s->disabled);
 323     qemu_put_be64s(f, &s->disabled_mask);
 324     qemu_put_sbe64s(f, &s->clock_offset);
 325
 326     qemu_put_timer(f, s->qtimer);
 327 }
 328
 329 void cpu_get_timer(QEMUFile *f, CPUTimer *s)
 330 {
 331     qemu_get_be32s(f, &s->frequency);
 332     qemu_get_be32s(f, &s->disabled);
 333     qemu_get_be64s(f, &s->disabled_mask);
 334     qemu_get_sbe64s(f, &s->clock_offset);
 335
 336     qemu_get_timer(f, s->qtimer);
 337 }
 338
 339 static CPUTimer* cpu_timer_create(const char* name, CPUState *env,
 340                                   QEMUBHFunc *cb, uint32_t frequency,
 341                                   uint64_t disabled_mask)
 342 {
 343     CPUTimer *timer = qemu_mallocz(sizeof (CPUTimer));
 344
 345     timer->name = name;
 346     timer->frequency = frequency;
 347     timer->disabled_mask = disabled_mask;
 348
 349     timer->disabled = 1;
 350     timer->clock_offset = qemu_get_clock(vm_clock);
 351
 352     timer->qtimer = qemu_new_timer(vm_clock, cb, env);
 353
 354     return timer;
 355 }
 356
 357 static void cpu_timer_reset(CPUTimer *timer)
 358 {
 359     timer->disabled = 1;
 360     timer->clock_offset = qemu_get_clock(vm_clock);
 361
 362     qemu_del_timer(timer->qtimer);
 363 }
 364
 365 static void main_cpu_reset(void *opaque)
 366 {
 367     ResetData *s = (ResetData *)opaque;
 368     CPUState *env = s->env;
 369     static unsigned int nr_resets;
 370
 371     cpu_reset(env);
 372
 373     cpu_timer_reset(env->tick);
 374     cpu_timer_reset(env->stick);
 375     cpu_timer_reset(env->hstick);
 376
 377     env->gregs[1] = 0; // Memory start
 378     env->gregs[2] = ram_size; // Memory size
 379     env->gregs[3] = 0; // Machine description XXX
 380     if (nr_resets++ == 0) {
 381         /* Power on reset */
 382         env->pc = s->prom_addr + 0x20ULL;
 383     } else {
 384         env->pc = s->prom_addr + 0x40ULL;
 385     }
 386     env->npc = env->pc + 4;
 387 }
 388
 389 static void tick_irq(void *opaque)
 390 {
 391     CPUState *env = opaque;
 392
 393     CPUTimer* timer = env->tick;
 394
 395     if (timer->disabled) {
 396         CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
 397         return;
 398     } else {
 399         CPUIRQ_DPRINTF("tick: fire\n");
 400     }
 401
 402     env->softint |= SOFTINT_TIMER;
 403     cpu_kick_irq(env);
 404 }
 405
 406 static void stick_irq(void *opaque)
 407 {
 408     CPUState *env = opaque;
 409
 410     CPUTimer* timer = env->stick;
 411
 412     if (timer->disabled) {
 413         CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
 414         return;
 415     } else {
 416         CPUIRQ_DPRINTF("stick: fire\n");
 417     }
 418
 419     env->softint |= SOFTINT_STIMER;
 420     cpu_kick_irq(env);
 421 }
 422
 423 static void hstick_irq(void *opaque)
 424 {
 425     CPUState *env = opaque;
 426
 427     CPUTimer* timer = env->hstick;
 428
 429     if (timer->disabled) {
 430         CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
 431         return;
 432     } else {
 433         CPUIRQ_DPRINTF("hstick: fire\n");
 434     }
 435
 436     env->softint |= SOFTINT_STIMER;
 437     cpu_kick_irq(env);
 438 }
 439
 440 static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency)
 441 {
 442     return muldiv64(cpu_ticks, get_ticks_per_sec(), frequency);
 443 }
 444
 445 static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency)
 446 {
 447     return muldiv64(timer_ticks, frequency, get_ticks_per_sec());
 448 }
 449
 450 void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
 451 {
 452     uint64_t real_count = count & ~timer->disabled_mask;
 453     uint64_t disabled_bit = count & timer->disabled_mask;
 454
 455     int64_t vm_clock_offset = qemu_get_clock(vm_clock) -
 456                     cpu_to_timer_ticks(real_count, timer->frequency);
 457
 458     TIMER_DPRINTF("%s set_count count=0x%016lx (%s) p=%p\n",
 459                   timer->name, real_count,
 460                   timer->disabled?"disabled":"enabled", timer);
 461
 462     timer->disabled = disabled_bit ? 1 : 0;
 463     timer->clock_offset = vm_clock_offset;
 464 }
 465
 466 uint64_t cpu_tick_get_count(CPUTimer *timer)
 467 {
 468     uint64_t real_count = timer_to_cpu_ticks(
 469                     qemu_get_clock(vm_clock) - timer->clock_offset,
 470                     timer->frequency);
 471
 472     TIMER_DPRINTF("%s get_count count=0x%016lx (%s) p=%p\n",
 473            timer->name, real_count,
 474            timer->disabled?"disabled":"enabled", timer);
 475
 476     if (timer->disabled)
 477         real_count |= timer->disabled_mask;
 478
 479     return real_count;
 480 }
 481
 482 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
 483 {
 484     int64_t now = qemu_get_clock(vm_clock);
 485
 486     uint64_t real_limit = limit & ~timer->disabled_mask;
 487     timer->disabled = (limit & timer->disabled_mask) ? 1 : 0;
 488
 489     int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) +
 490                     timer->clock_offset;
 491
 492     if (expires < now) {
 493         expires = now + 1;
 494     }
 495
 496     TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
 497                   "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
 498                   timer->name, real_limit,
 499                   timer->disabled?"disabled":"enabled",
 500                   timer, limit,
 501                   timer_to_cpu_ticks(now - timer->clock_offset,
 502                                      timer->frequency),
 503                   timer_to_cpu_ticks(expires - now, timer->frequency));
 504
 505     if (!real_limit) {
 506         TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
 507                 timer->name);
 508         qemu_del_timer(timer->qtimer);
 509     } else if (timer->disabled) {
 510         qemu_del_timer(timer->qtimer);
 511     } else {
 512         qemu_mod_timer(timer->qtimer, expires);
 513     }
 514 }
 515
 516 static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
 517                               pcibus_t addr, pcibus_t size, int type)
 518 {
 519     EBUS_DPRINTF("Mapping region %d registers at %" FMT_PCIBUS "\n",
 520                  region_num, addr);
 521     switch (region_num) {
 522     case 0:
 523         isa_mmio_init(addr, 0x1000000, 1);
 524         break;
 525     case 1:
 526         isa_mmio_init(addr, 0x800000, 1);
 527         break;
 528     }
 529 }
 530
 531 static void dummy_isa_irq_handler(void *opaque, int n, int level)
 532 {
 533 }
 534
 535 /* EBUS (Eight bit bus) bridge */
 536 static void
 537 pci_ebus_init(PCIBus *bus, int devfn)
 538 {
 539     qemu_irq *isa_irq;
 540
 541     pci_create_simple(bus, devfn, "ebus");
 542     isa_irq = qemu_allocate_irqs(dummy_isa_irq_handler, NULL, 16);
 543     isa_bus_irqs(isa_irq);
 544 }
 545
 546 static int
 547 pci_ebus_init1(PCIDevice *s)
 548 {
 549     isa_bus_new(&s->qdev);
 550
 551     pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN);
 552     pci_config_set_device_id(s->config, PCI_DEVICE_ID_SUN_EBUS);
 553     s->config[0x04] = 0x06; // command = bus master, pci mem
 554     s->config[0x05] = 0x00;
 555     s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 556     s->config[0x07] = 0x03; // status = medium devsel
 557     s->config[0x08] = 0x01; // revision
 558     s->config[0x09] = 0x00; // programming i/f
 559     pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER);
 560     s->config[0x0D] = 0x0a; // latency_timer
 561     s->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 562
 563     pci_register_bar(s, 0, 0x1000000, PCI_BASE_ADDRESS_SPACE_MEMORY,
 564                            ebus_mmio_mapfunc);
 565     pci_register_bar(s, 1, 0x800000,  PCI_BASE_ADDRESS_SPACE_MEMORY,
 566                            ebus_mmio_mapfunc);
 567     return 0;
 568 }
 569
 570 static PCIDeviceInfo ebus_info = {
 571     .qdev.name = "ebus",
 572     .qdev.size = sizeof(PCIDevice),
 573     .init = pci_ebus_init1,
 574 };
 575
 576 static void pci_ebus_register(void)
 577 {
 578     pci_qdev_register(&ebus_info);
 579 }
 580
 581 device_init(pci_ebus_register);
 582
 583 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
 584 {
 585     target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
 586     return addr + *base_addr - PROM_VADDR;
 587 }
 588
 589 /* Boot PROM (OpenBIOS) */
 590 static void prom_init(target_phys_addr_t addr, const char *bios_name)
 591 {
 592     DeviceState *dev;
 593     SysBusDevice *s;
 594     char *filename;
 595     int ret;
 596
 597     dev = qdev_create(NULL, "openprom");
 598     qdev_init_nofail(dev);
 599     s = sysbus_from_qdev(dev);
 600
 601     sysbus_mmio_map(s, 0, addr);
 602
 603     /* load boot prom */
 604     if (bios_name == NULL) {
 605         bios_name = PROM_FILENAME;
 606     }
 607     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 608     if (filename) {
 609         ret = load_elf(filename, translate_prom_address, &addr,
 610                        NULL, NULL, NULL, 1, ELF_MACHINE, 0);
 611         if (ret < 0 || ret > PROM_SIZE_MAX) {
 612             ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
 613         }
 614         qemu_free(filename);
 615     } else {
 616         ret = -1;
 617     }
 618     if (ret < 0 || ret > PROM_SIZE_MAX) {
 619         fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
 620         exit(1);
 621     }
 622 }
 623
 624 static int prom_init1(SysBusDevice *dev)
 625 {
 626     ram_addr_t prom_offset;
 627
 628     prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
 629     sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
 630     return 0;
 631 }
 632
 633 static SysBusDeviceInfo prom_info = {
 634     .init = prom_init1,
 635     .qdev.name  = "openprom",
 636     .qdev.size  = sizeof(SysBusDevice),
 637     .qdev.props = (Property[]) {
 638         {/* end of property list */}
 639     }
 640 };
 641
 642 static void prom_register_devices(void)
 643 {
 644     sysbus_register_withprop(&prom_info);
 645 }
 646
 647 device_init(prom_register_devices);
 648
 649
 650 typedef struct RamDevice
 651 {
 652     SysBusDevice busdev;
 653     uint64_t size;
 654 } RamDevice;
 655
 656 /* System RAM */
 657 static int ram_init1(SysBusDevice *dev)
 658 {
 659     ram_addr_t RAM_size, ram_offset;
 660     RamDevice *d = FROM_SYSBUS(RamDevice, dev);
 661
 662     RAM_size = d->size;
 663
 664     ram_offset = qemu_ram_alloc(RAM_size);
 665     sysbus_init_mmio(dev, RAM_size, ram_offset);
 666     return 0;
 667 }
 668
 669 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size)
 670 {
 671     DeviceState *dev;
 672     SysBusDevice *s;
 673     RamDevice *d;
 674
 675     /* allocate RAM */
 676     dev = qdev_create(NULL, "memory");
 677     s = sysbus_from_qdev(dev);
 678
 679     d = FROM_SYSBUS(RamDevice, s);
 680     d->size = RAM_size;
 681     qdev_init_nofail(dev);
 682
 683     sysbus_mmio_map(s, 0, addr);
 684 }
 685
 686 static SysBusDeviceInfo ram_info = {
 687     .init = ram_init1,
 688     .qdev.name  = "memory",
 689     .qdev.size  = sizeof(RamDevice),
 690     .qdev.props = (Property[]) {
 691         DEFINE_PROP_UINT64("size", RamDevice, size, 0),
 692         DEFINE_PROP_END_OF_LIST(),
 693     }
 694 };
 695
 696 static void ram_register_devices(void)
 697 {
 698     sysbus_register_withprop(&ram_info);
 699 }
 700
 701 device_init(ram_register_devices);
 702
 703 static CPUState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef)
 704 {
 705     CPUState *env;
 706     ResetData *reset_info;
 707
 708     uint32_t   tick_frequency = 100*1000000;
 709     uint32_t  stick_frequency = 100*1000000;
 710     uint32_t hstick_frequency = 100*1000000;
 711
 712     if (!cpu_model)
 713         cpu_model = hwdef->default_cpu_model;
 714     env = cpu_init(cpu_model);
 715     if (!env) {
 716         fprintf(stderr, "Unable to find Sparc CPU definition\n");
 717         exit(1);
 718     }
 719
 720     env->tick = cpu_timer_create("tick", env, tick_irq,
 721                                   tick_frequency, TICK_NPT_MASK);
 722
 723     env->stick = cpu_timer_create("stick", env, stick_irq,
 724                                    stick_frequency, TICK_INT_DIS);
 725
 726     env->hstick = cpu_timer_create("hstick", env, hstick_irq,
 727                                     hstick_frequency, TICK_INT_DIS);
 728
 729     reset_info = qemu_mallocz(sizeof(ResetData));
 730     reset_info->env = env;
 731     reset_info->prom_addr = hwdef->prom_addr;
 732     qemu_register_reset(main_cpu_reset, reset_info);
 733
 734     return env;
 735 }
 736
 737 static void sun4uv_init(ram_addr_t RAM_size,
 738                         const char *boot_devices,
 739                         const char *kernel_filename, const char *kernel_cmdline,
 740                         const char *initrd_filename, const char *cpu_model,
 741                         const struct hwdef *hwdef)
 742 {
 743     CPUState *env;
 744     M48t59State *nvram;
 745     unsigned int i;
 746     long initrd_size, kernel_size;
 747     PCIBus *pci_bus, *pci_bus2, *pci_bus3;
 748     qemu_irq *irq;
 749     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 750     DriveInfo *fd[MAX_FD];
 751     void *fw_cfg;
 752
 753     /* init CPUs */
 754     env = cpu_devinit(cpu_model, hwdef);
 755
 756     /* set up devices */
 757     ram_init(0, RAM_size);
 758
 759     prom_init(hwdef->prom_addr, bios_name);
 760
 761
 762     irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
 763     pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, irq, &pci_bus2,
 764                            &pci_bus3);
 765     isa_mem_base = VGA_BASE;
 766     pci_vga_init(pci_bus, 0, 0);
 767
 768     // XXX Should be pci_bus3
 769     pci_ebus_init(pci_bus, -1);
 770
 771     i = 0;
 772     if (hwdef->console_serial_base) {
 773         serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200,
 774                        serial_hds[i], 1, 1);
 775         i++;
 776     }
 777     for(; i < MAX_SERIAL_PORTS; i++) {
 778         if (serial_hds[i]) {
 779             serial_isa_init(i, serial_hds[i]);
 780         }
 781     }
 782
 783     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 784         if (parallel_hds[i]) {
 785             parallel_init(i, parallel_hds[i]);
 786         }
 787     }
 788
 789     for(i = 0; i < nb_nics; i++)
 790         pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 791
 792     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 793         fprintf(stderr, "qemu: too many IDE bus\n");
 794         exit(1);
 795     }
 796     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 797         hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS,
 798                           i % MAX_IDE_DEVS);
 799     }
 800
 801     pci_cmd646_ide_init(pci_bus, hd, 1);
 802
 803     isa_create_simple("i8042");
 804     for(i = 0; i < MAX_FD; i++) {
 805         fd[i] = drive_get(IF_FLOPPY, 0, i);
 806     }
 807     fdctrl_init_isa(fd);
 808     nvram = m48t59_init_isa(0x0074, NVRAM_SIZE, 59);
 809
 810     initrd_size = 0;
 811     kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename,
 812                                     ram_size, &initrd_size);
 813
 814     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
 815                            KERNEL_LOAD_ADDR, kernel_size,
 816                            kernel_cmdline,
 817                            INITRD_LOAD_ADDR, initrd_size,
 818                            /* XXX: need an option to load a NVRAM image */
 819                            0,
 820                            graphic_width, graphic_height, graphic_depth,
 821                            (uint8_t *)&nd_table[0].macaddr);
 822
 823     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 824     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 825     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 826     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 827     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
 828     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 829     if (kernel_cmdline) {
 830         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
 831                        strlen(kernel_cmdline) + 1);
 832         fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 833                          (uint8_t*)strdup(kernel_cmdline),
 834                          strlen(kernel_cmdline) + 1);
 835     } else {
 836         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
 837     }
 838     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
 839     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 840     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
 841
 842     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
 843     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
 844     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
 845
 846     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 847 }
 848
 849 enum {
 850     sun4u_id = 0,
 851     sun4v_id = 64,
 852     niagara_id,
 853 };
 854
 855 static const struct hwdef hwdefs[] = {
 856     /* Sun4u generic PC-like machine */
 857     {
 858         .default_cpu_model = "TI UltraSparc II",
 859         .machine_id = sun4u_id,
 860         .prom_addr = 0x1fff0000000ULL,
 861         .console_serial_base = 0,
 862     },
 863     /* Sun4v generic PC-like machine */
 864     {
 865         .default_cpu_model = "Sun UltraSparc T1",
 866         .machine_id = sun4v_id,
 867         .prom_addr = 0x1fff0000000ULL,
 868         .console_serial_base = 0,
 869     },
 870     /* Sun4v generic Niagara machine */
 871     {
 872         .default_cpu_model = "Sun UltraSparc T1",
 873         .machine_id = niagara_id,
 874         .prom_addr = 0xfff0000000ULL,
 875         .console_serial_base = 0xfff0c2c000ULL,
 876     },
 877 };
 878
 879 /* Sun4u hardware initialisation */
 880 static void sun4u_init(ram_addr_t RAM_size,
 881                        const char *boot_devices,
 882                        const char *kernel_filename, const char *kernel_cmdline,
 883                        const char *initrd_filename, const char *cpu_model)
 884 {
 885     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 886                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
 887 }
 888
 889 /* Sun4v hardware initialisation */
 890 static void sun4v_init(ram_addr_t RAM_size,
 891                        const char *boot_devices,
 892                        const char *kernel_filename, const char *kernel_cmdline,
 893                        const char *initrd_filename, const char *cpu_model)
 894 {
 895     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 896                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
 897 }
 898
 899 /* Niagara hardware initialisation */
 900 static void niagara_init(ram_addr_t RAM_size,
 901                          const char *boot_devices,
 902                          const char *kernel_filename, const char *kernel_cmdline,
 903                          const char *initrd_filename, const char *cpu_model)
 904 {
 905     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 906                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
 907 }
 908
 909 static QEMUMachine sun4u_machine = {
 910     .name = "sun4u",
 911     .desc = "Sun4u platform",
 912     .init = sun4u_init,
 913     .max_cpus = 1, // XXX for now
 914     .is_default = 1,
 915 };
 916
 917 static QEMUMachine sun4v_machine = {
 918     .name = "sun4v",
 919     .desc = "Sun4v platform",
 920     .init = sun4v_init,
 921     .max_cpus = 1, // XXX for now
 922 };
 923
 924 static QEMUMachine niagara_machine = {
 925     .name = "Niagara",
 926     .desc = "Sun4v platform, Niagara",
 927     .init = niagara_init,
 928     .max_cpus = 1, // XXX for now
 929 };
 930
 931 static void sun4u_machine_init(void)
 932 {
 933     qemu_register_machine(&sun4u_machine);
 934     qemu_register_machine(&sun4v_machine);
 935     qemu_register_machine(&niagara_machine);
 936 }
 937
 938 machine_init(sun4u_machine_init);