PCI: Bus number from the bridge, not the device
[qemu/mdroth.git] / hw / hpet_emul.h
blob8bf312ab21f38886f9aaee5a3e625308e3df6faf
1 /*
2 * QEMU Emulated HPET support
4 * Copyright IBM, Corp. 2008
6 * Authors:
7 * Beth Kon <bkon@us.ibm.com>
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
13 #ifndef QEMU_HPET_EMUL_H
14 #define QEMU_HPET_EMUL_H
16 #define HPET_BASE 0xfed00000
17 #define HPET_CLK_PERIOD 10000000ULL /* 10000000 femtoseconds == 10ns*/
19 #define FS_PER_NS 1000000
20 #define HPET_MIN_TIMERS 3
21 #define HPET_MAX_TIMERS 32
23 #define HPET_NUM_IRQ_ROUTES 32
25 #define HPET_CFG_ENABLE 0x001
26 #define HPET_CFG_LEGACY 0x002
28 #define HPET_ID 0x000
29 #define HPET_PERIOD 0x004
30 #define HPET_CFG 0x010
31 #define HPET_STATUS 0x020
32 #define HPET_COUNTER 0x0f0
33 #define HPET_TN_CFG 0x000
34 #define HPET_TN_CMP 0x008
35 #define HPET_TN_ROUTE 0x010
36 #define HPET_CFG_WRITE_MASK 0x3
38 #define HPET_ID_NUM_TIM_SHIFT 8
39 #define HPET_ID_NUM_TIM_MASK 0x1f00
41 #define HPET_TN_TYPE_LEVEL 0x002
42 #define HPET_TN_ENABLE 0x004
43 #define HPET_TN_PERIODIC 0x008
44 #define HPET_TN_PERIODIC_CAP 0x010
45 #define HPET_TN_SIZE_CAP 0x020
46 #define HPET_TN_SETVAL 0x040
47 #define HPET_TN_32BIT 0x100
48 #define HPET_TN_INT_ROUTE_MASK 0x3e00
49 #define HPET_TN_FSB_ENABLE 0x4000
50 #define HPET_TN_FSB_CAP 0x8000
51 #define HPET_TN_CFG_WRITE_MASK 0x7f4e
52 #define HPET_TN_INT_ROUTE_SHIFT 9
53 #define HPET_TN_INT_ROUTE_CAP_SHIFT 32
54 #define HPET_TN_CFG_BITS_READONLY_OR_RESERVED 0xffff80b1U
56 struct hpet_fw_entry
58 uint32_t event_timer_block_id;
59 uint64_t address;
60 uint16_t min_tick;
61 uint8_t page_prot;
62 } __attribute__ ((packed));
64 struct hpet_fw_config
66 uint8_t count;
67 struct hpet_fw_entry hpet[8];
68 } __attribute__ ((packed));
70 extern struct hpet_fw_config hpet_cfg;
71 #endif