hw/xio3130_upstream.c

   1 /*
   2  * xio3130_upstream.c
   3  * TI X3130 pci express upstream port switch
   4  *
   5  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   6  *                    VA Linux Systems Japan K.K.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "pci_ids.h"
  23 #include "msi.h"
  24 #include "pcie.h"
  25 #include "xio3130_upstream.h"
  26
  27 #define PCI_DEVICE_ID_TI_XIO3130U       0x8232  /* upstream port */
  28 #define XIO3130_REVISION                0x2
  29 #define XIO3130_MSI_OFFSET              0x70
  30 #define XIO3130_MSI_SUPPORTED_FLAGS     PCI_MSI_FLAGS_64BIT
  31 #define XIO3130_MSI_NR_VECTOR           1
  32 #define XIO3130_SSVID_OFFSET            0x80
  33 #define XIO3130_SSVID_SVID              0
  34 #define XIO3130_SSVID_SSID              0
  35 #define XIO3130_EXP_OFFSET              0x90
  36 #define XIO3130_AER_OFFSET              0x100
  37
  38 static void xio3130_upstream_write_config(PCIDevice *d, uint32_t address,
  39                                           uint32_t val, int len)
  40 {
  41     pci_bridge_write_config(d, address, val, len);
  42     pcie_cap_flr_write_config(d, address, val, len);
  43     msi_write_config(d, address, val, len);
  44     /* TODO: AER */
  45 }
  46
  47 static void xio3130_upstream_reset(DeviceState *qdev)
  48 {
  49     PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
  50     msi_reset(d);
  51     pci_bridge_reset(qdev);
  52     pcie_cap_deverr_reset(d);
  53 }
  54
  55 static int xio3130_upstream_initfn(PCIDevice *d)
  56 {
  57     PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
  58     PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
  59     int rc;
  60
  61     rc = pci_bridge_initfn(d);
  62     if (rc < 0) {
  63         return rc;
  64     }
  65
  66     pcie_port_init_reg(d);
  67     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_TI);
  68     pci_config_set_device_id(d->config, PCI_DEVICE_ID_TI_XIO3130U);
  69     d->config[PCI_REVISION_ID] = XIO3130_REVISION;
  70
  71     rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR,
  72                   XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
  73                   XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT);
  74     if (rc < 0) {
  75         return rc;
  76     }
  77     rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,
  78                                XIO3130_SSVID_SVID, XIO3130_SSVID_SSID);
  79     if (rc < 0) {
  80         return rc;
  81     }
  82     rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM,
  83                        p->port);
  84     if (rc < 0) {
  85         return rc;
  86     }
  87
  88     /* TODO: implement FLR */
  89     pcie_cap_flr_init(d);
  90
  91     pcie_cap_deverr_init(d);
  92     /* TODO: AER */
  93
  94     return 0;
  95 }
  96
  97 static int xio3130_upstream_exitfn(PCIDevice *d)
  98 {
  99     /* TODO: AER */
 100     msi_uninit(d);
 101     pcie_cap_exit(d);
 102     return pci_bridge_exitfn(d);
 103 }
 104
 105 PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn, bool multifunction,
 106                              const char *bus_name, pci_map_irq_fn map_irq,
 107                              uint8_t port)
 108 {
 109     PCIDevice *d;
 110     PCIBridge *br;
 111     DeviceState *qdev;
 112
 113     d = pci_create_multifunction(bus, devfn, multifunction, "x3130-upstream");
 114     if (!d) {
 115         return NULL;
 116     }
 117     br = DO_UPCAST(PCIBridge, dev, d);
 118
 119     qdev = &br->dev.qdev;
 120     pci_bridge_map_irq(br, bus_name, map_irq);
 121     qdev_prop_set_uint8(qdev, "port", port);
 122     qdev_init_nofail(qdev);
 123
 124     return DO_UPCAST(PCIEPort, br, br);
 125 }
 126
 127 static const VMStateDescription vmstate_xio3130_upstream = {
 128     .name = "xio3130-express-upstream-port",
 129     .version_id = 1,
 130     .minimum_version_id = 1,
 131     .minimum_version_id_old = 1,
 132     .fields = (VMStateField[]) {
 133         VMSTATE_PCIE_DEVICE(br.dev, PCIEPort),
 134         /* TODO: AER */
 135         VMSTATE_END_OF_LIST()
 136     }
 137 };
 138
 139 static PCIDeviceInfo xio3130_upstream_info = {
 140     .qdev.name = "x3130-upstream",
 141     .qdev.desc = "TI X3130 Upstream Port of PCI Express Switch",
 142     .qdev.size = sizeof(PCIEPort),
 143     .qdev.reset = xio3130_upstream_reset,
 144     .qdev.vmsd = &vmstate_xio3130_upstream,
 145
 146     .is_express = 1,
 147     .is_bridge = 1,
 148     .config_write = xio3130_upstream_write_config,
 149     .init = xio3130_upstream_initfn,
 150     .exit = xio3130_upstream_exitfn,
 151
 152     .qdev.props = (Property[]) {
 153         DEFINE_PROP_UINT8("port", PCIEPort, port, 0),
 154         /* TODO: AER */
 155         DEFINE_PROP_END_OF_LIST(),
 156     }
 157 };
 158
 159 static void xio3130_upstream_register(void)
 160 {
 161     pci_qdev_register(&xio3130_upstream_info);
 162 }
 163
 164 device_init(xio3130_upstream_register);
 165
 166
 167 /*
 168  * Local variables:
 169  *  c-indent-level: 4
 170  *  c-basic-offset: 4
 171  *  tab-width: 8
 172  *  indent-tab-mode: nil
 173  * End:
 174  */