hw/arm_timer.c

   1 /*
   2  * ARM PrimeCell Timer modules.
   3  *
   4  * Copyright (c) 2005-2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "sysbus.h"
  11 #include "qemu-timer.h"
  12
  13 /* Common timer implementation.  */
  14
  15 #define TIMER_CTRL_ONESHOT      (1 << 0)
  16 #define TIMER_CTRL_32BIT        (1 << 1)
  17 #define TIMER_CTRL_DIV1         (0 << 2)
  18 #define TIMER_CTRL_DIV16        (1 << 2)
  19 #define TIMER_CTRL_DIV256       (2 << 2)
  20 #define TIMER_CTRL_IE           (1 << 5)
  21 #define TIMER_CTRL_PERIODIC     (1 << 6)
  22 #define TIMER_CTRL_ENABLE       (1 << 7)
  23
  24 typedef struct {
  25     ptimer_state *timer;
  26     uint32_t control;
  27     uint32_t limit;
  28     int freq;
  29     int int_level;
  30     qemu_irq irq;
  31 } arm_timer_state;
  32
  33 /* Check all active timers, and schedule the next timer interrupt.  */
  34
  35 static void arm_timer_update(arm_timer_state *s)
  36 {
  37     /* Update interrupts.  */
  38     if (s->int_level && (s->control & TIMER_CTRL_IE)) {
  39         qemu_irq_raise(s->irq);
  40     } else {
  41         qemu_irq_lower(s->irq);
  42     }
  43 }
  44
  45 static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
  46 {
  47     arm_timer_state *s = (arm_timer_state *)opaque;
  48
  49     switch (offset >> 2) {
  50     case 0: /* TimerLoad */
  51     case 6: /* TimerBGLoad */
  52         return s->limit;
  53     case 1: /* TimerValue */
  54         return ptimer_get_count(s->timer);
  55     case 2: /* TimerControl */
  56         return s->control;
  57     case 4: /* TimerRIS */
  58         return s->int_level;
  59     case 5: /* TimerMIS */
  60         if ((s->control & TIMER_CTRL_IE) == 0)
  61             return 0;
  62         return s->int_level;
  63     default:
  64         hw_error("arm_timer_read: Bad offset %x\n", (int)offset);
  65         return 0;
  66     }
  67 }
  68
  69 /* Reset the timer limit after settings have changed.  */
  70 static void arm_timer_recalibrate(arm_timer_state *s, int reload)
  71 {
  72     uint32_t limit;
  73
  74     if ((s->control & (TIMER_CTRL_PERIODIC | TIMER_CTRL_ONESHOT)) == 0) {
  75         /* Free running.  */
  76         if (s->control & TIMER_CTRL_32BIT)
  77             limit = 0xffffffff;
  78         else
  79             limit = 0xffff;
  80     } else {
  81           /* Periodic.  */
  82           limit = s->limit;
  83     }
  84     ptimer_set_limit(s->timer, limit, reload);
  85 }
  86
  87 static void arm_timer_write(void *opaque, target_phys_addr_t offset,
  88                             uint32_t value)
  89 {
  90     arm_timer_state *s = (arm_timer_state *)opaque;
  91     int freq;
  92
  93     switch (offset >> 2) {
  94     case 0: /* TimerLoad */
  95         s->limit = value;
  96         arm_timer_recalibrate(s, 1);
  97         break;
  98     case 1: /* TimerValue */
  99         /* ??? Linux seems to want to write to this readonly register.
 100            Ignore it.  */
 101         break;
 102     case 2: /* TimerControl */
 103         if (s->control & TIMER_CTRL_ENABLE) {
 104             /* Pause the timer if it is running.  This may cause some
 105                inaccuracy dure to rounding, but avoids a whole lot of other
 106                messyness.  */
 107             ptimer_stop(s->timer);
 108         }
 109         s->control = value;
 110         freq = s->freq;
 111         /* ??? Need to recalculate expiry time after changing divisor.  */
 112         switch ((value >> 2) & 3) {
 113         case 1: freq >>= 4; break;
 114         case 2: freq >>= 8; break;
 115         }
 116         arm_timer_recalibrate(s, s->control & TIMER_CTRL_ENABLE);
 117         ptimer_set_freq(s->timer, freq);
 118         if (s->control & TIMER_CTRL_ENABLE) {
 119             /* Restart the timer if still enabled.  */
 120             ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0);
 121         }
 122         break;
 123     case 3: /* TimerIntClr */
 124         s->int_level = 0;
 125         break;
 126     case 6: /* TimerBGLoad */
 127         s->limit = value;
 128         arm_timer_recalibrate(s, 0);
 129         break;
 130     default:
 131         hw_error("arm_timer_write: Bad offset %x\n", (int)offset);
 132     }
 133     arm_timer_update(s);
 134 }
 135
 136 static void arm_timer_tick(void *opaque)
 137 {
 138     arm_timer_state *s = (arm_timer_state *)opaque;
 139     s->int_level = 1;
 140     arm_timer_update(s);
 141 }
 142
 143 static const VMStateDescription vmstate_arm_timer = {
 144     .name = "arm_timer",
 145     .version_id = 1,
 146     .minimum_version_id = 1,
 147     .minimum_version_id_old = 1,
 148     .fields      = (VMStateField[]) {
 149         VMSTATE_UINT32(control, arm_timer_state),
 150         VMSTATE_UINT32(limit, arm_timer_state),
 151         VMSTATE_INT32(int_level, arm_timer_state),
 152         VMSTATE_PTIMER(timer, arm_timer_state),
 153         VMSTATE_END_OF_LIST()
 154     }
 155 };
 156
 157 static arm_timer_state *arm_timer_init(uint32_t freq)
 158 {
 159     arm_timer_state *s;
 160     QEMUBH *bh;
 161
 162     s = (arm_timer_state *)g_malloc0(sizeof(arm_timer_state));
 163     s->freq = freq;
 164     s->control = TIMER_CTRL_IE;
 165
 166     bh = qemu_bh_new(arm_timer_tick, s);
 167     s->timer = ptimer_init(bh);
 168     vmstate_register(NULL, -1, &vmstate_arm_timer, s);
 169     return s;
 170 }
 171
 172 /* ARM PrimeCell SP804 dual timer module.
 173    Docs for this device don't seem to be publicly available.  This
 174    implementation is based on guesswork, the linux kernel sources and the
 175    Integrator/CP timer modules.  */
 176
 177 typedef struct {
 178     SysBusDevice busdev;
 179     arm_timer_state *timer[2];
 180     int level[2];
 181     qemu_irq irq;
 182 } sp804_state;
 183
 184 /* Merge the IRQs from the two component devices.  */
 185 static void sp804_set_irq(void *opaque, int irq, int level)
 186 {
 187     sp804_state *s = (sp804_state *)opaque;
 188
 189     s->level[irq] = level;
 190     qemu_set_irq(s->irq, s->level[0] || s->level[1]);
 191 }
 192
 193 static uint32_t sp804_read(void *opaque, target_phys_addr_t offset)
 194 {
 195     sp804_state *s = (sp804_state *)opaque;
 196
 197     /* ??? Don't know the PrimeCell ID for this device.  */
 198     if (offset < 0x20) {
 199         return arm_timer_read(s->timer[0], offset);
 200     } else {
 201         return arm_timer_read(s->timer[1], offset - 0x20);
 202     }
 203 }
 204
 205 static void sp804_write(void *opaque, target_phys_addr_t offset,
 206                         uint32_t value)
 207 {
 208     sp804_state *s = (sp804_state *)opaque;
 209
 210     if (offset < 0x20) {
 211         arm_timer_write(s->timer[0], offset, value);
 212     } else {
 213         arm_timer_write(s->timer[1], offset - 0x20, value);
 214     }
 215 }
 216
 217 static CPUReadMemoryFunc * const sp804_readfn[] = {
 218    sp804_read,
 219    sp804_read,
 220    sp804_read
 221 };
 222
 223 static CPUWriteMemoryFunc * const sp804_writefn[] = {
 224    sp804_write,
 225    sp804_write,
 226    sp804_write
 227 };
 228
 229
 230 static const VMStateDescription vmstate_sp804 = {
 231     .name = "sp804",
 232     .version_id = 1,
 233     .minimum_version_id = 1,
 234     .minimum_version_id_old = 1,
 235     .fields      = (VMStateField[]) {
 236         VMSTATE_INT32_ARRAY(level, sp804_state, 2),
 237         VMSTATE_END_OF_LIST()
 238     }
 239 };
 240
 241 static int sp804_init(SysBusDevice *dev)
 242 {
 243     int iomemtype;
 244     sp804_state *s = FROM_SYSBUS(sp804_state, dev);
 245     qemu_irq *qi;
 246
 247     qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
 248     sysbus_init_irq(dev, &s->irq);
 249     /* ??? The timers are actually configurable between 32kHz and 1MHz, but
 250        we don't implement that.  */
 251     s->timer[0] = arm_timer_init(1000000);
 252     s->timer[1] = arm_timer_init(1000000);
 253     s->timer[0]->irq = qi[0];
 254     s->timer[1]->irq = qi[1];
 255     iomemtype = cpu_register_io_memory(sp804_readfn,
 256                                        sp804_writefn, s, DEVICE_NATIVE_ENDIAN);
 257     sysbus_init_mmio(dev, 0x1000, iomemtype);
 258     vmstate_register(&dev->qdev, -1, &vmstate_sp804, s);
 259     return 0;
 260 }
 261
 262
 263 /* Integrator/CP timer module.  */
 264
 265 typedef struct {
 266     SysBusDevice busdev;
 267     arm_timer_state *timer[3];
 268 } icp_pit_state;
 269
 270 static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
 271 {
 272     icp_pit_state *s = (icp_pit_state *)opaque;
 273     int n;
 274
 275     /* ??? Don't know the PrimeCell ID for this device.  */
 276     n = offset >> 8;
 277     if (n > 3) {
 278         hw_error("sp804_read: Bad timer %d\n", n);
 279     }
 280
 281     return arm_timer_read(s->timer[n], offset & 0xff);
 282 }
 283
 284 static void icp_pit_write(void *opaque, target_phys_addr_t offset,
 285                           uint32_t value)
 286 {
 287     icp_pit_state *s = (icp_pit_state *)opaque;
 288     int n;
 289
 290     n = offset >> 8;
 291     if (n > 3) {
 292         hw_error("sp804_write: Bad timer %d\n", n);
 293     }
 294
 295     arm_timer_write(s->timer[n], offset & 0xff, value);
 296 }
 297
 298
 299 static CPUReadMemoryFunc * const icp_pit_readfn[] = {
 300    icp_pit_read,
 301    icp_pit_read,
 302    icp_pit_read
 303 };
 304
 305 static CPUWriteMemoryFunc * const icp_pit_writefn[] = {
 306    icp_pit_write,
 307    icp_pit_write,
 308    icp_pit_write
 309 };
 310
 311 static int icp_pit_init(SysBusDevice *dev)
 312 {
 313     int iomemtype;
 314     icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev);
 315
 316     /* Timer 0 runs at the system clock speed (40MHz).  */
 317     s->timer[0] = arm_timer_init(40000000);
 318     /* The other two timers run at 1MHz.  */
 319     s->timer[1] = arm_timer_init(1000000);
 320     s->timer[2] = arm_timer_init(1000000);
 321
 322     sysbus_init_irq(dev, &s->timer[0]->irq);
 323     sysbus_init_irq(dev, &s->timer[1]->irq);
 324     sysbus_init_irq(dev, &s->timer[2]->irq);
 325
 326     iomemtype = cpu_register_io_memory(icp_pit_readfn,
 327                                        icp_pit_writefn, s,
 328                                        DEVICE_NATIVE_ENDIAN);
 329     sysbus_init_mmio(dev, 0x1000, iomemtype);
 330     /* This device has no state to save/restore.  The component timers will
 331        save themselves.  */
 332     return 0;
 333 }
 334
 335 static void arm_timer_register_devices(void)
 336 {
 337     sysbus_register_dev("integrator_pit", sizeof(icp_pit_state), icp_pit_init);
 338     sysbus_register_dev("sp804", sizeof(sp804_state), sp804_init);
 339 }
 340
 341 device_init(arm_timer_register_devices)