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Merge branch 'master' of git://git.qemu.org/qemu
[qemu/mdroth.git] / hw / pci.c
blob4dc13d2561f8752ec808b68b996fdf7851caad25
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "pci.h"
26 #include "pci_bridge.h"
27 #include "pci_internals.h"
28 #include "monitor.h"
29 #include "net.h"
30 #include "sysemu.h"
31 #include "loader.h"
32 #include "qemu-objects.h"
33 #include "range.h"
34
35 //#define DEBUG_PCI
36 #ifdef DEBUG_PCI
37 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
38 #else
39 # define PCI_DPRINTF(format, ...) do { } while (0)
40 #endif
41
42 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
43 static char *pcibus_get_dev_path(DeviceState *dev);
44 static char *pcibus_get_fw_dev_path(DeviceState *dev);
45 static int pcibus_reset(BusState *qbus);
46
47 struct BusInfo pci_bus_info = {
48 .name = "PCI",
49 .size = sizeof(PCIBus),
50 .print_dev = pcibus_dev_print,
51 .get_dev_path = pcibus_get_dev_path,
52 .get_fw_dev_path = pcibus_get_fw_dev_path,
53 .reset = pcibus_reset,
54 .props = (Property[]) {
55 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
56 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
57 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
58 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
59 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
60 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
61 QEMU_PCI_CAP_SERR_BITNR, true),
62 DEFINE_PROP_END_OF_LIST()
63 }
64 };
65
66 static void pci_update_mappings(PCIDevice *d);
67 static void pci_set_irq(void *opaque, int irq_num, int level);
68 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
69 static void pci_del_option_rom(PCIDevice *pdev);
70
71 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
72 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
73
74 struct PCIHostBus {
75 int domain;
76 struct PCIBus *bus;
77 QLIST_ENTRY(PCIHostBus) next;
78 };
79 static QLIST_HEAD(, PCIHostBus) host_buses;
80
81 static const VMStateDescription vmstate_pcibus = {
82 .name = "PCIBUS",
83 .version_id = 1,
84 .minimum_version_id = 1,
85 .minimum_version_id_old = 1,
86 .fields = (VMStateField []) {
87 VMSTATE_INT32_EQUAL(nirq, PCIBus),
88 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
89 VMSTATE_END_OF_LIST()
90 }
91 };
92
93 static int pci_bar(PCIDevice *d, int reg)
94 {
95 uint8_t type;
96
97 if (reg != PCI_ROM_SLOT)
98 return PCI_BASE_ADDRESS_0 + reg * 4;
99
100 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
101 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
102 }
103
104 static inline int pci_irq_state(PCIDevice *d, int irq_num)
105 {
106 return (d->irq_state >> irq_num) & 0x1;
107 }
108
109 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
110 {
111 d->irq_state &= ~(0x1 << irq_num);
112 d->irq_state |= level << irq_num;
113 }
114
115 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
116 {
117 PCIBus *bus;
118 for (;;) {
119 bus = pci_dev->bus;
120 irq_num = bus->map_irq(pci_dev, irq_num);
121 if (bus->set_irq)
122 break;
123 pci_dev = bus->parent_dev;
124 }
125 bus->irq_count[irq_num] += change;
126 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
127 }
128
129 int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
130 {
131 assert(irq_num >= 0);
132 assert(irq_num < bus->nirq);
133 return !!bus->irq_count[irq_num];
134 }
135
136 /* Update interrupt status bit in config space on interrupt
137 * state change. */
138 static void pci_update_irq_status(PCIDevice *dev)
139 {
140 if (dev->irq_state) {
141 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
142 } else {
143 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
144 }
145 }
146
147 void pci_device_deassert_intx(PCIDevice *dev)
148 {
149 int i;
150 for (i = 0; i < PCI_NUM_PINS; ++i) {
151 qemu_set_irq(dev->irq[i], 0);
152 }
153 }
154
155 /*
156 * This function is called on #RST and FLR.
157 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
158 */
159 void pci_device_reset(PCIDevice *dev)
160 {
161 int r;
162 /* TODO: call the below unconditionally once all pci devices
163 * are qdevified */
164 if (dev->qdev.info) {
165 qdev_reset_all(&dev->qdev);
166 }
167
168 dev->irq_state = 0;
169 pci_update_irq_status(dev);
170 pci_device_deassert_intx(dev);
171 /* Clear all writable bits */
172 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
173 pci_get_word(dev->wmask + PCI_COMMAND) |
174 pci_get_word(dev->w1cmask + PCI_COMMAND));
175 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
176 pci_get_word(dev->wmask + PCI_STATUS) |
177 pci_get_word(dev->w1cmask + PCI_STATUS));
178 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
179 dev->config[PCI_INTERRUPT_LINE] = 0x0;
180 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
181 PCIIORegion *region = &dev->io_regions[r];
182 if (!region->size) {
183 continue;
184 }
185
186 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
187 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
188 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
189 } else {
190 pci_set_long(dev->config + pci_bar(dev, r), region->type);
191 }
192 }
193 pci_update_mappings(dev);
194 }
195
196 /*
197 * Trigger pci bus reset under a given bus.
198 * To be called on RST# assert.
199 */
200 void pci_bus_reset(PCIBus *bus)
201 {
202 int i;
203
204 for (i = 0; i < bus->nirq; i++) {
205 bus->irq_count[i] = 0;
206 }
207 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
208 if (bus->devices[i]) {
209 pci_device_reset(bus->devices[i]);
210 }
211 }
212 }
213
214 static int pcibus_reset(BusState *qbus)
215 {
216 pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus));
217
218 /* topology traverse is done by pci_bus_reset().
219 Tell qbus/qdev walker not to traverse the tree */
220 return 1;
221 }
222
223 static void pci_host_bus_register(int domain, PCIBus *bus)
224 {
225 struct PCIHostBus *host;
226 host = g_malloc0(sizeof(*host));
227 host->domain = domain;
228 host->bus = bus;
229 QLIST_INSERT_HEAD(&host_buses, host, next);
230 }
231
232 PCIBus *pci_find_root_bus(int domain)
233 {
234 struct PCIHostBus *host;
235
236 QLIST_FOREACH(host, &host_buses, next) {
237 if (host->domain == domain) {
238 return host->bus;
239 }
240 }
241
242 return NULL;
243 }
244
245 int pci_find_domain(const PCIBus *bus)
246 {
247 PCIDevice *d;
248 struct PCIHostBus *host;
249
250 /* obtain root bus */
251 while ((d = bus->parent_dev) != NULL) {
252 bus = d->bus;
253 }
254
255 QLIST_FOREACH(host, &host_buses, next) {
256 if (host->bus == bus) {
257 return host->domain;
258 }
259 }
260
261 abort(); /* should not be reached */
262 return -1;
263 }
264
265 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
266 const char *name,
267 MemoryRegion *address_space_mem,
268 MemoryRegion *address_space_io,
269 uint8_t devfn_min)
270 {
271 qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
272 assert(PCI_FUNC(devfn_min) == 0);
273 bus->devfn_min = devfn_min;
274 bus->address_space_mem = address_space_mem;
275 bus->address_space_io = address_space_io;
276
277 /* host bridge */
278 QLIST_INIT(&bus->child);
279 pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
280
281 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
282 }
283
284 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
285 MemoryRegion *address_space_mem,
286 MemoryRegion *address_space_io,
287 uint8_t devfn_min)
288 {
289 PCIBus *bus;
290
291 bus = g_malloc0(sizeof(*bus));
292 bus->qbus.qdev_allocated = 1;
293 pci_bus_new_inplace(bus, parent, name, address_space_mem,
294 address_space_io, devfn_min);
295 return bus;
296 }
297
298 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
299 void *irq_opaque, int nirq)
300 {
301 bus->set_irq = set_irq;
302 bus->map_irq = map_irq;
303 bus->irq_opaque = irq_opaque;
304 bus->nirq = nirq;
305 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
306 }
307
308 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
309 {
310 bus->qbus.allow_hotplug = 1;
311 bus->hotplug = hotplug;
312 bus->hotplug_qdev = qdev;
313 }
314
315 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base)
316 {
317 bus->mem_base = base;
318 }
319
320 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
321 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
322 void *irq_opaque,
323 MemoryRegion *address_space_mem,
324 MemoryRegion *address_space_io,
325 uint8_t devfn_min, int nirq)
326 {
327 PCIBus *bus;
328
329 bus = pci_bus_new(parent, name, address_space_mem,
330 address_space_io, devfn_min);
331 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
332 return bus;
333 }
334
335 int pci_bus_num(PCIBus *s)
336 {
337 if (!s->parent_dev)
338 return 0; /* pci host bridge */
339 return s->parent_dev->config[PCI_SECONDARY_BUS];
340 }
341
342 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
343 {
344 PCIDevice *s = container_of(pv, PCIDevice, config);
345 uint8_t *config;
346 int i;
347
348 assert(size == pci_config_size(s));
349 config = g_malloc(size);
350
351 qemu_get_buffer(f, config, size);
352 for (i = 0; i < size; ++i) {
353 if ((config[i] ^ s->config[i]) &
354 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
355 g_free(config);
356 return -EINVAL;
357 }
358 }
359 memcpy(s->config, config, size);
360
361 pci_update_mappings(s);
362
363 g_free(config);
364 return 0;
365 }
366
367 /* just put buffer */
368 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
369 {
370 const uint8_t **v = pv;
371 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
372 qemu_put_buffer(f, *v, size);
373 }
374
375 static VMStateInfo vmstate_info_pci_config = {
376 .name = "pci config",
377 .get = get_pci_config_device,
378 .put = put_pci_config_device,
379 };
380
381 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
382 {
383 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
384 uint32_t irq_state[PCI_NUM_PINS];
385 int i;
386 for (i = 0; i < PCI_NUM_PINS; ++i) {
387 irq_state[i] = qemu_get_be32(f);
388 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
389 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
390 irq_state[i]);
391 return -EINVAL;
392 }
393 }
394
395 for (i = 0; i < PCI_NUM_PINS; ++i) {
396 pci_set_irq_state(s, i, irq_state[i]);
397 }
398
399 return 0;
400 }
401
402 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
403 {
404 int i;
405 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
406
407 for (i = 0; i < PCI_NUM_PINS; ++i) {
408 qemu_put_be32(f, pci_irq_state(s, i));
409 }
410 }
411
412 static VMStateInfo vmstate_info_pci_irq_state = {
413 .name = "pci irq state",
414 .get = get_pci_irq_state,
415 .put = put_pci_irq_state,
416 };
417
418 const VMStateDescription vmstate_pci_device = {
419 .name = "PCIDevice",
420 .version_id = 2,
421 .minimum_version_id = 1,
422 .minimum_version_id_old = 1,
423 .fields = (VMStateField []) {
424 VMSTATE_INT32_LE(version_id, PCIDevice),
425 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
426 vmstate_info_pci_config,
427 PCI_CONFIG_SPACE_SIZE),
428 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
429 vmstate_info_pci_irq_state,
430 PCI_NUM_PINS * sizeof(int32_t)),
431 VMSTATE_END_OF_LIST()
432 }
433 };
434
435 const VMStateDescription vmstate_pcie_device = {
436 .name = "PCIDevice",
437 .version_id = 2,
438 .minimum_version_id = 1,
439 .minimum_version_id_old = 1,
440 .fields = (VMStateField []) {
441 VMSTATE_INT32_LE(version_id, PCIDevice),
442 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
443 vmstate_info_pci_config,
444 PCIE_CONFIG_SPACE_SIZE),
445 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
446 vmstate_info_pci_irq_state,
447 PCI_NUM_PINS * sizeof(int32_t)),
448 VMSTATE_END_OF_LIST()
449 }
450 };
451
452 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
453 {
454 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
455 }
456
457 void pci_device_save(PCIDevice *s, QEMUFile *f)
458 {
459 /* Clear interrupt status bit: it is implicit
460 * in irq_state which we are saving.
461 * This makes us compatible with old devices
462 * which never set or clear this bit. */
463 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
464 vmstate_save_state(f, pci_get_vmstate(s), s);
465 /* Restore the interrupt status bit. */
466 pci_update_irq_status(s);
467 }
468
469 int pci_device_load(PCIDevice *s, QEMUFile *f)
470 {
471 int ret;
472 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
473 /* Restore the interrupt status bit. */
474 pci_update_irq_status(s);
475 return ret;
476 }
477
478 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
479 {
480 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
481 pci_default_sub_vendor_id);
482 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
483 pci_default_sub_device_id);
484 }
485
486 /*
487 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
488 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
489 */
490 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
491 unsigned int *slotp, unsigned int *funcp)
492 {
493 const char *p;
494 char *e;
495 unsigned long val;
496 unsigned long dom = 0, bus = 0;
497 unsigned int slot = 0;
498 unsigned int func = 0;
499
500 p = addr;
501 val = strtoul(p, &e, 16);
502 if (e == p)
503 return -1;
504 if (*e == ':') {
505 bus = val;
506 p = e + 1;
507 val = strtoul(p, &e, 16);
508 if (e == p)
509 return -1;
510 if (*e == ':') {
511 dom = bus;
512 bus = val;
513 p = e + 1;
514 val = strtoul(p, &e, 16);
515 if (e == p)
516 return -1;
517 }
518 }
519
520 slot = val;
521
522 if (funcp != NULL) {
523 if (*e != '.')
524 return -1;
525
526 p = e + 1;
527 val = strtoul(p, &e, 16);
528 if (e == p)
529 return -1;
530
531 func = val;
532 }
533
534 /* if funcp == NULL func is 0 */
535 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
536 return -1;
537
538 if (*e)
539 return -1;
540
541 /* Note: QEMU doesn't implement domains other than 0 */
542 if (!pci_find_bus(pci_find_root_bus(dom), bus))
543 return -1;
544
545 *domp = dom;
546 *busp = bus;
547 *slotp = slot;
548 if (funcp != NULL)
549 *funcp = func;
550 return 0;
551 }
552
553 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
554 unsigned *slotp)
555 {
556 /* strip legacy tag */
557 if (!strncmp(addr, "pci_addr=", 9)) {
558 addr += 9;
559 }
560 if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) {
561 monitor_printf(mon, "Invalid pci address\n");
562 return -1;
563 }
564 return 0;
565 }
566
567 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
568 {
569 int dom, bus;
570 unsigned slot;
571
572 if (!devaddr) {
573 *devfnp = -1;
574 return pci_find_bus(pci_find_root_bus(0), 0);
575 }
576
577 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
578 return NULL;
579 }
580
581 *devfnp = PCI_DEVFN(slot, 0);
582 return pci_find_bus(pci_find_root_bus(dom), bus);
583 }
584
585 static void pci_init_cmask(PCIDevice *dev)
586 {
587 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
588 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
589 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
590 dev->cmask[PCI_REVISION_ID] = 0xff;
591 dev->cmask[PCI_CLASS_PROG] = 0xff;
592 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
593 dev->cmask[PCI_HEADER_TYPE] = 0xff;
594 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
595 }
596
597 static void pci_init_wmask(PCIDevice *dev)
598 {
599 int config_size = pci_config_size(dev);
600
601 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
602 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
603 pci_set_word(dev->wmask + PCI_COMMAND,
604 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
605 PCI_COMMAND_INTX_DISABLE);
606 if (dev->cap_present & QEMU_PCI_CAP_SERR) {
607 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
608 }
609
610 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
611 config_size - PCI_CONFIG_HEADER_SIZE);
612 }
613
614 static void pci_init_w1cmask(PCIDevice *dev)
615 {
616 /*
617 * Note: It's okay to set w1cmask even for readonly bits as
618 * long as their value is hardwired to 0.
619 */
620 pci_set_word(dev->w1cmask + PCI_STATUS,
621 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
622 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
623 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
624 }
625
626 static void pci_init_wmask_bridge(PCIDevice *d)
627 {
628 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
629 PCI_SEC_LETENCY_TIMER */
630 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
631
632 /* base and limit */
633 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
634 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
635 pci_set_word(d->wmask + PCI_MEMORY_BASE,
636 PCI_MEMORY_RANGE_MASK & 0xffff);
637 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
638 PCI_MEMORY_RANGE_MASK & 0xffff);
639 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
640 PCI_PREF_RANGE_MASK & 0xffff);
641 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
642 PCI_PREF_RANGE_MASK & 0xffff);
643
644 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
645 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
646
647 /* TODO: add this define to pci_regs.h in linux and then in qemu. */
648 #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */
649 #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */
650 #define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */
651 #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */
652 #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */
653 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
654 PCI_BRIDGE_CTL_PARITY |
655 PCI_BRIDGE_CTL_SERR |
656 PCI_BRIDGE_CTL_ISA |
657 PCI_BRIDGE_CTL_VGA |
658 PCI_BRIDGE_CTL_VGA_16BIT |
659 PCI_BRIDGE_CTL_MASTER_ABORT |
660 PCI_BRIDGE_CTL_BUS_RESET |
661 PCI_BRIDGE_CTL_FAST_BACK |
662 PCI_BRIDGE_CTL_DISCARD |
663 PCI_BRIDGE_CTL_SEC_DISCARD |
664 PCI_BRIDGE_CTL_DISCARD_SERR);
665 /* Below does not do anything as we never set this bit, put here for
666 * completeness. */
667 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
668 PCI_BRIDGE_CTL_DISCARD_STATUS);
669 }
670
671 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
672 {
673 uint8_t slot = PCI_SLOT(dev->devfn);
674 uint8_t func;
675
676 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
677 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
678 }
679
680 /*
681 * multifunction bit is interpreted in two ways as follows.
682 * - all functions must set the bit to 1.
683 * Example: Intel X53
684 * - function 0 must set the bit, but the rest function (> 0)
685 * is allowed to leave the bit to 0.
686 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
687 *
688 * So OS (at least Linux) checks the bit of only function 0,
689 * and doesn't see the bit of function > 0.
690 *
691 * The below check allows both interpretation.
692 */
693 if (PCI_FUNC(dev->devfn)) {
694 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
695 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
696 /* function 0 should set multifunction bit */
697 error_report("PCI: single function device can't be populated "
698 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
699 return -1;
700 }
701 return 0;
702 }
703
704 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
705 return 0;
706 }
707 /* function 0 indicates single function, so function > 0 must be NULL */
708 for (func = 1; func < PCI_FUNC_MAX; ++func) {
709 if (bus->devices[PCI_DEVFN(slot, func)]) {
710 error_report("PCI: %x.0 indicates single function, "
711 "but %x.%x is already populated.",
712 slot, slot, func);
713 return -1;
714 }
715 }
716 return 0;
717 }
718
719 static void pci_config_alloc(PCIDevice *pci_dev)
720 {
721 int config_size = pci_config_size(pci_dev);
722
723 pci_dev->config = g_malloc0(config_size);
724 pci_dev->cmask = g_malloc0(config_size);
725 pci_dev->wmask = g_malloc0(config_size);
726 pci_dev->w1cmask = g_malloc0(config_size);
727 pci_dev->used = g_malloc0(config_size);
728 }
729
730 static void pci_config_free(PCIDevice *pci_dev)
731 {
732 g_free(pci_dev->config);
733 g_free(pci_dev->cmask);
734 g_free(pci_dev->wmask);
735 g_free(pci_dev->w1cmask);
736 g_free(pci_dev->used);
737 }
738
739 /* -1 for devfn means auto assign */
740 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
741 const char *name, int devfn,
742 const PCIDeviceInfo *info)
743 {
744 PCIConfigReadFunc *config_read = info->config_read;
745 PCIConfigWriteFunc *config_write = info->config_write;
746
747 if (devfn < 0) {
748 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
749 devfn += PCI_FUNC_MAX) {
750 if (!bus->devices[devfn])
751 goto found;
752 }
753 error_report("PCI: no slot/function available for %s, all in use", name);
754 return NULL;
755 found: ;
756 } else if (bus->devices[devfn]) {
757 error_report("PCI: slot %d function %d not available for %s, in use by %s",
758 PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
759 return NULL;
760 }
761 pci_dev->bus = bus;
762 pci_dev->devfn = devfn;
763 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
764 pci_dev->irq_state = 0;
765 pci_config_alloc(pci_dev);
766
767 pci_config_set_vendor_id(pci_dev->config, info->vendor_id);
768 pci_config_set_device_id(pci_dev->config, info->device_id);
769 pci_config_set_revision(pci_dev->config, info->revision);
770 pci_config_set_class(pci_dev->config, info->class_id);
771
772 if (!info->is_bridge) {
773 if (info->subsystem_vendor_id || info->subsystem_id) {
774 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
775 info->subsystem_vendor_id);
776 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
777 info->subsystem_id);
778 } else {
779 pci_set_default_subsystem_id(pci_dev);
780 }
781 } else {
782 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
783 assert(!info->subsystem_vendor_id);
784 assert(!info->subsystem_id);
785 }
786 pci_init_cmask(pci_dev);
787 pci_init_wmask(pci_dev);
788 pci_init_w1cmask(pci_dev);
789 if (info->is_bridge) {
790 pci_init_wmask_bridge(pci_dev);
791 }
792 if (pci_init_multifunction(bus, pci_dev)) {
793 pci_config_free(pci_dev);
794 return NULL;
795 }
796
797 if (!config_read)
798 config_read = pci_default_read_config;
799 if (!config_write)
800 config_write = pci_default_write_config;
801 pci_dev->config_read = config_read;
802 pci_dev->config_write = config_write;
803 bus->devices[devfn] = pci_dev;
804 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
805 pci_dev->version_id = 2; /* Current pci device vmstate version */
806 return pci_dev;
807 }
808
809 static void do_pci_unregister_device(PCIDevice *pci_dev)
810 {
811 qemu_free_irqs(pci_dev->irq);
812 pci_dev->bus->devices[pci_dev->devfn] = NULL;
813 pci_config_free(pci_dev);
814 }
815
816 /* TODO: obsolete. eliminate this once all pci devices are qdevifed. */
817 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
818 int instance_size, int devfn,
819 PCIConfigReadFunc *config_read,
820 PCIConfigWriteFunc *config_write)
821 {
822 PCIDevice *pci_dev;
823 PCIDeviceInfo info = {
824 .config_read = config_read,
825 .config_write = config_write,
826 };
827
828 pci_dev = g_malloc0(instance_size);
829 pci_dev = do_pci_register_device(pci_dev, bus, name, devfn, &info);
830 if (pci_dev == NULL) {
831 hw_error("PCI: can't register device\n");
832 }
833 return pci_dev;
834 }
835
836 static target_phys_addr_t pci_to_cpu_addr(PCIBus *bus,
837 target_phys_addr_t addr)
838 {
839 return addr + bus->mem_base;
840 }
841
842 static void pci_unregister_io_regions(PCIDevice *pci_dev)
843 {
844 PCIIORegion *r;
845 int i;
846
847 for(i = 0; i < PCI_NUM_REGIONS; i++) {
848 r = &pci_dev->io_regions[i];
849 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
850 continue;
851 memory_region_del_subregion(r->address_space, r->memory);
852 }
853 }
854
855 static int pci_unregister_device(DeviceState *dev)
856 {
857 PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
858 PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
859 int ret = 0;
860
861 if (info->exit)
862 ret = info->exit(pci_dev);
863 if (ret)
864 return ret;
865
866 pci_unregister_io_regions(pci_dev);
867 pci_del_option_rom(pci_dev);
868 g_free(pci_dev->romfile);
869 do_pci_unregister_device(pci_dev);
870 return 0;
871 }
872
873 void pci_register_bar(PCIDevice *pci_dev, int region_num,
874 uint8_t type, MemoryRegion *memory)
875 {
876 PCIIORegion *r;
877 uint32_t addr;
878 uint64_t wmask;
879 pcibus_t size = memory_region_size(memory);
880
881 assert(region_num >= 0);
882 assert(region_num < PCI_NUM_REGIONS);
883 if (size & (size-1)) {
884 fprintf(stderr, "ERROR: PCI region size must be pow2 "
885 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
886 exit(1);
887 }
888
889 r = &pci_dev->io_regions[region_num];
890 r->addr = PCI_BAR_UNMAPPED;
891 r->size = size;
892 r->filtered_size = size;
893 r->type = type;
894 r->memory = NULL;
895
896 wmask = ~(size - 1);
897 addr = pci_bar(pci_dev, region_num);
898 if (region_num == PCI_ROM_SLOT) {
899 /* ROM enable bit is writable */
900 wmask |= PCI_ROM_ADDRESS_ENABLE;
901 }
902 pci_set_long(pci_dev->config + addr, type);
903 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
904 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
905 pci_set_quad(pci_dev->wmask + addr, wmask);
906 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
907 } else {
908 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
909 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
910 }
911 pci_dev->io_regions[region_num].memory = memory;
912 pci_dev->io_regions[region_num].address_space
913 = type & PCI_BASE_ADDRESS_SPACE_IO
914 ? pci_dev->bus->address_space_io
915 : pci_dev->bus->address_space_mem;
916 }
917
918 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
919 {
920 return pci_dev->io_regions[region_num].addr;
921 }
922
923 static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
924 uint8_t type)
925 {
926 pcibus_t base = *addr;
927 pcibus_t limit = *addr + *size - 1;
928 PCIDevice *br;
929
930 for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
931 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
932
933 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
934 if (!(cmd & PCI_COMMAND_IO)) {
935 goto no_map;
936 }
937 } else {
938 if (!(cmd & PCI_COMMAND_MEMORY)) {
939 goto no_map;
940 }
941 }
942
943 base = MAX(base, pci_bridge_get_base(br, type));
944 limit = MIN(limit, pci_bridge_get_limit(br, type));
945 }
946
947 if (base > limit) {
948 goto no_map;
949 }
950 *addr = base;
951 *size = limit - base + 1;
952 return;
953 no_map:
954 *addr = PCI_BAR_UNMAPPED;
955 *size = 0;
956 }
957
958 static pcibus_t pci_bar_address(PCIDevice *d,
959 int reg, uint8_t type, pcibus_t size)
960 {
961 pcibus_t new_addr, last_addr;
962 int bar = pci_bar(d, reg);
963 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
964
965 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
966 if (!(cmd & PCI_COMMAND_IO)) {
967 return PCI_BAR_UNMAPPED;
968 }
969 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
970 last_addr = new_addr + size - 1;
971 /* NOTE: we have only 64K ioports on PC */
972 if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
973 return PCI_BAR_UNMAPPED;
974 }
975 return new_addr;
976 }
977
978 if (!(cmd & PCI_COMMAND_MEMORY)) {
979 return PCI_BAR_UNMAPPED;
980 }
981 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
982 new_addr = pci_get_quad(d->config + bar);
983 } else {
984 new_addr = pci_get_long(d->config + bar);
985 }
986 /* the ROM slot has a specific enable bit */
987 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
988 return PCI_BAR_UNMAPPED;
989 }
990 new_addr &= ~(size - 1);
991 last_addr = new_addr + size - 1;
992 /* NOTE: we do not support wrapping */
993 /* XXX: as we cannot support really dynamic
994 mappings, we handle specific values as invalid
995 mappings. */
996 if (last_addr <= new_addr || new_addr == 0 ||
997 last_addr == PCI_BAR_UNMAPPED) {
998 return PCI_BAR_UNMAPPED;
999 }
1000
1001 /* Now pcibus_t is 64bit.
1002 * Check if 32 bit BAR wraps around explicitly.
1003 * Without this, PC ide doesn't work well.
1004 * TODO: remove this work around.
1005 */
1006 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
1007 return PCI_BAR_UNMAPPED;
1008 }
1009
1010 /*
1011 * OS is allowed to set BAR beyond its addressable
1012 * bits. For example, 32 bit OS can set 64bit bar
1013 * to >4G. Check it. TODO: we might need to support
1014 * it in the future for e.g. PAE.
1015 */
1016 if (last_addr >= TARGET_PHYS_ADDR_MAX) {
1017 return PCI_BAR_UNMAPPED;
1018 }
1019
1020 return new_addr;
1021 }
1022
1023 static void pci_update_mappings(PCIDevice *d)
1024 {
1025 PCIIORegion *r;
1026 int i;
1027 pcibus_t new_addr, filtered_size;
1028
1029 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1030 r = &d->io_regions[i];
1031
1032 /* this region isn't registered */
1033 if (!r->size)
1034 continue;
1035
1036 new_addr = pci_bar_address(d, i, r->type, r->size);
1037
1038 /* bridge filtering */
1039 filtered_size = r->size;
1040 if (new_addr != PCI_BAR_UNMAPPED) {
1041 pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
1042 }
1043
1044 /* This bar isn't changed */
1045 if (new_addr == r->addr && filtered_size == r->filtered_size)
1046 continue;
1047
1048 /* now do the real mapping */
1049 if (r->addr != PCI_BAR_UNMAPPED) {
1050 memory_region_del_subregion(r->address_space, r->memory);
1051 }
1052 r->addr = new_addr;
1053 r->filtered_size = filtered_size;
1054 if (r->addr != PCI_BAR_UNMAPPED) {
1055 /*
1056 * TODO: currently almost all the map funcions assumes
1057 * filtered_size == size and addr & ~(size - 1) == addr.
1058 * However with bridge filtering, they aren't always true.
1059 * Teach them such cases, such that filtered_size < size and
1060 * addr & (size - 1) != 0.
1061 */
1062 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1063 memory_region_add_subregion_overlap(r->address_space,
1064 r->addr,
1065 r->memory,
1066 1);
1067 } else {
1068 memory_region_add_subregion_overlap(r->address_space,
1069 pci_to_cpu_addr(d->bus,
1070 r->addr),
1071 r->memory,
1072 1);
1073 }
1074 }
1075 }
1076 }
1077
1078 static inline int pci_irq_disabled(PCIDevice *d)
1079 {
1080 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1081 }
1082
1083 /* Called after interrupt disabled field update in config space,
1084 * assert/deassert interrupts if necessary.
1085 * Gets original interrupt disable bit value (before update). */
1086 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1087 {
1088 int i, disabled = pci_irq_disabled(d);
1089 if (disabled == was_irq_disabled)
1090 return;
1091 for (i = 0; i < PCI_NUM_PINS; ++i) {
1092 int state = pci_irq_state(d, i);
1093 pci_change_irq_level(d, i, disabled ? -state : state);
1094 }
1095 }
1096
1097 uint32_t pci_default_read_config(PCIDevice *d,
1098 uint32_t address, int len)
1099 {
1100 uint32_t val = 0;
1101
1102 memcpy(&val, d->config + address, len);
1103 return le32_to_cpu(val);
1104 }
1105
1106 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
1107 {
1108 int i, was_irq_disabled = pci_irq_disabled(d);
1109
1110 for (i = 0; i < l; val >>= 8, ++i) {
1111 uint8_t wmask = d->wmask[addr + i];
1112 uint8_t w1cmask = d->w1cmask[addr + i];
1113 assert(!(wmask & w1cmask));
1114 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1115 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1116 }
1117 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1118 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1119 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1120 range_covers_byte(addr, l, PCI_COMMAND))
1121 pci_update_mappings(d);
1122
1123 if (range_covers_byte(addr, l, PCI_COMMAND))
1124 pci_update_irq_disabled(d, was_irq_disabled);
1125 }
1126
1127 /***********************************************************/
1128 /* generic PCI irq support */
1129
1130 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1131 static void pci_set_irq(void *opaque, int irq_num, int level)
1132 {
1133 PCIDevice *pci_dev = opaque;
1134 int change;
1135
1136 change = level - pci_irq_state(pci_dev, irq_num);
1137 if (!change)
1138 return;
1139
1140 pci_set_irq_state(pci_dev, irq_num, level);
1141 pci_update_irq_status(pci_dev);
1142 if (pci_irq_disabled(pci_dev))
1143 return;
1144 pci_change_irq_level(pci_dev, irq_num, change);
1145 }
1146
1147 /***********************************************************/
1148 /* monitor info on PCI */
1149
1150 typedef struct {
1151 uint16_t class;
1152 const char *desc;
1153 const char *fw_name;
1154 uint16_t fw_ign_bits;
1155 } pci_class_desc;
1156
1157 static const pci_class_desc pci_class_descriptions[] =
1158 {
1159 { 0x0001, "VGA controller", "display"},
1160 { 0x0100, "SCSI controller", "scsi"},
1161 { 0x0101, "IDE controller", "ide"},
1162 { 0x0102, "Floppy controller", "fdc"},
1163 { 0x0103, "IPI controller", "ipi"},
1164 { 0x0104, "RAID controller", "raid"},
1165 { 0x0106, "SATA controller"},
1166 { 0x0107, "SAS controller"},
1167 { 0x0180, "Storage controller"},
1168 { 0x0200, "Ethernet controller", "ethernet"},
1169 { 0x0201, "Token Ring controller", "token-ring"},
1170 { 0x0202, "FDDI controller", "fddi"},
1171 { 0x0203, "ATM controller", "atm"},
1172 { 0x0280, "Network controller"},
1173 { 0x0300, "VGA controller", "display", 0x00ff},
1174 { 0x0301, "XGA controller"},
1175 { 0x0302, "3D controller"},
1176 { 0x0380, "Display controller"},
1177 { 0x0400, "Video controller", "video"},
1178 { 0x0401, "Audio controller", "sound"},
1179 { 0x0402, "Phone"},
1180 { 0x0403, "Audio controller", "sound"},
1181 { 0x0480, "Multimedia controller"},
1182 { 0x0500, "RAM controller", "memory"},
1183 { 0x0501, "Flash controller", "flash"},
1184 { 0x0580, "Memory controller"},
1185 { 0x0600, "Host bridge", "host"},
1186 { 0x0601, "ISA bridge", "isa"},
1187 { 0x0602, "EISA bridge", "eisa"},
1188 { 0x0603, "MC bridge", "mca"},
1189 { 0x0604, "PCI bridge", "pci"},
1190 { 0x0605, "PCMCIA bridge", "pcmcia"},
1191 { 0x0606, "NUBUS bridge", "nubus"},
1192 { 0x0607, "CARDBUS bridge", "cardbus"},
1193 { 0x0608, "RACEWAY bridge"},
1194 { 0x0680, "Bridge"},
1195 { 0x0700, "Serial port", "serial"},
1196 { 0x0701, "Parallel port", "parallel"},
1197 { 0x0800, "Interrupt controller", "interrupt-controller"},
1198 { 0x0801, "DMA controller", "dma-controller"},
1199 { 0x0802, "Timer", "timer"},
1200 { 0x0803, "RTC", "rtc"},
1201 { 0x0900, "Keyboard", "keyboard"},
1202 { 0x0901, "Pen", "pen"},
1203 { 0x0902, "Mouse", "mouse"},
1204 { 0x0A00, "Dock station", "dock", 0x00ff},
1205 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1206 { 0x0c00, "Fireware contorller", "fireware"},
1207 { 0x0c01, "Access bus controller", "access-bus"},
1208 { 0x0c02, "SSA controller", "ssa"},
1209 { 0x0c03, "USB controller", "usb"},
1210 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1211 { 0, NULL}
1212 };
1213
1214 static void pci_for_each_device_under_bus(PCIBus *bus,
1215 void (*fn)(PCIBus *b, PCIDevice *d))
1216 {
1217 PCIDevice *d;
1218 int devfn;
1219
1220 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1221 d = bus->devices[devfn];
1222 if (d) {
1223 fn(bus, d);
1224 }
1225 }
1226 }
1227
1228 void pci_for_each_device(PCIBus *bus, int bus_num,
1229 void (*fn)(PCIBus *b, PCIDevice *d))
1230 {
1231 bus = pci_find_bus(bus, bus_num);
1232
1233 if (bus) {
1234 pci_for_each_device_under_bus(bus, fn);
1235 }
1236 }
1237
1238 static void pci_device_print(Monitor *mon, QDict *device)
1239 {
1240 QDict *qdict;
1241 QListEntry *entry;
1242 uint64_t addr, size;
1243
1244 monitor_printf(mon, " Bus %2" PRId64 ", ", qdict_get_int(device, "bus"));
1245 monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n",
1246 qdict_get_int(device, "slot"),
1247 qdict_get_int(device, "function"));
1248 monitor_printf(mon, " ");
1249
1250 qdict = qdict_get_qdict(device, "class_info");
1251 if (qdict_haskey(qdict, "desc")) {
1252 monitor_printf(mon, "%s", qdict_get_str(qdict, "desc"));
1253 } else {
1254 monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class"));
1255 }
1256
1257 qdict = qdict_get_qdict(device, "id");
1258 monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
1259 qdict_get_int(qdict, "device"),
1260 qdict_get_int(qdict, "vendor"));
1261
1262 if (qdict_haskey(device, "irq")) {
1263 monitor_printf(mon, " IRQ %" PRId64 ".\n",
1264 qdict_get_int(device, "irq"));
1265 }
1266
1267 if (qdict_haskey(device, "pci_bridge")) {
1268 QDict *info;
1269
1270 qdict = qdict_get_qdict(device, "pci_bridge");
1271
1272 info = qdict_get_qdict(qdict, "bus");
1273 monitor_printf(mon, " BUS %" PRId64 ".\n",
1274 qdict_get_int(info, "number"));
1275 monitor_printf(mon, " secondary bus %" PRId64 ".\n",
1276 qdict_get_int(info, "secondary"));
1277 monitor_printf(mon, " subordinate bus %" PRId64 ".\n",
1278 qdict_get_int(info, "subordinate"));
1279
1280 info = qdict_get_qdict(qdict, "io_range");
1281 monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
1282 qdict_get_int(info, "base"),
1283 qdict_get_int(info, "limit"));
1284
1285 info = qdict_get_qdict(qdict, "memory_range");
1286 monitor_printf(mon,
1287 " memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
1288 qdict_get_int(info, "base"),
1289 qdict_get_int(info, "limit"));
1290
1291 info = qdict_get_qdict(qdict, "prefetchable_range");
1292 monitor_printf(mon, " prefetchable memory range "
1293 "[0x%08"PRIx64", 0x%08"PRIx64"]\n",
1294 qdict_get_int(info, "base"),
1295 qdict_get_int(info, "limit"));
1296 }
1297
1298 QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) {
1299 qdict = qobject_to_qdict(qlist_entry_obj(entry));
1300 monitor_printf(mon, " BAR%d: ", (int) qdict_get_int(qdict, "bar"));
1301
1302 addr = qdict_get_int(qdict, "address");
1303 size = qdict_get_int(qdict, "size");
1304
1305 if (!strcmp(qdict_get_str(qdict, "type"), "io")) {
1306 monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1307 " [0x%04"FMT_PCIBUS"].\n",
1308 addr, addr + size - 1);
1309 } else {
1310 monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS
1311 " [0x%08"FMT_PCIBUS"].\n",
1312 qdict_get_bool(qdict, "mem_type_64") ? 64 : 32,
1313 qdict_get_bool(qdict, "prefetch") ?
1314 " prefetchable" : "", addr, addr + size - 1);
1315 }
1316 }
1317
1318 monitor_printf(mon, " id \"%s\"\n", qdict_get_str(device, "qdev_id"));
1319
1320 if (qdict_haskey(device, "pci_bridge")) {
1321 qdict = qdict_get_qdict(device, "pci_bridge");
1322 if (qdict_haskey(qdict, "devices")) {
1323 QListEntry *dev;
1324 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1325 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1326 }
1327 }
1328 }
1329 }
1330
1331 void do_pci_info_print(Monitor *mon, const QObject *data)
1332 {
1333 QListEntry *bus, *dev;
1334
1335 QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) {
1336 QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus));
1337 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1338 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1339 }
1340 }
1341 }
1342
1343 static QObject *pci_get_dev_class(const PCIDevice *dev)
1344 {
1345 int class;
1346 const pci_class_desc *desc;
1347
1348 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1349 desc = pci_class_descriptions;
1350 while (desc->desc && class != desc->class)
1351 desc++;
1352
1353 if (desc->desc) {
1354 return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1355 desc->desc, class);
1356 } else {
1357 return qobject_from_jsonf("{ 'class': %d }", class);
1358 }
1359 }
1360
1361 static QObject *pci_get_dev_id(const PCIDevice *dev)
1362 {
1363 return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1364 pci_get_word(dev->config + PCI_VENDOR_ID),
1365 pci_get_word(dev->config + PCI_DEVICE_ID));
1366 }
1367
1368 static QObject *pci_get_regions_list(const PCIDevice *dev)
1369 {
1370 int i;
1371 QList *regions_list;
1372
1373 regions_list = qlist_new();
1374
1375 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1376 QObject *obj;
1377 const PCIIORegion *r = &dev->io_regions[i];
1378
1379 if (!r->size) {
1380 continue;
1381 }
1382
1383 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1384 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1385 "'address': %" PRId64 ", "
1386 "'size': %" PRId64 " }",
1387 i, r->addr, r->size);
1388 } else {
1389 int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64;
1390
1391 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1392 "'mem_type_64': %i, 'prefetch': %i, "
1393 "'address': %" PRId64 ", "
1394 "'size': %" PRId64 " }",
1395 i, mem_type_64,
1396 r->type & PCI_BASE_ADDRESS_MEM_PREFETCH,
1397 r->addr, r->size);
1398 }
1399
1400 qlist_append_obj(regions_list, obj);
1401 }
1402
1403 return QOBJECT(regions_list);
1404 }
1405
1406 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num);
1407
1408 static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num)
1409 {
1410 uint8_t type;
1411 QObject *obj;
1412
1413 obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p,"
1414 " 'qdev_id': %s }",
1415 bus_num,
1416 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
1417 pci_get_dev_class(dev), pci_get_dev_id(dev),
1418 pci_get_regions_list(dev),
1419 dev->qdev.id ? dev->qdev.id : "");
1420
1421 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1422 QDict *qdict = qobject_to_qdict(obj);
1423 qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE]));
1424 }
1425
1426 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1427 if (type == PCI_HEADER_TYPE_BRIDGE) {
1428 QDict *qdict;
1429 QObject *pci_bridge;
1430
1431 pci_bridge = qobject_from_jsonf("{ 'bus': "
1432 "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1433 "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1434 "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1435 "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }",
1436 dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS],
1437 dev->config[PCI_SUBORDINATE_BUS],
1438 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO),
1439 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO),
1440 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1441 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1442 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1443 PCI_BASE_ADDRESS_MEM_PREFETCH),
1444 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1445 PCI_BASE_ADDRESS_MEM_PREFETCH));
1446
1447 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1448 PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
1449
1450 if (child_bus) {
1451 qdict = qobject_to_qdict(pci_bridge);
1452 qdict_put_obj(qdict, "devices",
1453 pci_get_devices_list(child_bus,
1454 dev->config[PCI_SECONDARY_BUS]));
1455 }
1456 }
1457 qdict = qobject_to_qdict(obj);
1458 qdict_put_obj(qdict, "pci_bridge", pci_bridge);
1459 }
1460
1461 return obj;
1462 }
1463
1464 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num)
1465 {
1466 int devfn;
1467 PCIDevice *dev;
1468 QList *dev_list;
1469
1470 dev_list = qlist_new();
1471
1472 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1473 dev = bus->devices[devfn];
1474 if (dev) {
1475 qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num));
1476 }
1477 }
1478
1479 return QOBJECT(dev_list);
1480 }
1481
1482 static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num)
1483 {
1484 bus = pci_find_bus(bus, bus_num);
1485 if (bus) {
1486 return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1487 bus_num, pci_get_devices_list(bus, bus_num));
1488 }
1489
1490 return NULL;
1491 }
1492
1493 void do_pci_info(Monitor *mon, QObject **ret_data)
1494 {
1495 QList *bus_list;
1496 struct PCIHostBus *host;
1497
1498 bus_list = qlist_new();
1499
1500 QLIST_FOREACH(host, &host_buses, next) {
1501 QObject *obj = pci_get_bus_dict(host->bus, 0);
1502 if (obj) {
1503 qlist_append_obj(bus_list, obj);
1504 }
1505 }
1506
1507 *ret_data = QOBJECT(bus_list);
1508 }
1509
1510 static const char * const pci_nic_models[] = {
1511 "ne2k_pci",
1512 "i82551",
1513 "i82557b",
1514 "i82559er",
1515 "rtl8139",
1516 "e1000",
1517 "pcnet",
1518 "virtio",
1519 NULL
1520 };
1521
1522 static const char * const pci_nic_names[] = {
1523 "ne2k_pci",
1524 "i82551",
1525 "i82557b",
1526 "i82559er",
1527 "rtl8139",
1528 "e1000",
1529 "pcnet",
1530 "virtio-net-pci",
1531 NULL
1532 };
1533
1534 /* Initialize a PCI NIC. */
1535 /* FIXME callers should check for failure, but don't */
1536 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1537 const char *default_devaddr)
1538 {
1539 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1540 PCIBus *bus;
1541 int devfn;
1542 PCIDevice *pci_dev;
1543 DeviceState *dev;
1544 int i;
1545
1546 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1547 if (i < 0)
1548 return NULL;
1549
1550 bus = pci_get_bus_devfn(&devfn, devaddr);
1551 if (!bus) {
1552 error_report("Invalid PCI device address %s for device %s",
1553 devaddr, pci_nic_names[i]);
1554 return NULL;
1555 }
1556
1557 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1558 dev = &pci_dev->qdev;
1559 qdev_set_nic_properties(dev, nd);
1560 if (qdev_init(dev) < 0)
1561 return NULL;
1562 return pci_dev;
1563 }
1564
1565 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1566 const char *default_devaddr)
1567 {
1568 PCIDevice *res;
1569
1570 if (qemu_show_nic_models(nd->model, pci_nic_models))
1571 exit(0);
1572
1573 res = pci_nic_init(nd, default_model, default_devaddr);
1574 if (!res)
1575 exit(1);
1576 return res;
1577 }
1578
1579 static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
1580 {
1581 pci_update_mappings(d);
1582 }
1583
1584 void pci_bridge_update_mappings(PCIBus *b)
1585 {
1586 PCIBus *child;
1587
1588 pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
1589
1590 QLIST_FOREACH(child, &b->child, sibling) {
1591 pci_bridge_update_mappings(child);
1592 }
1593 }
1594
1595 /* Whether a given bus number is in range of the secondary
1596 * bus of the given bridge device. */
1597 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1598 {
1599 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1600 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
1601 dev->config[PCI_SECONDARY_BUS] < bus_num &&
1602 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1603 }
1604
1605 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1606 {
1607 PCIBus *sec;
1608
1609 if (!bus) {
1610 return NULL;
1611 }
1612
1613 if (pci_bus_num(bus) == bus_num) {
1614 return bus;
1615 }
1616
1617 /* Consider all bus numbers in range for the host pci bridge. */
1618 if (bus->parent_dev &&
1619 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1620 return NULL;
1621 }
1622
1623 /* try child bus */
1624 for (; bus; bus = sec) {
1625 QLIST_FOREACH(sec, &bus->child, sibling) {
1626 assert(sec->parent_dev);
1627 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1628 return sec;
1629 }
1630 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1631 break;
1632 }
1633 }
1634 }
1635
1636 return NULL;
1637 }
1638
1639 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
1640 {
1641 bus = pci_find_bus(bus, bus_num);
1642
1643 if (!bus)
1644 return NULL;
1645
1646 return bus->devices[devfn];
1647 }
1648
1649 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1650 {
1651 PCIDevice *pci_dev = (PCIDevice *)qdev;
1652 PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1653 PCIBus *bus;
1654 int rc;
1655 bool is_default_rom;
1656
1657 /* initialize cap_present for pci_is_express() and pci_config_size() */
1658 if (info->is_express) {
1659 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1660 }
1661
1662 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1663 pci_dev = do_pci_register_device(pci_dev, bus, base->name,
1664 pci_dev->devfn, info);
1665 if (pci_dev == NULL)
1666 return -1;
1667 if (qdev->hotplugged && info->no_hotplug) {
1668 qerror_report(QERR_DEVICE_NO_HOTPLUG, info->qdev.name);
1669 do_pci_unregister_device(pci_dev);
1670 return -1;
1671 }
1672 if (info->init) {
1673 rc = info->init(pci_dev);
1674 if (rc != 0) {
1675 do_pci_unregister_device(pci_dev);
1676 return rc;
1677 }
1678 }
1679
1680 /* rom loading */
1681 is_default_rom = false;
1682 if (pci_dev->romfile == NULL && info->romfile != NULL) {
1683 pci_dev->romfile = g_strdup(info->romfile);
1684 is_default_rom = true;
1685 }
1686 pci_add_option_rom(pci_dev, is_default_rom);
1687
1688 if (bus->hotplug) {
1689 /* Let buses differentiate between hotplug and when device is
1690 * enabled during qemu machine creation. */
1691 rc = bus->hotplug(bus->hotplug_qdev, pci_dev,
1692 qdev->hotplugged ? PCI_HOTPLUG_ENABLED:
1693 PCI_COLDPLUG_ENABLED);
1694 if (rc != 0) {
1695 int r = pci_unregister_device(&pci_dev->qdev);
1696 assert(!r);
1697 return rc;
1698 }
1699 }
1700 return 0;
1701 }
1702
1703 static int pci_unplug_device(DeviceState *qdev)
1704 {
1705 PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1706 PCIDeviceInfo *info = container_of(qdev->info, PCIDeviceInfo, qdev);
1707
1708 if (info->no_hotplug) {
1709 qerror_report(QERR_DEVICE_NO_HOTPLUG, info->qdev.name);
1710 return -1;
1711 }
1712 return dev->bus->hotplug(dev->bus->hotplug_qdev, dev,
1713 PCI_HOTPLUG_DISABLED);
1714 }
1715
1716 void pci_qdev_register(PCIDeviceInfo *info)
1717 {
1718 info->qdev.init = pci_qdev_init;
1719 info->qdev.unplug = pci_unplug_device;
1720 info->qdev.exit = pci_unregister_device;
1721 info->qdev.bus_info = &pci_bus_info;
1722 qdev_register(&info->qdev);
1723 }
1724
1725 void pci_qdev_register_many(PCIDeviceInfo *info)
1726 {
1727 while (info->qdev.name) {
1728 pci_qdev_register(info);
1729 info++;
1730 }
1731 }
1732
1733 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1734 const char *name)
1735 {
1736 DeviceState *dev;
1737
1738 dev = qdev_create(&bus->qbus, name);
1739 qdev_prop_set_uint32(dev, "addr", devfn);
1740 qdev_prop_set_bit(dev, "multifunction", multifunction);
1741 return DO_UPCAST(PCIDevice, qdev, dev);
1742 }
1743
1744 PCIDevice *pci_try_create_multifunction(PCIBus *bus, int devfn,
1745 bool multifunction,
1746 const char *name)
1747 {
1748 DeviceState *dev;
1749
1750 dev = qdev_try_create(&bus->qbus, name);
1751 if (!dev) {
1752 return NULL;
1753 }
1754 qdev_prop_set_uint32(dev, "addr", devfn);
1755 qdev_prop_set_bit(dev, "multifunction", multifunction);
1756 return DO_UPCAST(PCIDevice, qdev, dev);
1757 }
1758
1759 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1760 bool multifunction,
1761 const char *name)
1762 {
1763 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1764 qdev_init_nofail(&dev->qdev);
1765 return dev;
1766 }
1767
1768 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1769 {
1770 return pci_create_multifunction(bus, devfn, false, name);
1771 }
1772
1773 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1774 {
1775 return pci_create_simple_multifunction(bus, devfn, false, name);
1776 }
1777
1778 PCIDevice *pci_try_create(PCIBus *bus, int devfn, const char *name)
1779 {
1780 return pci_try_create_multifunction(bus, devfn, false, name);
1781 }
1782
1783 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1784 {
1785 int config_size = pci_config_size(pdev);
1786 int offset = PCI_CONFIG_HEADER_SIZE;
1787 int i;
1788 for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1789 if (pdev->used[i])
1790 offset = i + 1;
1791 else if (i - offset + 1 == size)
1792 return offset;
1793 return 0;
1794 }
1795
1796 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1797 uint8_t *prev_p)
1798 {
1799 uint8_t next, prev;
1800
1801 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1802 return 0;
1803
1804 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1805 prev = next + PCI_CAP_LIST_NEXT)
1806 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1807 break;
1808
1809 if (prev_p)
1810 *prev_p = prev;
1811 return next;
1812 }
1813
1814 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1815 This is needed for an option rom which is used for more than one device. */
1816 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
1817 {
1818 uint16_t vendor_id;
1819 uint16_t device_id;
1820 uint16_t rom_vendor_id;
1821 uint16_t rom_device_id;
1822 uint16_t rom_magic;
1823 uint16_t pcir_offset;
1824 uint8_t checksum;
1825
1826 /* Words in rom data are little endian (like in PCI configuration),
1827 so they can be read / written with pci_get_word / pci_set_word. */
1828
1829 /* Only a valid rom will be patched. */
1830 rom_magic = pci_get_word(ptr);
1831 if (rom_magic != 0xaa55) {
1832 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
1833 return;
1834 }
1835 pcir_offset = pci_get_word(ptr + 0x18);
1836 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
1837 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
1838 return;
1839 }
1840
1841 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
1842 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
1843 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
1844 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
1845
1846 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
1847 vendor_id, device_id, rom_vendor_id, rom_device_id);
1848
1849 checksum = ptr[6];
1850
1851 if (vendor_id != rom_vendor_id) {
1852 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1853 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
1854 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
1855 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1856 ptr[6] = checksum;
1857 pci_set_word(ptr + pcir_offset + 4, vendor_id);
1858 }
1859
1860 if (device_id != rom_device_id) {
1861 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1862 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
1863 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
1864 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1865 ptr[6] = checksum;
1866 pci_set_word(ptr + pcir_offset + 6, device_id);
1867 }
1868 }
1869
1870 /* Add an option rom for the device */
1871 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
1872 {
1873 int size;
1874 char *path;
1875 void *ptr;
1876 char name[32];
1877
1878 if (!pdev->romfile)
1879 return 0;
1880 if (strlen(pdev->romfile) == 0)
1881 return 0;
1882
1883 if (!pdev->rom_bar) {
1884 /*
1885 * Load rom via fw_cfg instead of creating a rom bar,
1886 * for 0.11 compatibility.
1887 */
1888 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1889 if (class == 0x0300) {
1890 rom_add_vga(pdev->romfile);
1891 } else {
1892 rom_add_option(pdev->romfile, -1);
1893 }
1894 return 0;
1895 }
1896
1897 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1898 if (path == NULL) {
1899 path = g_strdup(pdev->romfile);
1900 }
1901
1902 size = get_image_size(path);
1903 if (size < 0) {
1904 error_report("%s: failed to find romfile \"%s\"",
1905 __FUNCTION__, pdev->romfile);
1906 g_free(path);
1907 return -1;
1908 }
1909 if (size & (size - 1)) {
1910 size = 1 << qemu_fls(size);
1911 }
1912
1913 if (pdev->qdev.info->vmsd)
1914 snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->vmsd->name);
1915 else
1916 snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name);
1917 pdev->has_rom = true;
1918 memory_region_init_ram(&pdev->rom, &pdev->qdev, name, size);
1919 ptr = memory_region_get_ram_ptr(&pdev->rom);
1920 load_image(path, ptr);
1921 g_free(path);
1922
1923 if (is_default_rom) {
1924 /* Only the default rom images will be patched (if needed). */
1925 pci_patch_ids(pdev, ptr, size);
1926 }
1927
1928 qemu_put_ram_ptr(ptr);
1929
1930 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
1931
1932 return 0;
1933 }
1934
1935 static void pci_del_option_rom(PCIDevice *pdev)
1936 {
1937 if (!pdev->has_rom)
1938 return;
1939
1940 memory_region_destroy(&pdev->rom);
1941 pdev->has_rom = false;
1942 }
1943
1944 /*
1945 * if !offset
1946 * Reserve space and add capability to the linked list in pci config space
1947 *
1948 * if offset = 0,
1949 * Find and reserve space and add capability to the linked list
1950 * in pci config space */
1951 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
1952 uint8_t offset, uint8_t size)
1953 {
1954 uint8_t *config;
1955 if (!offset) {
1956 offset = pci_find_space(pdev, size);
1957 if (!offset) {
1958 return -ENOSPC;
1959 }
1960 }
1961
1962 config = pdev->config + offset;
1963 config[PCI_CAP_LIST_ID] = cap_id;
1964 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1965 pdev->config[PCI_CAPABILITY_LIST] = offset;
1966 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1967 memset(pdev->used + offset, 0xFF, size);
1968 /* Make capability read-only by default */
1969 memset(pdev->wmask + offset, 0, size);
1970 /* Check capability by default */
1971 memset(pdev->cmask + offset, 0xFF, size);
1972 return offset;
1973 }
1974
1975 /* Unlink capability from the pci config space. */
1976 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1977 {
1978 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1979 if (!offset)
1980 return;
1981 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1982 /* Make capability writable again */
1983 memset(pdev->wmask + offset, 0xff, size);
1984 memset(pdev->w1cmask + offset, 0, size);
1985 /* Clear cmask as device-specific registers can't be checked */
1986 memset(pdev->cmask + offset, 0, size);
1987 memset(pdev->used + offset, 0, size);
1988
1989 if (!pdev->config[PCI_CAPABILITY_LIST])
1990 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1991 }
1992
1993 /* Reserve space for capability at a known offset (to call after load). */
1994 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1995 {
1996 memset(pdev->used + offset, 0xff, size);
1997 }
1998
1999 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
2000 {
2001 return pci_find_capability_list(pdev, cap_id, NULL);
2002 }
2003
2004 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
2005 {
2006 PCIDevice *d = (PCIDevice *)dev;
2007 const pci_class_desc *desc;
2008 char ctxt[64];
2009 PCIIORegion *r;
2010 int i, class;
2011
2012 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2013 desc = pci_class_descriptions;
2014 while (desc->desc && class != desc->class)
2015 desc++;
2016 if (desc->desc) {
2017 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
2018 } else {
2019 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
2020 }
2021
2022 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
2023 "pci id %04x:%04x (sub %04x:%04x)\n",
2024 indent, "", ctxt, pci_bus_num(d->bus),
2025 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
2026 pci_get_word(d->config + PCI_VENDOR_ID),
2027 pci_get_word(d->config + PCI_DEVICE_ID),
2028 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
2029 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
2030 for (i = 0; i < PCI_NUM_REGIONS; i++) {
2031 r = &d->io_regions[i];
2032 if (!r->size)
2033 continue;
2034 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2035 " [0x%"FMT_PCIBUS"]\n",
2036 indent, "",
2037 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
2038 r->addr, r->addr + r->size - 1);
2039 }
2040 }
2041
2042 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
2043 {
2044 PCIDevice *d = (PCIDevice *)dev;
2045 const char *name = NULL;
2046 const pci_class_desc *desc = pci_class_descriptions;
2047 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2048
2049 while (desc->desc &&
2050 (class & ~desc->fw_ign_bits) !=
2051 (desc->class & ~desc->fw_ign_bits)) {
2052 desc++;
2053 }
2054
2055 if (desc->desc) {
2056 name = desc->fw_name;
2057 }
2058
2059 if (name) {
2060 pstrcpy(buf, len, name);
2061 } else {
2062 snprintf(buf, len, "pci%04x,%04x",
2063 pci_get_word(d->config + PCI_VENDOR_ID),
2064 pci_get_word(d->config + PCI_DEVICE_ID));
2065 }
2066
2067 return buf;
2068 }
2069
2070 static char *pcibus_get_fw_dev_path(DeviceState *dev)
2071 {
2072 PCIDevice *d = (PCIDevice *)dev;
2073 char path[50], name[33];
2074 int off;
2075
2076 off = snprintf(path, sizeof(path), "%s@%x",
2077 pci_dev_fw_name(dev, name, sizeof name),
2078 PCI_SLOT(d->devfn));
2079 if (PCI_FUNC(d->devfn))
2080 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
2081 return strdup(path);
2082 }
2083
2084 static char *pcibus_get_dev_path(DeviceState *dev)
2085 {
2086 PCIDevice *d = container_of(dev, PCIDevice, qdev);
2087 PCIDevice *t;
2088 int slot_depth;
2089 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2090 * 00 is added here to make this format compatible with
2091 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2092 * Slot.Function list specifies the slot and function numbers for all
2093 * devices on the path from root to the specific device. */
2094 char domain[] = "DDDD:00";
2095 char slot[] = ":SS.F";
2096 int domain_len = sizeof domain - 1 /* For '\0' */;
2097 int slot_len = sizeof slot - 1 /* For '\0' */;
2098 int path_len;
2099 char *path, *p;
2100 int s;
2101
2102 /* Calculate # of slots on path between device and root. */;
2103 slot_depth = 0;
2104 for (t = d; t; t = t->bus->parent_dev) {
2105 ++slot_depth;
2106 }
2107
2108 path_len = domain_len + slot_len * slot_depth;
2109
2110 /* Allocate memory, fill in the terminating null byte. */
2111 path = g_malloc(path_len + 1 /* For '\0' */);
2112 path[path_len] = '\0';
2113
2114 /* First field is the domain. */
2115 s = snprintf(domain, sizeof domain, "%04x:00", pci_find_domain(d->bus));
2116 assert(s == domain_len);
2117 memcpy(path, domain, domain_len);
2118
2119 /* Fill in slot numbers. We walk up from device to root, so need to print
2120 * them in the reverse order, last to first. */
2121 p = path + path_len;
2122 for (t = d; t; t = t->bus->parent_dev) {
2123 p -= slot_len;
2124 s = snprintf(slot, sizeof slot, ":%02x.%x",
2125 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
2126 assert(s == slot_len);
2127 memcpy(p, slot, slot_len);
2128 }
2129
2130 return path;
2131 }
2132
2133 static int pci_qdev_find_recursive(PCIBus *bus,
2134 const char *id, PCIDevice **pdev)
2135 {
2136 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2137 if (!qdev) {
2138 return -ENODEV;
2139 }
2140
2141 /* roughly check if given qdev is pci device */
2142 if (qdev->info->init == &pci_qdev_init &&
2143 qdev->parent_bus->info == &pci_bus_info) {
2144 *pdev = DO_UPCAST(PCIDevice, qdev, qdev);
2145 return 0;
2146 }
2147 return -EINVAL;
2148 }
2149
2150 int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2151 {
2152 struct PCIHostBus *host;
2153 int rc = -ENODEV;
2154
2155 QLIST_FOREACH(host, &host_buses, next) {
2156 int tmp = pci_qdev_find_recursive(host->bus, id, pdev);
2157 if (!tmp) {
2158 rc = 0;
2159 break;
2160 }
2161 if (tmp != -ENODEV) {
2162 rc = tmp;
2163 }
2164 }
2165
2166 return rc;
2167 }
various patches