cpu-common.h

   1 #ifndef CPU_COMMON_H
   2 #define CPU_COMMON_H 1
   3
   4 /* CPU interfaces that are target indpendent.  */
   5
   6 #if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__) || defined(__ia64__)
   7 #define WORDS_ALIGNED
   8 #endif
   9
  10 #ifdef TARGET_PHYS_ADDR_BITS
  11 #include "targphys.h"
  12 #endif
  13
  14 #ifndef NEED_CPU_H
  15 #include "poison.h"
  16 #endif
  17
  18 #include "bswap.h"
  19 #include "qemu-queue.h"
  20
  21 #if !defined(CONFIG_USER_ONLY)
  22
  23 enum device_endian {
  24     DEVICE_NATIVE_ENDIAN,
  25     DEVICE_BIG_ENDIAN,
  26     DEVICE_LITTLE_ENDIAN,
  27 };
  28
  29 /* address in the RAM (different from a physical address) */
  30 typedef unsigned long ram_addr_t;
  31
  32 /* memory API */
  33
  34 typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
  35 typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
  36
  37 void cpu_register_physical_memory_log(target_phys_addr_t start_addr,
  38                                       ram_addr_t size,
  39                                       ram_addr_t phys_offset,
  40                                       ram_addr_t region_offset,
  41                                       bool log_dirty);
  42
  43 static inline void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
  44                                                        ram_addr_t size,
  45                                                        ram_addr_t phys_offset,
  46                                                        ram_addr_t region_offset)
  47 {
  48     cpu_register_physical_memory_log(start_addr, size, phys_offset,
  49                                      region_offset, false);
  50 }
  51
  52 static inline void cpu_register_physical_memory(target_phys_addr_t start_addr,
  53                                                 ram_addr_t size,
  54                                                 ram_addr_t phys_offset)
  55 {
  56     cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0);
  57 }
  58
  59 ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr);
  60 ram_addr_t qemu_ram_alloc_from_ptr(DeviceState *dev, const char *name,
  61                         ram_addr_t size, void *host);
  62 ram_addr_t qemu_ram_alloc(DeviceState *dev, const char *name, ram_addr_t size);
  63 void qemu_ram_free(ram_addr_t addr);
  64 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
  65 /* This should only be used for ram local to a device.  */
  66 void *qemu_get_ram_ptr(ram_addr_t addr);
  67 /* Same but slower, to use for migration, where the order of
  68  * RAMBlocks must not change. */
  69 void *qemu_safe_ram_ptr(ram_addr_t addr);
  70 /* This should not be used by devices.  */
  71 int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr);
  72 ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr);
  73
  74 int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
  75                            CPUWriteMemoryFunc * const *mem_write,
  76                            void *opaque, enum device_endian endian);
  77 void cpu_unregister_io_memory(int table_address);
  78
  79 void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
  80                             int len, int is_write);
  81 static inline void cpu_physical_memory_read(target_phys_addr_t addr,
  82                                             uint8_t *buf, int len)
  83 {
  84     cpu_physical_memory_rw(addr, buf, len, 0);
  85 }
  86 static inline void cpu_physical_memory_write(target_phys_addr_t addr,
  87                                              const uint8_t *buf, int len)
  88 {
  89     cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
  90 }
  91 void *cpu_physical_memory_map(target_phys_addr_t addr,
  92                               target_phys_addr_t *plen,
  93                               int is_write);
  94 void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
  95                                int is_write, target_phys_addr_t access_len);
  96 void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque));
  97 void cpu_unregister_map_client(void *cookie);
  98
  99 struct CPUPhysMemoryClient;
 100 typedef struct CPUPhysMemoryClient CPUPhysMemoryClient;
 101 struct CPUPhysMemoryClient {
 102     void (*set_memory)(struct CPUPhysMemoryClient *client,
 103                        target_phys_addr_t start_addr,
 104                        ram_addr_t size,
 105                        ram_addr_t phys_offset,
 106                        bool log_dirty);
 107     int (*sync_dirty_bitmap)(struct CPUPhysMemoryClient *client,
 108                              target_phys_addr_t start_addr,
 109                              target_phys_addr_t end_addr);
 110     int (*migration_log)(struct CPUPhysMemoryClient *client,
 111                          int enable);
 112     int (*log_start)(struct CPUPhysMemoryClient *client,
 113                      target_phys_addr_t phys_addr, ram_addr_t size);
 114     int (*log_stop)(struct CPUPhysMemoryClient *client,
 115                     target_phys_addr_t phys_addr, ram_addr_t size);
 116     QLIST_ENTRY(CPUPhysMemoryClient) list;
 117 };
 118
 119 void cpu_register_phys_memory_client(CPUPhysMemoryClient *);
 120 void cpu_unregister_phys_memory_client(CPUPhysMemoryClient *);
 121
 122 /* Coalesced MMIO regions are areas where write operations can be reordered.
 123  * This usually implies that write operations are side-effect free.  This allows
 124  * batching which can make a major impact on performance when using
 125  * virtualization.
 126  */
 127 void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
 128
 129 void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
 130
 131 void qemu_flush_coalesced_mmio_buffer(void);
 132
 133 uint32_t ldub_phys(target_phys_addr_t addr);
 134 uint32_t lduw_phys(target_phys_addr_t addr);
 135 uint32_t ldl_phys(target_phys_addr_t addr);
 136 uint64_t ldq_phys(target_phys_addr_t addr);
 137 void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
 138 void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
 139 void stb_phys(target_phys_addr_t addr, uint32_t val);
 140 void stw_phys(target_phys_addr_t addr, uint32_t val);
 141 void stl_phys(target_phys_addr_t addr, uint32_t val);
 142 void stq_phys(target_phys_addr_t addr, uint64_t val);
 143
 144 void cpu_physical_memory_write_rom(target_phys_addr_t addr,
 145                                    const uint8_t *buf, int len);
 146
 147 #define IO_MEM_SHIFT       3
 148
 149 #define IO_MEM_RAM         (0 << IO_MEM_SHIFT) /* hardcoded offset */
 150 #define IO_MEM_ROM         (1 << IO_MEM_SHIFT) /* hardcoded offset */
 151 #define IO_MEM_UNASSIGNED  (2 << IO_MEM_SHIFT)
 152 #define IO_MEM_NOTDIRTY    (3 << IO_MEM_SHIFT)
 153
 154 /* Acts like a ROM when read and like a device when written.  */
 155 #define IO_MEM_ROMD        (1)
 156 #define IO_MEM_SUBPAGE     (2)
 157
 158 #endif
 159
 160 #endif /* !CPU_COMMON_H */