target-sh4/op_helper.c

   1 /*
   2  *  SH4 emulation
   3  *
   4  *  Copyright (c) 2005 Samuel Tardieu
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <assert.h>
  20 #include <stdlib.h>
  21 #include "exec.h"
  22 #include "helper.h"
  23
  24 static void cpu_restore_state_from_retaddr(void *retaddr)
  25 {
  26     TranslationBlock *tb;
  27     unsigned long pc;
  28
  29     if (retaddr) {
  30         pc = (unsigned long) retaddr;
  31         tb = tb_find_pc(pc);
  32         if (tb) {
  33             /* the PC is inside the translated code. It means that we have
  34                a virtual CPU fault */
  35             cpu_restore_state(tb, env, pc, NULL);
  36         }
  37     }
  38 }
  39
  40 #ifndef CONFIG_USER_ONLY
  41
  42 #define MMUSUFFIX _mmu
  43
  44 #define SHIFT 0
  45 #include "softmmu_template.h"
  46
  47 #define SHIFT 1
  48 #include "softmmu_template.h"
  49
  50 #define SHIFT 2
  51 #include "softmmu_template.h"
  52
  53 #define SHIFT 3
  54 #include "softmmu_template.h"
  55
  56 void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
  57 {
  58     CPUState *saved_env;
  59     int ret;
  60
  61     /* XXX: hack to restore env in all cases, even if not called from
  62        generated code */
  63     saved_env = env;
  64     env = cpu_single_env;
  65     ret = cpu_sh4_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
  66     if (ret) {
  67         /* now we have a real cpu fault */
  68         cpu_restore_state_from_retaddr(retaddr);
  69         cpu_loop_exit();
  70     }
  71     env = saved_env;
  72 }
  73
  74 #endif
  75
  76 void helper_ldtlb(void)
  77 {
  78 #ifdef CONFIG_USER_ONLY
  79     /* XXXXX */
  80     cpu_abort(env, "Unhandled ldtlb");
  81 #else
  82     cpu_load_tlb(env);
  83 #endif
  84 }
  85
  86 static inline void raise_exception(int index, void *retaddr)
  87 {
  88     env->exception_index = index;
  89     cpu_restore_state_from_retaddr(retaddr);
  90     cpu_loop_exit();
  91 }
  92
  93 void helper_raise_illegal_instruction(void)
  94 {
  95     raise_exception(0x180, GETPC());
  96 }
  97
  98 void helper_raise_slot_illegal_instruction(void)
  99 {
 100     raise_exception(0x1a0, GETPC());
 101 }
 102
 103 void helper_raise_fpu_disable(void)
 104 {
 105     raise_exception(0x800, GETPC());
 106 }
 107
 108 void helper_raise_slot_fpu_disable(void)
 109 {
 110     raise_exception(0x820, GETPC());
 111 }
 112
 113 void helper_debug(void)
 114 {
 115     env->exception_index = EXCP_DEBUG;
 116     cpu_loop_exit();
 117 }
 118
 119 void helper_sleep(uint32_t next_pc)
 120 {
 121     env->halted = 1;
 122     env->in_sleep = 1;
 123     env->exception_index = EXCP_HLT;
 124     env->pc = next_pc;
 125     cpu_loop_exit();
 126 }
 127
 128 void helper_trapa(uint32_t tra)
 129 {
 130     env->tra = tra << 2;
 131     raise_exception(0x160, GETPC());
 132 }
 133
 134 void helper_movcal(uint32_t address, uint32_t value)
 135 {
 136     if (cpu_sh4_is_cached (env, address))
 137     {
 138         memory_content *r = malloc (sizeof(memory_content));
 139         r->address = address;
 140         r->value = value;
 141         r->next = NULL;
 142
 143         *(env->movcal_backup_tail) = r;
 144         env->movcal_backup_tail = &(r->next);
 145     }
 146 }
 147
 148 void helper_discard_movcal_backup(void)
 149 {
 150     memory_content *current = env->movcal_backup;
 151
 152     while(current)
 153     {
 154         memory_content *next = current->next;
 155         free (current);
 156         env->movcal_backup = current = next;
 157         if (current == NULL)
 158             env->movcal_backup_tail = &(env->movcal_backup);
 159     }
 160 }
 161
 162 void helper_ocbi(uint32_t address)
 163 {
 164     memory_content **current = &(env->movcal_backup);
 165     while (*current)
 166     {
 167         uint32_t a = (*current)->address;
 168         if ((a & ~0x1F) == (address & ~0x1F))
 169         {
 170             memory_content *next = (*current)->next;
 171             stl(a, (*current)->value);
 172
 173             if (next == NULL)
 174             {
 175                 env->movcal_backup_tail = current;
 176             }
 177
 178             free (*current);
 179             *current = next;
 180             break;
 181         }
 182     }
 183 }
 184
 185 uint32_t helper_addc(uint32_t arg0, uint32_t arg1)
 186 {
 187     uint32_t tmp0, tmp1;
 188
 189     tmp1 = arg0 + arg1;
 190     tmp0 = arg1;
 191     arg1 = tmp1 + (env->sr & 1);
 192     if (tmp0 > tmp1)
 193         env->sr |= SR_T;
 194     else
 195         env->sr &= ~SR_T;
 196     if (tmp1 > arg1)
 197         env->sr |= SR_T;
 198     return arg1;
 199 }
 200
 201 uint32_t helper_addv(uint32_t arg0, uint32_t arg1)
 202 {
 203     uint32_t dest, src, ans;
 204
 205     if ((int32_t) arg1 >= 0)
 206         dest = 0;
 207     else
 208         dest = 1;
 209     if ((int32_t) arg0 >= 0)
 210         src = 0;
 211     else
 212         src = 1;
 213     src += dest;
 214     arg1 += arg0;
 215     if ((int32_t) arg1 >= 0)
 216         ans = 0;
 217     else
 218         ans = 1;
 219     ans += dest;
 220     if (src == 0 || src == 2) {
 221         if (ans == 1)
 222             env->sr |= SR_T;
 223         else
 224             env->sr &= ~SR_T;
 225     } else
 226         env->sr &= ~SR_T;
 227     return arg1;
 228 }
 229
 230 #define T (env->sr & SR_T)
 231 #define Q (env->sr & SR_Q ? 1 : 0)
 232 #define M (env->sr & SR_M ? 1 : 0)
 233 #define SETT env->sr |= SR_T
 234 #define CLRT env->sr &= ~SR_T
 235 #define SETQ env->sr |= SR_Q
 236 #define CLRQ env->sr &= ~SR_Q
 237 #define SETM env->sr |= SR_M
 238 #define CLRM env->sr &= ~SR_M
 239
 240 uint32_t helper_div1(uint32_t arg0, uint32_t arg1)
 241 {
 242     uint32_t tmp0, tmp2;
 243     uint8_t old_q, tmp1 = 0xff;
 244
 245     //printf("div1 arg0=0x%08x arg1=0x%08x M=%d Q=%d T=%d\n", arg0, arg1, M, Q, T);
 246     old_q = Q;
 247     if ((0x80000000 & arg1) != 0)
 248         SETQ;
 249     else
 250         CLRQ;
 251     tmp2 = arg0;
 252     arg1 <<= 1;
 253     arg1 |= T;
 254     switch (old_q) {
 255     case 0:
 256         switch (M) {
 257         case 0:
 258             tmp0 = arg1;
 259             arg1 -= tmp2;
 260             tmp1 = arg1 > tmp0;
 261             switch (Q) {
 262             case 0:
 263                 if (tmp1)
 264                     SETQ;
 265                 else
 266                     CLRQ;
 267                 break;
 268             case 1:
 269                 if (tmp1 == 0)
 270                     SETQ;
 271                 else
 272                     CLRQ;
 273                 break;
 274             }
 275             break;
 276         case 1:
 277             tmp0 = arg1;
 278             arg1 += tmp2;
 279             tmp1 = arg1 < tmp0;
 280             switch (Q) {
 281             case 0:
 282                 if (tmp1 == 0)
 283                     SETQ;
 284                 else
 285                     CLRQ;
 286                 break;
 287             case 1:
 288                 if (tmp1)
 289                     SETQ;
 290                 else
 291                     CLRQ;
 292                 break;
 293             }
 294             break;
 295         }
 296         break;
 297     case 1:
 298         switch (M) {
 299         case 0:
 300             tmp0 = arg1;
 301             arg1 += tmp2;
 302             tmp1 = arg1 < tmp0;
 303             switch (Q) {
 304             case 0:
 305                 if (tmp1)
 306                     SETQ;
 307                 else
 308                     CLRQ;
 309                 break;
 310             case 1:
 311                 if (tmp1 == 0)
 312                     SETQ;
 313                 else
 314                     CLRQ;
 315                 break;
 316             }
 317             break;
 318         case 1:
 319             tmp0 = arg1;
 320             arg1 -= tmp2;
 321             tmp1 = arg1 > tmp0;
 322             switch (Q) {
 323             case 0:
 324                 if (tmp1 == 0)
 325                     SETQ;
 326                 else
 327                     CLRQ;
 328                 break;
 329             case 1:
 330                 if (tmp1)
 331                     SETQ;
 332                 else
 333                     CLRQ;
 334                 break;
 335             }
 336             break;
 337         }
 338         break;
 339     }
 340     if (Q == M)
 341         SETT;
 342     else
 343         CLRT;
 344     //printf("Output: arg1=0x%08x M=%d Q=%d T=%d\n", arg1, M, Q, T);
 345     return arg1;
 346 }
 347
 348 void helper_macl(uint32_t arg0, uint32_t arg1)
 349 {
 350     int64_t res;
 351
 352     res = ((uint64_t) env->mach << 32) | env->macl;
 353     res += (int64_t) (int32_t) arg0 *(int64_t) (int32_t) arg1;
 354     env->mach = (res >> 32) & 0xffffffff;
 355     env->macl = res & 0xffffffff;
 356     if (env->sr & SR_S) {
 357         if (res < 0)
 358             env->mach |= 0xffff0000;
 359         else
 360             env->mach &= 0x00007fff;
 361     }
 362 }
 363
 364 void helper_macw(uint32_t arg0, uint32_t arg1)
 365 {
 366     int64_t res;
 367
 368     res = ((uint64_t) env->mach << 32) | env->macl;
 369     res += (int64_t) (int16_t) arg0 *(int64_t) (int16_t) arg1;
 370     env->mach = (res >> 32) & 0xffffffff;
 371     env->macl = res & 0xffffffff;
 372     if (env->sr & SR_S) {
 373         if (res < -0x80000000) {
 374             env->mach = 1;
 375             env->macl = 0x80000000;
 376         } else if (res > 0x000000007fffffff) {
 377             env->mach = 1;
 378             env->macl = 0x7fffffff;
 379         }
 380     }
 381 }
 382
 383 uint32_t helper_subc(uint32_t arg0, uint32_t arg1)
 384 {
 385     uint32_t tmp0, tmp1;
 386
 387     tmp1 = arg1 - arg0;
 388     tmp0 = arg1;
 389     arg1 = tmp1 - (env->sr & SR_T);
 390     if (tmp0 < tmp1)
 391         env->sr |= SR_T;
 392     else
 393         env->sr &= ~SR_T;
 394     if (tmp1 < arg1)
 395         env->sr |= SR_T;
 396     return arg1;
 397 }
 398
 399 uint32_t helper_subv(uint32_t arg0, uint32_t arg1)
 400 {
 401     int32_t dest, src, ans;
 402
 403     if ((int32_t) arg1 >= 0)
 404         dest = 0;
 405     else
 406         dest = 1;
 407     if ((int32_t) arg0 >= 0)
 408         src = 0;
 409     else
 410         src = 1;
 411     src += dest;
 412     arg1 -= arg0;
 413     if ((int32_t) arg1 >= 0)
 414         ans = 0;
 415     else
 416         ans = 1;
 417     ans += dest;
 418     if (src == 1) {
 419         if (ans == 1)
 420             env->sr |= SR_T;
 421         else
 422             env->sr &= ~SR_T;
 423     } else
 424         env->sr &= ~SR_T;
 425     return arg1;
 426 }
 427
 428 static inline void set_t(void)
 429 {
 430     env->sr |= SR_T;
 431 }
 432
 433 static inline void clr_t(void)
 434 {
 435     env->sr &= ~SR_T;
 436 }
 437
 438 void helper_ld_fpscr(uint32_t val)
 439 {
 440     env->fpscr = val & FPSCR_MASK;
 441     if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) {
 442         set_float_rounding_mode(float_round_to_zero, &env->fp_status);
 443     } else {
 444         set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
 445     }
 446     set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status);
 447 }
 448
 449 static void update_fpscr(void *retaddr)
 450 {
 451     int xcpt, cause, enable;
 452
 453     xcpt = get_float_exception_flags(&env->fp_status);
 454
 455     /* Clear the flag entries */
 456     env->fpscr &= ~FPSCR_FLAG_MASK;
 457
 458     if (unlikely(xcpt)) {
 459         if (xcpt & float_flag_invalid) {
 460             env->fpscr |= FPSCR_FLAG_V;
 461         }
 462         if (xcpt & float_flag_divbyzero) {
 463             env->fpscr |= FPSCR_FLAG_Z;
 464         }
 465         if (xcpt & float_flag_overflow) {
 466             env->fpscr |= FPSCR_FLAG_O;
 467         }
 468         if (xcpt & float_flag_underflow) {
 469             env->fpscr |= FPSCR_FLAG_U;
 470         }
 471         if (xcpt & float_flag_inexact) {
 472             env->fpscr |= FPSCR_FLAG_I;
 473         }
 474
 475         /* Accumulate in cause entries */
 476         env->fpscr |= (env->fpscr & FPSCR_FLAG_MASK)
 477                       << (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT);
 478
 479         /* Generate an exception if enabled */
 480         cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT;
 481         enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT;
 482         if (cause & enable) {
 483             cpu_restore_state_from_retaddr(retaddr);
 484             env->exception_index = 0x120;
 485             cpu_loop_exit();
 486         }
 487     }
 488 }
 489
 490 uint32_t helper_fabs_FT(uint32_t t0)
 491 {
 492     CPU_FloatU f;
 493     f.l = t0;
 494     f.f = float32_abs(f.f);
 495     return f.l;
 496 }
 497
 498 uint64_t helper_fabs_DT(uint64_t t0)
 499 {
 500     CPU_DoubleU d;
 501     d.ll = t0;
 502     d.d = float64_abs(d.d);
 503     return d.ll;
 504 }
 505
 506 uint32_t helper_fadd_FT(uint32_t t0, uint32_t t1)
 507 {
 508     CPU_FloatU f0, f1;
 509     f0.l = t0;
 510     f1.l = t1;
 511     set_float_exception_flags(0, &env->fp_status);
 512     f0.f = float32_add(f0.f, f1.f, &env->fp_status);
 513     update_fpscr(GETPC());
 514     return f0.l;
 515 }
 516
 517 uint64_t helper_fadd_DT(uint64_t t0, uint64_t t1)
 518 {
 519     CPU_DoubleU d0, d1;
 520     d0.ll = t0;
 521     d1.ll = t1;
 522     set_float_exception_flags(0, &env->fp_status);
 523     d0.d = float64_add(d0.d, d1.d, &env->fp_status);
 524     update_fpscr(GETPC());
 525     return d0.ll;
 526 }
 527
 528 void helper_fcmp_eq_FT(uint32_t t0, uint32_t t1)
 529 {
 530     CPU_FloatU f0, f1;
 531     int relation;
 532     f0.l = t0;
 533     f1.l = t1;
 534
 535     set_float_exception_flags(0, &env->fp_status);
 536     relation = float32_compare(f0.f, f1.f, &env->fp_status);
 537     if (unlikely(relation == float_relation_unordered)) {
 538         update_fpscr(GETPC());
 539     } else if (relation == float_relation_equal) {
 540         set_t();
 541     } else {
 542         clr_t();
 543     }
 544 }
 545
 546 void helper_fcmp_eq_DT(uint64_t t0, uint64_t t1)
 547 {
 548     CPU_DoubleU d0, d1;
 549     int relation;
 550     d0.ll = t0;
 551     d1.ll = t1;
 552
 553     set_float_exception_flags(0, &env->fp_status);
 554     relation = float64_compare(d0.d, d1.d, &env->fp_status);
 555     if (unlikely(relation == float_relation_unordered)) {
 556         update_fpscr(GETPC());
 557     } else if (relation == float_relation_equal) {
 558         set_t();
 559     } else {
 560         clr_t();
 561     }
 562 }
 563
 564 void helper_fcmp_gt_FT(uint32_t t0, uint32_t t1)
 565 {
 566     CPU_FloatU f0, f1;
 567     int relation;
 568     f0.l = t0;
 569     f1.l = t1;
 570
 571     set_float_exception_flags(0, &env->fp_status);
 572     relation = float32_compare(f0.f, f1.f, &env->fp_status);
 573     if (unlikely(relation == float_relation_unordered)) {
 574         update_fpscr(GETPC());
 575     } else if (relation == float_relation_greater) {
 576         set_t();
 577     } else {
 578         clr_t();
 579     }
 580 }
 581
 582 void helper_fcmp_gt_DT(uint64_t t0, uint64_t t1)
 583 {
 584     CPU_DoubleU d0, d1;
 585     int relation;
 586     d0.ll = t0;
 587     d1.ll = t1;
 588
 589     set_float_exception_flags(0, &env->fp_status);
 590     relation = float64_compare(d0.d, d1.d, &env->fp_status);
 591     if (unlikely(relation == float_relation_unordered)) {
 592         update_fpscr(GETPC());
 593     } else if (relation == float_relation_greater) {
 594         set_t();
 595     } else {
 596         clr_t();
 597     }
 598 }
 599
 600 uint64_t helper_fcnvsd_FT_DT(uint32_t t0)
 601 {
 602     CPU_DoubleU d;
 603     CPU_FloatU f;
 604     f.l = t0;
 605     set_float_exception_flags(0, &env->fp_status);
 606     d.d = float32_to_float64(f.f, &env->fp_status);
 607     update_fpscr(GETPC());
 608     return d.ll;
 609 }
 610
 611 uint32_t helper_fcnvds_DT_FT(uint64_t t0)
 612 {
 613     CPU_DoubleU d;
 614     CPU_FloatU f;
 615     d.ll = t0;
 616     set_float_exception_flags(0, &env->fp_status);
 617     f.f = float64_to_float32(d.d, &env->fp_status);
 618     update_fpscr(GETPC());
 619     return f.l;
 620 }
 621
 622 uint32_t helper_fdiv_FT(uint32_t t0, uint32_t t1)
 623 {
 624     CPU_FloatU f0, f1;
 625     f0.l = t0;
 626     f1.l = t1;
 627     set_float_exception_flags(0, &env->fp_status);
 628     f0.f = float32_div(f0.f, f1.f, &env->fp_status);
 629     update_fpscr(GETPC());
 630     return f0.l;
 631 }
 632
 633 uint64_t helper_fdiv_DT(uint64_t t0, uint64_t t1)
 634 {
 635     CPU_DoubleU d0, d1;
 636     d0.ll = t0;
 637     d1.ll = t1;
 638     set_float_exception_flags(0, &env->fp_status);
 639     d0.d = float64_div(d0.d, d1.d, &env->fp_status);
 640     update_fpscr(GETPC());
 641     return d0.ll;
 642 }
 643
 644 uint32_t helper_float_FT(uint32_t t0)
 645 {
 646     CPU_FloatU f;
 647
 648     set_float_exception_flags(0, &env->fp_status);
 649     f.f = int32_to_float32(t0, &env->fp_status);
 650     update_fpscr(GETPC());
 651
 652     return f.l;
 653 }
 654
 655 uint64_t helper_float_DT(uint32_t t0)
 656 {
 657     CPU_DoubleU d;
 658     set_float_exception_flags(0, &env->fp_status);
 659     d.d = int32_to_float64(t0, &env->fp_status);
 660     update_fpscr(GETPC());
 661     return d.ll;
 662 }
 663
 664 uint32_t helper_fmac_FT(uint32_t t0, uint32_t t1, uint32_t t2)
 665 {
 666     CPU_FloatU f0, f1, f2;
 667     f0.l = t0;
 668     f1.l = t1;
 669     f2.l = t2;
 670     set_float_exception_flags(0, &env->fp_status);
 671     f0.f = float32_mul(f0.f, f1.f, &env->fp_status);
 672     f0.f = float32_add(f0.f, f2.f, &env->fp_status);
 673     update_fpscr(GETPC());
 674
 675     return f0.l;
 676 }
 677
 678 uint32_t helper_fmul_FT(uint32_t t0, uint32_t t1)
 679 {
 680     CPU_FloatU f0, f1;
 681     f0.l = t0;
 682     f1.l = t1;
 683     set_float_exception_flags(0, &env->fp_status);
 684     f0.f = float32_mul(f0.f, f1.f, &env->fp_status);
 685     update_fpscr(GETPC());
 686     return f0.l;
 687 }
 688
 689 uint64_t helper_fmul_DT(uint64_t t0, uint64_t t1)
 690 {
 691     CPU_DoubleU d0, d1;
 692     d0.ll = t0;
 693     d1.ll = t1;
 694     set_float_exception_flags(0, &env->fp_status);
 695     d0.d = float64_mul(d0.d, d1.d, &env->fp_status);
 696     update_fpscr(GETPC());
 697
 698     return d0.ll;
 699 }
 700
 701 uint32_t helper_fneg_T(uint32_t t0)
 702 {
 703     CPU_FloatU f;
 704     f.l = t0;
 705     f.f = float32_chs(f.f);
 706     return f.l;
 707 }
 708
 709 uint32_t helper_fsqrt_FT(uint32_t t0)
 710 {
 711     CPU_FloatU f;
 712     f.l = t0;
 713     set_float_exception_flags(0, &env->fp_status);
 714     f.f = float32_sqrt(f.f, &env->fp_status);
 715     update_fpscr(GETPC());
 716     return f.l;
 717 }
 718
 719 uint64_t helper_fsqrt_DT(uint64_t t0)
 720 {
 721     CPU_DoubleU d;
 722     d.ll = t0;
 723     set_float_exception_flags(0, &env->fp_status);
 724     d.d = float64_sqrt(d.d, &env->fp_status);
 725     update_fpscr(GETPC());
 726     return d.ll;
 727 }
 728
 729 uint32_t helper_fsub_FT(uint32_t t0, uint32_t t1)
 730 {
 731     CPU_FloatU f0, f1;
 732     f0.l = t0;
 733     f1.l = t1;
 734     set_float_exception_flags(0, &env->fp_status);
 735     f0.f = float32_sub(f0.f, f1.f, &env->fp_status);
 736     update_fpscr(GETPC());
 737     return f0.l;
 738 }
 739
 740 uint64_t helper_fsub_DT(uint64_t t0, uint64_t t1)
 741 {
 742     CPU_DoubleU d0, d1;
 743
 744     d0.ll = t0;
 745     d1.ll = t1;
 746     set_float_exception_flags(0, &env->fp_status);
 747     d0.d = float64_sub(d0.d, d1.d, &env->fp_status);
 748     update_fpscr(GETPC());
 749     return d0.ll;
 750 }
 751
 752 uint32_t helper_ftrc_FT(uint32_t t0)
 753 {
 754     CPU_FloatU f;
 755     uint32_t ret;
 756     f.l = t0;
 757     set_float_exception_flags(0, &env->fp_status);
 758     ret = float32_to_int32_round_to_zero(f.f, &env->fp_status);
 759     update_fpscr(GETPC());
 760     return ret;
 761 }
 762
 763 uint32_t helper_ftrc_DT(uint64_t t0)
 764 {
 765     CPU_DoubleU d;
 766     uint32_t ret;
 767     d.ll = t0;
 768     set_float_exception_flags(0, &env->fp_status);
 769     ret = float64_to_int32_round_to_zero(d.d, &env->fp_status);
 770     update_fpscr(GETPC());
 771     return ret;
 772 }
 773
 774 void helper_fipr(uint32_t m, uint32_t n)
 775 {
 776     int bank, i;
 777     float32 r, p;
 778
 779     bank = (env->sr & FPSCR_FR) ? 16 : 0;
 780     r = float32_zero;
 781     set_float_exception_flags(0, &env->fp_status);
 782
 783     for (i = 0 ; i < 4 ; i++) {
 784         p = float32_mul(env->fregs[bank + m + i],
 785                         env->fregs[bank + n + i],
 786                         &env->fp_status);
 787         r = float32_add(r, p, &env->fp_status);
 788     }
 789     update_fpscr(GETPC());
 790
 791     env->fregs[bank + n + 3] = r;
 792 }
 793
 794 void helper_ftrv(uint32_t n)
 795 {
 796     int bank_matrix, bank_vector;
 797     int i, j;
 798     float32 r[4];
 799     float32 p;
 800
 801     bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16;
 802     bank_vector = (env->sr & FPSCR_FR) ? 16 : 0;
 803     set_float_exception_flags(0, &env->fp_status);
 804     for (i = 0 ; i < 4 ; i++) {
 805         r[i] = float32_zero;
 806         for (j = 0 ; j < 4 ; j++) {
 807             p = float32_mul(env->fregs[bank_matrix + 4 * j + i],
 808                             env->fregs[bank_vector + j],
 809                             &env->fp_status);
 810             r[i] = float32_add(r[i], p, &env->fp_status);
 811         }
 812     }
 813     update_fpscr(GETPC());
 814
 815     for (i = 0 ; i < 4 ; i++) {
 816         env->fregs[bank_vector + i] = r[i];
 817     }
 818 }