hw/piix_pci.c

   1 /*
   2  * QEMU i440FX/PIIX3 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "pc.h"
  27 #include "pci.h"
  28 #include "pci_host.h"
  29 #include "isa.h"
  30 #include "sysbus.h"
  31 #include "range.h"
  32 #include "xen.h"
  33
  34 /*
  35  * I440FX chipset data sheet.
  36  * http://download.intel.com/design/chipsets/datashts/29054901.pdf
  37  */
  38
  39 typedef PCIHostState I440FXState;
  40
  41 #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
  42 #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
  43 #define XEN_PIIX_NUM_PIRQS      128ULL
  44 #define PIIX_PIRQC              0x60
  45
  46 typedef struct PIIX3State {
  47     PCIDevice dev;
  48
  49     /*
  50      * bitmap to track pic levels.
  51      * The pic level is the logical OR of all the PCI irqs mapped to it
  52      * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
  53      *
  54      * PIRQ is mapped to PIC pins, we track it by
  55      * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
  56      * pic_irq * PIIX_NUM_PIRQS + pirq
  57      */
  58 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
  59 #error "unable to encode pic state in 64bit in pic_levels."
  60 #endif
  61     uint64_t pic_levels;
  62
  63     qemu_irq *pic;
  64
  65     /* This member isn't used. Just for save/load compatibility */
  66     int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
  67 } PIIX3State;
  68
  69 struct PCII440FXState {
  70     PCIDevice dev;
  71     target_phys_addr_t isa_page_descs[384 / 4];
  72     uint8_t smm_enabled;
  73     PIIX3State *piix3;
  74 };
  75
  76
  77 #define I440FX_PAM      0x59
  78 #define I440FX_PAM_SIZE 7
  79 #define I440FX_SMRAM    0x72
  80
  81 static void piix3_set_irq(void *opaque, int pirq, int level);
  82 static void piix3_write_config_xen(PCIDevice *dev,
  83                                uint32_t address, uint32_t val, int len);
  84
  85 /* return the global irq number corresponding to a given device irq
  86    pin. We could also use the bus number to have a more precise
  87    mapping. */
  88 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
  89 {
  90     int slot_addend;
  91     slot_addend = (pci_dev->devfn >> 3) - 1;
  92     return (pci_intx + slot_addend) & 3;
  93 }
  94
  95 static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
  96 {
  97     uint32_t addr;
  98
  99     //    printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
 100     switch(r) {
 101     case 3:
 102         /* RAM */
 103         cpu_register_physical_memory(start, end - start,
 104                                      start);
 105         break;
 106     case 1:
 107         /* ROM (XXX: not quite correct) */
 108         cpu_register_physical_memory(start, end - start,
 109                                      start | IO_MEM_ROM);
 110         break;
 111     case 2:
 112     case 0:
 113         /* XXX: should distinguish read/write cases */
 114         for(addr = start; addr < end; addr += 4096) {
 115             cpu_register_physical_memory(addr, 4096,
 116                                          d->isa_page_descs[(addr - 0xa0000) >> 12]);
 117         }
 118         break;
 119     }
 120 }
 121
 122 static void i440fx_update_memory_mappings(PCII440FXState *d)
 123 {
 124     int i, r;
 125     uint32_t smram, addr;
 126
 127     update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3);
 128     for(i = 0; i < 12; i++) {
 129         r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
 130         update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
 131     }
 132     smram = d->dev.config[I440FX_SMRAM];
 133     if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
 134         cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
 135     } else {
 136         for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
 137             cpu_register_physical_memory(addr, 4096,
 138                                          d->isa_page_descs[(addr - 0xa0000) >> 12]);
 139         }
 140     }
 141 }
 142
 143 static void i440fx_set_smm(int val, void *arg)
 144 {
 145     PCII440FXState *d = arg;
 146
 147     val = (val != 0);
 148     if (d->smm_enabled != val) {
 149         d->smm_enabled = val;
 150         i440fx_update_memory_mappings(d);
 151     }
 152 }
 153
 154
 155 /* XXX: suppress when better memory API. We make the assumption that
 156    no device (in particular the VGA) changes the memory mappings in
 157    the 0xa0000-0x100000 range */
 158 void i440fx_init_memory_mappings(PCII440FXState *d)
 159 {
 160     int i;
 161     for(i = 0; i < 96; i++) {
 162         d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
 163     }
 164 }
 165
 166 static void i440fx_write_config(PCIDevice *dev,
 167                                 uint32_t address, uint32_t val, int len)
 168 {
 169     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 170
 171     /* XXX: implement SMRAM.D_LOCK */
 172     pci_default_write_config(dev, address, val, len);
 173     if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
 174         range_covers_byte(address, len, I440FX_SMRAM)) {
 175         i440fx_update_memory_mappings(d);
 176     }
 177 }
 178
 179 static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
 180 {
 181     PCII440FXState *d = opaque;
 182     int ret, i;
 183
 184     ret = pci_device_load(&d->dev, f);
 185     if (ret < 0)
 186         return ret;
 187     i440fx_update_memory_mappings(d);
 188     qemu_get_8s(f, &d->smm_enabled);
 189
 190     if (version_id == 2) {
 191         for (i = 0; i < PIIX_NUM_PIRQS; i++) {
 192             qemu_get_be32(f); /* dummy load for compatibility */
 193         }
 194     }
 195
 196     return 0;
 197 }
 198
 199 static int i440fx_post_load(void *opaque, int version_id)
 200 {
 201     PCII440FXState *d = opaque;
 202
 203     i440fx_update_memory_mappings(d);
 204     return 0;
 205 }
 206
 207 static const VMStateDescription vmstate_i440fx = {
 208     .name = "I440FX",
 209     .version_id = 3,
 210     .minimum_version_id = 3,
 211     .minimum_version_id_old = 1,
 212     .load_state_old = i440fx_load_old,
 213     .post_load = i440fx_post_load,
 214     .fields      = (VMStateField []) {
 215         VMSTATE_PCI_DEVICE(dev, PCII440FXState),
 216         VMSTATE_UINT8(smm_enabled, PCII440FXState),
 217         VMSTATE_END_OF_LIST()
 218     }
 219 };
 220
 221 static int i440fx_pcihost_initfn(SysBusDevice *dev)
 222 {
 223     I440FXState *s = FROM_SYSBUS(I440FXState, dev);
 224
 225     pci_host_conf_register_ioport(0xcf8, s);
 226
 227     pci_host_data_register_ioport(0xcfc, s);
 228     return 0;
 229 }
 230
 231 static int i440fx_initfn(PCIDevice *dev)
 232 {
 233     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 234
 235     d->dev.config[I440FX_SMRAM] = 0x02;
 236
 237     cpu_smm_register(&i440fx_set_smm, d);
 238     return 0;
 239 }
 240
 241 static PCIBus *i440fx_common_init(const char *device_name,
 242                                   PCII440FXState **pi440fx_state,
 243                                   int *piix3_devfn,
 244                                   qemu_irq *pic, ram_addr_t ram_size)
 245 {
 246     DeviceState *dev;
 247     PCIBus *b;
 248     PCIDevice *d;
 249     I440FXState *s;
 250     PIIX3State *piix3;
 251
 252     dev = qdev_create(NULL, "i440FX-pcihost");
 253     s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
 254     b = pci_bus_new(&s->busdev.qdev, NULL, 0);
 255     s->bus = b;
 256     qdev_init_nofail(dev);
 257
 258     d = pci_create_simple(b, 0, device_name);
 259     *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
 260
 261     /* Xen supports additional interrupt routes from the PCI devices to
 262      * the IOAPIC: the four pins of each PCI device on the bus are also
 263      * connected to the IOAPIC directly.
 264      * These additional routes can be discovered through ACPI. */
 265     if (xen_enabled()) {
 266         piix3 = DO_UPCAST(PIIX3State, dev,
 267                 pci_create_simple_multifunction(b, -1, true, "PIIX3-xen"));
 268         pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
 269                 piix3, XEN_PIIX_NUM_PIRQS);
 270     } else {
 271         piix3 = DO_UPCAST(PIIX3State, dev,
 272                 pci_create_simple_multifunction(b, -1, true, "PIIX3"));
 273         pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
 274                 PIIX_NUM_PIRQS);
 275     }
 276     piix3->pic = pic;
 277
 278     (*pi440fx_state)->piix3 = piix3;
 279
 280     *piix3_devfn = piix3->dev.devfn;
 281
 282     ram_size = ram_size / 8 / 1024 / 1024;
 283     if (ram_size > 255)
 284         ram_size = 255;
 285     (*pi440fx_state)->dev.config[0x57]=ram_size;
 286
 287     return b;
 288 }
 289
 290 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
 291                     qemu_irq *pic, ram_addr_t ram_size)
 292 {
 293     PCIBus *b;
 294
 295     b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, pic, ram_size);
 296     return b;
 297 }
 298
 299 /* PIIX3 PCI to ISA bridge */
 300 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
 301 {
 302     qemu_set_irq(piix3->pic[pic_irq],
 303                  !!(piix3->pic_levels &
 304                     (((1ULL << PIIX_NUM_PIRQS) - 1) <<
 305                      (pic_irq * PIIX_NUM_PIRQS))));
 306 }
 307
 308 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
 309 {
 310     int pic_irq;
 311     uint64_t mask;
 312
 313     pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
 314     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
 315         return;
 316     }
 317
 318     mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
 319     piix3->pic_levels &= ~mask;
 320     piix3->pic_levels |= mask * !!level;
 321
 322     piix3_set_irq_pic(piix3, pic_irq);
 323 }
 324
 325 static void piix3_set_irq(void *opaque, int pirq, int level)
 326 {
 327     PIIX3State *piix3 = opaque;
 328     piix3_set_irq_level(piix3, pirq, level);
 329 }
 330
 331 /* irq routing is changed. so rebuild bitmap */
 332 static void piix3_update_irq_levels(PIIX3State *piix3)
 333 {
 334     int pirq;
 335
 336     piix3->pic_levels = 0;
 337     for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
 338         piix3_set_irq_level(piix3, pirq,
 339                             pci_bus_get_irq_level(piix3->dev.bus, pirq));
 340     }
 341 }
 342
 343 static void piix3_write_config(PCIDevice *dev,
 344                                uint32_t address, uint32_t val, int len)
 345 {
 346     pci_default_write_config(dev, address, val, len);
 347     if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
 348         PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
 349         int pic_irq;
 350         piix3_update_irq_levels(piix3);
 351         for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
 352             piix3_set_irq_pic(piix3, pic_irq);
 353         }
 354     }
 355 }
 356
 357 static void piix3_write_config_xen(PCIDevice *dev,
 358                                uint32_t address, uint32_t val, int len)
 359 {
 360     xen_piix_pci_write_config_client(address, val, len);
 361     piix3_write_config(dev, address, val, len);
 362 }
 363
 364 static void piix3_reset(void *opaque)
 365 {
 366     PIIX3State *d = opaque;
 367     uint8_t *pci_conf = d->dev.config;
 368
 369     pci_conf[0x04] = 0x07; // master, memory and I/O
 370     pci_conf[0x05] = 0x00;
 371     pci_conf[0x06] = 0x00;
 372     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
 373     pci_conf[0x4c] = 0x4d;
 374     pci_conf[0x4e] = 0x03;
 375     pci_conf[0x4f] = 0x00;
 376     pci_conf[0x60] = 0x80;
 377     pci_conf[0x61] = 0x80;
 378     pci_conf[0x62] = 0x80;
 379     pci_conf[0x63] = 0x80;
 380     pci_conf[0x69] = 0x02;
 381     pci_conf[0x70] = 0x80;
 382     pci_conf[0x76] = 0x0c;
 383     pci_conf[0x77] = 0x0c;
 384     pci_conf[0x78] = 0x02;
 385     pci_conf[0x79] = 0x00;
 386     pci_conf[0x80] = 0x00;
 387     pci_conf[0x82] = 0x00;
 388     pci_conf[0xa0] = 0x08;
 389     pci_conf[0xa2] = 0x00;
 390     pci_conf[0xa3] = 0x00;
 391     pci_conf[0xa4] = 0x00;
 392     pci_conf[0xa5] = 0x00;
 393     pci_conf[0xa6] = 0x00;
 394     pci_conf[0xa7] = 0x00;
 395     pci_conf[0xa8] = 0x0f;
 396     pci_conf[0xaa] = 0x00;
 397     pci_conf[0xab] = 0x00;
 398     pci_conf[0xac] = 0x00;
 399     pci_conf[0xae] = 0x00;
 400
 401     d->pic_levels = 0;
 402 }
 403
 404 static int piix3_post_load(void *opaque, int version_id)
 405 {
 406     PIIX3State *piix3 = opaque;
 407     piix3_update_irq_levels(piix3);
 408     return 0;
 409 }
 410
 411 static void piix3_pre_save(void *opaque)
 412 {
 413     int i;
 414     PIIX3State *piix3 = opaque;
 415
 416     for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
 417         piix3->pci_irq_levels_vmstate[i] =
 418             pci_bus_get_irq_level(piix3->dev.bus, i);
 419     }
 420 }
 421
 422 static const VMStateDescription vmstate_piix3 = {
 423     .name = "PIIX3",
 424     .version_id = 3,
 425     .minimum_version_id = 2,
 426     .minimum_version_id_old = 2,
 427     .post_load = piix3_post_load,
 428     .pre_save = piix3_pre_save,
 429     .fields      = (VMStateField []) {
 430         VMSTATE_PCI_DEVICE(dev, PIIX3State),
 431         VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
 432                               PIIX_NUM_PIRQS, 3),
 433         VMSTATE_END_OF_LIST()
 434     }
 435 };
 436
 437 static int piix3_initfn(PCIDevice *dev)
 438 {
 439     PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
 440
 441     isa_bus_new(&d->dev.qdev);
 442     qemu_register_reset(piix3_reset, d);
 443     return 0;
 444 }
 445
 446 static PCIDeviceInfo i440fx_info[] = {
 447     {
 448         .qdev.name    = "i440FX",
 449         .qdev.desc    = "Host bridge",
 450         .qdev.size    = sizeof(PCII440FXState),
 451         .qdev.vmsd    = &vmstate_i440fx,
 452         .qdev.no_user = 1,
 453         .no_hotplug   = 1,
 454         .init         = i440fx_initfn,
 455         .config_write = i440fx_write_config,
 456         .vendor_id    = PCI_VENDOR_ID_INTEL,
 457         .device_id    = PCI_DEVICE_ID_INTEL_82441,
 458         .revision     = 0x02,
 459         .class_id     = PCI_CLASS_BRIDGE_HOST,
 460     },{
 461         .qdev.name    = "PIIX3",
 462         .qdev.desc    = "ISA bridge",
 463         .qdev.size    = sizeof(PIIX3State),
 464         .qdev.vmsd    = &vmstate_piix3,
 465         .qdev.no_user = 1,
 466         .no_hotplug   = 1,
 467         .init         = piix3_initfn,
 468         .config_write = piix3_write_config,
 469         .vendor_id    = PCI_VENDOR_ID_INTEL,
 470         .device_id    = PCI_DEVICE_ID_INTEL_82371SB_0, // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 471         .class_id     = PCI_CLASS_BRIDGE_ISA,
 472     },{
 473         .qdev.name    = "PIIX3-xen",
 474         .qdev.desc    = "ISA bridge",
 475         .qdev.size    = sizeof(PIIX3State),
 476         .qdev.vmsd    = &vmstate_piix3,
 477         .qdev.no_user = 1,
 478         .no_hotplug   = 1,
 479         .init         = piix3_initfn,
 480         .config_write = piix3_write_config_xen,
 481         .vendor_id    = PCI_VENDOR_ID_INTEL,
 482         .device_id    = PCI_DEVICE_ID_INTEL_82371SB_0, // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 483         .class_id     = PCI_CLASS_BRIDGE_ISA,
 484     },{
 485         /* end of list */
 486     }
 487 };
 488
 489 static SysBusDeviceInfo i440fx_pcihost_info = {
 490     .init         = i440fx_pcihost_initfn,
 491     .qdev.name    = "i440FX-pcihost",
 492     .qdev.fw_name = "pci",
 493     .qdev.size    = sizeof(I440FXState),
 494     .qdev.no_user = 1,
 495 };
 496
 497 static void i440fx_register(void)
 498 {
 499     sysbus_register_withprop(&i440fx_pcihost_info);
 500     pci_qdev_register_many(i440fx_info);
 501 }
 502 device_init(i440fx_register);