qapi: add QMP dispatch functions
[qemu/mdroth.git] / hw / zaurus.c
blobc24aeb5763e36e9e1a2248b6c837861f8d4a44b8
1 /*
2 * Copyright (c) 2006-2008 Openedhand Ltd.
3 * Written by Andrzej Zaborowski <balrog@zabor.org>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 or
8 * (at your option) version 3 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
18 #include "hw.h"
19 #include "sharpsl.h"
20 #include "sysbus.h"
22 #undef REG_FMT
23 #define REG_FMT "0x%02lx"
25 /* SCOOP devices */
27 typedef struct ScoopInfo ScoopInfo;
28 struct ScoopInfo {
29 SysBusDevice busdev;
30 qemu_irq handler[16];
31 uint16_t status;
32 uint16_t power;
33 uint32_t gpio_level;
34 uint32_t gpio_dir;
35 uint32_t prev_level;
37 uint16_t mcr;
38 uint16_t cdr;
39 uint16_t ccr;
40 uint16_t irr;
41 uint16_t imr;
42 uint16_t isr;
45 #define SCOOP_MCR 0x00
46 #define SCOOP_CDR 0x04
47 #define SCOOP_CSR 0x08
48 #define SCOOP_CPR 0x0c
49 #define SCOOP_CCR 0x10
50 #define SCOOP_IRR_IRM 0x14
51 #define SCOOP_IMR 0x18
52 #define SCOOP_ISR 0x1c
53 #define SCOOP_GPCR 0x20
54 #define SCOOP_GPWR 0x24
55 #define SCOOP_GPRR 0x28
57 static inline void scoop_gpio_handler_update(ScoopInfo *s) {
58 uint32_t level, diff;
59 int bit;
60 level = s->gpio_level & s->gpio_dir;
62 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
63 bit = ffs(diff) - 1;
64 qemu_set_irq(s->handler[bit], (level >> bit) & 1);
67 s->prev_level = level;
70 static uint32_t scoop_readb(void *opaque, target_phys_addr_t addr)
72 ScoopInfo *s = (ScoopInfo *) opaque;
74 switch (addr & 0x3f) {
75 case SCOOP_MCR:
76 return s->mcr;
77 case SCOOP_CDR:
78 return s->cdr;
79 case SCOOP_CSR:
80 return s->status;
81 case SCOOP_CPR:
82 return s->power;
83 case SCOOP_CCR:
84 return s->ccr;
85 case SCOOP_IRR_IRM:
86 return s->irr;
87 case SCOOP_IMR:
88 return s->imr;
89 case SCOOP_ISR:
90 return s->isr;
91 case SCOOP_GPCR:
92 return s->gpio_dir;
93 case SCOOP_GPWR:
94 case SCOOP_GPRR:
95 return s->gpio_level;
96 default:
97 zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
100 return 0;
103 static void scoop_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
105 ScoopInfo *s = (ScoopInfo *) opaque;
106 value &= 0xffff;
108 switch (addr & 0x3f) {
109 case SCOOP_MCR:
110 s->mcr = value;
111 break;
112 case SCOOP_CDR:
113 s->cdr = value;
114 break;
115 case SCOOP_CPR:
116 s->power = value;
117 if (value & 0x80)
118 s->power |= 0x8040;
119 break;
120 case SCOOP_CCR:
121 s->ccr = value;
122 break;
123 case SCOOP_IRR_IRM:
124 s->irr = value;
125 break;
126 case SCOOP_IMR:
127 s->imr = value;
128 break;
129 case SCOOP_ISR:
130 s->isr = value;
131 break;
132 case SCOOP_GPCR:
133 s->gpio_dir = value;
134 scoop_gpio_handler_update(s);
135 break;
136 case SCOOP_GPWR:
137 case SCOOP_GPRR: /* GPRR is probably R/O in real HW */
138 s->gpio_level = value & s->gpio_dir;
139 scoop_gpio_handler_update(s);
140 break;
141 default:
142 zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
146 static CPUReadMemoryFunc * const scoop_readfn[] = {
147 scoop_readb,
148 scoop_readb,
149 scoop_readb,
151 static CPUWriteMemoryFunc * const scoop_writefn[] = {
152 scoop_writeb,
153 scoop_writeb,
154 scoop_writeb,
157 static void scoop_gpio_set(void *opaque, int line, int level)
159 ScoopInfo *s = (ScoopInfo *) opaque;
161 if (level)
162 s->gpio_level |= (1 << line);
163 else
164 s->gpio_level &= ~(1 << line);
167 static int scoop_init(SysBusDevice *dev)
169 ScoopInfo *s = FROM_SYSBUS(ScoopInfo, dev);
170 int iomemtype;
172 s->status = 0x02;
173 qdev_init_gpio_out(&s->busdev.qdev, s->handler, 16);
174 qdev_init_gpio_in(&s->busdev.qdev, scoop_gpio_set, 16);
175 iomemtype = cpu_register_io_memory(scoop_readfn,
176 scoop_writefn, s, DEVICE_NATIVE_ENDIAN);
178 sysbus_init_mmio(dev, 0x1000, iomemtype);
180 return 0;
183 static int scoop_post_load(void *opaque, int version_id)
185 ScoopInfo *s = (ScoopInfo *) opaque;
186 int i;
187 uint32_t level;
189 level = s->gpio_level & s->gpio_dir;
191 for (i = 0; i < 16; i++) {
192 qemu_set_irq(s->handler[i], (level >> i) & 1);
195 s->prev_level = level;
197 return 0;
200 static bool is_version_0 (void *opaque, int version_id)
202 return version_id == 0;
205 static const VMStateDescription vmstate_scoop_regs = {
206 .name = "scoop",
207 .version_id = 1,
208 .minimum_version_id = 0,
209 .minimum_version_id_old = 0,
210 .post_load = scoop_post_load,
211 .fields = (VMStateField []) {
212 VMSTATE_UINT16(status, ScoopInfo),
213 VMSTATE_UINT16(power, ScoopInfo),
214 VMSTATE_UINT32(gpio_level, ScoopInfo),
215 VMSTATE_UINT32(gpio_dir, ScoopInfo),
216 VMSTATE_UINT32(prev_level, ScoopInfo),
217 VMSTATE_UINT16(mcr, ScoopInfo),
218 VMSTATE_UINT16(cdr, ScoopInfo),
219 VMSTATE_UINT16(ccr, ScoopInfo),
220 VMSTATE_UINT16(irr, ScoopInfo),
221 VMSTATE_UINT16(imr, ScoopInfo),
222 VMSTATE_UINT16(isr, ScoopInfo),
223 VMSTATE_UNUSED_TEST(is_version_0, 2),
224 VMSTATE_END_OF_LIST(),
228 static SysBusDeviceInfo scoop_sysbus_info = {
229 .init = scoop_init,
230 .qdev.name = "scoop",
231 .qdev.desc = "Scoop2 Sharp custom ASIC",
232 .qdev.size = sizeof(ScoopInfo),
233 .qdev.vmsd = &vmstate_scoop_regs,
234 .qdev.props = (Property[]) {
235 DEFINE_PROP_END_OF_LIST(),
239 static void scoop_register(void)
241 sysbus_register_withprop(&scoop_sysbus_info);
243 device_init(scoop_register);
245 /* Write the bootloader parameters memory area. */
247 #define MAGIC_CHG(a, b, c, d) ((d << 24) | (c << 16) | (b << 8) | a)
249 static struct __attribute__ ((__packed__)) sl_param_info {
250 uint32_t comadj_keyword;
251 int32_t comadj;
253 uint32_t uuid_keyword;
254 char uuid[16];
256 uint32_t touch_keyword;
257 int32_t touch_xp;
258 int32_t touch_yp;
259 int32_t touch_xd;
260 int32_t touch_yd;
262 uint32_t adadj_keyword;
263 int32_t adadj;
265 uint32_t phad_keyword;
266 int32_t phadadj;
267 } zaurus_bootparam = {
268 .comadj_keyword = MAGIC_CHG('C', 'M', 'A', 'D'),
269 .comadj = 125,
270 .uuid_keyword = MAGIC_CHG('U', 'U', 'I', 'D'),
271 .uuid = { -1 },
272 .touch_keyword = MAGIC_CHG('T', 'U', 'C', 'H'),
273 .touch_xp = -1,
274 .adadj_keyword = MAGIC_CHG('B', 'V', 'A', 'D'),
275 .adadj = -1,
276 .phad_keyword = MAGIC_CHG('P', 'H', 'A', 'D'),
277 .phadadj = 0x01,
280 void sl_bootparam_write(target_phys_addr_t ptr)
282 cpu_physical_memory_write(ptr, (void *)&zaurus_bootparam,
283 sizeof(struct sl_param_info));