hw/pxa2xx_gpio.c

   1 /*
   2  * Intel XScale PXA255/270 GPIO controller emulation.
   3  *
   4  * Copyright (c) 2006 Openedhand Ltd.
   5  * Written by Andrzej Zaborowski <balrog@zabor.org>
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "hw.h"
  11 #include "sysbus.h"
  12 #include "pxa.h"
  13
  14 #define PXA2XX_GPIO_BANKS       4
  15
  16 typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
  17 struct PXA2xxGPIOInfo {
  18     SysBusDevice busdev;
  19     qemu_irq irq0, irq1, irqX;
  20     int lines;
  21     int ncpu;
  22     CPUState *cpu_env;
  23
  24     /* XXX: GNU C vectors are more suitable */
  25     uint32_t ilevel[PXA2XX_GPIO_BANKS];
  26     uint32_t olevel[PXA2XX_GPIO_BANKS];
  27     uint32_t dir[PXA2XX_GPIO_BANKS];
  28     uint32_t rising[PXA2XX_GPIO_BANKS];
  29     uint32_t falling[PXA2XX_GPIO_BANKS];
  30     uint32_t status[PXA2XX_GPIO_BANKS];
  31     uint32_t gpsr[PXA2XX_GPIO_BANKS];
  32     uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
  33
  34     uint32_t prev_level[PXA2XX_GPIO_BANKS];
  35     qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
  36     qemu_irq read_notify;
  37 };
  38
  39 static struct {
  40     enum {
  41         GPIO_NONE,
  42         GPLR,
  43         GPSR,
  44         GPCR,
  45         GPDR,
  46         GRER,
  47         GFER,
  48         GEDR,
  49         GAFR_L,
  50         GAFR_U,
  51     } reg;
  52     int bank;
  53 } pxa2xx_gpio_regs[0x200] = {
  54     [0 ... 0x1ff] = { GPIO_NONE, 0 },
  55 #define PXA2XX_REG(reg, a0, a1, a2, a3) \
  56     [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
  57
  58     PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
  59     PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
  60     PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
  61     PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
  62     PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
  63     PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
  64     PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
  65     PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
  66     PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
  67 };
  68
  69 static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
  70 {
  71     if (s->status[0] & (1 << 0))
  72         qemu_irq_raise(s->irq0);
  73     else
  74         qemu_irq_lower(s->irq0);
  75
  76     if (s->status[0] & (1 << 1))
  77         qemu_irq_raise(s->irq1);
  78     else
  79         qemu_irq_lower(s->irq1);
  80
  81     if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3])
  82         qemu_irq_raise(s->irqX);
  83     else
  84         qemu_irq_lower(s->irqX);
  85 }
  86
  87 /* Bitmap of pins used as standby and sleep wake-up sources.  */
  88 static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
  89     0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
  90 };
  91
  92 static void pxa2xx_gpio_set(void *opaque, int line, int level)
  93 {
  94     PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
  95     int bank;
  96     uint32_t mask;
  97
  98     if (line >= s->lines) {
  99         printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
 100         return;
 101     }
 102
 103     bank = line >> 5;
 104     mask = 1 << (line & 31);
 105
 106     if (level) {
 107         s->status[bank] |= s->rising[bank] & mask &
 108                 ~s->ilevel[bank] & ~s->dir[bank];
 109         s->ilevel[bank] |= mask;
 110     } else {
 111         s->status[bank] |= s->falling[bank] & mask &
 112                 s->ilevel[bank] & ~s->dir[bank];
 113         s->ilevel[bank] &= ~mask;
 114     }
 115
 116     if (s->status[bank] & mask)
 117         pxa2xx_gpio_irq_update(s);
 118
 119     /* Wake-up GPIOs */
 120     if (s->cpu_env->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank]))
 121         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_EXITTB);
 122 }
 123
 124 static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
 125     uint32_t level, diff;
 126     int i, bit, line;
 127     for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
 128         level = s->olevel[i] & s->dir[i];
 129
 130         for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
 131             bit = ffs(diff) - 1;
 132             line = bit + 32 * i;
 133             qemu_set_irq(s->handler[line], (level >> bit) & 1);
 134         }
 135
 136         s->prev_level[i] = level;
 137     }
 138 }
 139
 140 static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset)
 141 {
 142     PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
 143     uint32_t ret;
 144     int bank;
 145     if (offset >= 0x200)
 146         return 0;
 147
 148     bank = pxa2xx_gpio_regs[offset].bank;
 149     switch (pxa2xx_gpio_regs[offset].reg) {
 150     case GPDR:          /* GPIO Pin-Direction registers */
 151         return s->dir[bank];
 152
 153     case GPSR:          /* GPIO Pin-Output Set registers */
 154         printf("%s: Read from a write-only register " REG_FMT "\n",
 155                         __FUNCTION__, offset);
 156         return s->gpsr[bank];   /* Return last written value.  */
 157
 158     case GPCR:          /* GPIO Pin-Output Clear registers */
 159         printf("%s: Read from a write-only register " REG_FMT "\n",
 160                         __FUNCTION__, offset);
 161         return 31337;           /* Specified as unpredictable in the docs.  */
 162
 163     case GRER:          /* GPIO Rising-Edge Detect Enable registers */
 164         return s->rising[bank];
 165
 166     case GFER:          /* GPIO Falling-Edge Detect Enable registers */
 167         return s->falling[bank];
 168
 169     case GAFR_L:        /* GPIO Alternate Function registers */
 170         return s->gafr[bank * 2];
 171
 172     case GAFR_U:        /* GPIO Alternate Function registers */
 173         return s->gafr[bank * 2 + 1];
 174
 175     case GPLR:          /* GPIO Pin-Level registers */
 176         ret = (s->olevel[bank] & s->dir[bank]) |
 177                 (s->ilevel[bank] & ~s->dir[bank]);
 178         qemu_irq_raise(s->read_notify);
 179         return ret;
 180
 181     case GEDR:          /* GPIO Edge Detect Status registers */
 182         return s->status[bank];
 183
 184     default:
 185         hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
 186     }
 187
 188     return 0;
 189 }
 190
 191 static void pxa2xx_gpio_write(void *opaque,
 192                 target_phys_addr_t offset, uint32_t value)
 193 {
 194     PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
 195     int bank;
 196     if (offset >= 0x200)
 197         return;
 198
 199     bank = pxa2xx_gpio_regs[offset].bank;
 200     switch (pxa2xx_gpio_regs[offset].reg) {
 201     case GPDR:          /* GPIO Pin-Direction registers */
 202         s->dir[bank] = value;
 203         pxa2xx_gpio_handler_update(s);
 204         break;
 205
 206     case GPSR:          /* GPIO Pin-Output Set registers */
 207         s->olevel[bank] |= value;
 208         pxa2xx_gpio_handler_update(s);
 209         s->gpsr[bank] = value;
 210         break;
 211
 212     case GPCR:          /* GPIO Pin-Output Clear registers */
 213         s->olevel[bank] &= ~value;
 214         pxa2xx_gpio_handler_update(s);
 215         break;
 216
 217     case GRER:          /* GPIO Rising-Edge Detect Enable registers */
 218         s->rising[bank] = value;
 219         break;
 220
 221     case GFER:          /* GPIO Falling-Edge Detect Enable registers */
 222         s->falling[bank] = value;
 223         break;
 224
 225     case GAFR_L:        /* GPIO Alternate Function registers */
 226         s->gafr[bank * 2] = value;
 227         break;
 228
 229     case GAFR_U:        /* GPIO Alternate Function registers */
 230         s->gafr[bank * 2 + 1] = value;
 231         break;
 232
 233     case GEDR:          /* GPIO Edge Detect Status registers */
 234         s->status[bank] &= ~value;
 235         pxa2xx_gpio_irq_update(s);
 236         break;
 237
 238     default:
 239         hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
 240     }
 241 }
 242
 243 static CPUReadMemoryFunc * const pxa2xx_gpio_readfn[] = {
 244     pxa2xx_gpio_read,
 245     pxa2xx_gpio_read,
 246     pxa2xx_gpio_read
 247 };
 248
 249 static CPUWriteMemoryFunc * const pxa2xx_gpio_writefn[] = {
 250     pxa2xx_gpio_write,
 251     pxa2xx_gpio_write,
 252     pxa2xx_gpio_write
 253 };
 254
 255 DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
 256                 CPUState *env, qemu_irq *pic, int lines)
 257 {
 258     DeviceState *dev;
 259
 260     dev = qdev_create(NULL, "pxa2xx-gpio");
 261     qdev_prop_set_int32(dev, "lines", lines);
 262     qdev_prop_set_int32(dev, "ncpu", env->cpu_index);
 263     qdev_init_nofail(dev);
 264
 265     sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
 266     sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[PXA2XX_PIC_GPIO_0]);
 267     sysbus_connect_irq(sysbus_from_qdev(dev), 1, pic[PXA2XX_PIC_GPIO_1]);
 268     sysbus_connect_irq(sysbus_from_qdev(dev), 2, pic[PXA2XX_PIC_GPIO_X]);
 269
 270     return dev;
 271 }
 272
 273 static int pxa2xx_gpio_initfn(SysBusDevice *dev)
 274 {
 275     int iomemtype;
 276     PXA2xxGPIOInfo *s;
 277
 278     s = FROM_SYSBUS(PXA2xxGPIOInfo, dev);
 279
 280     s->cpu_env = qemu_get_cpu(s->ncpu);
 281
 282     qdev_init_gpio_in(&dev->qdev, pxa2xx_gpio_set, s->lines);
 283     qdev_init_gpio_out(&dev->qdev, s->handler, s->lines);
 284
 285     iomemtype = cpu_register_io_memory(pxa2xx_gpio_readfn,
 286                     pxa2xx_gpio_writefn, s, DEVICE_NATIVE_ENDIAN);
 287
 288     sysbus_init_mmio(dev, 0x1000, iomemtype);
 289     sysbus_init_irq(dev, &s->irq0);
 290     sysbus_init_irq(dev, &s->irq1);
 291     sysbus_init_irq(dev, &s->irqX);
 292
 293     return 0;
 294 }
 295
 296 /*
 297  * Registers a callback to notify on GPLR reads.  This normally
 298  * shouldn't be needed but it is used for the hack on Spitz machines.
 299  */
 300 void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
 301 {
 302     PXA2xxGPIOInfo *s = FROM_SYSBUS(PXA2xxGPIOInfo, sysbus_from_qdev(dev));
 303     s->read_notify = handler;
 304 }
 305
 306 static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
 307     .name = "pxa2xx-gpio",
 308     .version_id = 1,
 309     .minimum_version_id = 1,
 310     .minimum_version_id_old = 1,
 311     .fields = (VMStateField []) {
 312         VMSTATE_INT32(lines, PXA2xxGPIOInfo),
 313         VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
 314         VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
 315         VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
 316         VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
 317         VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
 318         VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
 319         VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
 320         VMSTATE_END_OF_LIST(),
 321     },
 322 };
 323
 324 static SysBusDeviceInfo pxa2xx_gpio_info = {
 325     .init       = pxa2xx_gpio_initfn,
 326     .qdev.name  = "pxa2xx-gpio",
 327     .qdev.desc  = "PXA2xx GPIO controller",
 328     .qdev.size  = sizeof(PXA2xxGPIOInfo),
 329     .qdev.props = (Property []) {
 330         DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
 331         DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0),
 332         DEFINE_PROP_END_OF_LIST(),
 333     }
 334 };
 335
 336 static void pxa2xx_gpio_register(void)
 337 {
 338     sysbus_register_withprop(&pxa2xx_gpio_info);
 339 }
 340 device_init(pxa2xx_gpio_register);