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spice/qxl: zap spice 0.4 migration compatibility bits
[qemu/mdroth.git] / target-cris / translate.c
blobf4cc1252a5a484197b4fa7582cad8e7e4d632498
1 /*
2 * CRIS emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /*
22 * FIXME:
23 * The condition code translation is in need of attention.
24 */
25
26 #include <stdarg.h>
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <string.h>
30 #include <inttypes.h>
31
32 #include "cpu.h"
33 #include "exec-all.h"
34 #include "disas.h"
35 #include "tcg-op.h"
36 #include "helper.h"
37 #include "mmu.h"
38 #include "crisv32-decode.h"
39 #include "qemu-common.h"
40
41 #define GEN_HELPER 1
42 #include "helper.h"
43
44 #define DISAS_CRIS 0
45 #if DISAS_CRIS
46 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
47 #else
48 # define LOG_DIS(...) do { } while (0)
49 #endif
50
51 #define D(x)
52 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
53 #define BUG_ON(x) ({if (x) BUG();})
54
55 #define DISAS_SWI 5
56
57 /* Used by the decoder. */
58 #define EXTRACT_FIELD(src, start, end) \
59 (((src) >> start) & ((1 << (end - start + 1)) - 1))
60
61 #define CC_MASK_NZ 0xc
62 #define CC_MASK_NZV 0xe
63 #define CC_MASK_NZVC 0xf
64 #define CC_MASK_RNZV 0x10e
65
66 static TCGv_ptr cpu_env;
67 static TCGv cpu_R[16];
68 static TCGv cpu_PR[16];
69 static TCGv cc_x;
70 static TCGv cc_src;
71 static TCGv cc_dest;
72 static TCGv cc_result;
73 static TCGv cc_op;
74 static TCGv cc_size;
75 static TCGv cc_mask;
76
77 static TCGv env_btaken;
78 static TCGv env_btarget;
79 static TCGv env_pc;
80
81 #include "gen-icount.h"
82
83 /* This is the state at translation time. */
84 typedef struct DisasContext {
85 CPUState *env;
86 target_ulong pc, ppc;
87
88 /* Decoder. */
89 unsigned int (*decoder)(struct DisasContext *dc);
90 uint32_t ir;
91 uint32_t opcode;
92 unsigned int op1;
93 unsigned int op2;
94 unsigned int zsize, zzsize;
95 unsigned int mode;
96 unsigned int postinc;
97
98 unsigned int size;
99 unsigned int src;
100 unsigned int dst;
101 unsigned int cond;
102
103 int update_cc;
104 int cc_op;
105 int cc_size;
106 uint32_t cc_mask;
107
108 int cc_size_uptodate; /* -1 invalid or last written value. */
109
110 int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not uptodate. */
111 int flags_uptodate; /* Wether or not $ccs is uptodate. */
112 int flagx_known; /* Wether or not flags_x has the x flag known at
113 translation time. */
114 int flags_x;
115
116 int clear_x; /* Clear x after this insn? */
117 int clear_prefix; /* Clear prefix after this insn? */
118 int clear_locked_irq; /* Clear the irq lockout. */
119 int cpustate_changed;
120 unsigned int tb_flags; /* tb dependent flags. */
121 int is_jmp;
122
123 #define JMP_NOJMP 0
124 #define JMP_DIRECT 1
125 #define JMP_DIRECT_CC 2
126 #define JMP_INDIRECT 3
127 int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
128 uint32_t jmp_pc;
129
130 int delayed_branch;
131
132 struct TranslationBlock *tb;
133 int singlestep_enabled;
134 } DisasContext;
135
136 static void gen_BUG(DisasContext *dc, const char *file, int line)
137 {
138 printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);
139 qemu_log("BUG: pc=%x %s %d\n", dc->pc, file, line);
140 cpu_abort(dc->env, "%s:%d\n", file, line);
141 }
142
143 static const char *regnames[] =
144 {
145 "$r0", "$r1", "$r2", "$r3",
146 "$r4", "$r5", "$r6", "$r7",
147 "$r8", "$r9", "$r10", "$r11",
148 "$r12", "$r13", "$sp", "$acr",
149 };
150 static const char *pregnames[] =
151 {
152 "$bz", "$vr", "$pid", "$srs",
153 "$wz", "$exs", "$eda", "$mof",
154 "$dz", "$ebp", "$erp", "$srp",
155 "$nrp", "$ccs", "$usp", "$spc",
156 };
157
158 /* We need this table to handle preg-moves with implicit width. */
159 static int preg_sizes[] = {
160 1, /* bz. */
161 1, /* vr. */
162 4, /* pid. */
163 1, /* srs. */
164 2, /* wz. */
165 4, 4, 4,
166 4, 4, 4, 4,
167 4, 4, 4, 4,
168 };
169
170 #define t_gen_mov_TN_env(tn, member) \
171 _t_gen_mov_TN_env((tn), offsetof(CPUState, member))
172 #define t_gen_mov_env_TN(member, tn) \
173 _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))
174
175 static inline void t_gen_mov_TN_reg(TCGv tn, int r)
176 {
177 if (r < 0 || r > 15)
178 fprintf(stderr, "wrong register read $r%d\n", r);
179 tcg_gen_mov_tl(tn, cpu_R[r]);
180 }
181 static inline void t_gen_mov_reg_TN(int r, TCGv tn)
182 {
183 if (r < 0 || r > 15)
184 fprintf(stderr, "wrong register write $r%d\n", r);
185 tcg_gen_mov_tl(cpu_R[r], tn);
186 }
187
188 static inline void _t_gen_mov_TN_env(TCGv tn, int offset)
189 {
190 if (offset > sizeof (CPUState))
191 fprintf(stderr, "wrong load from env from off=%d\n", offset);
192 tcg_gen_ld_tl(tn, cpu_env, offset);
193 }
194 static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
195 {
196 if (offset > sizeof (CPUState))
197 fprintf(stderr, "wrong store to env at off=%d\n", offset);
198 tcg_gen_st_tl(tn, cpu_env, offset);
199 }
200
201 static inline void t_gen_mov_TN_preg(TCGv tn, int r)
202 {
203 if (r < 0 || r > 15)
204 fprintf(stderr, "wrong register read $p%d\n", r);
205 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
206 tcg_gen_mov_tl(tn, tcg_const_tl(0));
207 else if (r == PR_VR)
208 tcg_gen_mov_tl(tn, tcg_const_tl(32));
209 else
210 tcg_gen_mov_tl(tn, cpu_PR[r]);
211 }
212 static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
213 {
214 if (r < 0 || r > 15)
215 fprintf(stderr, "wrong register write $p%d\n", r);
216 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
217 return;
218 else if (r == PR_SRS)
219 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
220 else {
221 if (r == PR_PID)
222 gen_helper_tlb_flush_pid(tn);
223 if (dc->tb_flags & S_FLAG && r == PR_SPC)
224 gen_helper_spc_write(tn);
225 else if (r == PR_CCS)
226 dc->cpustate_changed = 1;
227 tcg_gen_mov_tl(cpu_PR[r], tn);
228 }
229 }
230
231 /* Sign extend at translation time. */
232 static int sign_extend(unsigned int val, unsigned int width)
233 {
234 int sval;
235
236 /* LSL. */
237 val <<= 31 - width;
238 sval = val;
239 /* ASR. */
240 sval >>= 31 - width;
241 return sval;
242 }
243
244 static int cris_fetch(DisasContext *dc, uint32_t addr,
245 unsigned int size, unsigned int sign)
246 {
247 int r;
248
249 switch (size) {
250 case 4:
251 {
252 r = ldl_code(addr);
253 break;
254 }
255 case 2:
256 {
257 if (sign) {
258 r = ldsw_code(addr);
259 } else {
260 r = lduw_code(addr);
261 }
262 break;
263 }
264 case 1:
265 {
266 if (sign) {
267 r = ldsb_code(addr);
268 } else {
269 r = ldub_code(addr);
270 }
271 break;
272 }
273 default:
274 cpu_abort(dc->env, "Invalid fetch size %d\n", size);
275 break;
276 }
277 return r;
278 }
279
280 static void cris_lock_irq(DisasContext *dc)
281 {
282 dc->clear_locked_irq = 0;
283 t_gen_mov_env_TN(locked_irq, tcg_const_tl(1));
284 }
285
286 static inline void t_gen_raise_exception(uint32_t index)
287 {
288 TCGv_i32 tmp = tcg_const_i32(index);
289 gen_helper_raise_exception(tmp);
290 tcg_temp_free_i32(tmp);
291 }
292
293 static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
294 {
295 TCGv t0, t_31;
296
297 t0 = tcg_temp_new();
298 t_31 = tcg_const_tl(31);
299 tcg_gen_shl_tl(d, a, b);
300
301 tcg_gen_sub_tl(t0, t_31, b);
302 tcg_gen_sar_tl(t0, t0, t_31);
303 tcg_gen_and_tl(t0, t0, d);
304 tcg_gen_xor_tl(d, d, t0);
305 tcg_temp_free(t0);
306 tcg_temp_free(t_31);
307 }
308
309 static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
310 {
311 TCGv t0, t_31;
312
313 t0 = tcg_temp_new();
314 t_31 = tcg_temp_new();
315 tcg_gen_shr_tl(d, a, b);
316
317 tcg_gen_movi_tl(t_31, 31);
318 tcg_gen_sub_tl(t0, t_31, b);
319 tcg_gen_sar_tl(t0, t0, t_31);
320 tcg_gen_and_tl(t0, t0, d);
321 tcg_gen_xor_tl(d, d, t0);
322 tcg_temp_free(t0);
323 tcg_temp_free(t_31);
324 }
325
326 static void t_gen_asr(TCGv d, TCGv a, TCGv b)
327 {
328 TCGv t0, t_31;
329
330 t0 = tcg_temp_new();
331 t_31 = tcg_temp_new();
332 tcg_gen_sar_tl(d, a, b);
333
334 tcg_gen_movi_tl(t_31, 31);
335 tcg_gen_sub_tl(t0, t_31, b);
336 tcg_gen_sar_tl(t0, t0, t_31);
337 tcg_gen_or_tl(d, d, t0);
338 tcg_temp_free(t0);
339 tcg_temp_free(t_31);
340 }
341
342 /* 64-bit signed mul, lower result in d and upper in d2. */
343 static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
344 {
345 TCGv_i64 t0, t1;
346
347 t0 = tcg_temp_new_i64();
348 t1 = tcg_temp_new_i64();
349
350 tcg_gen_ext_i32_i64(t0, a);
351 tcg_gen_ext_i32_i64(t1, b);
352 tcg_gen_mul_i64(t0, t0, t1);
353
354 tcg_gen_trunc_i64_i32(d, t0);
355 tcg_gen_shri_i64(t0, t0, 32);
356 tcg_gen_trunc_i64_i32(d2, t0);
357
358 tcg_temp_free_i64(t0);
359 tcg_temp_free_i64(t1);
360 }
361
362 /* 64-bit unsigned muls, lower result in d and upper in d2. */
363 static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
364 {
365 TCGv_i64 t0, t1;
366
367 t0 = tcg_temp_new_i64();
368 t1 = tcg_temp_new_i64();
369
370 tcg_gen_extu_i32_i64(t0, a);
371 tcg_gen_extu_i32_i64(t1, b);
372 tcg_gen_mul_i64(t0, t0, t1);
373
374 tcg_gen_trunc_i64_i32(d, t0);
375 tcg_gen_shri_i64(t0, t0, 32);
376 tcg_gen_trunc_i64_i32(d2, t0);
377
378 tcg_temp_free_i64(t0);
379 tcg_temp_free_i64(t1);
380 }
381
382 static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
383 {
384 int l1;
385
386 l1 = gen_new_label();
387
388 /*
389 * d <<= 1
390 * if (d >= s)
391 * d -= s;
392 */
393 tcg_gen_shli_tl(d, a, 1);
394 tcg_gen_brcond_tl(TCG_COND_LTU, d, b, l1);
395 tcg_gen_sub_tl(d, d, b);
396 gen_set_label(l1);
397 }
398
399 static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv ccs)
400 {
401 TCGv t;
402
403 /*
404 * d <<= 1
405 * if (n)
406 * d += s;
407 */
408 t = tcg_temp_new();
409 tcg_gen_shli_tl(d, a, 1);
410 tcg_gen_shli_tl(t, ccs, 31 - 3);
411 tcg_gen_sari_tl(t, t, 31);
412 tcg_gen_and_tl(t, t, b);
413 tcg_gen_add_tl(d, d, t);
414 tcg_temp_free(t);
415 }
416
417 /* Extended arithmetics on CRIS. */
418 static inline void t_gen_add_flag(TCGv d, int flag)
419 {
420 TCGv c;
421
422 c = tcg_temp_new();
423 t_gen_mov_TN_preg(c, PR_CCS);
424 /* Propagate carry into d. */
425 tcg_gen_andi_tl(c, c, 1 << flag);
426 if (flag)
427 tcg_gen_shri_tl(c, c, flag);
428 tcg_gen_add_tl(d, d, c);
429 tcg_temp_free(c);
430 }
431
432 static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
433 {
434 if (dc->flagx_known) {
435 if (dc->flags_x) {
436 TCGv c;
437
438 c = tcg_temp_new();
439 t_gen_mov_TN_preg(c, PR_CCS);
440 /* C flag is already at bit 0. */
441 tcg_gen_andi_tl(c, c, C_FLAG);
442 tcg_gen_add_tl(d, d, c);
443 tcg_temp_free(c);
444 }
445 } else {
446 TCGv x, c;
447
448 x = tcg_temp_new();
449 c = tcg_temp_new();
450 t_gen_mov_TN_preg(x, PR_CCS);
451 tcg_gen_mov_tl(c, x);
452
453 /* Propagate carry into d if X is set. Branch free. */
454 tcg_gen_andi_tl(c, c, C_FLAG);
455 tcg_gen_andi_tl(x, x, X_FLAG);
456 tcg_gen_shri_tl(x, x, 4);
457
458 tcg_gen_and_tl(x, x, c);
459 tcg_gen_add_tl(d, d, x);
460 tcg_temp_free(x);
461 tcg_temp_free(c);
462 }
463 }
464
465 static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
466 {
467 if (dc->flagx_known) {
468 if (dc->flags_x) {
469 TCGv c;
470
471 c = tcg_temp_new();
472 t_gen_mov_TN_preg(c, PR_CCS);
473 /* C flag is already at bit 0. */
474 tcg_gen_andi_tl(c, c, C_FLAG);
475 tcg_gen_sub_tl(d, d, c);
476 tcg_temp_free(c);
477 }
478 } else {
479 TCGv x, c;
480
481 x = tcg_temp_new();
482 c = tcg_temp_new();
483 t_gen_mov_TN_preg(x, PR_CCS);
484 tcg_gen_mov_tl(c, x);
485
486 /* Propagate carry into d if X is set. Branch free. */
487 tcg_gen_andi_tl(c, c, C_FLAG);
488 tcg_gen_andi_tl(x, x, X_FLAG);
489 tcg_gen_shri_tl(x, x, 4);
490
491 tcg_gen_and_tl(x, x, c);
492 tcg_gen_sub_tl(d, d, x);
493 tcg_temp_free(x);
494 tcg_temp_free(c);
495 }
496 }
497
498 /* Swap the two bytes within each half word of the s operand.
499 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
500 static inline void t_gen_swapb(TCGv d, TCGv s)
501 {
502 TCGv t, org_s;
503
504 t = tcg_temp_new();
505 org_s = tcg_temp_new();
506
507 /* d and s may refer to the same object. */
508 tcg_gen_mov_tl(org_s, s);
509 tcg_gen_shli_tl(t, org_s, 8);
510 tcg_gen_andi_tl(d, t, 0xff00ff00);
511 tcg_gen_shri_tl(t, org_s, 8);
512 tcg_gen_andi_tl(t, t, 0x00ff00ff);
513 tcg_gen_or_tl(d, d, t);
514 tcg_temp_free(t);
515 tcg_temp_free(org_s);
516 }
517
518 /* Swap the halfwords of the s operand. */
519 static inline void t_gen_swapw(TCGv d, TCGv s)
520 {
521 TCGv t;
522 /* d and s refer the same object. */
523 t = tcg_temp_new();
524 tcg_gen_mov_tl(t, s);
525 tcg_gen_shli_tl(d, t, 16);
526 tcg_gen_shri_tl(t, t, 16);
527 tcg_gen_or_tl(d, d, t);
528 tcg_temp_free(t);
529 }
530
531 /* Reverse the within each byte.
532 T0 = (((T0 << 7) & 0x80808080) |
533 ((T0 << 5) & 0x40404040) |
534 ((T0 << 3) & 0x20202020) |
535 ((T0 << 1) & 0x10101010) |
536 ((T0 >> 1) & 0x08080808) |
537 ((T0 >> 3) & 0x04040404) |
538 ((T0 >> 5) & 0x02020202) |
539 ((T0 >> 7) & 0x01010101));
540 */
541 static inline void t_gen_swapr(TCGv d, TCGv s)
542 {
543 struct {
544 int shift; /* LSL when positive, LSR when negative. */
545 uint32_t mask;
546 } bitrev [] = {
547 {7, 0x80808080},
548 {5, 0x40404040},
549 {3, 0x20202020},
550 {1, 0x10101010},
551 {-1, 0x08080808},
552 {-3, 0x04040404},
553 {-5, 0x02020202},
554 {-7, 0x01010101}
555 };
556 int i;
557 TCGv t, org_s;
558
559 /* d and s refer the same object. */
560 t = tcg_temp_new();
561 org_s = tcg_temp_new();
562 tcg_gen_mov_tl(org_s, s);
563
564 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
565 tcg_gen_andi_tl(d, t, bitrev[0].mask);
566 for (i = 1; i < ARRAY_SIZE(bitrev); i++) {
567 if (bitrev[i].shift >= 0) {
568 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
569 } else {
570 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
571 }
572 tcg_gen_andi_tl(t, t, bitrev[i].mask);
573 tcg_gen_or_tl(d, d, t);
574 }
575 tcg_temp_free(t);
576 tcg_temp_free(org_s);
577 }
578
579 static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
580 {
581 int l1;
582
583 l1 = gen_new_label();
584
585 /* Conditional jmp. */
586 tcg_gen_mov_tl(env_pc, pc_false);
587 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
588 tcg_gen_mov_tl(env_pc, pc_true);
589 gen_set_label(l1);
590 }
591
592 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
593 {
594 TranslationBlock *tb;
595 tb = dc->tb;
596 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
597 tcg_gen_goto_tb(n);
598 tcg_gen_movi_tl(env_pc, dest);
599 tcg_gen_exit_tb((long)tb + n);
600 } else {
601 tcg_gen_movi_tl(env_pc, dest);
602 tcg_gen_exit_tb(0);
603 }
604 }
605
606 static inline void cris_clear_x_flag(DisasContext *dc)
607 {
608 if (dc->flagx_known && dc->flags_x)
609 dc->flags_uptodate = 0;
610
611 dc->flagx_known = 1;
612 dc->flags_x = 0;
613 }
614
615 static void cris_flush_cc_state(DisasContext *dc)
616 {
617 if (dc->cc_size_uptodate != dc->cc_size) {
618 tcg_gen_movi_tl(cc_size, dc->cc_size);
619 dc->cc_size_uptodate = dc->cc_size;
620 }
621 tcg_gen_movi_tl(cc_op, dc->cc_op);
622 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
623 }
624
625 static void cris_evaluate_flags(DisasContext *dc)
626 {
627 if (dc->flags_uptodate)
628 return;
629
630 cris_flush_cc_state(dc);
631
632 switch (dc->cc_op)
633 {
634 case CC_OP_MCP:
635 gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS],
636 cpu_PR[PR_CCS], cc_src,
637 cc_dest, cc_result);
638 break;
639 case CC_OP_MULS:
640 gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS],
641 cpu_PR[PR_CCS], cc_result,
642 cpu_PR[PR_MOF]);
643 break;
644 case CC_OP_MULU:
645 gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS],
646 cpu_PR[PR_CCS], cc_result,
647 cpu_PR[PR_MOF]);
648 break;
649 case CC_OP_MOVE:
650 case CC_OP_AND:
651 case CC_OP_OR:
652 case CC_OP_XOR:
653 case CC_OP_ASR:
654 case CC_OP_LSR:
655 case CC_OP_LSL:
656 switch (dc->cc_size)
657 {
658 case 4:
659 gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
660 cpu_PR[PR_CCS], cc_result);
661 break;
662 case 2:
663 gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
664 cpu_PR[PR_CCS], cc_result);
665 break;
666 default:
667 gen_helper_evaluate_flags();
668 break;
669 }
670 break;
671 case CC_OP_FLAGS:
672 /* live. */
673 break;
674 case CC_OP_SUB:
675 case CC_OP_CMP:
676 if (dc->cc_size == 4)
677 gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS],
678 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
679 else
680 gen_helper_evaluate_flags();
681
682 break;
683 default:
684 switch (dc->cc_size)
685 {
686 case 4:
687 gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS],
688 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
689 break;
690 default:
691 gen_helper_evaluate_flags();
692 break;
693 }
694 break;
695 }
696
697 if (dc->flagx_known) {
698 if (dc->flags_x)
699 tcg_gen_ori_tl(cpu_PR[PR_CCS],
700 cpu_PR[PR_CCS], X_FLAG);
701 else if (dc->cc_op == CC_OP_FLAGS)
702 tcg_gen_andi_tl(cpu_PR[PR_CCS],
703 cpu_PR[PR_CCS], ~X_FLAG);
704 }
705 dc->flags_uptodate = 1;
706 }
707
708 static void cris_cc_mask(DisasContext *dc, unsigned int mask)
709 {
710 uint32_t ovl;
711
712 if (!mask) {
713 dc->update_cc = 0;
714 return;
715 }
716
717 /* Check if we need to evaluate the condition codes due to
718 CC overlaying. */
719 ovl = (dc->cc_mask ^ mask) & ~mask;
720 if (ovl) {
721 /* TODO: optimize this case. It trigs all the time. */
722 cris_evaluate_flags (dc);
723 }
724 dc->cc_mask = mask;
725 dc->update_cc = 1;
726 }
727
728 static void cris_update_cc_op(DisasContext *dc, int op, int size)
729 {
730 dc->cc_op = op;
731 dc->cc_size = size;
732 dc->flags_uptodate = 0;
733 }
734
735 static inline void cris_update_cc_x(DisasContext *dc)
736 {
737 /* Save the x flag state at the time of the cc snapshot. */
738 if (dc->flagx_known) {
739 if (dc->cc_x_uptodate == (2 | dc->flags_x))
740 return;
741 tcg_gen_movi_tl(cc_x, dc->flags_x);
742 dc->cc_x_uptodate = 2 | dc->flags_x;
743 }
744 else {
745 tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);
746 dc->cc_x_uptodate = 1;
747 }
748 }
749
750 /* Update cc prior to executing ALU op. Needs source operands untouched. */
751 static void cris_pre_alu_update_cc(DisasContext *dc, int op,
752 TCGv dst, TCGv src, int size)
753 {
754 if (dc->update_cc) {
755 cris_update_cc_op(dc, op, size);
756 tcg_gen_mov_tl(cc_src, src);
757
758 if (op != CC_OP_MOVE
759 && op != CC_OP_AND
760 && op != CC_OP_OR
761 && op != CC_OP_XOR
762 && op != CC_OP_ASR
763 && op != CC_OP_LSR
764 && op != CC_OP_LSL)
765 tcg_gen_mov_tl(cc_dest, dst);
766
767 cris_update_cc_x(dc);
768 }
769 }
770
771 /* Update cc after executing ALU op. needs the result. */
772 static inline void cris_update_result(DisasContext *dc, TCGv res)
773 {
774 if (dc->update_cc)
775 tcg_gen_mov_tl(cc_result, res);
776 }
777
778 /* Returns one if the write back stage should execute. */
779 static void cris_alu_op_exec(DisasContext *dc, int op,
780 TCGv dst, TCGv a, TCGv b, int size)
781 {
782 /* Emit the ALU insns. */
783 switch (op)
784 {
785 case CC_OP_ADD:
786 tcg_gen_add_tl(dst, a, b);
787 /* Extended arithmetics. */
788 t_gen_addx_carry(dc, dst);
789 break;
790 case CC_OP_ADDC:
791 tcg_gen_add_tl(dst, a, b);
792 t_gen_add_flag(dst, 0); /* C_FLAG. */
793 break;
794 case CC_OP_MCP:
795 tcg_gen_add_tl(dst, a, b);
796 t_gen_add_flag(dst, 8); /* R_FLAG. */
797 break;
798 case CC_OP_SUB:
799 tcg_gen_sub_tl(dst, a, b);
800 /* Extended arithmetics. */
801 t_gen_subx_carry(dc, dst);
802 break;
803 case CC_OP_MOVE:
804 tcg_gen_mov_tl(dst, b);
805 break;
806 case CC_OP_OR:
807 tcg_gen_or_tl(dst, a, b);
808 break;
809 case CC_OP_AND:
810 tcg_gen_and_tl(dst, a, b);
811 break;
812 case CC_OP_XOR:
813 tcg_gen_xor_tl(dst, a, b);
814 break;
815 case CC_OP_LSL:
816 t_gen_lsl(dst, a, b);
817 break;
818 case CC_OP_LSR:
819 t_gen_lsr(dst, a, b);
820 break;
821 case CC_OP_ASR:
822 t_gen_asr(dst, a, b);
823 break;
824 case CC_OP_NEG:
825 tcg_gen_neg_tl(dst, b);
826 /* Extended arithmetics. */
827 t_gen_subx_carry(dc, dst);
828 break;
829 case CC_OP_LZ:
830 gen_helper_lz(dst, b);
831 break;
832 case CC_OP_MULS:
833 t_gen_muls(dst, cpu_PR[PR_MOF], a, b);
834 break;
835 case CC_OP_MULU:
836 t_gen_mulu(dst, cpu_PR[PR_MOF], a, b);
837 break;
838 case CC_OP_DSTEP:
839 t_gen_cris_dstep(dst, a, b);
840 break;
841 case CC_OP_MSTEP:
842 t_gen_cris_mstep(dst, a, b, cpu_PR[PR_CCS]);
843 break;
844 case CC_OP_BOUND:
845 {
846 int l1;
847 l1 = gen_new_label();
848 tcg_gen_mov_tl(dst, a);
849 tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1);
850 tcg_gen_mov_tl(dst, b);
851 gen_set_label(l1);
852 }
853 break;
854 case CC_OP_CMP:
855 tcg_gen_sub_tl(dst, a, b);
856 /* Extended arithmetics. */
857 t_gen_subx_carry(dc, dst);
858 break;
859 default:
860 qemu_log("illegal ALU op.\n");
861 BUG();
862 break;
863 }
864
865 if (size == 1)
866 tcg_gen_andi_tl(dst, dst, 0xff);
867 else if (size == 2)
868 tcg_gen_andi_tl(dst, dst, 0xffff);
869 }
870
871 static void cris_alu(DisasContext *dc, int op,
872 TCGv d, TCGv op_a, TCGv op_b, int size)
873 {
874 TCGv tmp;
875 int writeback;
876
877 writeback = 1;
878
879 if (op == CC_OP_CMP) {
880 tmp = tcg_temp_new();
881 writeback = 0;
882 } else if (size == 4) {
883 tmp = d;
884 writeback = 0;
885 } else
886 tmp = tcg_temp_new();
887
888
889 cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
890 cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
891 cris_update_result(dc, tmp);
892
893 /* Writeback. */
894 if (writeback) {
895 if (size == 1)
896 tcg_gen_andi_tl(d, d, ~0xff);
897 else
898 tcg_gen_andi_tl(d, d, ~0xffff);
899 tcg_gen_or_tl(d, d, tmp);
900 }
901 if (!TCGV_EQUAL(tmp, d))
902 tcg_temp_free(tmp);
903 }
904
905 static int arith_cc(DisasContext *dc)
906 {
907 if (dc->update_cc) {
908 switch (dc->cc_op) {
909 case CC_OP_ADDC: return 1;
910 case CC_OP_ADD: return 1;
911 case CC_OP_SUB: return 1;
912 case CC_OP_DSTEP: return 1;
913 case CC_OP_LSL: return 1;
914 case CC_OP_LSR: return 1;
915 case CC_OP_ASR: return 1;
916 case CC_OP_CMP: return 1;
917 case CC_OP_NEG: return 1;
918 case CC_OP_OR: return 1;
919 case CC_OP_AND: return 1;
920 case CC_OP_XOR: return 1;
921 case CC_OP_MULU: return 1;
922 case CC_OP_MULS: return 1;
923 default:
924 return 0;
925 }
926 }
927 return 0;
928 }
929
930 static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond)
931 {
932 int arith_opt, move_opt;
933
934 /* TODO: optimize more condition codes. */
935
936 /*
937 * If the flags are live, we've gotta look into the bits of CCS.
938 * Otherwise, if we just did an arithmetic operation we try to
939 * evaluate the condition code faster.
940 *
941 * When this function is done, T0 should be non-zero if the condition
942 * code is true.
943 */
944 arith_opt = arith_cc(dc) && !dc->flags_uptodate;
945 move_opt = (dc->cc_op == CC_OP_MOVE);
946 switch (cond) {
947 case CC_EQ:
948 if ((arith_opt || move_opt)
949 && dc->cc_x_uptodate != (2 | X_FLAG)) {
950 /* If cc_result is zero, T0 should be
951 non-zero otherwise T0 should be zero. */
952 int l1;
953 l1 = gen_new_label();
954 tcg_gen_movi_tl(cc, 0);
955 tcg_gen_brcondi_tl(TCG_COND_NE, cc_result,
956 0, l1);
957 tcg_gen_movi_tl(cc, 1);
958 gen_set_label(l1);
959 }
960 else {
961 cris_evaluate_flags(dc);
962 tcg_gen_andi_tl(cc,
963 cpu_PR[PR_CCS], Z_FLAG);
964 }
965 break;
966 case CC_NE:
967 if ((arith_opt || move_opt)
968 && dc->cc_x_uptodate != (2 | X_FLAG)) {
969 tcg_gen_mov_tl(cc, cc_result);
970 } else {
971 cris_evaluate_flags(dc);
972 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
973 Z_FLAG);
974 tcg_gen_andi_tl(cc, cc, Z_FLAG);
975 }
976 break;
977 case CC_CS:
978 cris_evaluate_flags(dc);
979 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG);
980 break;
981 case CC_CC:
982 cris_evaluate_flags(dc);
983 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG);
984 tcg_gen_andi_tl(cc, cc, C_FLAG);
985 break;
986 case CC_VS:
987 cris_evaluate_flags(dc);
988 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG);
989 break;
990 case CC_VC:
991 cris_evaluate_flags(dc);
992 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
993 V_FLAG);
994 tcg_gen_andi_tl(cc, cc, V_FLAG);
995 break;
996 case CC_PL:
997 if (arith_opt || move_opt) {
998 int bits = 31;
999
1000 if (dc->cc_size == 1)
1001 bits = 7;
1002 else if (dc->cc_size == 2)
1003 bits = 15;
1004
1005 tcg_gen_shri_tl(cc, cc_result, bits);
1006 tcg_gen_xori_tl(cc, cc, 1);
1007 } else {
1008 cris_evaluate_flags(dc);
1009 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
1010 N_FLAG);
1011 tcg_gen_andi_tl(cc, cc, N_FLAG);
1012 }
1013 break;
1014 case CC_MI:
1015 if (arith_opt || move_opt) {
1016 int bits = 31;
1017
1018 if (dc->cc_size == 1)
1019 bits = 7;
1020 else if (dc->cc_size == 2)
1021 bits = 15;
1022
1023 tcg_gen_shri_tl(cc, cc_result, bits);
1024 tcg_gen_andi_tl(cc, cc, 1);
1025 }
1026 else {
1027 cris_evaluate_flags(dc);
1028 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
1029 N_FLAG);
1030 }
1031 break;
1032 case CC_LS:
1033 cris_evaluate_flags(dc);
1034 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
1035 C_FLAG | Z_FLAG);
1036 break;
1037 case CC_HI:
1038 cris_evaluate_flags(dc);
1039 {
1040 TCGv tmp;
1041
1042 tmp = tcg_temp_new();
1043 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
1044 C_FLAG | Z_FLAG);
1045 /* Overlay the C flag on top of the Z. */
1046 tcg_gen_shli_tl(cc, tmp, 2);
1047 tcg_gen_and_tl(cc, tmp, cc);
1048 tcg_gen_andi_tl(cc, cc, Z_FLAG);
1049
1050 tcg_temp_free(tmp);
1051 }
1052 break;
1053 case CC_GE:
1054 cris_evaluate_flags(dc);
1055 /* Overlay the V flag on top of the N. */
1056 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
1057 tcg_gen_xor_tl(cc,
1058 cpu_PR[PR_CCS], cc);
1059 tcg_gen_andi_tl(cc, cc, N_FLAG);
1060 tcg_gen_xori_tl(cc, cc, N_FLAG);
1061 break;
1062 case CC_LT:
1063 cris_evaluate_flags(dc);
1064 /* Overlay the V flag on top of the N. */
1065 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
1066 tcg_gen_xor_tl(cc,
1067 cpu_PR[PR_CCS], cc);
1068 tcg_gen_andi_tl(cc, cc, N_FLAG);
1069 break;
1070 case CC_GT:
1071 cris_evaluate_flags(dc);
1072 {
1073 TCGv n, z;
1074
1075 n = tcg_temp_new();
1076 z = tcg_temp_new();
1077
1078 /* To avoid a shift we overlay everything on
1079 the V flag. */
1080 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1081 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1082 /* invert Z. */
1083 tcg_gen_xori_tl(z, z, 2);
1084
1085 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1086 tcg_gen_xori_tl(n, n, 2);
1087 tcg_gen_and_tl(cc, z, n);
1088 tcg_gen_andi_tl(cc, cc, 2);
1089
1090 tcg_temp_free(n);
1091 tcg_temp_free(z);
1092 }
1093 break;
1094 case CC_LE:
1095 cris_evaluate_flags(dc);
1096 {
1097 TCGv n, z;
1098
1099 n = tcg_temp_new();
1100 z = tcg_temp_new();
1101
1102 /* To avoid a shift we overlay everything on
1103 the V flag. */
1104 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1105 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1106
1107 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1108 tcg_gen_or_tl(cc, z, n);
1109 tcg_gen_andi_tl(cc, cc, 2);
1110
1111 tcg_temp_free(n);
1112 tcg_temp_free(z);
1113 }
1114 break;
1115 case CC_P:
1116 cris_evaluate_flags(dc);
1117 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG);
1118 break;
1119 case CC_A:
1120 tcg_gen_movi_tl(cc, 1);
1121 break;
1122 default:
1123 BUG();
1124 break;
1125 };
1126 }
1127
1128 static void cris_store_direct_jmp(DisasContext *dc)
1129 {
1130 /* Store the direct jmp state into the cpu-state. */
1131 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
1132 if (dc->jmp == JMP_DIRECT) {
1133 tcg_gen_movi_tl(env_btaken, 1);
1134 }
1135 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1136 dc->jmp = JMP_INDIRECT;
1137 }
1138 }
1139
1140 static void cris_prepare_cc_branch (DisasContext *dc,
1141 int offset, int cond)
1142 {
1143 /* This helps us re-schedule the micro-code to insns in delay-slots
1144 before the actual jump. */
1145 dc->delayed_branch = 2;
1146 dc->jmp = JMP_DIRECT_CC;
1147 dc->jmp_pc = dc->pc + offset;
1148
1149 gen_tst_cc (dc, env_btaken, cond);
1150 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1151 }
1152
1153
1154 /* jumps, when the dest is in a live reg for example. Direct should be set
1155 when the dest addr is constant to allow tb chaining. */
1156 static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
1157 {
1158 /* This helps us re-schedule the micro-code to insns in delay-slots
1159 before the actual jump. */
1160 dc->delayed_branch = 2;
1161 dc->jmp = type;
1162 if (type == JMP_INDIRECT) {
1163 tcg_gen_movi_tl(env_btaken, 1);
1164 }
1165 }
1166
1167 static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
1168 {
1169 int mem_index = cpu_mmu_index(dc->env);
1170
1171 /* If we get a fault on a delayslot we must keep the jmp state in
1172 the cpu-state to be able to re-execute the jmp. */
1173 if (dc->delayed_branch == 1)
1174 cris_store_direct_jmp(dc);
1175
1176 tcg_gen_qemu_ld64(dst, addr, mem_index);
1177 }
1178
1179 static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
1180 unsigned int size, int sign)
1181 {
1182 int mem_index = cpu_mmu_index(dc->env);
1183
1184 /* If we get a fault on a delayslot we must keep the jmp state in
1185 the cpu-state to be able to re-execute the jmp. */
1186 if (dc->delayed_branch == 1)
1187 cris_store_direct_jmp(dc);
1188
1189 if (size == 1) {
1190 if (sign)
1191 tcg_gen_qemu_ld8s(dst, addr, mem_index);
1192 else
1193 tcg_gen_qemu_ld8u(dst, addr, mem_index);
1194 }
1195 else if (size == 2) {
1196 if (sign)
1197 tcg_gen_qemu_ld16s(dst, addr, mem_index);
1198 else
1199 tcg_gen_qemu_ld16u(dst, addr, mem_index);
1200 }
1201 else if (size == 4) {
1202 tcg_gen_qemu_ld32u(dst, addr, mem_index);
1203 }
1204 else {
1205 abort();
1206 }
1207 }
1208
1209 static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
1210 unsigned int size)
1211 {
1212 int mem_index = cpu_mmu_index(dc->env);
1213
1214 /* If we get a fault on a delayslot we must keep the jmp state in
1215 the cpu-state to be able to re-execute the jmp. */
1216 if (dc->delayed_branch == 1)
1217 cris_store_direct_jmp(dc);
1218
1219
1220 /* Conditional writes. We only support the kind were X and P are known
1221 at translation time. */
1222 if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) {
1223 dc->postinc = 0;
1224 cris_evaluate_flags(dc);
1225 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);
1226 return;
1227 }
1228
1229 if (size == 1)
1230 tcg_gen_qemu_st8(val, addr, mem_index);
1231 else if (size == 2)
1232 tcg_gen_qemu_st16(val, addr, mem_index);
1233 else
1234 tcg_gen_qemu_st32(val, addr, mem_index);
1235
1236 if (dc->flagx_known && dc->flags_x) {
1237 cris_evaluate_flags(dc);
1238 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);
1239 }
1240 }
1241
1242 static inline void t_gen_sext(TCGv d, TCGv s, int size)
1243 {
1244 if (size == 1)
1245 tcg_gen_ext8s_i32(d, s);
1246 else if (size == 2)
1247 tcg_gen_ext16s_i32(d, s);
1248 else if(!TCGV_EQUAL(d, s))
1249 tcg_gen_mov_tl(d, s);
1250 }
1251
1252 static inline void t_gen_zext(TCGv d, TCGv s, int size)
1253 {
1254 if (size == 1)
1255 tcg_gen_ext8u_i32(d, s);
1256 else if (size == 2)
1257 tcg_gen_ext16u_i32(d, s);
1258 else if (!TCGV_EQUAL(d, s))
1259 tcg_gen_mov_tl(d, s);
1260 }
1261
1262 #if DISAS_CRIS
1263 static char memsize_char(int size)
1264 {
1265 switch (size)
1266 {
1267 case 1: return 'b'; break;
1268 case 2: return 'w'; break;
1269 case 4: return 'd'; break;
1270 default:
1271 return 'x';
1272 break;
1273 }
1274 }
1275 #endif
1276
1277 static inline unsigned int memsize_z(DisasContext *dc)
1278 {
1279 return dc->zsize + 1;
1280 }
1281
1282 static inline unsigned int memsize_zz(DisasContext *dc)
1283 {
1284 switch (dc->zzsize)
1285 {
1286 case 0: return 1;
1287 case 1: return 2;
1288 default:
1289 return 4;
1290 }
1291 }
1292
1293 static inline void do_postinc (DisasContext *dc, int size)
1294 {
1295 if (dc->postinc)
1296 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1297 }
1298
1299 static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1300 int size, int s_ext, TCGv dst)
1301 {
1302 if (s_ext)
1303 t_gen_sext(dst, cpu_R[rs], size);
1304 else
1305 t_gen_zext(dst, cpu_R[rs], size);
1306 }
1307
1308 /* Prepare T0 and T1 for a register alu operation.
1309 s_ext decides if the operand1 should be sign-extended or zero-extended when
1310 needed. */
1311 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1312 int size, int s_ext, TCGv dst, TCGv src)
1313 {
1314 dec_prep_move_r(dc, rs, rd, size, s_ext, src);
1315
1316 if (s_ext)
1317 t_gen_sext(dst, cpu_R[rd], size);
1318 else
1319 t_gen_zext(dst, cpu_R[rd], size);
1320 }
1321
1322 static int dec_prep_move_m(DisasContext *dc, int s_ext, int memsize,
1323 TCGv dst)
1324 {
1325 unsigned int rs;
1326 uint32_t imm;
1327 int is_imm;
1328 int insn_len = 2;
1329
1330 rs = dc->op1;
1331 is_imm = rs == 15 && dc->postinc;
1332
1333 /* Load [$rs] onto T1. */
1334 if (is_imm) {
1335 insn_len = 2 + memsize;
1336 if (memsize == 1)
1337 insn_len++;
1338
1339 imm = cris_fetch(dc, dc->pc + 2, memsize, s_ext);
1340 tcg_gen_movi_tl(dst, imm);
1341 dc->postinc = 0;
1342 } else {
1343 cris_flush_cc_state(dc);
1344 gen_load(dc, dst, cpu_R[rs], memsize, 0);
1345 if (s_ext)
1346 t_gen_sext(dst, dst, memsize);
1347 else
1348 t_gen_zext(dst, dst, memsize);
1349 }
1350 return insn_len;
1351 }
1352
1353 /* Prepare T0 and T1 for a memory + alu operation.
1354 s_ext decides if the operand1 should be sign-extended or zero-extended when
1355 needed. */
1356 static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize,
1357 TCGv dst, TCGv src)
1358 {
1359 int insn_len;
1360
1361 insn_len = dec_prep_move_m(dc, s_ext, memsize, src);
1362 tcg_gen_mov_tl(dst, cpu_R[dc->op2]);
1363 return insn_len;
1364 }
1365
1366 #if DISAS_CRIS
1367 static const char *cc_name(int cc)
1368 {
1369 static const char *cc_names[16] = {
1370 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1371 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1372 };
1373 assert(cc < 16);
1374 return cc_names[cc];
1375 }
1376 #endif
1377
1378 /* Start of insn decoders. */
1379
1380 static int dec_bccq(DisasContext *dc)
1381 {
1382 int32_t offset;
1383 int sign;
1384 uint32_t cond = dc->op2;
1385
1386 offset = EXTRACT_FIELD (dc->ir, 1, 7);
1387 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1388
1389 offset *= 2;
1390 offset |= sign << 8;
1391 offset = sign_extend(offset, 8);
1392
1393 LOG_DIS("b%s %x\n", cc_name(cond), dc->pc + offset);
1394
1395 /* op2 holds the condition-code. */
1396 cris_cc_mask(dc, 0);
1397 cris_prepare_cc_branch (dc, offset, cond);
1398 return 2;
1399 }
1400 static int dec_addoq(DisasContext *dc)
1401 {
1402 int32_t imm;
1403
1404 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1405 imm = sign_extend(dc->op1, 7);
1406
1407 LOG_DIS("addoq %d, $r%u\n", imm, dc->op2);
1408 cris_cc_mask(dc, 0);
1409 /* Fetch register operand, */
1410 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
1411
1412 return 2;
1413 }
1414 static int dec_addq(DisasContext *dc)
1415 {
1416 LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2);
1417
1418 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1419
1420 cris_cc_mask(dc, CC_MASK_NZVC);
1421
1422 cris_alu(dc, CC_OP_ADD,
1423 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1424 return 2;
1425 }
1426 static int dec_moveq(DisasContext *dc)
1427 {
1428 uint32_t imm;
1429
1430 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1431 imm = sign_extend(dc->op1, 5);
1432 LOG_DIS("moveq %d, $r%u\n", imm, dc->op2);
1433
1434 tcg_gen_movi_tl(cpu_R[dc->op2], imm);
1435 return 2;
1436 }
1437 static int dec_subq(DisasContext *dc)
1438 {
1439 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1440
1441 LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2);
1442
1443 cris_cc_mask(dc, CC_MASK_NZVC);
1444 cris_alu(dc, CC_OP_SUB,
1445 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1446 return 2;
1447 }
1448 static int dec_cmpq(DisasContext *dc)
1449 {
1450 uint32_t imm;
1451 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1452 imm = sign_extend(dc->op1, 5);
1453
1454 LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2);
1455 cris_cc_mask(dc, CC_MASK_NZVC);
1456
1457 cris_alu(dc, CC_OP_CMP,
1458 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1459 return 2;
1460 }
1461 static int dec_andq(DisasContext *dc)
1462 {
1463 uint32_t imm;
1464 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1465 imm = sign_extend(dc->op1, 5);
1466
1467 LOG_DIS("andq %d, $r%d\n", imm, dc->op2);
1468 cris_cc_mask(dc, CC_MASK_NZ);
1469
1470 cris_alu(dc, CC_OP_AND,
1471 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1472 return 2;
1473 }
1474 static int dec_orq(DisasContext *dc)
1475 {
1476 uint32_t imm;
1477 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1478 imm = sign_extend(dc->op1, 5);
1479 LOG_DIS("orq %d, $r%d\n", imm, dc->op2);
1480 cris_cc_mask(dc, CC_MASK_NZ);
1481
1482 cris_alu(dc, CC_OP_OR,
1483 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1484 return 2;
1485 }
1486 static int dec_btstq(DisasContext *dc)
1487 {
1488 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1489 LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);
1490
1491 cris_cc_mask(dc, CC_MASK_NZ);
1492 cris_evaluate_flags(dc);
1493 gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
1494 tcg_const_tl(dc->op1), cpu_PR[PR_CCS]);
1495 cris_alu(dc, CC_OP_MOVE,
1496 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1497 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1498 dc->flags_uptodate = 1;
1499 return 2;
1500 }
1501 static int dec_asrq(DisasContext *dc)
1502 {
1503 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1504 LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2);
1505 cris_cc_mask(dc, CC_MASK_NZ);
1506
1507 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1508 cris_alu(dc, CC_OP_MOVE,
1509 cpu_R[dc->op2],
1510 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1511 return 2;
1512 }
1513 static int dec_lslq(DisasContext *dc)
1514 {
1515 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1516 LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2);
1517
1518 cris_cc_mask(dc, CC_MASK_NZ);
1519
1520 tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1521
1522 cris_alu(dc, CC_OP_MOVE,
1523 cpu_R[dc->op2],
1524 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1525 return 2;
1526 }
1527 static int dec_lsrq(DisasContext *dc)
1528 {
1529 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1530 LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2);
1531
1532 cris_cc_mask(dc, CC_MASK_NZ);
1533
1534 tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1535 cris_alu(dc, CC_OP_MOVE,
1536 cpu_R[dc->op2],
1537 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1538 return 2;
1539 }
1540
1541 static int dec_move_r(DisasContext *dc)
1542 {
1543 int size = memsize_zz(dc);
1544
1545 LOG_DIS("move.%c $r%u, $r%u\n",
1546 memsize_char(size), dc->op1, dc->op2);
1547
1548 cris_cc_mask(dc, CC_MASK_NZ);
1549 if (size == 4) {
1550 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
1551 cris_cc_mask(dc, CC_MASK_NZ);
1552 cris_update_cc_op(dc, CC_OP_MOVE, 4);
1553 cris_update_cc_x(dc);
1554 cris_update_result(dc, cpu_R[dc->op2]);
1555 }
1556 else {
1557 TCGv t0;
1558
1559 t0 = tcg_temp_new();
1560 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1561 cris_alu(dc, CC_OP_MOVE,
1562 cpu_R[dc->op2],
1563 cpu_R[dc->op2], t0, size);
1564 tcg_temp_free(t0);
1565 }
1566 return 2;
1567 }
1568
1569 static int dec_scc_r(DisasContext *dc)
1570 {
1571 int cond = dc->op2;
1572
1573 LOG_DIS("s%s $r%u\n",
1574 cc_name(cond), dc->op1);
1575
1576 if (cond != CC_A)
1577 {
1578 int l1;
1579
1580 gen_tst_cc (dc, cpu_R[dc->op1], cond);
1581 l1 = gen_new_label();
1582 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[dc->op1], 0, l1);
1583 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1584 gen_set_label(l1);
1585 }
1586 else
1587 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1588
1589 cris_cc_mask(dc, 0);
1590 return 2;
1591 }
1592
1593 static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t)
1594 {
1595 if (size == 4) {
1596 t[0] = cpu_R[dc->op2];
1597 t[1] = cpu_R[dc->op1];
1598 } else {
1599 t[0] = tcg_temp_new();
1600 t[1] = tcg_temp_new();
1601 }
1602 }
1603
1604 static inline void cris_alu_free_temps(DisasContext *dc, int size, TCGv *t)
1605 {
1606 if (size != 4) {
1607 tcg_temp_free(t[0]);
1608 tcg_temp_free(t[1]);
1609 }
1610 }
1611
1612 static int dec_and_r(DisasContext *dc)
1613 {
1614 TCGv t[2];
1615 int size = memsize_zz(dc);
1616
1617 LOG_DIS("and.%c $r%u, $r%u\n",
1618 memsize_char(size), dc->op1, dc->op2);
1619
1620 cris_cc_mask(dc, CC_MASK_NZ);
1621
1622 cris_alu_alloc_temps(dc, size, t);
1623 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1624 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size);
1625 cris_alu_free_temps(dc, size, t);
1626 return 2;
1627 }
1628
1629 static int dec_lz_r(DisasContext *dc)
1630 {
1631 TCGv t0;
1632 LOG_DIS("lz $r%u, $r%u\n",
1633 dc->op1, dc->op2);
1634 cris_cc_mask(dc, CC_MASK_NZ);
1635 t0 = tcg_temp_new();
1636 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0);
1637 cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1638 tcg_temp_free(t0);
1639 return 2;
1640 }
1641
1642 static int dec_lsl_r(DisasContext *dc)
1643 {
1644 TCGv t[2];
1645 int size = memsize_zz(dc);
1646
1647 LOG_DIS("lsl.%c $r%u, $r%u\n",
1648 memsize_char(size), dc->op1, dc->op2);
1649
1650 cris_cc_mask(dc, CC_MASK_NZ);
1651 cris_alu_alloc_temps(dc, size, t);
1652 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1653 tcg_gen_andi_tl(t[1], t[1], 63);
1654 cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size);
1655 cris_alu_alloc_temps(dc, size, t);
1656 return 2;
1657 }
1658
1659 static int dec_lsr_r(DisasContext *dc)
1660 {
1661 TCGv t[2];
1662 int size = memsize_zz(dc);
1663
1664 LOG_DIS("lsr.%c $r%u, $r%u\n",
1665 memsize_char(size), dc->op1, dc->op2);
1666
1667 cris_cc_mask(dc, CC_MASK_NZ);
1668 cris_alu_alloc_temps(dc, size, t);
1669 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1670 tcg_gen_andi_tl(t[1], t[1], 63);
1671 cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size);
1672 cris_alu_free_temps(dc, size, t);
1673 return 2;
1674 }
1675
1676 static int dec_asr_r(DisasContext *dc)
1677 {
1678 TCGv t[2];
1679 int size = memsize_zz(dc);
1680
1681 LOG_DIS("asr.%c $r%u, $r%u\n",
1682 memsize_char(size), dc->op1, dc->op2);
1683
1684 cris_cc_mask(dc, CC_MASK_NZ);
1685 cris_alu_alloc_temps(dc, size, t);
1686 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1687 tcg_gen_andi_tl(t[1], t[1], 63);
1688 cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size);
1689 cris_alu_free_temps(dc, size, t);
1690 return 2;
1691 }
1692
1693 static int dec_muls_r(DisasContext *dc)
1694 {
1695 TCGv t[2];
1696 int size = memsize_zz(dc);
1697
1698 LOG_DIS("muls.%c $r%u, $r%u\n",
1699 memsize_char(size), dc->op1, dc->op2);
1700 cris_cc_mask(dc, CC_MASK_NZV);
1701 cris_alu_alloc_temps(dc, size, t);
1702 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1703
1704 cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4);
1705 cris_alu_free_temps(dc, size, t);
1706 return 2;
1707 }
1708
1709 static int dec_mulu_r(DisasContext *dc)
1710 {
1711 TCGv t[2];
1712 int size = memsize_zz(dc);
1713
1714 LOG_DIS("mulu.%c $r%u, $r%u\n",
1715 memsize_char(size), dc->op1, dc->op2);
1716 cris_cc_mask(dc, CC_MASK_NZV);
1717 cris_alu_alloc_temps(dc, size, t);
1718 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1719
1720 cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4);
1721 cris_alu_alloc_temps(dc, size, t);
1722 return 2;
1723 }
1724
1725
1726 static int dec_dstep_r(DisasContext *dc)
1727 {
1728 LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2);
1729 cris_cc_mask(dc, CC_MASK_NZ);
1730 cris_alu(dc, CC_OP_DSTEP,
1731 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1732 return 2;
1733 }
1734
1735 static int dec_xor_r(DisasContext *dc)
1736 {
1737 TCGv t[2];
1738 int size = memsize_zz(dc);
1739 LOG_DIS("xor.%c $r%u, $r%u\n",
1740 memsize_char(size), dc->op1, dc->op2);
1741 BUG_ON(size != 4); /* xor is dword. */
1742 cris_cc_mask(dc, CC_MASK_NZ);
1743 cris_alu_alloc_temps(dc, size, t);
1744 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1745
1746 cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4);
1747 cris_alu_free_temps(dc, size, t);
1748 return 2;
1749 }
1750
1751 static int dec_bound_r(DisasContext *dc)
1752 {
1753 TCGv l0;
1754 int size = memsize_zz(dc);
1755 LOG_DIS("bound.%c $r%u, $r%u\n",
1756 memsize_char(size), dc->op1, dc->op2);
1757 cris_cc_mask(dc, CC_MASK_NZ);
1758 l0 = tcg_temp_local_new();
1759 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0);
1760 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4);
1761 tcg_temp_free(l0);
1762 return 2;
1763 }
1764
1765 static int dec_cmp_r(DisasContext *dc)
1766 {
1767 TCGv t[2];
1768 int size = memsize_zz(dc);
1769 LOG_DIS("cmp.%c $r%u, $r%u\n",
1770 memsize_char(size), dc->op1, dc->op2);
1771 cris_cc_mask(dc, CC_MASK_NZVC);
1772 cris_alu_alloc_temps(dc, size, t);
1773 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1774
1775 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size);
1776 cris_alu_free_temps(dc, size, t);
1777 return 2;
1778 }
1779
1780 static int dec_abs_r(DisasContext *dc)
1781 {
1782 TCGv t0;
1783
1784 LOG_DIS("abs $r%u, $r%u\n",
1785 dc->op1, dc->op2);
1786 cris_cc_mask(dc, CC_MASK_NZ);
1787
1788 t0 = tcg_temp_new();
1789 tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31);
1790 tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0);
1791 tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0);
1792 tcg_temp_free(t0);
1793
1794 cris_alu(dc, CC_OP_MOVE,
1795 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1796 return 2;
1797 }
1798
1799 static int dec_add_r(DisasContext *dc)
1800 {
1801 TCGv t[2];
1802 int size = memsize_zz(dc);
1803 LOG_DIS("add.%c $r%u, $r%u\n",
1804 memsize_char(size), dc->op1, dc->op2);
1805 cris_cc_mask(dc, CC_MASK_NZVC);
1806 cris_alu_alloc_temps(dc, size, t);
1807 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1808
1809 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size);
1810 cris_alu_free_temps(dc, size, t);
1811 return 2;
1812 }
1813
1814 static int dec_addc_r(DisasContext *dc)
1815 {
1816 LOG_DIS("addc $r%u, $r%u\n",
1817 dc->op1, dc->op2);
1818 cris_evaluate_flags(dc);
1819 /* Set for this insn. */
1820 dc->flagx_known = 1;
1821 dc->flags_x = X_FLAG;
1822
1823 cris_cc_mask(dc, CC_MASK_NZVC);
1824 cris_alu(dc, CC_OP_ADDC,
1825 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1826 return 2;
1827 }
1828
1829 static int dec_mcp_r(DisasContext *dc)
1830 {
1831 LOG_DIS("mcp $p%u, $r%u\n",
1832 dc->op2, dc->op1);
1833 cris_evaluate_flags(dc);
1834 cris_cc_mask(dc, CC_MASK_RNZV);
1835 cris_alu(dc, CC_OP_MCP,
1836 cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
1837 return 2;
1838 }
1839
1840 #if DISAS_CRIS
1841 static char * swapmode_name(int mode, char *modename) {
1842 int i = 0;
1843 if (mode & 8)
1844 modename[i++] = 'n';
1845 if (mode & 4)
1846 modename[i++] = 'w';
1847 if (mode & 2)
1848 modename[i++] = 'b';
1849 if (mode & 1)
1850 modename[i++] = 'r';
1851 modename[i++] = 0;
1852 return modename;
1853 }
1854 #endif
1855
1856 static int dec_swap_r(DisasContext *dc)
1857 {
1858 TCGv t0;
1859 #if DISAS_CRIS
1860 char modename[4];
1861 #endif
1862 LOG_DIS("swap%s $r%u\n",
1863 swapmode_name(dc->op2, modename), dc->op1);
1864
1865 cris_cc_mask(dc, CC_MASK_NZ);
1866 t0 = tcg_temp_new();
1867 t_gen_mov_TN_reg(t0, dc->op1);
1868 if (dc->op2 & 8)
1869 tcg_gen_not_tl(t0, t0);
1870 if (dc->op2 & 4)
1871 t_gen_swapw(t0, t0);
1872 if (dc->op2 & 2)
1873 t_gen_swapb(t0, t0);
1874 if (dc->op2 & 1)
1875 t_gen_swapr(t0, t0);
1876 cris_alu(dc, CC_OP_MOVE,
1877 cpu_R[dc->op1], cpu_R[dc->op1], t0, 4);
1878 tcg_temp_free(t0);
1879 return 2;
1880 }
1881
1882 static int dec_or_r(DisasContext *dc)
1883 {
1884 TCGv t[2];
1885 int size = memsize_zz(dc);
1886 LOG_DIS("or.%c $r%u, $r%u\n",
1887 memsize_char(size), dc->op1, dc->op2);
1888 cris_cc_mask(dc, CC_MASK_NZ);
1889 cris_alu_alloc_temps(dc, size, t);
1890 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1891 cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size);
1892 cris_alu_free_temps(dc, size, t);
1893 return 2;
1894 }
1895
1896 static int dec_addi_r(DisasContext *dc)
1897 {
1898 TCGv t0;
1899 LOG_DIS("addi.%c $r%u, $r%u\n",
1900 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1901 cris_cc_mask(dc, 0);
1902 t0 = tcg_temp_new();
1903 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1904 tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0);
1905 tcg_temp_free(t0);
1906 return 2;
1907 }
1908
1909 static int dec_addi_acr(DisasContext *dc)
1910 {
1911 TCGv t0;
1912 LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
1913 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1914 cris_cc_mask(dc, 0);
1915 t0 = tcg_temp_new();
1916 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1917 tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0);
1918 tcg_temp_free(t0);
1919 return 2;
1920 }
1921
1922 static int dec_neg_r(DisasContext *dc)
1923 {
1924 TCGv t[2];
1925 int size = memsize_zz(dc);
1926 LOG_DIS("neg.%c $r%u, $r%u\n",
1927 memsize_char(size), dc->op1, dc->op2);
1928 cris_cc_mask(dc, CC_MASK_NZVC);
1929 cris_alu_alloc_temps(dc, size, t);
1930 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1931
1932 cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size);
1933 cris_alu_free_temps(dc, size, t);
1934 return 2;
1935 }
1936
1937 static int dec_btst_r(DisasContext *dc)
1938 {
1939 LOG_DIS("btst $r%u, $r%u\n",
1940 dc->op1, dc->op2);
1941 cris_cc_mask(dc, CC_MASK_NZ);
1942 cris_evaluate_flags(dc);
1943 gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
1944 cpu_R[dc->op1], cpu_PR[PR_CCS]);
1945 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
1946 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1947 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1948 dc->flags_uptodate = 1;
1949 return 2;
1950 }
1951
1952 static int dec_sub_r(DisasContext *dc)
1953 {
1954 TCGv t[2];
1955 int size = memsize_zz(dc);
1956 LOG_DIS("sub.%c $r%u, $r%u\n",
1957 memsize_char(size), dc->op1, dc->op2);
1958 cris_cc_mask(dc, CC_MASK_NZVC);
1959 cris_alu_alloc_temps(dc, size, t);
1960 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1961 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size);
1962 cris_alu_free_temps(dc, size, t);
1963 return 2;
1964 }
1965
1966 /* Zero extension. From size to dword. */
1967 static int dec_movu_r(DisasContext *dc)
1968 {
1969 TCGv t0;
1970 int size = memsize_z(dc);
1971 LOG_DIS("movu.%c $r%u, $r%u\n",
1972 memsize_char(size),
1973 dc->op1, dc->op2);
1974
1975 cris_cc_mask(dc, CC_MASK_NZ);
1976 t0 = tcg_temp_new();
1977 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1978 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1979 tcg_temp_free(t0);
1980 return 2;
1981 }
1982
1983 /* Sign extension. From size to dword. */
1984 static int dec_movs_r(DisasContext *dc)
1985 {
1986 TCGv t0;
1987 int size = memsize_z(dc);
1988 LOG_DIS("movs.%c $r%u, $r%u\n",
1989 memsize_char(size),
1990 dc->op1, dc->op2);
1991
1992 cris_cc_mask(dc, CC_MASK_NZ);
1993 t0 = tcg_temp_new();
1994 /* Size can only be qi or hi. */
1995 t_gen_sext(t0, cpu_R[dc->op1], size);
1996 cris_alu(dc, CC_OP_MOVE,
1997 cpu_R[dc->op2], cpu_R[dc->op1], t0, 4);
1998 tcg_temp_free(t0);
1999 return 2;
2000 }
2001
2002 /* zero extension. From size to dword. */
2003 static int dec_addu_r(DisasContext *dc)
2004 {
2005 TCGv t0;
2006 int size = memsize_z(dc);
2007 LOG_DIS("addu.%c $r%u, $r%u\n",
2008 memsize_char(size),
2009 dc->op1, dc->op2);
2010
2011 cris_cc_mask(dc, CC_MASK_NZVC);
2012 t0 = tcg_temp_new();
2013 /* Size can only be qi or hi. */
2014 t_gen_zext(t0, cpu_R[dc->op1], size);
2015 cris_alu(dc, CC_OP_ADD,
2016 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2017 tcg_temp_free(t0);
2018 return 2;
2019 }
2020
2021 /* Sign extension. From size to dword. */
2022 static int dec_adds_r(DisasContext *dc)
2023 {
2024 TCGv t0;
2025 int size = memsize_z(dc);
2026 LOG_DIS("adds.%c $r%u, $r%u\n",
2027 memsize_char(size),
2028 dc->op1, dc->op2);
2029
2030 cris_cc_mask(dc, CC_MASK_NZVC);
2031 t0 = tcg_temp_new();
2032 /* Size can only be qi or hi. */
2033 t_gen_sext(t0, cpu_R[dc->op1], size);
2034 cris_alu(dc, CC_OP_ADD,
2035 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2036 tcg_temp_free(t0);
2037 return 2;
2038 }
2039
2040 /* Zero extension. From size to dword. */
2041 static int dec_subu_r(DisasContext *dc)
2042 {
2043 TCGv t0;
2044 int size = memsize_z(dc);
2045 LOG_DIS("subu.%c $r%u, $r%u\n",
2046 memsize_char(size),
2047 dc->op1, dc->op2);
2048
2049 cris_cc_mask(dc, CC_MASK_NZVC);
2050 t0 = tcg_temp_new();
2051 /* Size can only be qi or hi. */
2052 t_gen_zext(t0, cpu_R[dc->op1], size);
2053 cris_alu(dc, CC_OP_SUB,
2054 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2055 tcg_temp_free(t0);
2056 return 2;
2057 }
2058
2059 /* Sign extension. From size to dword. */
2060 static int dec_subs_r(DisasContext *dc)
2061 {
2062 TCGv t0;
2063 int size = memsize_z(dc);
2064 LOG_DIS("subs.%c $r%u, $r%u\n",
2065 memsize_char(size),
2066 dc->op1, dc->op2);
2067
2068 cris_cc_mask(dc, CC_MASK_NZVC);
2069 t0 = tcg_temp_new();
2070 /* Size can only be qi or hi. */
2071 t_gen_sext(t0, cpu_R[dc->op1], size);
2072 cris_alu(dc, CC_OP_SUB,
2073 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2074 tcg_temp_free(t0);
2075 return 2;
2076 }
2077
2078 static int dec_setclrf(DisasContext *dc)
2079 {
2080 uint32_t flags;
2081 int set = (~dc->opcode >> 2) & 1;
2082
2083
2084 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
2085 | EXTRACT_FIELD(dc->ir, 0, 3);
2086 if (set && flags == 0) {
2087 LOG_DIS("nop\n");
2088 return 2;
2089 } else if (!set && (flags & 0x20)) {
2090 LOG_DIS("di\n");
2091 }
2092 else {
2093 LOG_DIS("%sf %x\n",
2094 set ? "set" : "clr",
2095 flags);
2096 }
2097
2098 /* User space is not allowed to touch these. Silently ignore. */
2099 if (dc->tb_flags & U_FLAG) {
2100 flags &= ~(S_FLAG | I_FLAG | U_FLAG);
2101 }
2102
2103 if (flags & X_FLAG) {
2104 dc->flagx_known = 1;
2105 if (set)
2106 dc->flags_x = X_FLAG;
2107 else
2108 dc->flags_x = 0;
2109 }
2110
2111 /* Break the TB if any of the SPI flag changes. */
2112 if (flags & (P_FLAG | S_FLAG)) {
2113 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2114 dc->is_jmp = DISAS_UPDATE;
2115 dc->cpustate_changed = 1;
2116 }
2117
2118 /* For the I flag, only act on posedge. */
2119 if ((flags & I_FLAG)) {
2120 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2121 dc->is_jmp = DISAS_UPDATE;
2122 dc->cpustate_changed = 1;
2123 }
2124
2125
2126 /* Simply decode the flags. */
2127 cris_evaluate_flags (dc);
2128 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2129 cris_update_cc_x(dc);
2130 tcg_gen_movi_tl(cc_op, dc->cc_op);
2131
2132 if (set) {
2133 if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) {
2134 /* Enter user mode. */
2135 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
2136 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
2137 dc->cpustate_changed = 1;
2138 }
2139 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
2140 }
2141 else
2142 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
2143
2144 dc->flags_uptodate = 1;
2145 dc->clear_x = 0;
2146 return 2;
2147 }
2148
2149 static int dec_move_rs(DisasContext *dc)
2150 {
2151 LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
2152 cris_cc_mask(dc, 0);
2153 gen_helper_movl_sreg_reg(tcg_const_tl(dc->op2), tcg_const_tl(dc->op1));
2154 return 2;
2155 }
2156 static int dec_move_sr(DisasContext *dc)
2157 {
2158 LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
2159 cris_cc_mask(dc, 0);
2160 gen_helper_movl_reg_sreg(tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
2161 return 2;
2162 }
2163
2164 static int dec_move_rp(DisasContext *dc)
2165 {
2166 TCGv t[2];
2167 LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2);
2168 cris_cc_mask(dc, 0);
2169
2170 t[0] = tcg_temp_new();
2171 if (dc->op2 == PR_CCS) {
2172 cris_evaluate_flags(dc);
2173 t_gen_mov_TN_reg(t[0], dc->op1);
2174 if (dc->tb_flags & U_FLAG) {
2175 t[1] = tcg_temp_new();
2176 /* User space is not allowed to touch all flags. */
2177 tcg_gen_andi_tl(t[0], t[0], 0x39f);
2178 tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f);
2179 tcg_gen_or_tl(t[0], t[1], t[0]);
2180 tcg_temp_free(t[1]);
2181 }
2182 }
2183 else
2184 t_gen_mov_TN_reg(t[0], dc->op1);
2185
2186 t_gen_mov_preg_TN(dc, dc->op2, t[0]);
2187 if (dc->op2 == PR_CCS) {
2188 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2189 dc->flags_uptodate = 1;
2190 }
2191 tcg_temp_free(t[0]);
2192 return 2;
2193 }
2194 static int dec_move_pr(DisasContext *dc)
2195 {
2196 TCGv t0;
2197 LOG_DIS("move $p%u, $r%u\n", dc->op2, dc->op1);
2198 cris_cc_mask(dc, 0);
2199
2200 if (dc->op2 == PR_CCS)
2201 cris_evaluate_flags(dc);
2202
2203 if (dc->op2 == PR_DZ) {
2204 tcg_gen_movi_tl(cpu_R[dc->op1], 0);
2205 } else {
2206 t0 = tcg_temp_new();
2207 t_gen_mov_TN_preg(t0, dc->op2);
2208 cris_alu(dc, CC_OP_MOVE,
2209 cpu_R[dc->op1], cpu_R[dc->op1], t0,
2210 preg_sizes[dc->op2]);
2211 tcg_temp_free(t0);
2212 }
2213 return 2;
2214 }
2215
2216 static int dec_move_mr(DisasContext *dc)
2217 {
2218 int memsize = memsize_zz(dc);
2219 int insn_len;
2220 LOG_DIS("move.%c [$r%u%s, $r%u\n",
2221 memsize_char(memsize),
2222 dc->op1, dc->postinc ? "+]" : "]",
2223 dc->op2);
2224
2225 if (memsize == 4) {
2226 insn_len = dec_prep_move_m(dc, 0, 4, cpu_R[dc->op2]);
2227 cris_cc_mask(dc, CC_MASK_NZ);
2228 cris_update_cc_op(dc, CC_OP_MOVE, 4);
2229 cris_update_cc_x(dc);
2230 cris_update_result(dc, cpu_R[dc->op2]);
2231 }
2232 else {
2233 TCGv t0;
2234
2235 t0 = tcg_temp_new();
2236 insn_len = dec_prep_move_m(dc, 0, memsize, t0);
2237 cris_cc_mask(dc, CC_MASK_NZ);
2238 cris_alu(dc, CC_OP_MOVE,
2239 cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize);
2240 tcg_temp_free(t0);
2241 }
2242 do_postinc(dc, memsize);
2243 return insn_len;
2244 }
2245
2246 static inline void cris_alu_m_alloc_temps(TCGv *t)
2247 {
2248 t[0] = tcg_temp_new();
2249 t[1] = tcg_temp_new();
2250 }
2251
2252 static inline void cris_alu_m_free_temps(TCGv *t)
2253 {
2254 tcg_temp_free(t[0]);
2255 tcg_temp_free(t[1]);
2256 }
2257
2258 static int dec_movs_m(DisasContext *dc)
2259 {
2260 TCGv t[2];
2261 int memsize = memsize_z(dc);
2262 int insn_len;
2263 LOG_DIS("movs.%c [$r%u%s, $r%u\n",
2264 memsize_char(memsize),
2265 dc->op1, dc->postinc ? "+]" : "]",
2266 dc->op2);
2267
2268 cris_alu_m_alloc_temps(t);
2269 /* sign extend. */
2270 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2271 cris_cc_mask(dc, CC_MASK_NZ);
2272 cris_alu(dc, CC_OP_MOVE,
2273 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2274 do_postinc(dc, memsize);
2275 cris_alu_m_free_temps(t);
2276 return insn_len;
2277 }
2278
2279 static int dec_addu_m(DisasContext *dc)
2280 {
2281 TCGv t[2];
2282 int memsize = memsize_z(dc);
2283 int insn_len;
2284 LOG_DIS("addu.%c [$r%u%s, $r%u\n",
2285 memsize_char(memsize),
2286 dc->op1, dc->postinc ? "+]" : "]",
2287 dc->op2);
2288
2289 cris_alu_m_alloc_temps(t);
2290 /* sign extend. */
2291 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2292 cris_cc_mask(dc, CC_MASK_NZVC);
2293 cris_alu(dc, CC_OP_ADD,
2294 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2295 do_postinc(dc, memsize);
2296 cris_alu_m_free_temps(t);
2297 return insn_len;
2298 }
2299
2300 static int dec_adds_m(DisasContext *dc)
2301 {
2302 TCGv t[2];
2303 int memsize = memsize_z(dc);
2304 int insn_len;
2305 LOG_DIS("adds.%c [$r%u%s, $r%u\n",
2306 memsize_char(memsize),
2307 dc->op1, dc->postinc ? "+]" : "]",
2308 dc->op2);
2309
2310 cris_alu_m_alloc_temps(t);
2311 /* sign extend. */
2312 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2313 cris_cc_mask(dc, CC_MASK_NZVC);
2314 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2315 do_postinc(dc, memsize);
2316 cris_alu_m_free_temps(t);
2317 return insn_len;
2318 }
2319
2320 static int dec_subu_m(DisasContext *dc)
2321 {
2322 TCGv t[2];
2323 int memsize = memsize_z(dc);
2324 int insn_len;
2325 LOG_DIS("subu.%c [$r%u%s, $r%u\n",
2326 memsize_char(memsize),
2327 dc->op1, dc->postinc ? "+]" : "]",
2328 dc->op2);
2329
2330 cris_alu_m_alloc_temps(t);
2331 /* sign extend. */
2332 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2333 cris_cc_mask(dc, CC_MASK_NZVC);
2334 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2335 do_postinc(dc, memsize);
2336 cris_alu_m_free_temps(t);
2337 return insn_len;
2338 }
2339
2340 static int dec_subs_m(DisasContext *dc)
2341 {
2342 TCGv t[2];
2343 int memsize = memsize_z(dc);
2344 int insn_len;
2345 LOG_DIS("subs.%c [$r%u%s, $r%u\n",
2346 memsize_char(memsize),
2347 dc->op1, dc->postinc ? "+]" : "]",
2348 dc->op2);
2349
2350 cris_alu_m_alloc_temps(t);
2351 /* sign extend. */
2352 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2353 cris_cc_mask(dc, CC_MASK_NZVC);
2354 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2355 do_postinc(dc, memsize);
2356 cris_alu_m_free_temps(t);
2357 return insn_len;
2358 }
2359
2360 static int dec_movu_m(DisasContext *dc)
2361 {
2362 TCGv t[2];
2363 int memsize = memsize_z(dc);
2364 int insn_len;
2365
2366 LOG_DIS("movu.%c [$r%u%s, $r%u\n",
2367 memsize_char(memsize),
2368 dc->op1, dc->postinc ? "+]" : "]",
2369 dc->op2);
2370
2371 cris_alu_m_alloc_temps(t);
2372 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2373 cris_cc_mask(dc, CC_MASK_NZ);
2374 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2375 do_postinc(dc, memsize);
2376 cris_alu_m_free_temps(t);
2377 return insn_len;
2378 }
2379
2380 static int dec_cmpu_m(DisasContext *dc)
2381 {
2382 TCGv t[2];
2383 int memsize = memsize_z(dc);
2384 int insn_len;
2385 LOG_DIS("cmpu.%c [$r%u%s, $r%u\n",
2386 memsize_char(memsize),
2387 dc->op1, dc->postinc ? "+]" : "]",
2388 dc->op2);
2389
2390 cris_alu_m_alloc_temps(t);
2391 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2392 cris_cc_mask(dc, CC_MASK_NZVC);
2393 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2394 do_postinc(dc, memsize);
2395 cris_alu_m_free_temps(t);
2396 return insn_len;
2397 }
2398
2399 static int dec_cmps_m(DisasContext *dc)
2400 {
2401 TCGv t[2];
2402 int memsize = memsize_z(dc);
2403 int insn_len;
2404 LOG_DIS("cmps.%c [$r%u%s, $r%u\n",
2405 memsize_char(memsize),
2406 dc->op1, dc->postinc ? "+]" : "]",
2407 dc->op2);
2408
2409 cris_alu_m_alloc_temps(t);
2410 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2411 cris_cc_mask(dc, CC_MASK_NZVC);
2412 cris_alu(dc, CC_OP_CMP,
2413 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2414 memsize_zz(dc));
2415 do_postinc(dc, memsize);
2416 cris_alu_m_free_temps(t);
2417 return insn_len;
2418 }
2419
2420 static int dec_cmp_m(DisasContext *dc)
2421 {
2422 TCGv t[2];
2423 int memsize = memsize_zz(dc);
2424 int insn_len;
2425 LOG_DIS("cmp.%c [$r%u%s, $r%u\n",
2426 memsize_char(memsize),
2427 dc->op1, dc->postinc ? "+]" : "]",
2428 dc->op2);
2429
2430 cris_alu_m_alloc_temps(t);
2431 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2432 cris_cc_mask(dc, CC_MASK_NZVC);
2433 cris_alu(dc, CC_OP_CMP,
2434 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2435 memsize_zz(dc));
2436 do_postinc(dc, memsize);
2437 cris_alu_m_free_temps(t);
2438 return insn_len;
2439 }
2440
2441 static int dec_test_m(DisasContext *dc)
2442 {
2443 TCGv t[2];
2444 int memsize = memsize_zz(dc);
2445 int insn_len;
2446 LOG_DIS("test.%c [$r%u%s] op2=%x\n",
2447 memsize_char(memsize),
2448 dc->op1, dc->postinc ? "+]" : "]",
2449 dc->op2);
2450
2451 cris_evaluate_flags(dc);
2452
2453 cris_alu_m_alloc_temps(t);
2454 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2455 cris_cc_mask(dc, CC_MASK_NZ);
2456 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
2457
2458 cris_alu(dc, CC_OP_CMP,
2459 cpu_R[dc->op2], t[1], tcg_const_tl(0), memsize_zz(dc));
2460 do_postinc(dc, memsize);
2461 cris_alu_m_free_temps(t);
2462 return insn_len;
2463 }
2464
2465 static int dec_and_m(DisasContext *dc)
2466 {
2467 TCGv t[2];
2468 int memsize = memsize_zz(dc);
2469 int insn_len;
2470 LOG_DIS("and.%c [$r%u%s, $r%u\n",
2471 memsize_char(memsize),
2472 dc->op1, dc->postinc ? "+]" : "]",
2473 dc->op2);
2474
2475 cris_alu_m_alloc_temps(t);
2476 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2477 cris_cc_mask(dc, CC_MASK_NZ);
2478 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2479 do_postinc(dc, memsize);
2480 cris_alu_m_free_temps(t);
2481 return insn_len;
2482 }
2483
2484 static int dec_add_m(DisasContext *dc)
2485 {
2486 TCGv t[2];
2487 int memsize = memsize_zz(dc);
2488 int insn_len;
2489 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2490 memsize_char(memsize),
2491 dc->op1, dc->postinc ? "+]" : "]",
2492 dc->op2);
2493
2494 cris_alu_m_alloc_temps(t);
2495 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2496 cris_cc_mask(dc, CC_MASK_NZVC);
2497 cris_alu(dc, CC_OP_ADD,
2498 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2499 do_postinc(dc, memsize);
2500 cris_alu_m_free_temps(t);
2501 return insn_len;
2502 }
2503
2504 static int dec_addo_m(DisasContext *dc)
2505 {
2506 TCGv t[2];
2507 int memsize = memsize_zz(dc);
2508 int insn_len;
2509 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2510 memsize_char(memsize),
2511 dc->op1, dc->postinc ? "+]" : "]",
2512 dc->op2);
2513
2514 cris_alu_m_alloc_temps(t);
2515 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2516 cris_cc_mask(dc, 0);
2517 cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4);
2518 do_postinc(dc, memsize);
2519 cris_alu_m_free_temps(t);
2520 return insn_len;
2521 }
2522
2523 static int dec_bound_m(DisasContext *dc)
2524 {
2525 TCGv l[2];
2526 int memsize = memsize_zz(dc);
2527 int insn_len;
2528 LOG_DIS("bound.%c [$r%u%s, $r%u\n",
2529 memsize_char(memsize),
2530 dc->op1, dc->postinc ? "+]" : "]",
2531 dc->op2);
2532
2533 l[0] = tcg_temp_local_new();
2534 l[1] = tcg_temp_local_new();
2535 insn_len = dec_prep_alu_m(dc, 0, memsize, l[0], l[1]);
2536 cris_cc_mask(dc, CC_MASK_NZ);
2537 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4);
2538 do_postinc(dc, memsize);
2539 tcg_temp_free(l[0]);
2540 tcg_temp_free(l[1]);
2541 return insn_len;
2542 }
2543
2544 static int dec_addc_mr(DisasContext *dc)
2545 {
2546 TCGv t[2];
2547 int insn_len = 2;
2548 LOG_DIS("addc [$r%u%s, $r%u\n",
2549 dc->op1, dc->postinc ? "+]" : "]",
2550 dc->op2);
2551
2552 cris_evaluate_flags(dc);
2553
2554 /* Set for this insn. */
2555 dc->flagx_known = 1;
2556 dc->flags_x = X_FLAG;
2557
2558 cris_alu_m_alloc_temps(t);
2559 insn_len = dec_prep_alu_m(dc, 0, 4, t[0], t[1]);
2560 cris_cc_mask(dc, CC_MASK_NZVC);
2561 cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4);
2562 do_postinc(dc, 4);
2563 cris_alu_m_free_temps(t);
2564 return insn_len;
2565 }
2566
2567 static int dec_sub_m(DisasContext *dc)
2568 {
2569 TCGv t[2];
2570 int memsize = memsize_zz(dc);
2571 int insn_len;
2572 LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2573 memsize_char(memsize),
2574 dc->op1, dc->postinc ? "+]" : "]",
2575 dc->op2, dc->ir, dc->zzsize);
2576
2577 cris_alu_m_alloc_temps(t);
2578 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2579 cris_cc_mask(dc, CC_MASK_NZVC);
2580 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize);
2581 do_postinc(dc, memsize);
2582 cris_alu_m_free_temps(t);
2583 return insn_len;
2584 }
2585
2586 static int dec_or_m(DisasContext *dc)
2587 {
2588 TCGv t[2];
2589 int memsize = memsize_zz(dc);
2590 int insn_len;
2591 LOG_DIS("or.%c [$r%u%s, $r%u pc=%x\n",
2592 memsize_char(memsize),
2593 dc->op1, dc->postinc ? "+]" : "]",
2594 dc->op2, dc->pc);
2595
2596 cris_alu_m_alloc_temps(t);
2597 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2598 cris_cc_mask(dc, CC_MASK_NZ);
2599 cris_alu(dc, CC_OP_OR,
2600 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2601 do_postinc(dc, memsize);
2602 cris_alu_m_free_temps(t);
2603 return insn_len;
2604 }
2605
2606 static int dec_move_mp(DisasContext *dc)
2607 {
2608 TCGv t[2];
2609 int memsize = memsize_zz(dc);
2610 int insn_len = 2;
2611
2612 LOG_DIS("move.%c [$r%u%s, $p%u\n",
2613 memsize_char(memsize),
2614 dc->op1,
2615 dc->postinc ? "+]" : "]",
2616 dc->op2);
2617
2618 cris_alu_m_alloc_temps(t);
2619 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2620 cris_cc_mask(dc, 0);
2621 if (dc->op2 == PR_CCS) {
2622 cris_evaluate_flags(dc);
2623 if (dc->tb_flags & U_FLAG) {
2624 /* User space is not allowed to touch all flags. */
2625 tcg_gen_andi_tl(t[1], t[1], 0x39f);
2626 tcg_gen_andi_tl(t[0], cpu_PR[PR_CCS], ~0x39f);
2627 tcg_gen_or_tl(t[1], t[0], t[1]);
2628 }
2629 }
2630
2631 t_gen_mov_preg_TN(dc, dc->op2, t[1]);
2632
2633 do_postinc(dc, memsize);
2634 cris_alu_m_free_temps(t);
2635 return insn_len;
2636 }
2637
2638 static int dec_move_pm(DisasContext *dc)
2639 {
2640 TCGv t0;
2641 int memsize;
2642
2643 memsize = preg_sizes[dc->op2];
2644
2645 LOG_DIS("move.%c $p%u, [$r%u%s\n",
2646 memsize_char(memsize),
2647 dc->op2, dc->op1, dc->postinc ? "+]" : "]");
2648
2649 /* prepare store. Address in T0, value in T1. */
2650 if (dc->op2 == PR_CCS)
2651 cris_evaluate_flags(dc);
2652 t0 = tcg_temp_new();
2653 t_gen_mov_TN_preg(t0, dc->op2);
2654 cris_flush_cc_state(dc);
2655 gen_store(dc, cpu_R[dc->op1], t0, memsize);
2656 tcg_temp_free(t0);
2657
2658 cris_cc_mask(dc, 0);
2659 if (dc->postinc)
2660 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2661 return 2;
2662 }
2663
2664 static int dec_movem_mr(DisasContext *dc)
2665 {
2666 TCGv_i64 tmp[16];
2667 TCGv tmp32;
2668 TCGv addr;
2669 int i;
2670 int nr = dc->op2 + 1;
2671
2672 LOG_DIS("movem [$r%u%s, $r%u\n", dc->op1,
2673 dc->postinc ? "+]" : "]", dc->op2);
2674
2675 addr = tcg_temp_new();
2676 /* There are probably better ways of doing this. */
2677 cris_flush_cc_state(dc);
2678 for (i = 0; i < (nr >> 1); i++) {
2679 tmp[i] = tcg_temp_new_i64();
2680 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2681 gen_load64(dc, tmp[i], addr);
2682 }
2683 if (nr & 1) {
2684 tmp32 = tcg_temp_new_i32();
2685 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2686 gen_load(dc, tmp32, addr, 4, 0);
2687 } else
2688 TCGV_UNUSED(tmp32);
2689 tcg_temp_free(addr);
2690
2691 for (i = 0; i < (nr >> 1); i++) {
2692 tcg_gen_trunc_i64_i32(cpu_R[i * 2], tmp[i]);
2693 tcg_gen_shri_i64(tmp[i], tmp[i], 32);
2694 tcg_gen_trunc_i64_i32(cpu_R[i * 2 + 1], tmp[i]);
2695 tcg_temp_free_i64(tmp[i]);
2696 }
2697 if (nr & 1) {
2698 tcg_gen_mov_tl(cpu_R[dc->op2], tmp32);
2699 tcg_temp_free(tmp32);
2700 }
2701
2702 /* writeback the updated pointer value. */
2703 if (dc->postinc)
2704 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4);
2705
2706 /* gen_load might want to evaluate the previous insns flags. */
2707 cris_cc_mask(dc, 0);
2708 return 2;
2709 }
2710
2711 static int dec_movem_rm(DisasContext *dc)
2712 {
2713 TCGv tmp;
2714 TCGv addr;
2715 int i;
2716
2717 LOG_DIS("movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2718 dc->postinc ? "+]" : "]");
2719
2720 cris_flush_cc_state(dc);
2721
2722 tmp = tcg_temp_new();
2723 addr = tcg_temp_new();
2724 tcg_gen_movi_tl(tmp, 4);
2725 tcg_gen_mov_tl(addr, cpu_R[dc->op1]);
2726 for (i = 0; i <= dc->op2; i++) {
2727 /* Displace addr. */
2728 /* Perform the store. */
2729 gen_store(dc, addr, cpu_R[i], 4);
2730 tcg_gen_add_tl(addr, addr, tmp);
2731 }
2732 if (dc->postinc)
2733 tcg_gen_mov_tl(cpu_R[dc->op1], addr);
2734 cris_cc_mask(dc, 0);
2735 tcg_temp_free(tmp);
2736 tcg_temp_free(addr);
2737 return 2;
2738 }
2739
2740 static int dec_move_rm(DisasContext *dc)
2741 {
2742 int memsize;
2743
2744 memsize = memsize_zz(dc);
2745
2746 LOG_DIS("move.%c $r%u, [$r%u]\n",
2747 memsize_char(memsize), dc->op2, dc->op1);
2748
2749 /* prepare store. */
2750 cris_flush_cc_state(dc);
2751 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
2752
2753 if (dc->postinc)
2754 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2755 cris_cc_mask(dc, 0);
2756 return 2;
2757 }
2758
2759 static int dec_lapcq(DisasContext *dc)
2760 {
2761 LOG_DIS("lapcq %x, $r%u\n",
2762 dc->pc + dc->op1*2, dc->op2);
2763 cris_cc_mask(dc, 0);
2764 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
2765 return 2;
2766 }
2767
2768 static int dec_lapc_im(DisasContext *dc)
2769 {
2770 unsigned int rd;
2771 int32_t imm;
2772 int32_t pc;
2773
2774 rd = dc->op2;
2775
2776 cris_cc_mask(dc, 0);
2777 imm = cris_fetch(dc, dc->pc + 2, 4, 0);
2778 LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2);
2779
2780 pc = dc->pc;
2781 pc += imm;
2782 tcg_gen_movi_tl(cpu_R[rd], pc);
2783 return 6;
2784 }
2785
2786 /* Jump to special reg. */
2787 static int dec_jump_p(DisasContext *dc)
2788 {
2789 LOG_DIS("jump $p%u\n", dc->op2);
2790
2791 if (dc->op2 == PR_CCS)
2792 cris_evaluate_flags(dc);
2793 t_gen_mov_TN_preg(env_btarget, dc->op2);
2794 /* rete will often have low bit set to indicate delayslot. */
2795 tcg_gen_andi_tl(env_btarget, env_btarget, ~1);
2796 cris_cc_mask(dc, 0);
2797 cris_prepare_jmp(dc, JMP_INDIRECT);
2798 return 2;
2799 }
2800
2801 /* Jump and save. */
2802 static int dec_jas_r(DisasContext *dc)
2803 {
2804 LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2);
2805 cris_cc_mask(dc, 0);
2806 /* Store the return address in Pd. */
2807 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2808 if (dc->op2 > 15)
2809 abort();
2810 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4));
2811
2812 cris_prepare_jmp(dc, JMP_INDIRECT);
2813 return 2;
2814 }
2815
2816 static int dec_jas_im(DisasContext *dc)
2817 {
2818 uint32_t imm;
2819
2820 imm = cris_fetch(dc, dc->pc + 2, 4, 0);
2821
2822 LOG_DIS("jas 0x%x\n", imm);
2823 cris_cc_mask(dc, 0);
2824 /* Store the return address in Pd. */
2825 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2826
2827 dc->jmp_pc = imm;
2828 cris_prepare_jmp(dc, JMP_DIRECT);
2829 return 6;
2830 }
2831
2832 static int dec_jasc_im(DisasContext *dc)
2833 {
2834 uint32_t imm;
2835
2836 imm = cris_fetch(dc, dc->pc + 2, 4, 0);
2837
2838 LOG_DIS("jasc 0x%x\n", imm);
2839 cris_cc_mask(dc, 0);
2840 /* Store the return address in Pd. */
2841 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
2842
2843 dc->jmp_pc = imm;
2844 cris_prepare_jmp(dc, JMP_DIRECT);
2845 return 6;
2846 }
2847
2848 static int dec_jasc_r(DisasContext *dc)
2849 {
2850 LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2);
2851 cris_cc_mask(dc, 0);
2852 /* Store the return address in Pd. */
2853 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2854 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4));
2855 cris_prepare_jmp(dc, JMP_INDIRECT);
2856 return 2;
2857 }
2858
2859 static int dec_bcc_im(DisasContext *dc)
2860 {
2861 int32_t offset;
2862 uint32_t cond = dc->op2;
2863
2864 offset = cris_fetch(dc, dc->pc + 2, 2, 1);
2865
2866 LOG_DIS("b%s %d pc=%x dst=%x\n",
2867 cc_name(cond), offset,
2868 dc->pc, dc->pc + offset);
2869
2870 cris_cc_mask(dc, 0);
2871 /* op2 holds the condition-code. */
2872 cris_prepare_cc_branch (dc, offset, cond);
2873 return 4;
2874 }
2875
2876 static int dec_bas_im(DisasContext *dc)
2877 {
2878 int32_t simm;
2879
2880
2881 simm = cris_fetch(dc, dc->pc + 2, 4, 0);
2882
2883 LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2884 cris_cc_mask(dc, 0);
2885 /* Store the return address in Pd. */
2886 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2887
2888 dc->jmp_pc = dc->pc + simm;
2889 cris_prepare_jmp(dc, JMP_DIRECT);
2890 return 6;
2891 }
2892
2893 static int dec_basc_im(DisasContext *dc)
2894 {
2895 int32_t simm;
2896 simm = cris_fetch(dc, dc->pc + 2, 4, 0);
2897
2898 LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2899 cris_cc_mask(dc, 0);
2900 /* Store the return address in Pd. */
2901 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
2902
2903 dc->jmp_pc = dc->pc + simm;
2904 cris_prepare_jmp(dc, JMP_DIRECT);
2905 return 6;
2906 }
2907
2908 static int dec_rfe_etc(DisasContext *dc)
2909 {
2910 cris_cc_mask(dc, 0);
2911
2912 if (dc->op2 == 15) {
2913 t_gen_mov_env_TN(halted, tcg_const_tl(1));
2914 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2915 t_gen_raise_exception(EXCP_HLT);
2916 return 2;
2917 }
2918
2919 switch (dc->op2 & 7) {
2920 case 2:
2921 /* rfe. */
2922 LOG_DIS("rfe\n");
2923 cris_evaluate_flags(dc);
2924 gen_helper_rfe();
2925 dc->is_jmp = DISAS_UPDATE;
2926 break;
2927 case 5:
2928 /* rfn. */
2929 LOG_DIS("rfn\n");
2930 cris_evaluate_flags(dc);
2931 gen_helper_rfn();
2932 dc->is_jmp = DISAS_UPDATE;
2933 break;
2934 case 6:
2935 LOG_DIS("break %d\n", dc->op1);
2936 cris_evaluate_flags (dc);
2937 /* break. */
2938 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2939
2940 /* Breaks start at 16 in the exception vector. */
2941 t_gen_mov_env_TN(trap_vector,
2942 tcg_const_tl(dc->op1 + 16));
2943 t_gen_raise_exception(EXCP_BREAK);
2944 dc->is_jmp = DISAS_UPDATE;
2945 break;
2946 default:
2947 printf ("op2=%x\n", dc->op2);
2948 BUG();
2949 break;
2950
2951 }
2952 return 2;
2953 }
2954
2955 static int dec_ftag_fidx_d_m(DisasContext *dc)
2956 {
2957 return 2;
2958 }
2959
2960 static int dec_ftag_fidx_i_m(DisasContext *dc)
2961 {
2962 return 2;
2963 }
2964
2965 static int dec_null(DisasContext *dc)
2966 {
2967 printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2968 dc->pc, dc->opcode, dc->op1, dc->op2);
2969 fflush(NULL);
2970 BUG();
2971 return 2;
2972 }
2973
2974 static struct decoder_info {
2975 struct {
2976 uint32_t bits;
2977 uint32_t mask;
2978 };
2979 int (*dec)(DisasContext *dc);
2980 } decinfo[] = {
2981 /* Order matters here. */
2982 {DEC_MOVEQ, dec_moveq},
2983 {DEC_BTSTQ, dec_btstq},
2984 {DEC_CMPQ, dec_cmpq},
2985 {DEC_ADDOQ, dec_addoq},
2986 {DEC_ADDQ, dec_addq},
2987 {DEC_SUBQ, dec_subq},
2988 {DEC_ANDQ, dec_andq},
2989 {DEC_ORQ, dec_orq},
2990 {DEC_ASRQ, dec_asrq},
2991 {DEC_LSLQ, dec_lslq},
2992 {DEC_LSRQ, dec_lsrq},
2993 {DEC_BCCQ, dec_bccq},
2994
2995 {DEC_BCC_IM, dec_bcc_im},
2996 {DEC_JAS_IM, dec_jas_im},
2997 {DEC_JAS_R, dec_jas_r},
2998 {DEC_JASC_IM, dec_jasc_im},
2999 {DEC_JASC_R, dec_jasc_r},
3000 {DEC_BAS_IM, dec_bas_im},
3001 {DEC_BASC_IM, dec_basc_im},
3002 {DEC_JUMP_P, dec_jump_p},
3003 {DEC_LAPC_IM, dec_lapc_im},
3004 {DEC_LAPCQ, dec_lapcq},
3005
3006 {DEC_RFE_ETC, dec_rfe_etc},
3007 {DEC_ADDC_MR, dec_addc_mr},
3008
3009 {DEC_MOVE_MP, dec_move_mp},
3010 {DEC_MOVE_PM, dec_move_pm},
3011 {DEC_MOVEM_MR, dec_movem_mr},
3012 {DEC_MOVEM_RM, dec_movem_rm},
3013 {DEC_MOVE_PR, dec_move_pr},
3014 {DEC_SCC_R, dec_scc_r},
3015 {DEC_SETF, dec_setclrf},
3016 {DEC_CLEARF, dec_setclrf},
3017
3018 {DEC_MOVE_SR, dec_move_sr},
3019 {DEC_MOVE_RP, dec_move_rp},
3020 {DEC_SWAP_R, dec_swap_r},
3021 {DEC_ABS_R, dec_abs_r},
3022 {DEC_LZ_R, dec_lz_r},
3023 {DEC_MOVE_RS, dec_move_rs},
3024 {DEC_BTST_R, dec_btst_r},
3025 {DEC_ADDC_R, dec_addc_r},
3026
3027 {DEC_DSTEP_R, dec_dstep_r},
3028 {DEC_XOR_R, dec_xor_r},
3029 {DEC_MCP_R, dec_mcp_r},
3030 {DEC_CMP_R, dec_cmp_r},
3031
3032 {DEC_ADDI_R, dec_addi_r},
3033 {DEC_ADDI_ACR, dec_addi_acr},
3034
3035 {DEC_ADD_R, dec_add_r},
3036 {DEC_SUB_R, dec_sub_r},
3037
3038 {DEC_ADDU_R, dec_addu_r},
3039 {DEC_ADDS_R, dec_adds_r},
3040 {DEC_SUBU_R, dec_subu_r},
3041 {DEC_SUBS_R, dec_subs_r},
3042 {DEC_LSL_R, dec_lsl_r},
3043
3044 {DEC_AND_R, dec_and_r},
3045 {DEC_OR_R, dec_or_r},
3046 {DEC_BOUND_R, dec_bound_r},
3047 {DEC_ASR_R, dec_asr_r},
3048 {DEC_LSR_R, dec_lsr_r},
3049
3050 {DEC_MOVU_R, dec_movu_r},
3051 {DEC_MOVS_R, dec_movs_r},
3052 {DEC_NEG_R, dec_neg_r},
3053 {DEC_MOVE_R, dec_move_r},
3054
3055 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
3056 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
3057
3058 {DEC_MULS_R, dec_muls_r},
3059 {DEC_MULU_R, dec_mulu_r},
3060
3061 {DEC_ADDU_M, dec_addu_m},
3062 {DEC_ADDS_M, dec_adds_m},
3063 {DEC_SUBU_M, dec_subu_m},
3064 {DEC_SUBS_M, dec_subs_m},
3065
3066 {DEC_CMPU_M, dec_cmpu_m},
3067 {DEC_CMPS_M, dec_cmps_m},
3068 {DEC_MOVU_M, dec_movu_m},
3069 {DEC_MOVS_M, dec_movs_m},
3070
3071 {DEC_CMP_M, dec_cmp_m},
3072 {DEC_ADDO_M, dec_addo_m},
3073 {DEC_BOUND_M, dec_bound_m},
3074 {DEC_ADD_M, dec_add_m},
3075 {DEC_SUB_M, dec_sub_m},
3076 {DEC_AND_M, dec_and_m},
3077 {DEC_OR_M, dec_or_m},
3078 {DEC_MOVE_RM, dec_move_rm},
3079 {DEC_TEST_M, dec_test_m},
3080 {DEC_MOVE_MR, dec_move_mr},
3081
3082 {{0, 0}, dec_null}
3083 };
3084
3085 static unsigned int crisv32_decoder(DisasContext *dc)
3086 {
3087 int insn_len = 2;
3088 int i;
3089
3090 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
3091 tcg_gen_debug_insn_start(dc->pc);
3092
3093 /* Load a halfword onto the instruction register. */
3094 dc->ir = cris_fetch(dc, dc->pc, 2, 0);
3095
3096 /* Now decode it. */
3097 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
3098 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
3099 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
3100 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
3101 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
3102 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
3103
3104 /* Large switch for all insns. */
3105 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
3106 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits)
3107 {
3108 insn_len = decinfo[i].dec(dc);
3109 break;
3110 }
3111 }
3112
3113 #if !defined(CONFIG_USER_ONLY)
3114 /* Single-stepping ? */
3115 if (dc->tb_flags & S_FLAG) {
3116 int l1;
3117
3118 l1 = gen_new_label();
3119 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1);
3120 /* We treat SPC as a break with an odd trap vector. */
3121 cris_evaluate_flags (dc);
3122 t_gen_mov_env_TN(trap_vector, tcg_const_tl(3));
3123 tcg_gen_movi_tl(env_pc, dc->pc + insn_len);
3124 tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len);
3125 t_gen_raise_exception(EXCP_BREAK);
3126 gen_set_label(l1);
3127 }
3128 #endif
3129 return insn_len;
3130 }
3131
3132 static void check_breakpoint(CPUState *env, DisasContext *dc)
3133 {
3134 CPUBreakpoint *bp;
3135
3136 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
3137 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
3138 if (bp->pc == dc->pc) {
3139 cris_evaluate_flags (dc);
3140 tcg_gen_movi_tl(env_pc, dc->pc);
3141 t_gen_raise_exception(EXCP_DEBUG);
3142 dc->is_jmp = DISAS_UPDATE;
3143 }
3144 }
3145 }
3146 }
3147
3148 #include "translate_v10.c"
3149
3150 /*
3151 * Delay slots on QEMU/CRIS.
3152 *
3153 * If an exception hits on a delayslot, the core will let ERP (the Exception
3154 * Return Pointer) point to the branch (the previous) insn and set the lsb to
3155 * to give SW a hint that the exception actually hit on the dslot.
3156 *
3157 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
3158 * the core and any jmp to an odd addresses will mask off that lsb. It is
3159 * simply there to let sw know there was an exception on a dslot.
3160 *
3161 * When the software returns from an exception, the branch will re-execute.
3162 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3163 * and the branch and delayslot dont share pages.
3164 *
3165 * The TB contaning the branch insn will set up env->btarget and evaluate
3166 * env->btaken. When the translation loop exits we will note that the branch
3167 * sequence is broken and let env->dslot be the size of the branch insn (those
3168 * vary in length).
3169 *
3170 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3171 * set). It will also expect to have env->dslot setup with the size of the
3172 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3173 * will execute the dslot and take the branch, either to btarget or just one
3174 * insn ahead.
3175 *
3176 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3177 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3178 * branch and set lsb). Then env->dslot gets cleared so that the exception
3179 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3180 * masked off and we will reexecute the branch insn.
3181 *
3182 */
3183
3184 /* generate intermediate code for basic block 'tb'. */
3185 static void
3186 gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
3187 int search_pc)
3188 {
3189 uint16_t *gen_opc_end;
3190 uint32_t pc_start;
3191 unsigned int insn_len;
3192 int j, lj;
3193 struct DisasContext ctx;
3194 struct DisasContext *dc = &ctx;
3195 uint32_t next_page_start;
3196 target_ulong npc;
3197 int num_insns;
3198 int max_insns;
3199
3200 qemu_log_try_set_file(stderr);
3201
3202 if (env->pregs[PR_VR] == 32) {
3203 dc->decoder = crisv32_decoder;
3204 dc->clear_locked_irq = 0;
3205 } else {
3206 dc->decoder = crisv10_decoder;
3207 dc->clear_locked_irq = 1;
3208 }
3209
3210 /* Odd PC indicates that branch is rexecuting due to exception in the
3211 * delayslot, like in real hw.
3212 */
3213 pc_start = tb->pc & ~1;
3214 dc->env = env;
3215 dc->tb = tb;
3216
3217 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3218
3219 dc->is_jmp = DISAS_NEXT;
3220 dc->ppc = pc_start;
3221 dc->pc = pc_start;
3222 dc->singlestep_enabled = env->singlestep_enabled;
3223 dc->flags_uptodate = 1;
3224 dc->flagx_known = 1;
3225 dc->flags_x = tb->flags & X_FLAG;
3226 dc->cc_x_uptodate = 0;
3227 dc->cc_mask = 0;
3228 dc->update_cc = 0;
3229 dc->clear_prefix = 0;
3230
3231 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
3232 dc->cc_size_uptodate = -1;
3233
3234 /* Decode TB flags. */
3235 dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG \
3236 | X_FLAG | PFIX_FLAG);
3237 dc->delayed_branch = !!(tb->flags & 7);
3238 if (dc->delayed_branch)
3239 dc->jmp = JMP_INDIRECT;
3240 else
3241 dc->jmp = JMP_NOJMP;
3242
3243 dc->cpustate_changed = 0;
3244
3245 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3246 qemu_log(
3247 "srch=%d pc=%x %x flg=%" PRIx64 " bt=%x ds=%u ccs=%x\n"
3248 "pid=%x usp=%x\n"
3249 "%x.%x.%x.%x\n"
3250 "%x.%x.%x.%x\n"
3251 "%x.%x.%x.%x\n"
3252 "%x.%x.%x.%x\n",
3253 search_pc, dc->pc, dc->ppc,
3254 (uint64_t)tb->flags,
3255 env->btarget, (unsigned)tb->flags & 7,
3256 env->pregs[PR_CCS],
3257 env->pregs[PR_PID], env->pregs[PR_USP],
3258 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
3259 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
3260 env->regs[8], env->regs[9],
3261 env->regs[10], env->regs[11],
3262 env->regs[12], env->regs[13],
3263 env->regs[14], env->regs[15]);
3264 qemu_log("--------------\n");
3265 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3266 }
3267
3268 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3269 lj = -1;
3270 num_insns = 0;
3271 max_insns = tb->cflags & CF_COUNT_MASK;
3272 if (max_insns == 0)
3273 max_insns = CF_COUNT_MASK;
3274
3275 gen_icount_start();
3276 do
3277 {
3278 check_breakpoint(env, dc);
3279
3280 if (search_pc) {
3281 j = gen_opc_ptr - gen_opc_buf;
3282 if (lj < j) {
3283 lj++;
3284 while (lj < j)
3285 gen_opc_instr_start[lj++] = 0;
3286 }
3287 if (dc->delayed_branch == 1)
3288 gen_opc_pc[lj] = dc->ppc | 1;
3289 else
3290 gen_opc_pc[lj] = dc->pc;
3291 gen_opc_instr_start[lj] = 1;
3292 gen_opc_icount[lj] = num_insns;
3293 }
3294
3295 /* Pretty disas. */
3296 LOG_DIS("%8.8x:\t", dc->pc);
3297
3298 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
3299 gen_io_start();
3300 dc->clear_x = 1;
3301
3302 insn_len = dc->decoder(dc);
3303 dc->ppc = dc->pc;
3304 dc->pc += insn_len;
3305 if (dc->clear_x)
3306 cris_clear_x_flag(dc);
3307
3308 num_insns++;
3309 /* Check for delayed branches here. If we do it before
3310 actually generating any host code, the simulator will just
3311 loop doing nothing for on this program location. */
3312 if (dc->delayed_branch) {
3313 dc->delayed_branch--;
3314 if (dc->delayed_branch == 0)
3315 {
3316 if (tb->flags & 7)
3317 t_gen_mov_env_TN(dslot,
3318 tcg_const_tl(0));
3319 if (dc->cpustate_changed || !dc->flagx_known
3320 || (dc->flags_x != (tb->flags & X_FLAG))) {
3321 cris_store_direct_jmp(dc);
3322 }
3323
3324 if (dc->clear_locked_irq) {
3325 dc->clear_locked_irq = 0;
3326 t_gen_mov_env_TN(locked_irq,
3327 tcg_const_tl(0));
3328 }
3329
3330 if (dc->jmp == JMP_DIRECT_CC) {
3331 int l1;
3332
3333 l1 = gen_new_label();
3334 cris_evaluate_flags(dc);
3335
3336 /* Conditional jmp. */
3337 tcg_gen_brcondi_tl(TCG_COND_EQ,
3338 env_btaken, 0, l1);
3339 gen_goto_tb(dc, 1, dc->jmp_pc);
3340 gen_set_label(l1);
3341 gen_goto_tb(dc, 0, dc->pc);
3342 dc->is_jmp = DISAS_TB_JUMP;
3343 dc->jmp = JMP_NOJMP;
3344 } else if (dc->jmp == JMP_DIRECT) {
3345 cris_evaluate_flags(dc);
3346 gen_goto_tb(dc, 0, dc->jmp_pc);
3347 dc->is_jmp = DISAS_TB_JUMP;
3348 dc->jmp = JMP_NOJMP;
3349 } else {
3350 t_gen_cc_jmp(env_btarget,
3351 tcg_const_tl(dc->pc));
3352 dc->is_jmp = DISAS_JUMP;
3353 }
3354 break;
3355 }
3356 }
3357
3358 /* If we are rexecuting a branch due to exceptions on
3359 delay slots dont break. */
3360 if (!(tb->pc & 1) && env->singlestep_enabled)
3361 break;
3362 } while (!dc->is_jmp && !dc->cpustate_changed
3363 && gen_opc_ptr < gen_opc_end
3364 && !singlestep
3365 && (dc->pc < next_page_start)
3366 && num_insns < max_insns);
3367
3368 if (dc->clear_locked_irq)
3369 t_gen_mov_env_TN(locked_irq, tcg_const_tl(0));
3370
3371 npc = dc->pc;
3372
3373 if (tb->cflags & CF_LAST_IO)
3374 gen_io_end();
3375 /* Force an update if the per-tb cpu state has changed. */
3376 if (dc->is_jmp == DISAS_NEXT
3377 && (dc->cpustate_changed || !dc->flagx_known
3378 || (dc->flags_x != (tb->flags & X_FLAG)))) {
3379 dc->is_jmp = DISAS_UPDATE;
3380 tcg_gen_movi_tl(env_pc, npc);
3381 }
3382 /* Broken branch+delayslot sequence. */
3383 if (dc->delayed_branch == 1) {
3384 /* Set env->dslot to the size of the branch insn. */
3385 t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
3386 cris_store_direct_jmp(dc);
3387 }
3388
3389 cris_evaluate_flags (dc);
3390
3391 if (unlikely(env->singlestep_enabled)) {
3392 if (dc->is_jmp == DISAS_NEXT)
3393 tcg_gen_movi_tl(env_pc, npc);
3394 t_gen_raise_exception(EXCP_DEBUG);
3395 } else {
3396 switch(dc->is_jmp) {
3397 case DISAS_NEXT:
3398 gen_goto_tb(dc, 1, npc);
3399 break;
3400 default:
3401 case DISAS_JUMP:
3402 case DISAS_UPDATE:
3403 /* indicate that the hash table must be used
3404 to find the next TB */
3405 tcg_gen_exit_tb(0);
3406 break;
3407 case DISAS_SWI:
3408 case DISAS_TB_JUMP:
3409 /* nothing more to generate */
3410 break;
3411 }
3412 }
3413 gen_icount_end(tb, num_insns);
3414 *gen_opc_ptr = INDEX_op_end;
3415 if (search_pc) {
3416 j = gen_opc_ptr - gen_opc_buf;
3417 lj++;
3418 while (lj <= j)
3419 gen_opc_instr_start[lj++] = 0;
3420 } else {
3421 tb->size = dc->pc - pc_start;
3422 tb->icount = num_insns;
3423 }
3424
3425 #ifdef DEBUG_DISAS
3426 #if !DISAS_CRIS
3427 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3428 log_target_disas(pc_start, dc->pc - pc_start,
3429 dc->env->pregs[PR_VR]);
3430 qemu_log("\nisize=%d osize=%td\n",
3431 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
3432 }
3433 #endif
3434 #endif
3435 }
3436
3437 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
3438 {
3439 gen_intermediate_code_internal(env, tb, 0);
3440 }
3441
3442 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
3443 {
3444 gen_intermediate_code_internal(env, tb, 1);
3445 }
3446
3447 void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
3448 int flags)
3449 {
3450 int i;
3451 uint32_t srs;
3452
3453 if (!env || !f)
3454 return;
3455
3456 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3457 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3458 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
3459 env->cc_op,
3460 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
3461
3462
3463 for (i = 0; i < 16; i++) {
3464 cpu_fprintf(f, "%s=%8.8x ",regnames[i], env->regs[i]);
3465 if ((i + 1) % 4 == 0)
3466 cpu_fprintf(f, "\n");
3467 }
3468 cpu_fprintf(f, "\nspecial regs:\n");
3469 for (i = 0; i < 16; i++) {
3470 cpu_fprintf(f, "%s=%8.8x ", pregnames[i], env->pregs[i]);
3471 if ((i + 1) % 4 == 0)
3472 cpu_fprintf(f, "\n");
3473 }
3474 srs = env->pregs[PR_SRS];
3475 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
3476 if (srs < 256) {
3477 for (i = 0; i < 16; i++) {
3478 cpu_fprintf(f, "s%2.2d=%8.8x ",
3479 i, env->sregs[srs][i]);
3480 if ((i + 1) % 4 == 0)
3481 cpu_fprintf(f, "\n");
3482 }
3483 }
3484 cpu_fprintf(f, "\n\n");
3485
3486 }
3487
3488 struct
3489 {
3490 uint32_t vr;
3491 const char *name;
3492 } cris_cores[] = {
3493 {8, "crisv8"},
3494 {9, "crisv9"},
3495 {10, "crisv10"},
3496 {11, "crisv11"},
3497 {32, "crisv32"},
3498 };
3499
3500 void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf)
3501 {
3502 unsigned int i;
3503
3504 (*cpu_fprintf)(f, "Available CPUs:\n");
3505 for (i = 0; i < ARRAY_SIZE(cris_cores); i++) {
3506 (*cpu_fprintf)(f, " %s\n", cris_cores[i].name);
3507 }
3508 }
3509
3510 static uint32_t vr_by_name(const char *name)
3511 {
3512 unsigned int i;
3513 for (i = 0; i < ARRAY_SIZE(cris_cores); i++) {
3514 if (strcmp(name, cris_cores[i].name) == 0) {
3515 return cris_cores[i].vr;
3516 }
3517 }
3518 return 32;
3519 }
3520
3521 CPUCRISState *cpu_cris_init (const char *cpu_model)
3522 {
3523 CPUCRISState *env;
3524 static int tcg_initialized = 0;
3525 int i;
3526
3527 env = qemu_mallocz(sizeof(CPUCRISState));
3528
3529 env->pregs[PR_VR] = vr_by_name(cpu_model);
3530 cpu_exec_init(env);
3531 cpu_reset(env);
3532 qemu_init_vcpu(env);
3533
3534 if (tcg_initialized)
3535 return env;
3536
3537 tcg_initialized = 1;
3538
3539 #define GEN_HELPER 2
3540 #include "helper.h"
3541
3542 if (env->pregs[PR_VR] < 32) {
3543 cpu_crisv10_init(env);
3544 return env;
3545 }
3546
3547
3548 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
3549 cc_x = tcg_global_mem_new(TCG_AREG0,
3550 offsetof(CPUState, cc_x), "cc_x");
3551 cc_src = tcg_global_mem_new(TCG_AREG0,
3552 offsetof(CPUState, cc_src), "cc_src");
3553 cc_dest = tcg_global_mem_new(TCG_AREG0,
3554 offsetof(CPUState, cc_dest),
3555 "cc_dest");
3556 cc_result = tcg_global_mem_new(TCG_AREG0,
3557 offsetof(CPUState, cc_result),
3558 "cc_result");
3559 cc_op = tcg_global_mem_new(TCG_AREG0,
3560 offsetof(CPUState, cc_op), "cc_op");
3561 cc_size = tcg_global_mem_new(TCG_AREG0,
3562 offsetof(CPUState, cc_size),
3563 "cc_size");
3564 cc_mask = tcg_global_mem_new(TCG_AREG0,
3565 offsetof(CPUState, cc_mask),
3566 "cc_mask");
3567
3568 env_pc = tcg_global_mem_new(TCG_AREG0,
3569 offsetof(CPUState, pc),
3570 "pc");
3571 env_btarget = tcg_global_mem_new(TCG_AREG0,
3572 offsetof(CPUState, btarget),
3573 "btarget");
3574 env_btaken = tcg_global_mem_new(TCG_AREG0,
3575 offsetof(CPUState, btaken),
3576 "btaken");
3577 for (i = 0; i < 16; i++) {
3578 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
3579 offsetof(CPUState, regs[i]),
3580 regnames[i]);
3581 }
3582 for (i = 0; i < 16; i++) {
3583 cpu_PR[i] = tcg_global_mem_new(TCG_AREG0,
3584 offsetof(CPUState, pregs[i]),
3585 pregnames[i]);
3586 }
3587
3588 return env;
3589 }
3590
3591 void cpu_reset (CPUCRISState *env)
3592 {
3593 uint32_t vr;
3594
3595 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
3596 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
3597 log_cpu_state(env, 0);
3598 }
3599
3600 vr = env->pregs[PR_VR];
3601 memset(env, 0, offsetof(CPUCRISState, breakpoints));
3602 env->pregs[PR_VR] = vr;
3603 tlb_flush(env, 1);
3604
3605 #if defined(CONFIG_USER_ONLY)
3606 /* start in user mode with interrupts enabled. */
3607 env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG;
3608 #else
3609 cris_mmu_init(env);
3610 env->pregs[PR_CCS] = 0;
3611 #endif
3612 }
3613
3614 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
3615 unsigned long searched_pc, int pc_pos, void *puc)
3616 {
3617 env->pc = gen_opc_pc[pc_pos];
3618 }
various patches