hw/mcf5208.c

   1 /*
   2  * Motorola ColdFire MCF5208 SoC emulation.
   3  *
   4  * Copyright (c) 2007 CodeSourcery.
   5  *
   6  * This code is licensed under the GPL
   7  */
   8 #include "hw.h"
   9 #include "mcf.h"
  10 #include "qemu-timer.h"
  11 #include "sysemu.h"
  12 #include "net.h"
  13 #include "boards.h"
  14 #include "loader.h"
  15 #include "elf.h"
  16
  17 #define SYS_FREQ 66000000
  18
  19 #define PCSR_EN         0x0001
  20 #define PCSR_RLD        0x0002
  21 #define PCSR_PIF        0x0004
  22 #define PCSR_PIE        0x0008
  23 #define PCSR_OVW        0x0010
  24 #define PCSR_DBG        0x0020
  25 #define PCSR_DOZE       0x0040
  26 #define PCSR_PRE_SHIFT  8
  27 #define PCSR_PRE_MASK   0x0f00
  28
  29 typedef struct {
  30     qemu_irq irq;
  31     ptimer_state *timer;
  32     uint16_t pcsr;
  33     uint16_t pmr;
  34     uint16_t pcntr;
  35 } m5208_timer_state;
  36
  37 static void m5208_timer_update(m5208_timer_state *s)
  38 {
  39     if ((s->pcsr & (PCSR_PIE | PCSR_PIF)) == (PCSR_PIE | PCSR_PIF))
  40         qemu_irq_raise(s->irq);
  41     else
  42         qemu_irq_lower(s->irq);
  43 }
  44
  45 static void m5208_timer_write(void *opaque, target_phys_addr_t offset,
  46                               uint32_t value)
  47 {
  48     m5208_timer_state *s = (m5208_timer_state *)opaque;
  49     int prescale;
  50     int limit;
  51     switch (offset) {
  52     case 0:
  53         /* The PIF bit is set-to-clear.  */
  54         if (value & PCSR_PIF) {
  55             s->pcsr &= ~PCSR_PIF;
  56             value &= ~PCSR_PIF;
  57         }
  58         /* Avoid frobbing the timer if we're just twiddling IRQ bits. */
  59         if (((s->pcsr ^ value) & ~PCSR_PIE) == 0) {
  60             s->pcsr = value;
  61             m5208_timer_update(s);
  62             return;
  63         }
  64
  65         if (s->pcsr & PCSR_EN)
  66             ptimer_stop(s->timer);
  67
  68         s->pcsr = value;
  69
  70         prescale = 1 << ((s->pcsr & PCSR_PRE_MASK) >> PCSR_PRE_SHIFT);
  71         ptimer_set_freq(s->timer, (SYS_FREQ / 2) / prescale);
  72         if (s->pcsr & PCSR_RLD)
  73             limit = s->pmr;
  74         else
  75             limit = 0xffff;
  76         ptimer_set_limit(s->timer, limit, 0);
  77
  78         if (s->pcsr & PCSR_EN)
  79             ptimer_run(s->timer, 0);
  80         break;
  81     case 2:
  82         s->pmr = value;
  83         s->pcsr &= ~PCSR_PIF;
  84         if ((s->pcsr & PCSR_RLD) == 0) {
  85             if (s->pcsr & PCSR_OVW)
  86                 ptimer_set_count(s->timer, value);
  87         } else {
  88             ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW);
  89         }
  90         break;
  91     case 4:
  92         break;
  93     default:
  94         hw_error("m5208_timer_write: Bad offset 0x%x\n", (int)offset);
  95         break;
  96     }
  97     m5208_timer_update(s);
  98 }
  99
 100 static void m5208_timer_trigger(void *opaque)
 101 {
 102     m5208_timer_state *s = (m5208_timer_state *)opaque;
 103     s->pcsr |= PCSR_PIF;
 104     m5208_timer_update(s);
 105 }
 106
 107 static uint32_t m5208_timer_read(void *opaque, target_phys_addr_t addr)
 108 {
 109     m5208_timer_state *s = (m5208_timer_state *)opaque;
 110     switch (addr) {
 111     case 0:
 112         return s->pcsr;
 113     case 2:
 114         return s->pmr;
 115     case 4:
 116         return ptimer_get_count(s->timer);
 117     default:
 118         hw_error("m5208_timer_read: Bad offset 0x%x\n", (int)addr);
 119         return 0;
 120     }
 121 }
 122
 123 static CPUReadMemoryFunc * const m5208_timer_readfn[] = {
 124    m5208_timer_read,
 125    m5208_timer_read,
 126    m5208_timer_read
 127 };
 128
 129 static CPUWriteMemoryFunc * const m5208_timer_writefn[] = {
 130    m5208_timer_write,
 131    m5208_timer_write,
 132    m5208_timer_write
 133 };
 134
 135 static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr)
 136 {
 137     switch (addr) {
 138     case 0x110: /* SDCS0 */
 139         {
 140             int n;
 141             for (n = 0; n < 32; n++) {
 142                 if (ram_size < (2u << n))
 143                     break;
 144             }
 145             return (n - 1)  | 0x40000000;
 146         }
 147     case 0x114: /* SDCS1 */
 148         return 0;
 149
 150     default:
 151         hw_error("m5208_sys_read: Bad offset 0x%x\n", (int)addr);
 152         return 0;
 153     }
 154 }
 155
 156 static void m5208_sys_write(void *opaque, target_phys_addr_t addr,
 157                             uint32_t value)
 158 {
 159     hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr);
 160 }
 161
 162 static CPUReadMemoryFunc * const m5208_sys_readfn[] = {
 163    m5208_sys_read,
 164    m5208_sys_read,
 165    m5208_sys_read
 166 };
 167
 168 static CPUWriteMemoryFunc * const m5208_sys_writefn[] = {
 169    m5208_sys_write,
 170    m5208_sys_write,
 171    m5208_sys_write
 172 };
 173
 174 static void mcf5208_sys_init(qemu_irq *pic)
 175 {
 176     int iomemtype;
 177     m5208_timer_state *s;
 178     QEMUBH *bh;
 179     int i;
 180
 181     iomemtype = cpu_register_io_memory(m5208_sys_readfn,
 182                                        m5208_sys_writefn, NULL,
 183                                        DEVICE_NATIVE_ENDIAN);
 184     /* SDRAMC.  */
 185     cpu_register_physical_memory(0xfc0a8000, 0x00004000, iomemtype);
 186     /* Timers.  */
 187     for (i = 0; i < 2; i++) {
 188         s = (m5208_timer_state *)g_malloc0(sizeof(m5208_timer_state));
 189         bh = qemu_bh_new(m5208_timer_trigger, s);
 190         s->timer = ptimer_init(bh);
 191         iomemtype = cpu_register_io_memory(m5208_timer_readfn,
 192                                            m5208_timer_writefn, s,
 193                                            DEVICE_NATIVE_ENDIAN);
 194         cpu_register_physical_memory(0xfc080000 + 0x4000 * i, 0x00004000,
 195                                      iomemtype);
 196         s->irq = pic[4 + i];
 197     }
 198 }
 199
 200 static void mcf5208evb_init(ram_addr_t ram_size,
 201                      const char *boot_device,
 202                      const char *kernel_filename, const char *kernel_cmdline,
 203                      const char *initrd_filename, const char *cpu_model)
 204 {
 205     CPUState *env;
 206     int kernel_size;
 207     uint64_t elf_entry;
 208     target_phys_addr_t entry;
 209     qemu_irq *pic;
 210
 211     if (!cpu_model)
 212         cpu_model = "m5208";
 213     env = cpu_init(cpu_model);
 214     if (!env) {
 215         fprintf(stderr, "Unable to find m68k CPU definition\n");
 216         exit(1);
 217     }
 218
 219     /* Initialize CPU registers.  */
 220     env->vbr = 0;
 221     /* TODO: Configure BARs.  */
 222
 223     /* DRAM at 0x40000000 */
 224     cpu_register_physical_memory(0x40000000, ram_size,
 225         qemu_ram_alloc(NULL, "mcf5208.ram", ram_size) | IO_MEM_RAM);
 226
 227     /* Internal SRAM.  */
 228     cpu_register_physical_memory(0x80000000, 16384,
 229         qemu_ram_alloc(NULL, "mcf5208.sram", 16384) | IO_MEM_RAM);
 230
 231     /* Internal peripherals.  */
 232     pic = mcf_intc_init(0xfc048000, env);
 233
 234     mcf_uart_mm_init(0xfc060000, pic[26], serial_hds[0]);
 235     mcf_uart_mm_init(0xfc064000, pic[27], serial_hds[1]);
 236     mcf_uart_mm_init(0xfc068000, pic[28], serial_hds[2]);
 237
 238     mcf5208_sys_init(pic);
 239
 240     if (nb_nics > 1) {
 241         fprintf(stderr, "Too many NICs\n");
 242         exit(1);
 243     }
 244     if (nd_table[0].vlan)
 245         mcf_fec_init(&nd_table[0], 0xfc030000, pic + 36);
 246
 247     /*  0xfc000000 SCM.  */
 248     /*  0xfc004000 XBS.  */
 249     /*  0xfc008000 FlexBus CS.  */
 250     /* 0xfc030000 FEC.  */
 251     /*  0xfc040000 SCM + Power management.  */
 252     /*  0xfc044000 eDMA.  */
 253     /* 0xfc048000 INTC.  */
 254     /*  0xfc058000 I2C.  */
 255     /*  0xfc05c000 QSPI.  */
 256     /* 0xfc060000 UART0.  */
 257     /* 0xfc064000 UART0.  */
 258     /* 0xfc068000 UART0.  */
 259     /*  0xfc070000 DMA timers.  */
 260     /* 0xfc080000 PIT0.  */
 261     /* 0xfc084000 PIT1.  */
 262     /*  0xfc088000 EPORT.  */
 263     /*  0xfc08c000 Watchdog.  */
 264     /*  0xfc090000 clock module.  */
 265     /*  0xfc0a0000 CCM + reset.  */
 266     /*  0xfc0a4000 GPIO.  */
 267     /* 0xfc0a8000 SDRAM controller.  */
 268
 269     /* Load kernel.  */
 270     if (!kernel_filename) {
 271         fprintf(stderr, "Kernel image must be specified\n");
 272         exit(1);
 273     }
 274
 275     kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry,
 276                            NULL, NULL, 1, ELF_MACHINE, 0);
 277     entry = elf_entry;
 278     if (kernel_size < 0) {
 279         kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL);
 280     }
 281     if (kernel_size < 0) {
 282         kernel_size = load_image_targphys(kernel_filename, 0x40000000,
 283                                           ram_size);
 284         entry = 0x40000000;
 285     }
 286     if (kernel_size < 0) {
 287         fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
 288         exit(1);
 289     }
 290
 291     env->pc = entry;
 292 }
 293
 294 static QEMUMachine mcf5208evb_machine = {
 295     .name = "mcf5208evb",
 296     .desc = "MCF5206EVB",
 297     .init = mcf5208evb_init,
 298     .is_default = 1,
 299 };
 300
 301 static void mcf5208evb_machine_init(void)
 302 {
 303     qemu_register_machine(&mcf5208evb_machine);
 304 }
 305
 306 machine_init(mcf5208evb_machine_init);