exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef _EXEC_ALL_H_
  21 #define _EXEC_ALL_H_
  22
  23 #include "qemu-common.h"
  24
  25 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  26 #define DEBUG_DISAS
  27
  28 /* Page tracking code uses ram addresses in system mode, and virtual
  29    addresses in userspace mode.  Define tb_page_addr_t to be an appropriate
  30    type.  */
  31 #if defined(CONFIG_USER_ONLY)
  32 typedef abi_ulong tb_page_addr_t;
  33 #else
  34 typedef ram_addr_t tb_page_addr_t;
  35 #endif
  36
  37 /* is_jmp field values */
  38 #define DISAS_NEXT    0 /* next instruction can be analyzed */
  39 #define DISAS_JUMP    1 /* only pc was modified dynamically */
  40 #define DISAS_UPDATE  2 /* cpu state was modified dynamically */
  41 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
  42
  43 typedef struct TranslationBlock TranslationBlock;
  44
  45 /* XXX: make safe guess about sizes */
  46 #define MAX_OP_PER_INSTR 96
  47
  48 #if HOST_LONG_BITS == 32
  49 #define MAX_OPC_PARAM_PER_ARG 2
  50 #else
  51 #define MAX_OPC_PARAM_PER_ARG 1
  52 #endif
  53 #define MAX_OPC_PARAM_IARGS 4
  54 #define MAX_OPC_PARAM_OARGS 1
  55 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
  56
  57 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
  58  * and up to 4 + N parameters on 64-bit archs
  59  * (N = number of input arguments + output arguments).  */
  60 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
  61 #define OPC_BUF_SIZE 640
  62 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  63
  64 /* Maximum size a TCG op can expand to.  This is complicated because a
  65    single op may require several host instructions and register reloads.
  66    For now take a wild guess at 192 bytes, which should allow at least
  67    a couple of fixup instructions per argument.  */
  68 #define TCG_MAX_OP_SIZE 192
  69
  70 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
  71
  72 extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
  73 extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
  74 extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
  75
  76 #include "qemu-log.h"
  77
  78 void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
  79 void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
  80 void restore_state_to_opc(CPUState *env, struct TranslationBlock *tb,
  81                           int pc_pos);
  82
  83 void cpu_gen_init(void);
  84 int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
  85                  int *gen_code_size_ptr);
  86 int cpu_restore_state(struct TranslationBlock *tb,
  87                       CPUState *env, unsigned long searched_pc,
  88                       void *puc);
  89 void cpu_resume_from_signal(CPUState *env1, void *puc);
  90 void cpu_io_recompile(CPUState *env, void *retaddr);
  91 TranslationBlock *tb_gen_code(CPUState *env,
  92                               target_ulong pc, target_ulong cs_base, int flags,
  93                               int cflags);
  94 void cpu_exec_init(CPUState *env);
  95 void QEMU_NORETURN cpu_loop_exit(void);
  96 int page_unprotect(target_ulong address, unsigned long pc, void *puc);
  97 void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
  98                                    int is_cpu_write_access);
  99 void tb_invalidate_page_range(target_ulong start, target_ulong end);
 100 void tlb_flush_page(CPUState *env, target_ulong addr);
 101 void tlb_flush(CPUState *env, int flush_global);
 102 #if !defined(CONFIG_USER_ONLY)
 103 void tlb_set_page(CPUState *env, target_ulong vaddr,
 104                   target_phys_addr_t paddr, int prot,
 105                   int mmu_idx, target_ulong size);
 106 #endif
 107
 108 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 109
 110 #define CODE_GEN_PHYS_HASH_BITS     15
 111 #define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
 112
 113 #define MIN_CODE_GEN_BUFFER_SIZE     (1024 * 1024)
 114
 115 /* estimated block size for TB allocation */
 116 /* XXX: use a per code average code fragment size and modulate it
 117    according to the host CPU */
 118 #if defined(CONFIG_SOFTMMU)
 119 #define CODE_GEN_AVG_BLOCK_SIZE 128
 120 #else
 121 #define CODE_GEN_AVG_BLOCK_SIZE 64
 122 #endif
 123
 124 #if defined(_ARCH_PPC) || defined(__x86_64__) || defined(__arm__) || defined(__i386__)
 125 #define USE_DIRECT_JUMP
 126 #endif
 127
 128 struct TranslationBlock {
 129     target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
 130     target_ulong cs_base; /* CS base for this block */
 131     uint64_t flags; /* flags defining in which context the code was generated */
 132     uint16_t size;      /* size of target code for this block (1 <=
 133                            size <= TARGET_PAGE_SIZE) */
 134     uint16_t cflags;    /* compile flags */
 135 #define CF_COUNT_MASK  0x7fff
 136 #define CF_LAST_IO     0x8000 /* Last insn may be an IO access.  */
 137
 138     uint8_t *tc_ptr;    /* pointer to the translated code */
 139     /* next matching tb for physical address. */
 140     struct TranslationBlock *phys_hash_next;
 141     /* first and second physical page containing code. The lower bit
 142        of the pointer tells the index in page_next[] */
 143     struct TranslationBlock *page_next[2];
 144     tb_page_addr_t page_addr[2];
 145
 146     /* the following data are used to directly call another TB from
 147        the code of this one. */
 148     uint16_t tb_next_offset[2]; /* offset of original jump target */
 149 #ifdef USE_DIRECT_JUMP
 150     uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
 151 #else
 152     unsigned long tb_next[2]; /* address of jump generated code */
 153 #endif
 154     /* list of TBs jumping to this one. This is a circular list using
 155        the two least significant bits of the pointers to tell what is
 156        the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
 157        jmp_first */
 158     struct TranslationBlock *jmp_next[2];
 159     struct TranslationBlock *jmp_first;
 160     uint32_t icount;
 161 };
 162
 163 static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
 164 {
 165     target_ulong tmp;
 166     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 167     return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
 168 }
 169
 170 static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
 171 {
 172     target_ulong tmp;
 173     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 174     return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
 175             | (tmp & TB_JMP_ADDR_MASK));
 176 }
 177
 178 static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc)
 179 {
 180     return (pc >> 2) & (CODE_GEN_PHYS_HASH_SIZE - 1);
 181 }
 182
 183 void tb_free(TranslationBlock *tb);
 184 void tb_flush(CPUState *env);
 185 void tb_link_page(TranslationBlock *tb,
 186                   tb_page_addr_t phys_pc, tb_page_addr_t phys_page2);
 187 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
 188
 189 extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 190
 191 #if defined(USE_DIRECT_JUMP)
 192
 193 #if defined(_ARCH_PPC)
 194 void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr);
 195 #define tb_set_jmp_target1 ppc_tb_set_jmp_target
 196 #elif defined(__i386__) || defined(__x86_64__)
 197 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 198 {
 199     /* patch the branch destination */
 200     *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
 201     /* no need to flush icache explicitly */
 202 }
 203 #elif defined(__arm__)
 204 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 205 {
 206 #if !QEMU_GNUC_PREREQ(4, 1)
 207     register unsigned long _beg __asm ("a1");
 208     register unsigned long _end __asm ("a2");
 209     register unsigned long _flg __asm ("a3");
 210 #endif
 211
 212     /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
 213     *(uint32_t *)jmp_addr =
 214         (*(uint32_t *)jmp_addr & ~0xffffff)
 215         | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);
 216
 217 #if QEMU_GNUC_PREREQ(4, 1)
 218     __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
 219 #else
 220     /* flush icache */
 221     _beg = jmp_addr;
 222     _end = jmp_addr + 4;
 223     _flg = 0;
 224     __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
 225 #endif
 226 }
 227 #endif
 228
 229 static inline void tb_set_jmp_target(TranslationBlock *tb,
 230                                      int n, unsigned long addr)
 231 {
 232     unsigned long offset;
 233
 234     offset = tb->tb_jmp_offset[n];
 235     tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 236 }
 237
 238 #else
 239
 240 /* set the jump target */
 241 static inline void tb_set_jmp_target(TranslationBlock *tb,
 242                                      int n, unsigned long addr)
 243 {
 244     tb->tb_next[n] = addr;
 245 }
 246
 247 #endif
 248
 249 static inline void tb_add_jump(TranslationBlock *tb, int n,
 250                                TranslationBlock *tb_next)
 251 {
 252     /* NOTE: this test is only needed for thread safety */
 253     if (!tb->jmp_next[n]) {
 254         /* patch the native jump address */
 255         tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
 256
 257         /* add in TB jmp circular list */
 258         tb->jmp_next[n] = tb_next->jmp_first;
 259         tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
 260     }
 261 }
 262
 263 TranslationBlock *tb_find_pc(unsigned long pc_ptr);
 264
 265 #include "qemu-lock.h"
 266
 267 extern spinlock_t tb_lock;
 268
 269 extern int tb_invalidated_flag;
 270
 271 #if !defined(CONFIG_USER_ONLY)
 272
 273 extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
 274 extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
 275 extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
 276
 277 void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
 278               void *retaddr);
 279
 280 #include "softmmu_defs.h"
 281
 282 #define ACCESS_TYPE (NB_MMU_MODES + 1)
 283 #define MEMSUFFIX _code
 284 #define env cpu_single_env
 285
 286 #define DATA_SIZE 1
 287 #include "softmmu_header.h"
 288
 289 #define DATA_SIZE 2
 290 #include "softmmu_header.h"
 291
 292 #define DATA_SIZE 4
 293 #include "softmmu_header.h"
 294
 295 #define DATA_SIZE 8
 296 #include "softmmu_header.h"
 297
 298 #undef ACCESS_TYPE
 299 #undef MEMSUFFIX
 300 #undef env
 301
 302 #endif
 303
 304 #if defined(CONFIG_USER_ONLY)
 305 static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
 306 {
 307     return addr;
 308 }
 309 #else
 310 /* NOTE: this function can trigger an exception */
 311 /* NOTE2: the returned address is not exactly the physical address: it
 312    is the offset relative to phys_ram_base */
 313 static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
 314 {
 315     int mmu_idx, page_index, pd;
 316     void *p;
 317
 318     page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 319     mmu_idx = cpu_mmu_index(env1);
 320     if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
 321                  (addr & TARGET_PAGE_MASK))) {
 322         ldub_code(addr);
 323     }
 324     pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
 325     if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
 326 #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
 327         do_unassigned_access(addr, 0, 1, 0, 4);
 328 #else
 329         cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
 330 #endif
 331     }
 332     p = (void *)(unsigned long)addr
 333         + env1->tlb_table[mmu_idx][page_index].addend;
 334     return qemu_ram_addr_from_host_nofail(p);
 335 }
 336 #endif
 337
 338 typedef void (CPUDebugExcpHandler)(CPUState *env);
 339
 340 CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler);
 341
 342 /* vl.c */
 343 extern int singlestep;
 344
 345 /* cpu-exec.c */
 346 extern volatile sig_atomic_t exit_request;
 347
 348 #endif