hw/pxa2xx_lcd.c

   1 /*
   2  * Intel XScale PXA255/270 LCDC emulation.
   3  *
   4  * Copyright (c) 2006 Openedhand Ltd.
   5  * Written by Andrzej Zaborowski <balrog@zabor.org>
   6  *
   7  * This code is licensed under the GPLv2.
   8  */
   9
  10 #include "hw.h"
  11 #include "console.h"
  12 #include "pxa.h"
  13 #include "pixel_ops.h"
  14 /* FIXME: For graphic_rotate. Should probably be done in common code.  */
  15 #include "sysemu.h"
  16 #include "framebuffer.h"
  17
  18 struct pxa2xx_lcdc_s {
  19     qemu_irq irq;
  20     int irqlevel;
  21
  22     int invalidated;
  23     DisplayState *ds;
  24     drawfn *line_fn[2];
  25     int dest_width;
  26     int xres, yres;
  27     int pal_for;
  28     int transp;
  29     enum {
  30         pxa_lcdc_2bpp = 1,
  31         pxa_lcdc_4bpp = 2,
  32         pxa_lcdc_8bpp = 3,
  33         pxa_lcdc_16bpp = 4,
  34         pxa_lcdc_18bpp = 5,
  35         pxa_lcdc_18pbpp = 6,
  36         pxa_lcdc_19bpp = 7,
  37         pxa_lcdc_19pbpp = 8,
  38         pxa_lcdc_24bpp = 9,
  39         pxa_lcdc_25bpp = 10,
  40     } bpp;
  41
  42     uint32_t control[6];
  43     uint32_t status[2];
  44     uint32_t ovl1c[2];
  45     uint32_t ovl2c[2];
  46     uint32_t ccr;
  47     uint32_t cmdcr;
  48     uint32_t trgbr;
  49     uint32_t tcr;
  50     uint32_t liidr;
  51     uint8_t bscntr;
  52
  53     struct {
  54         target_phys_addr_t branch;
  55         int up;
  56         uint8_t palette[1024];
  57         uint8_t pbuffer[1024];
  58         void (*redraw)(struct pxa2xx_lcdc_s *s, target_phys_addr_t addr,
  59                         int *miny, int *maxy);
  60
  61         target_phys_addr_t descriptor;
  62         target_phys_addr_t source;
  63         uint32_t id;
  64         uint32_t command;
  65     } dma_ch[7];
  66
  67     qemu_irq vsync_cb;
  68     int orientation;
  69 };
  70
  71 struct __attribute__ ((__packed__)) pxa_frame_descriptor_s {
  72     uint32_t fdaddr;
  73     uint32_t fsaddr;
  74     uint32_t fidr;
  75     uint32_t ldcmd;
  76 };
  77
  78 #define LCCR0   0x000   /* LCD Controller Control register 0 */
  79 #define LCCR1   0x004   /* LCD Controller Control register 1 */
  80 #define LCCR2   0x008   /* LCD Controller Control register 2 */
  81 #define LCCR3   0x00c   /* LCD Controller Control register 3 */
  82 #define LCCR4   0x010   /* LCD Controller Control register 4 */
  83 #define LCCR5   0x014   /* LCD Controller Control register 5 */
  84
  85 #define FBR0    0x020   /* DMA Channel 0 Frame Branch register */
  86 #define FBR1    0x024   /* DMA Channel 1 Frame Branch register */
  87 #define FBR2    0x028   /* DMA Channel 2 Frame Branch register */
  88 #define FBR3    0x02c   /* DMA Channel 3 Frame Branch register */
  89 #define FBR4    0x030   /* DMA Channel 4 Frame Branch register */
  90 #define FBR5    0x110   /* DMA Channel 5 Frame Branch register */
  91 #define FBR6    0x114   /* DMA Channel 6 Frame Branch register */
  92
  93 #define LCSR1   0x034   /* LCD Controller Status register 1 */
  94 #define LCSR0   0x038   /* LCD Controller Status register 0 */
  95 #define LIIDR   0x03c   /* LCD Controller Interrupt ID register */
  96
  97 #define TRGBR   0x040   /* TMED RGB Seed register */
  98 #define TCR     0x044   /* TMED Control register */
  99
 100 #define OVL1C1  0x050   /* Overlay 1 Control register 1 */
 101 #define OVL1C2  0x060   /* Overlay 1 Control register 2 */
 102 #define OVL2C1  0x070   /* Overlay 2 Control register 1 */
 103 #define OVL2C2  0x080   /* Overlay 2 Control register 2 */
 104 #define CCR     0x090   /* Cursor Control register */
 105
 106 #define CMDCR   0x100   /* Command Control register */
 107 #define PRSR    0x104   /* Panel Read Status register */
 108
 109 #define PXA_LCDDMA_CHANS        7
 110 #define DMA_FDADR               0x00    /* Frame Descriptor Address register */
 111 #define DMA_FSADR               0x04    /* Frame Source Address register */
 112 #define DMA_FIDR                0x08    /* Frame ID register */
 113 #define DMA_LDCMD               0x0c    /* Command register */
 114
 115 /* LCD Buffer Strength Control register */
 116 #define BSCNTR  0x04000054
 117
 118 /* Bitfield masks */
 119 #define LCCR0_ENB       (1 << 0)
 120 #define LCCR0_CMS       (1 << 1)
 121 #define LCCR0_SDS       (1 << 2)
 122 #define LCCR0_LDM       (1 << 3)
 123 #define LCCR0_SOFM0     (1 << 4)
 124 #define LCCR0_IUM       (1 << 5)
 125 #define LCCR0_EOFM0     (1 << 6)
 126 #define LCCR0_PAS       (1 << 7)
 127 #define LCCR0_DPD       (1 << 9)
 128 #define LCCR0_DIS       (1 << 10)
 129 #define LCCR0_QDM       (1 << 11)
 130 #define LCCR0_PDD       (0xff << 12)
 131 #define LCCR0_BSM0      (1 << 20)
 132 #define LCCR0_OUM       (1 << 21)
 133 #define LCCR0_LCDT      (1 << 22)
 134 #define LCCR0_RDSTM     (1 << 23)
 135 #define LCCR0_CMDIM     (1 << 24)
 136 #define LCCR0_OUC       (1 << 25)
 137 #define LCCR0_LDDALT    (1 << 26)
 138 #define LCCR1_PPL(x)    ((x) & 0x3ff)
 139 #define LCCR2_LPP(x)    ((x) & 0x3ff)
 140 #define LCCR3_API       (15 << 16)
 141 #define LCCR3_BPP(x)    ((((x) >> 24) & 7) | (((x) >> 26) & 8))
 142 #define LCCR3_PDFOR(x)  (((x) >> 30) & 3)
 143 #define LCCR4_K1(x)     (((x) >> 0) & 7)
 144 #define LCCR4_K2(x)     (((x) >> 3) & 7)
 145 #define LCCR4_K3(x)     (((x) >> 6) & 7)
 146 #define LCCR4_PALFOR(x) (((x) >> 15) & 3)
 147 #define LCCR5_SOFM(ch)  (1 << (ch - 1))
 148 #define LCCR5_EOFM(ch)  (1 << (ch + 7))
 149 #define LCCR5_BSM(ch)   (1 << (ch + 15))
 150 #define LCCR5_IUM(ch)   (1 << (ch + 23))
 151 #define OVLC1_EN        (1 << 31)
 152 #define CCR_CEN         (1 << 31)
 153 #define FBR_BRA         (1 << 0)
 154 #define FBR_BINT        (1 << 1)
 155 #define FBR_SRCADDR     (0xfffffff << 4)
 156 #define LCSR0_LDD       (1 << 0)
 157 #define LCSR0_SOF0      (1 << 1)
 158 #define LCSR0_BER       (1 << 2)
 159 #define LCSR0_ABC       (1 << 3)
 160 #define LCSR0_IU0       (1 << 4)
 161 #define LCSR0_IU1       (1 << 5)
 162 #define LCSR0_OU        (1 << 6)
 163 #define LCSR0_QD        (1 << 7)
 164 #define LCSR0_EOF0      (1 << 8)
 165 #define LCSR0_BS0       (1 << 9)
 166 #define LCSR0_SINT      (1 << 10)
 167 #define LCSR0_RDST      (1 << 11)
 168 #define LCSR0_CMDINT    (1 << 12)
 169 #define LCSR0_BERCH(x)  (((x) & 7) << 28)
 170 #define LCSR1_SOF(ch)   (1 << (ch - 1))
 171 #define LCSR1_EOF(ch)   (1 << (ch + 7))
 172 #define LCSR1_BS(ch)    (1 << (ch + 15))
 173 #define LCSR1_IU(ch)    (1 << (ch + 23))
 174 #define LDCMD_LENGTH(x) ((x) & 0x001ffffc)
 175 #define LDCMD_EOFINT    (1 << 21)
 176 #define LDCMD_SOFINT    (1 << 22)
 177 #define LDCMD_PAL       (1 << 26)
 178
 179 /* Route internal interrupt lines to the global IC */
 180 static void pxa2xx_lcdc_int_update(struct pxa2xx_lcdc_s *s)
 181 {
 182     int level = 0;
 183     level |= (s->status[0] & LCSR0_LDD)    && !(s->control[0] & LCCR0_LDM);
 184     level |= (s->status[0] & LCSR0_SOF0)   && !(s->control[0] & LCCR0_SOFM0);
 185     level |= (s->status[0] & LCSR0_IU0)    && !(s->control[0] & LCCR0_IUM);
 186     level |= (s->status[0] & LCSR0_IU1)    && !(s->control[5] & LCCR5_IUM(1));
 187     level |= (s->status[0] & LCSR0_OU)     && !(s->control[0] & LCCR0_OUM);
 188     level |= (s->status[0] & LCSR0_QD)     && !(s->control[0] & LCCR0_QDM);
 189     level |= (s->status[0] & LCSR0_EOF0)   && !(s->control[0] & LCCR0_EOFM0);
 190     level |= (s->status[0] & LCSR0_BS0)    && !(s->control[0] & LCCR0_BSM0);
 191     level |= (s->status[0] & LCSR0_RDST)   && !(s->control[0] & LCCR0_RDSTM);
 192     level |= (s->status[0] & LCSR0_CMDINT) && !(s->control[0] & LCCR0_CMDIM);
 193     level |= (s->status[1] & ~s->control[5]);
 194
 195     qemu_set_irq(s->irq, !!level);
 196     s->irqlevel = level;
 197 }
 198
 199 /* Set Branch Status interrupt high and poke associated registers */
 200 static inline void pxa2xx_dma_bs_set(struct pxa2xx_lcdc_s *s, int ch)
 201 {
 202     int unmasked;
 203     if (ch == 0) {
 204         s->status[0] |= LCSR0_BS0;
 205         unmasked = !(s->control[0] & LCCR0_BSM0);
 206     } else {
 207         s->status[1] |= LCSR1_BS(ch);
 208         unmasked = !(s->control[5] & LCCR5_BSM(ch));
 209     }
 210
 211     if (unmasked) {
 212         if (s->irqlevel)
 213             s->status[0] |= LCSR0_SINT;
 214         else
 215             s->liidr = s->dma_ch[ch].id;
 216     }
 217 }
 218
 219 /* Set Start Of Frame Status interrupt high and poke associated registers */
 220 static inline void pxa2xx_dma_sof_set(struct pxa2xx_lcdc_s *s, int ch)
 221 {
 222     int unmasked;
 223     if (!(s->dma_ch[ch].command & LDCMD_SOFINT))
 224         return;
 225
 226     if (ch == 0) {
 227         s->status[0] |= LCSR0_SOF0;
 228         unmasked = !(s->control[0] & LCCR0_SOFM0);
 229     } else {
 230         s->status[1] |= LCSR1_SOF(ch);
 231         unmasked = !(s->control[5] & LCCR5_SOFM(ch));
 232     }
 233
 234     if (unmasked) {
 235         if (s->irqlevel)
 236             s->status[0] |= LCSR0_SINT;
 237         else
 238             s->liidr = s->dma_ch[ch].id;
 239     }
 240 }
 241
 242 /* Set End Of Frame Status interrupt high and poke associated registers */
 243 static inline void pxa2xx_dma_eof_set(struct pxa2xx_lcdc_s *s, int ch)
 244 {
 245     int unmasked;
 246     if (!(s->dma_ch[ch].command & LDCMD_EOFINT))
 247         return;
 248
 249     if (ch == 0) {
 250         s->status[0] |= LCSR0_EOF0;
 251         unmasked = !(s->control[0] & LCCR0_EOFM0);
 252     } else {
 253         s->status[1] |= LCSR1_EOF(ch);
 254         unmasked = !(s->control[5] & LCCR5_EOFM(ch));
 255     }
 256
 257     if (unmasked) {
 258         if (s->irqlevel)
 259             s->status[0] |= LCSR0_SINT;
 260         else
 261             s->liidr = s->dma_ch[ch].id;
 262     }
 263 }
 264
 265 /* Set Bus Error Status interrupt high and poke associated registers */
 266 static inline void pxa2xx_dma_ber_set(struct pxa2xx_lcdc_s *s, int ch)
 267 {
 268     s->status[0] |= LCSR0_BERCH(ch) | LCSR0_BER;
 269     if (s->irqlevel)
 270         s->status[0] |= LCSR0_SINT;
 271     else
 272         s->liidr = s->dma_ch[ch].id;
 273 }
 274
 275 /* Set Read Status interrupt high and poke associated registers */
 276 static inline void pxa2xx_dma_rdst_set(struct pxa2xx_lcdc_s *s)
 277 {
 278     s->status[0] |= LCSR0_RDST;
 279     if (s->irqlevel && !(s->control[0] & LCCR0_RDSTM))
 280         s->status[0] |= LCSR0_SINT;
 281 }
 282
 283 /* Load new Frame Descriptors from DMA */
 284 static void pxa2xx_descriptor_load(struct pxa2xx_lcdc_s *s)
 285 {
 286     struct pxa_frame_descriptor_s desc;
 287     target_phys_addr_t descptr;
 288     int i;
 289
 290     for (i = 0; i < PXA_LCDDMA_CHANS; i ++) {
 291         s->dma_ch[i].source = 0;
 292
 293         if (!s->dma_ch[i].up)
 294             continue;
 295
 296         if (s->dma_ch[i].branch & FBR_BRA) {
 297             descptr = s->dma_ch[i].branch & FBR_SRCADDR;
 298             if (s->dma_ch[i].branch & FBR_BINT)
 299                 pxa2xx_dma_bs_set(s, i);
 300             s->dma_ch[i].branch &= ~FBR_BRA;
 301         } else
 302             descptr = s->dma_ch[i].descriptor;
 303
 304         if (!(descptr >= PXA2XX_SDRAM_BASE && descptr +
 305                     sizeof(desc) <= PXA2XX_SDRAM_BASE + ram_size))
 306             continue;
 307
 308         cpu_physical_memory_read(descptr, (void *)&desc, sizeof(desc));
 309         s->dma_ch[i].descriptor = tswap32(desc.fdaddr);
 310         s->dma_ch[i].source = tswap32(desc.fsaddr);
 311         s->dma_ch[i].id = tswap32(desc.fidr);
 312         s->dma_ch[i].command = tswap32(desc.ldcmd);
 313     }
 314 }
 315
 316 static uint32_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset)
 317 {
 318     struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
 319     int ch;
 320
 321     switch (offset) {
 322     case LCCR0:
 323         return s->control[0];
 324     case LCCR1:
 325         return s->control[1];
 326     case LCCR2:
 327         return s->control[2];
 328     case LCCR3:
 329         return s->control[3];
 330     case LCCR4:
 331         return s->control[4];
 332     case LCCR5:
 333         return s->control[5];
 334
 335     case OVL1C1:
 336         return s->ovl1c[0];
 337     case OVL1C2:
 338         return s->ovl1c[1];
 339     case OVL2C1:
 340         return s->ovl2c[0];
 341     case OVL2C2:
 342         return s->ovl2c[1];
 343
 344     case CCR:
 345         return s->ccr;
 346
 347     case CMDCR:
 348         return s->cmdcr;
 349
 350     case TRGBR:
 351         return s->trgbr;
 352     case TCR:
 353         return s->tcr;
 354
 355     case 0x200 ... 0x1000:      /* DMA per-channel registers */
 356         ch = (offset - 0x200) >> 4;
 357         if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
 358             goto fail;
 359
 360         switch (offset & 0xf) {
 361         case DMA_FDADR:
 362             return s->dma_ch[ch].descriptor;
 363         case DMA_FSADR:
 364             return s->dma_ch[ch].source;
 365         case DMA_FIDR:
 366             return s->dma_ch[ch].id;
 367         case DMA_LDCMD:
 368             return s->dma_ch[ch].command;
 369         default:
 370             goto fail;
 371         }
 372
 373     case FBR0:
 374         return s->dma_ch[0].branch;
 375     case FBR1:
 376         return s->dma_ch[1].branch;
 377     case FBR2:
 378         return s->dma_ch[2].branch;
 379     case FBR3:
 380         return s->dma_ch[3].branch;
 381     case FBR4:
 382         return s->dma_ch[4].branch;
 383     case FBR5:
 384         return s->dma_ch[5].branch;
 385     case FBR6:
 386         return s->dma_ch[6].branch;
 387
 388     case BSCNTR:
 389         return s->bscntr;
 390
 391     case PRSR:
 392         return 0;
 393
 394     case LCSR0:
 395         return s->status[0];
 396     case LCSR1:
 397         return s->status[1];
 398     case LIIDR:
 399         return s->liidr;
 400
 401     default:
 402     fail:
 403         cpu_abort(cpu_single_env,
 404                 "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
 405     }
 406
 407     return 0;
 408 }
 409
 410 static void pxa2xx_lcdc_write(void *opaque,
 411                 target_phys_addr_t offset, uint32_t value)
 412 {
 413     struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
 414     int ch;
 415
 416     switch (offset) {
 417     case LCCR0:
 418         /* ACK Quick Disable done */
 419         if ((s->control[0] & LCCR0_ENB) && !(value & LCCR0_ENB))
 420             s->status[0] |= LCSR0_QD;
 421
 422         if (!(s->control[0] & LCCR0_LCDT) && (value & LCCR0_LCDT))
 423             printf("%s: internal frame buffer unsupported\n", __FUNCTION__);
 424
 425         if ((s->control[3] & LCCR3_API) &&
 426                 (value & LCCR0_ENB) && !(value & LCCR0_LCDT))
 427             s->status[0] |= LCSR0_ABC;
 428
 429         s->control[0] = value & 0x07ffffff;
 430         pxa2xx_lcdc_int_update(s);
 431
 432         s->dma_ch[0].up = !!(value & LCCR0_ENB);
 433         s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) || (value & LCCR0_SDS);
 434         break;
 435
 436     case LCCR1:
 437         s->control[1] = value;
 438         break;
 439
 440     case LCCR2:
 441         s->control[2] = value;
 442         break;
 443
 444     case LCCR3:
 445         s->control[3] = value & 0xefffffff;
 446         s->bpp = LCCR3_BPP(value);
 447         break;
 448
 449     case LCCR4:
 450         s->control[4] = value & 0x83ff81ff;
 451         break;
 452
 453     case LCCR5:
 454         s->control[5] = value & 0x3f3f3f3f;
 455         break;
 456
 457     case OVL1C1:
 458         if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN))
 459             printf("%s: Overlay 1 not supported\n", __FUNCTION__);
 460
 461         s->ovl1c[0] = value & 0x80ffffff;
 462         s->dma_ch[1].up = (value & OVLC1_EN) || (s->control[0] & LCCR0_SDS);
 463         break;
 464
 465     case OVL1C2:
 466         s->ovl1c[1] = value & 0x000fffff;
 467         break;
 468
 469     case OVL2C1:
 470         if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN))
 471             printf("%s: Overlay 2 not supported\n", __FUNCTION__);
 472
 473         s->ovl2c[0] = value & 0x80ffffff;
 474         s->dma_ch[2].up = !!(value & OVLC1_EN);
 475         s->dma_ch[3].up = !!(value & OVLC1_EN);
 476         s->dma_ch[4].up = !!(value & OVLC1_EN);
 477         break;
 478
 479     case OVL2C2:
 480         s->ovl2c[1] = value & 0x007fffff;
 481         break;
 482
 483     case CCR:
 484         if (!(s->ccr & CCR_CEN) && (value & CCR_CEN))
 485             printf("%s: Hardware cursor unimplemented\n", __FUNCTION__);
 486
 487         s->ccr = value & 0x81ffffe7;
 488         s->dma_ch[5].up = !!(value & CCR_CEN);
 489         break;
 490
 491     case CMDCR:
 492         s->cmdcr = value & 0xff;
 493         break;
 494
 495     case TRGBR:
 496         s->trgbr = value & 0x00ffffff;
 497         break;
 498
 499     case TCR:
 500         s->tcr = value & 0x7fff;
 501         break;
 502
 503     case 0x200 ... 0x1000:      /* DMA per-channel registers */
 504         ch = (offset - 0x200) >> 4;
 505         if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
 506             goto fail;
 507
 508         switch (offset & 0xf) {
 509         case DMA_FDADR:
 510             s->dma_ch[ch].descriptor = value & 0xfffffff0;
 511             break;
 512
 513         default:
 514             goto fail;
 515         }
 516         break;
 517
 518     case FBR0:
 519         s->dma_ch[0].branch = value & 0xfffffff3;
 520         break;
 521     case FBR1:
 522         s->dma_ch[1].branch = value & 0xfffffff3;
 523         break;
 524     case FBR2:
 525         s->dma_ch[2].branch = value & 0xfffffff3;
 526         break;
 527     case FBR3:
 528         s->dma_ch[3].branch = value & 0xfffffff3;
 529         break;
 530     case FBR4:
 531         s->dma_ch[4].branch = value & 0xfffffff3;
 532         break;
 533     case FBR5:
 534         s->dma_ch[5].branch = value & 0xfffffff3;
 535         break;
 536     case FBR6:
 537         s->dma_ch[6].branch = value & 0xfffffff3;
 538         break;
 539
 540     case BSCNTR:
 541         s->bscntr = value & 0xf;
 542         break;
 543
 544     case PRSR:
 545         break;
 546
 547     case LCSR0:
 548         s->status[0] &= ~(value & 0xfff);
 549         if (value & LCSR0_BER)
 550             s->status[0] &= ~LCSR0_BERCH(7);
 551         break;
 552
 553     case LCSR1:
 554         s->status[1] &= ~(value & 0x3e3f3f);
 555         break;
 556
 557     default:
 558     fail:
 559         cpu_abort(cpu_single_env,
 560                 "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
 561     }
 562 }
 563
 564 static CPUReadMemoryFunc *pxa2xx_lcdc_readfn[] = {
 565     pxa2xx_lcdc_read,
 566     pxa2xx_lcdc_read,
 567     pxa2xx_lcdc_read
 568 };
 569
 570 static CPUWriteMemoryFunc *pxa2xx_lcdc_writefn[] = {
 571     pxa2xx_lcdc_write,
 572     pxa2xx_lcdc_write,
 573     pxa2xx_lcdc_write
 574 };
 575
 576 /* Load new palette for a given DMA channel, convert to internal format */
 577 static void pxa2xx_palette_parse(struct pxa2xx_lcdc_s *s, int ch, int bpp)
 578 {
 579     int i, n, format, r, g, b, alpha;
 580     uint32_t *dest, *src;
 581     s->pal_for = LCCR4_PALFOR(s->control[4]);
 582     format = s->pal_for;
 583
 584     switch (bpp) {
 585     case pxa_lcdc_2bpp:
 586         n = 4;
 587         break;
 588     case pxa_lcdc_4bpp:
 589         n = 16;
 590         break;
 591     case pxa_lcdc_8bpp:
 592         n = 256;
 593         break;
 594     default:
 595         format = 0;
 596         return;
 597     }
 598
 599     src = (uint32_t *) s->dma_ch[ch].pbuffer;
 600     dest = (uint32_t *) s->dma_ch[ch].palette;
 601     alpha = r = g = b = 0;
 602
 603     for (i = 0; i < n; i ++) {
 604         switch (format) {
 605         case 0: /* 16 bpp, no transparency */
 606             alpha = 0;
 607             if (s->control[0] & LCCR0_CMS)
 608                 r = g = b = *src & 0xff;
 609             else {
 610                 r = (*src & 0xf800) >> 8;
 611                 g = (*src & 0x07e0) >> 3;
 612                 b = (*src & 0x001f) << 3;
 613             }
 614             break;
 615         case 1: /* 16 bpp plus transparency */
 616             alpha = *src & (1 << 24);
 617             if (s->control[0] & LCCR0_CMS)
 618                 r = g = b = *src & 0xff;
 619             else {
 620                 r = (*src & 0xf800) >> 8;
 621                 g = (*src & 0x07e0) >> 3;
 622                 b = (*src & 0x001f) << 3;
 623             }
 624             break;
 625         case 2: /* 18 bpp plus transparency */
 626             alpha = *src & (1 << 24);
 627             if (s->control[0] & LCCR0_CMS)
 628                 r = g = b = *src & 0xff;
 629             else {
 630                 r = (*src & 0xf80000) >> 16;
 631                 g = (*src & 0x00fc00) >> 8;
 632                 b = (*src & 0x0000f8);
 633             }
 634             break;
 635         case 3: /* 24 bpp plus transparency */
 636             alpha = *src & (1 << 24);
 637             if (s->control[0] & LCCR0_CMS)
 638                 r = g = b = *src & 0xff;
 639             else {
 640                 r = (*src & 0xff0000) >> 16;
 641                 g = (*src & 0x00ff00) >> 8;
 642                 b = (*src & 0x0000ff);
 643             }
 644             break;
 645         }
 646         switch (ds_get_bits_per_pixel(s->ds)) {
 647         case 8:
 648             *dest = rgb_to_pixel8(r, g, b) | alpha;
 649             break;
 650         case 15:
 651             *dest = rgb_to_pixel15(r, g, b) | alpha;
 652             break;
 653         case 16:
 654             *dest = rgb_to_pixel16(r, g, b) | alpha;
 655             break;
 656         case 24:
 657             *dest = rgb_to_pixel24(r, g, b) | alpha;
 658             break;
 659         case 32:
 660             *dest = rgb_to_pixel32(r, g, b) | alpha;
 661             break;
 662         }
 663         src ++;
 664         dest ++;
 665     }
 666 }
 667
 668 static void pxa2xx_lcdc_dma0_redraw_horiz(struct pxa2xx_lcdc_s *s,
 669                 target_phys_addr_t addr, int *miny, int *maxy)
 670 {
 671     int src_width, dest_width;
 672     drawfn fn = 0;
 673     if (s->dest_width)
 674         fn = s->line_fn[s->transp][s->bpp];
 675     if (!fn)
 676         return;
 677
 678     src_width = (s->xres + 3) & ~3;     /* Pad to a 4 pixels multiple */
 679     if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
 680         src_width *= 3;
 681     else if (s->bpp > pxa_lcdc_16bpp)
 682         src_width *= 4;
 683     else if (s->bpp > pxa_lcdc_8bpp)
 684         src_width *= 2;
 685
 686     dest_width = s->xres * s->dest_width;
 687     *miny = 0;
 688     framebuffer_update_display(s->ds,
 689                                addr, s->xres, s->yres,
 690                                src_width, dest_width, s->dest_width,
 691                                s->invalidated,
 692                                fn, s->dma_ch[0].palette, miny, maxy);
 693 }
 694
 695 static void pxa2xx_lcdc_dma0_redraw_vert(struct pxa2xx_lcdc_s *s,
 696                target_phys_addr_t addr, int *miny, int *maxy)
 697 {
 698     int src_width, dest_width;
 699     drawfn fn = 0;
 700     if (s->dest_width)
 701         fn = s->line_fn[s->transp][s->bpp];
 702     if (!fn)
 703         return;
 704
 705     src_width = (s->xres + 3) & ~3;     /* Pad to a 4 pixels multiple */
 706     if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
 707         src_width *= 3;
 708     else if (s->bpp > pxa_lcdc_16bpp)
 709         src_width *= 4;
 710     else if (s->bpp > pxa_lcdc_8bpp)
 711         src_width *= 2;
 712
 713     dest_width = s->yres * s->dest_width;
 714     *miny = 0;
 715     framebuffer_update_display(s->ds,
 716                                addr, s->xres, s->yres,
 717                                src_width, s->dest_width, -dest_width,
 718                                s->invalidated,
 719                                fn, s->dma_ch[0].palette,
 720                                miny, maxy);
 721 }
 722
 723 static void pxa2xx_lcdc_resize(struct pxa2xx_lcdc_s *s)
 724 {
 725     int width, height;
 726     if (!(s->control[0] & LCCR0_ENB))
 727         return;
 728
 729     width = LCCR1_PPL(s->control[1]) + 1;
 730     height = LCCR2_LPP(s->control[2]) + 1;
 731
 732     if (width != s->xres || height != s->yres) {
 733         if (s->orientation)
 734             qemu_console_resize(s->ds, height, width);
 735         else
 736             qemu_console_resize(s->ds, width, height);
 737         s->invalidated = 1;
 738         s->xres = width;
 739         s->yres = height;
 740     }
 741 }
 742
 743 static void pxa2xx_update_display(void *opaque)
 744 {
 745     struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
 746     target_phys_addr_t fbptr;
 747     int miny, maxy;
 748     int ch;
 749     if (!(s->control[0] & LCCR0_ENB))
 750         return;
 751
 752     pxa2xx_descriptor_load(s);
 753
 754     pxa2xx_lcdc_resize(s);
 755     miny = s->yres;
 756     maxy = 0;
 757     s->transp = s->dma_ch[2].up || s->dma_ch[3].up;
 758     /* Note: With overlay planes the order depends on LCCR0 bit 25.  */
 759     for (ch = 0; ch < PXA_LCDDMA_CHANS; ch ++)
 760         if (s->dma_ch[ch].up) {
 761             if (!s->dma_ch[ch].source) {
 762                 pxa2xx_dma_ber_set(s, ch);
 763                 continue;
 764             }
 765             fbptr = s->dma_ch[ch].source;
 766             if (!(fbptr >= PXA2XX_SDRAM_BASE &&
 767                     fbptr <= PXA2XX_SDRAM_BASE + ram_size)) {
 768                 pxa2xx_dma_ber_set(s, ch);
 769                 continue;
 770             }
 771
 772             if (s->dma_ch[ch].command & LDCMD_PAL) {
 773                 cpu_physical_memory_read(fbptr, s->dma_ch[ch].pbuffer,
 774                     MAX(LDCMD_LENGTH(s->dma_ch[ch].command),
 775                         sizeof(s->dma_ch[ch].pbuffer)));
 776                 pxa2xx_palette_parse(s, ch, s->bpp);
 777             } else {
 778                 /* Do we need to reparse palette */
 779                 if (LCCR4_PALFOR(s->control[4]) != s->pal_for)
 780                     pxa2xx_palette_parse(s, ch, s->bpp);
 781
 782                 /* ACK frame start */
 783                 pxa2xx_dma_sof_set(s, ch);
 784
 785                 s->dma_ch[ch].redraw(s, fbptr, &miny, &maxy);
 786                 s->invalidated = 0;
 787
 788                 /* ACK frame completed */
 789                 pxa2xx_dma_eof_set(s, ch);
 790             }
 791         }
 792
 793     if (s->control[0] & LCCR0_DIS) {
 794         /* ACK last frame completed */
 795         s->control[0] &= ~LCCR0_ENB;
 796         s->status[0] |= LCSR0_LDD;
 797     }
 798
 799     if (miny >= 0) {
 800         if (s->orientation)
 801             dpy_update(s->ds, miny, 0, maxy, s->xres);
 802         else
 803             dpy_update(s->ds, 0, miny, s->xres, maxy);
 804     }
 805     pxa2xx_lcdc_int_update(s);
 806
 807     qemu_irq_raise(s->vsync_cb);
 808 }
 809
 810 static void pxa2xx_invalidate_display(void *opaque)
 811 {
 812     struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
 813     s->invalidated = 1;
 814 }
 815
 816 static void pxa2xx_screen_dump(void *opaque, const char *filename)
 817 {
 818     /* TODO */
 819 }
 820
 821 static void pxa2xx_lcdc_orientation(void *opaque, int angle)
 822 {
 823     struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
 824
 825     if (angle) {
 826         s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_vert;
 827     } else {
 828         s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_horiz;
 829     }
 830
 831     s->orientation = angle;
 832     s->xres = s->yres = -1;
 833     pxa2xx_lcdc_resize(s);
 834 }
 835
 836 static void pxa2xx_lcdc_save(QEMUFile *f, void *opaque)
 837 {
 838     struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
 839     int i;
 840
 841     qemu_put_be32(f, s->irqlevel);
 842     qemu_put_be32(f, s->transp);
 843
 844     for (i = 0; i < 6; i ++)
 845         qemu_put_be32s(f, &s->control[i]);
 846     for (i = 0; i < 2; i ++)
 847         qemu_put_be32s(f, &s->status[i]);
 848     for (i = 0; i < 2; i ++)
 849         qemu_put_be32s(f, &s->ovl1c[i]);
 850     for (i = 0; i < 2; i ++)
 851         qemu_put_be32s(f, &s->ovl2c[i]);
 852     qemu_put_be32s(f, &s->ccr);
 853     qemu_put_be32s(f, &s->cmdcr);
 854     qemu_put_be32s(f, &s->trgbr);
 855     qemu_put_be32s(f, &s->tcr);
 856     qemu_put_be32s(f, &s->liidr);
 857     qemu_put_8s(f, &s->bscntr);
 858
 859     for (i = 0; i < 7; i ++) {
 860         qemu_put_betl(f, s->dma_ch[i].branch);
 861         qemu_put_byte(f, s->dma_ch[i].up);
 862         qemu_put_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer));
 863
 864         qemu_put_betl(f, s->dma_ch[i].descriptor);
 865         qemu_put_betl(f, s->dma_ch[i].source);
 866         qemu_put_be32s(f, &s->dma_ch[i].id);
 867         qemu_put_be32s(f, &s->dma_ch[i].command);
 868     }
 869 }
 870
 871 static int pxa2xx_lcdc_load(QEMUFile *f, void *opaque, int version_id)
 872 {
 873     struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
 874     int i;
 875
 876     s->irqlevel = qemu_get_be32(f);
 877     s->transp = qemu_get_be32(f);
 878
 879     for (i = 0; i < 6; i ++)
 880         qemu_get_be32s(f, &s->control[i]);
 881     for (i = 0; i < 2; i ++)
 882         qemu_get_be32s(f, &s->status[i]);
 883     for (i = 0; i < 2; i ++)
 884         qemu_get_be32s(f, &s->ovl1c[i]);
 885     for (i = 0; i < 2; i ++)
 886         qemu_get_be32s(f, &s->ovl2c[i]);
 887     qemu_get_be32s(f, &s->ccr);
 888     qemu_get_be32s(f, &s->cmdcr);
 889     qemu_get_be32s(f, &s->trgbr);
 890     qemu_get_be32s(f, &s->tcr);
 891     qemu_get_be32s(f, &s->liidr);
 892     qemu_get_8s(f, &s->bscntr);
 893
 894     for (i = 0; i < 7; i ++) {
 895         s->dma_ch[i].branch = qemu_get_betl(f);
 896         s->dma_ch[i].up = qemu_get_byte(f);
 897         qemu_get_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer));
 898
 899         s->dma_ch[i].descriptor = qemu_get_betl(f);
 900         s->dma_ch[i].source = qemu_get_betl(f);
 901         qemu_get_be32s(f, &s->dma_ch[i].id);
 902         qemu_get_be32s(f, &s->dma_ch[i].command);
 903     }
 904
 905     s->bpp = LCCR3_BPP(s->control[3]);
 906     s->xres = s->yres = s->pal_for = -1;
 907
 908     return 0;
 909 }
 910
 911 #define BITS 8
 912 #include "pxa2xx_template.h"
 913 #define BITS 15
 914 #include "pxa2xx_template.h"
 915 #define BITS 16
 916 #include "pxa2xx_template.h"
 917 #define BITS 24
 918 #include "pxa2xx_template.h"
 919 #define BITS 32
 920 #include "pxa2xx_template.h"
 921
 922 struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq)
 923 {
 924     int iomemtype;
 925     struct pxa2xx_lcdc_s *s;
 926
 927     s = (struct pxa2xx_lcdc_s *) qemu_mallocz(sizeof(struct pxa2xx_lcdc_s));
 928     s->invalidated = 1;
 929     s->irq = irq;
 930
 931     pxa2xx_lcdc_orientation(s, graphic_rotate);
 932
 933     iomemtype = cpu_register_io_memory(0, pxa2xx_lcdc_readfn,
 934                     pxa2xx_lcdc_writefn, s);
 935     cpu_register_physical_memory(base, 0x00100000, iomemtype);
 936
 937     s->ds = graphic_console_init(pxa2xx_update_display,
 938                                  pxa2xx_invalidate_display,
 939                                  pxa2xx_screen_dump, NULL, s);
 940
 941     switch (ds_get_bits_per_pixel(s->ds)) {
 942     case 0:
 943         s->dest_width = 0;
 944         break;
 945     case 8:
 946         s->line_fn[0] = pxa2xx_draw_fn_8;
 947         s->line_fn[1] = pxa2xx_draw_fn_8t;
 948         s->dest_width = 1;
 949         break;
 950     case 15:
 951         s->line_fn[0] = pxa2xx_draw_fn_15;
 952         s->line_fn[1] = pxa2xx_draw_fn_15t;
 953         s->dest_width = 2;
 954         break;
 955     case 16:
 956         s->line_fn[0] = pxa2xx_draw_fn_16;
 957         s->line_fn[1] = pxa2xx_draw_fn_16t;
 958         s->dest_width = 2;
 959         break;
 960     case 24:
 961         s->line_fn[0] = pxa2xx_draw_fn_24;
 962         s->line_fn[1] = pxa2xx_draw_fn_24t;
 963         s->dest_width = 3;
 964         break;
 965     case 32:
 966         s->line_fn[0] = pxa2xx_draw_fn_32;
 967         s->line_fn[1] = pxa2xx_draw_fn_32t;
 968         s->dest_width = 4;
 969         break;
 970     default:
 971         fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
 972         exit(1);
 973     }
 974
 975     register_savevm("pxa2xx_lcdc", 0, 0,
 976                     pxa2xx_lcdc_save, pxa2xx_lcdc_load, s);
 977
 978     return s;
 979 }
 980
 981 void pxa2xx_lcd_vsync_notifier(struct pxa2xx_lcdc_s *s, qemu_irq handler)
 982 {
 983     s->vsync_cb = handler;
 984 }