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x86/cpuid: Fix crash on -cpu ""
[qemu/opensuse.git] / hw / ac97.c
blob0dbba3b54a5ee2ebbe97ebb1550375f22ecb8240
1 /*
2 * Copyright (C) 2006 InnoTek Systemberatung GmbH
3 *
4 * This file is part of VirtualBox Open Source Edition (OSE), as
5 * available from http://www.virtualbox.org. This file is free software;
6 * you can redistribute it and/or modify it under the terms of the GNU
7 * General Public License as published by the Free Software Foundation,
8 * in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
9 * distribution. VirtualBox OSE is distributed in the hope that it will
10 * be useful, but WITHOUT ANY WARRANTY of any kind.
11 *
12 * If you received this file as part of a commercial VirtualBox
13 * distribution, then only the terms of your commercial VirtualBox
14 * license agreement apply instead of the previous paragraph.
15 */
16
17 #include "hw.h"
18 #include "audiodev.h"
19 #include "audio/audio.h"
20 #include "pci.h"
21 #include "dma.h"
22
23 enum {
24 AC97_Reset = 0x00,
25 AC97_Master_Volume_Mute = 0x02,
26 AC97_Headphone_Volume_Mute = 0x04,
27 AC97_Master_Volume_Mono_Mute = 0x06,
28 AC97_Master_Tone_RL = 0x08,
29 AC97_PC_BEEP_Volume_Mute = 0x0A,
30 AC97_Phone_Volume_Mute = 0x0C,
31 AC97_Mic_Volume_Mute = 0x0E,
32 AC97_Line_In_Volume_Mute = 0x10,
33 AC97_CD_Volume_Mute = 0x12,
34 AC97_Video_Volume_Mute = 0x14,
35 AC97_Aux_Volume_Mute = 0x16,
36 AC97_PCM_Out_Volume_Mute = 0x18,
37 AC97_Record_Select = 0x1A,
38 AC97_Record_Gain_Mute = 0x1C,
39 AC97_Record_Gain_Mic_Mute = 0x1E,
40 AC97_General_Purpose = 0x20,
41 AC97_3D_Control = 0x22,
42 AC97_AC_97_RESERVED = 0x24,
43 AC97_Powerdown_Ctrl_Stat = 0x26,
44 AC97_Extended_Audio_ID = 0x28,
45 AC97_Extended_Audio_Ctrl_Stat = 0x2A,
46 AC97_PCM_Front_DAC_Rate = 0x2C,
47 AC97_PCM_Surround_DAC_Rate = 0x2E,
48 AC97_PCM_LFE_DAC_Rate = 0x30,
49 AC97_PCM_LR_ADC_Rate = 0x32,
50 AC97_MIC_ADC_Rate = 0x34,
51 AC97_6Ch_Vol_C_LFE_Mute = 0x36,
52 AC97_6Ch_Vol_L_R_Surround_Mute = 0x38,
53 AC97_Vendor_Reserved = 0x58,
54 AC97_Vendor_ID1 = 0x7c,
55 AC97_Vendor_ID2 = 0x7e
56 };
57
58 #define SOFT_VOLUME
59 #define SR_FIFOE 16 /* rwc */
60 #define SR_BCIS 8 /* rwc */
61 #define SR_LVBCI 4 /* rwc */
62 #define SR_CELV 2 /* ro */
63 #define SR_DCH 1 /* ro */
64 #define SR_VALID_MASK ((1 << 5) - 1)
65 #define SR_WCLEAR_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI)
66 #define SR_RO_MASK (SR_DCH | SR_CELV)
67 #define SR_INT_MASK (SR_FIFOE | SR_BCIS | SR_LVBCI)
68
69 #define CR_IOCE 16 /* rw */
70 #define CR_FEIE 8 /* rw */
71 #define CR_LVBIE 4 /* rw */
72 #define CR_RR 2 /* rw */
73 #define CR_RPBM 1 /* rw */
74 #define CR_VALID_MASK ((1 << 5) - 1)
75 #define CR_DONT_CLEAR_MASK (CR_IOCE | CR_FEIE | CR_LVBIE)
76
77 #define GC_WR 4 /* rw */
78 #define GC_CR 2 /* rw */
79 #define GC_VALID_MASK ((1 << 6) - 1)
80
81 #define GS_MD3 (1<<17) /* rw */
82 #define GS_AD3 (1<<16) /* rw */
83 #define GS_RCS (1<<15) /* rwc */
84 #define GS_B3S12 (1<<14) /* ro */
85 #define GS_B2S12 (1<<13) /* ro */
86 #define GS_B1S12 (1<<12) /* ro */
87 #define GS_S1R1 (1<<11) /* rwc */
88 #define GS_S0R1 (1<<10) /* rwc */
89 #define GS_S1CR (1<<9) /* ro */
90 #define GS_S0CR (1<<8) /* ro */
91 #define GS_MINT (1<<7) /* ro */
92 #define GS_POINT (1<<6) /* ro */
93 #define GS_PIINT (1<<5) /* ro */
94 #define GS_RSRVD ((1<<4)|(1<<3))
95 #define GS_MOINT (1<<2) /* ro */
96 #define GS_MIINT (1<<1) /* ro */
97 #define GS_GSCI 1 /* rwc */
98 #define GS_RO_MASK (GS_B3S12| \
99 GS_B2S12| \
100 GS_B1S12| \
101 GS_S1CR| \
102 GS_S0CR| \
103 GS_MINT| \
104 GS_POINT| \
105 GS_PIINT| \
106 GS_RSRVD| \
107 GS_MOINT| \
108 GS_MIINT)
109 #define GS_VALID_MASK ((1 << 18) - 1)
110 #define GS_WCLEAR_MASK (GS_RCS|GS_S1R1|GS_S0R1|GS_GSCI)
111
112 #define BD_IOC (1<<31)
113 #define BD_BUP (1<<30)
114
115 #define EACS_VRA 1
116 #define EACS_VRM 8
117
118 #define VOL_MASK 0x1f
119 #define MUTE_SHIFT 15
120
121 #define REC_MASK 7
122 enum {
123 REC_MIC = 0,
124 REC_CD,
125 REC_VIDEO,
126 REC_AUX,
127 REC_LINE_IN,
128 REC_STEREO_MIX,
129 REC_MONO_MIX,
130 REC_PHONE
131 };
132
133 typedef struct BD {
134 uint32_t addr;
135 uint32_t ctl_len;
136 } BD;
137
138 typedef struct AC97BusMasterRegs {
139 uint32_t bdbar; /* rw 0 */
140 uint8_t civ; /* ro 0 */
141 uint8_t lvi; /* rw 0 */
142 uint16_t sr; /* rw 1 */
143 uint16_t picb; /* ro 0 */
144 uint8_t piv; /* ro 0 */
145 uint8_t cr; /* rw 0 */
146 unsigned int bd_valid;
147 BD bd;
148 } AC97BusMasterRegs;
149
150 typedef struct AC97LinkState {
151 PCIDevice dev;
152 QEMUSoundCard card;
153 uint32_t use_broken_id;
154 uint32_t glob_cnt;
155 uint32_t glob_sta;
156 uint32_t cas;
157 uint32_t last_samp;
158 AC97BusMasterRegs bm_regs[3];
159 uint8_t mixer_data[256];
160 SWVoiceIn *voice_pi;
161 SWVoiceOut *voice_po;
162 SWVoiceIn *voice_mc;
163 int invalid_freq[3];
164 uint8_t silence[128];
165 int bup_flag;
166 MemoryRegion io_nam;
167 MemoryRegion io_nabm;
168 } AC97LinkState;
169
170 enum {
171 BUP_SET = 1,
172 BUP_LAST = 2
173 };
174
175 #ifdef DEBUG_AC97
176 #define dolog(...) AUD_log ("ac97", __VA_ARGS__)
177 #else
178 #define dolog(...)
179 #endif
180
181 #define MKREGS(prefix, start) \
182 enum { \
183 prefix ## _BDBAR = start, \
184 prefix ## _CIV = start + 4, \
185 prefix ## _LVI = start + 5, \
186 prefix ## _SR = start + 6, \
187 prefix ## _PICB = start + 8, \
188 prefix ## _PIV = start + 10, \
189 prefix ## _CR = start + 11 \
190 }
191
192 enum {
193 PI_INDEX = 0,
194 PO_INDEX,
195 MC_INDEX,
196 LAST_INDEX
197 };
198
199 MKREGS (PI, PI_INDEX * 16);
200 MKREGS (PO, PO_INDEX * 16);
201 MKREGS (MC, MC_INDEX * 16);
202
203 enum {
204 GLOB_CNT = 0x2c,
205 GLOB_STA = 0x30,
206 CAS = 0x34
207 };
208
209 #define GET_BM(index) (((index) >> 4) & 3)
210
211 static void po_callback (void *opaque, int free);
212 static void pi_callback (void *opaque, int avail);
213 static void mc_callback (void *opaque, int avail);
214
215 static void warm_reset (AC97LinkState *s)
216 {
217 (void) s;
218 }
219
220 static void cold_reset (AC97LinkState * s)
221 {
222 (void) s;
223 }
224
225 static void fetch_bd (AC97LinkState *s, AC97BusMasterRegs *r)
226 {
227 uint8_t b[8];
228
229 pci_dma_read (&s->dev, r->bdbar + r->civ * 8, b, 8);
230 r->bd_valid = 1;
231 r->bd.addr = le32_to_cpu (*(uint32_t *) &b[0]) & ~3;
232 r->bd.ctl_len = le32_to_cpu (*(uint32_t *) &b[4]);
233 r->picb = r->bd.ctl_len & 0xffff;
234 dolog ("bd %2d addr=%#x ctl=%#06x len=%#x(%d bytes)\n",
235 r->civ, r->bd.addr, r->bd.ctl_len >> 16,
236 r->bd.ctl_len & 0xffff,
237 (r->bd.ctl_len & 0xffff) << 1);
238 }
239
240 static void update_sr (AC97LinkState *s, AC97BusMasterRegs *r, uint32_t new_sr)
241 {
242 int event = 0;
243 int level = 0;
244 uint32_t new_mask = new_sr & SR_INT_MASK;
245 uint32_t old_mask = r->sr & SR_INT_MASK;
246 uint32_t masks[] = {GS_PIINT, GS_POINT, GS_MINT};
247
248 if (new_mask ^ old_mask) {
249 /** @todo is IRQ deasserted when only one of status bits is cleared? */
250 if (!new_mask) {
251 event = 1;
252 level = 0;
253 }
254 else {
255 if ((new_mask & SR_LVBCI) && (r->cr & CR_LVBIE)) {
256 event = 1;
257 level = 1;
258 }
259 if ((new_mask & SR_BCIS) && (r->cr & CR_IOCE)) {
260 event = 1;
261 level = 1;
262 }
263 }
264 }
265
266 r->sr = new_sr;
267
268 dolog ("IOC%d LVB%d sr=%#x event=%d level=%d\n",
269 r->sr & SR_BCIS, r->sr & SR_LVBCI,
270 r->sr,
271 event, level);
272
273 if (!event)
274 return;
275
276 if (level) {
277 s->glob_sta |= masks[r - s->bm_regs];
278 dolog ("set irq level=1\n");
279 qemu_set_irq (s->dev.irq[0], 1);
280 }
281 else {
282 s->glob_sta &= ~masks[r - s->bm_regs];
283 dolog ("set irq level=0\n");
284 qemu_set_irq (s->dev.irq[0], 0);
285 }
286 }
287
288 static void voice_set_active (AC97LinkState *s, int bm_index, int on)
289 {
290 switch (bm_index) {
291 case PI_INDEX:
292 AUD_set_active_in (s->voice_pi, on);
293 break;
294
295 case PO_INDEX:
296 AUD_set_active_out (s->voice_po, on);
297 break;
298
299 case MC_INDEX:
300 AUD_set_active_in (s->voice_mc, on);
301 break;
302
303 default:
304 AUD_log ("ac97", "invalid bm_index(%d) in voice_set_active", bm_index);
305 break;
306 }
307 }
308
309 static void reset_bm_regs (AC97LinkState *s, AC97BusMasterRegs *r)
310 {
311 dolog ("reset_bm_regs\n");
312 r->bdbar = 0;
313 r->civ = 0;
314 r->lvi = 0;
315 /** todo do we need to do that? */
316 update_sr (s, r, SR_DCH);
317 r->picb = 0;
318 r->piv = 0;
319 r->cr = r->cr & CR_DONT_CLEAR_MASK;
320 r->bd_valid = 0;
321
322 voice_set_active (s, r - s->bm_regs, 0);
323 memset (s->silence, 0, sizeof (s->silence));
324 }
325
326 static void mixer_store (AC97LinkState *s, uint32_t i, uint16_t v)
327 {
328 if (i + 2 > sizeof (s->mixer_data)) {
329 dolog ("mixer_store: index %d out of bounds %zd\n",
330 i, sizeof (s->mixer_data));
331 return;
332 }
333
334 s->mixer_data[i + 0] = v & 0xff;
335 s->mixer_data[i + 1] = v >> 8;
336 }
337
338 static uint16_t mixer_load (AC97LinkState *s, uint32_t i)
339 {
340 uint16_t val = 0xffff;
341
342 if (i + 2 > sizeof (s->mixer_data)) {
343 dolog ("mixer_store: index %d out of bounds %zd\n",
344 i, sizeof (s->mixer_data));
345 }
346 else {
347 val = s->mixer_data[i + 0] | (s->mixer_data[i + 1] << 8);
348 }
349
350 return val;
351 }
352
353 static void open_voice (AC97LinkState *s, int index, int freq)
354 {
355 struct audsettings as;
356
357 as.freq = freq;
358 as.nchannels = 2;
359 as.fmt = AUD_FMT_S16;
360 as.endianness = 0;
361
362 if (freq > 0) {
363 s->invalid_freq[index] = 0;
364 switch (index) {
365 case PI_INDEX:
366 s->voice_pi = AUD_open_in (
367 &s->card,
368 s->voice_pi,
369 "ac97.pi",
370 s,
371 pi_callback,
372 &as
373 );
374 break;
375
376 case PO_INDEX:
377 s->voice_po = AUD_open_out (
378 &s->card,
379 s->voice_po,
380 "ac97.po",
381 s,
382 po_callback,
383 &as
384 );
385 break;
386
387 case MC_INDEX:
388 s->voice_mc = AUD_open_in (
389 &s->card,
390 s->voice_mc,
391 "ac97.mc",
392 s,
393 mc_callback,
394 &as
395 );
396 break;
397 }
398 }
399 else {
400 s->invalid_freq[index] = freq;
401 switch (index) {
402 case PI_INDEX:
403 AUD_close_in (&s->card, s->voice_pi);
404 s->voice_pi = NULL;
405 break;
406
407 case PO_INDEX:
408 AUD_close_out (&s->card, s->voice_po);
409 s->voice_po = NULL;
410 break;
411
412 case MC_INDEX:
413 AUD_close_in (&s->card, s->voice_mc);
414 s->voice_mc = NULL;
415 break;
416 }
417 }
418 }
419
420 static void reset_voices (AC97LinkState *s, uint8_t active[LAST_INDEX])
421 {
422 uint16_t freq;
423
424 freq = mixer_load (s, AC97_PCM_LR_ADC_Rate);
425 open_voice (s, PI_INDEX, freq);
426 AUD_set_active_in (s->voice_pi, active[PI_INDEX]);
427
428 freq = mixer_load (s, AC97_PCM_Front_DAC_Rate);
429 open_voice (s, PO_INDEX, freq);
430 AUD_set_active_out (s->voice_po, active[PO_INDEX]);
431
432 freq = mixer_load (s, AC97_MIC_ADC_Rate);
433 open_voice (s, MC_INDEX, freq);
434 AUD_set_active_in (s->voice_mc, active[MC_INDEX]);
435 }
436
437 #ifdef USE_MIXER
438 static void set_volume (AC97LinkState *s, int index,
439 audmixerctl_t mt, uint32_t val)
440 {
441 int mute = (val >> MUTE_SHIFT) & 1;
442 uint8_t rvol = VOL_MASK - (val & VOL_MASK);
443 uint8_t lvol = VOL_MASK - ((val >> 8) & VOL_MASK);
444 rvol = 255 * rvol / VOL_MASK;
445 lvol = 255 * lvol / VOL_MASK;
446
447 #ifdef SOFT_VOLUME
448 if (index == AC97_Master_Volume_Mute) {
449 AUD_set_volume_out (s->voice_po, mute, lvol, rvol);
450 }
451 else {
452 AUD_set_volume (mt, &mute, &lvol, &rvol);
453 }
454 #else
455 AUD_set_volume (mt, &mute, &lvol, &rvol);
456 #endif
457
458 rvol = VOL_MASK - ((VOL_MASK * rvol) / 255);
459 lvol = VOL_MASK - ((VOL_MASK * lvol) / 255);
460 mixer_store (s, index, val);
461 }
462
463 static audrecsource_t ac97_to_aud_record_source (uint8_t i)
464 {
465 switch (i) {
466 case REC_MIC:
467 return AUD_REC_MIC;
468
469 case REC_CD:
470 return AUD_REC_CD;
471
472 case REC_VIDEO:
473 return AUD_REC_VIDEO;
474
475 case REC_AUX:
476 return AUD_REC_AUX;
477
478 case REC_LINE_IN:
479 return AUD_REC_LINE_IN;
480
481 case REC_PHONE:
482 return AUD_REC_PHONE;
483
484 default:
485 dolog ("Unknown record source %d, using MIC\n", i);
486 return AUD_REC_MIC;
487 }
488 }
489
490 static uint8_t aud_to_ac97_record_source (audrecsource_t rs)
491 {
492 switch (rs) {
493 case AUD_REC_MIC:
494 return REC_MIC;
495
496 case AUD_REC_CD:
497 return REC_CD;
498
499 case AUD_REC_VIDEO:
500 return REC_VIDEO;
501
502 case AUD_REC_AUX:
503 return REC_AUX;
504
505 case AUD_REC_LINE_IN:
506 return REC_LINE_IN;
507
508 case AUD_REC_PHONE:
509 return REC_PHONE;
510
511 default:
512 dolog ("Unknown audio recording source %d using MIC\n", rs);
513 return REC_MIC;
514 }
515 }
516
517 static void record_select (AC97LinkState *s, uint32_t val)
518 {
519 uint8_t rs = val & REC_MASK;
520 uint8_t ls = (val >> 8) & REC_MASK;
521 audrecsource_t ars = ac97_to_aud_record_source (rs);
522 audrecsource_t als = ac97_to_aud_record_source (ls);
523 AUD_set_record_source (&als, &ars);
524 rs = aud_to_ac97_record_source (ars);
525 ls = aud_to_ac97_record_source (als);
526 mixer_store (s, AC97_Record_Select, rs | (ls << 8));
527 }
528 #endif
529
530 static void mixer_reset (AC97LinkState *s)
531 {
532 uint8_t active[LAST_INDEX];
533
534 dolog ("mixer_reset\n");
535 memset (s->mixer_data, 0, sizeof (s->mixer_data));
536 memset (active, 0, sizeof (active));
537 mixer_store (s, AC97_Reset , 0x0000); /* 6940 */
538 mixer_store (s, AC97_Master_Volume_Mono_Mute , 0x8000);
539 mixer_store (s, AC97_PC_BEEP_Volume_Mute , 0x0000);
540
541 mixer_store (s, AC97_Phone_Volume_Mute , 0x8008);
542 mixer_store (s, AC97_Mic_Volume_Mute , 0x8008);
543 mixer_store (s, AC97_CD_Volume_Mute , 0x8808);
544 mixer_store (s, AC97_Aux_Volume_Mute , 0x8808);
545 mixer_store (s, AC97_Record_Gain_Mic_Mute , 0x8000);
546 mixer_store (s, AC97_General_Purpose , 0x0000);
547 mixer_store (s, AC97_3D_Control , 0x0000);
548 mixer_store (s, AC97_Powerdown_Ctrl_Stat , 0x000f);
549
550 /*
551 * Sigmatel 9700 (STAC9700)
552 */
553 mixer_store (s, AC97_Vendor_ID1 , 0x8384);
554 mixer_store (s, AC97_Vendor_ID2 , 0x7600); /* 7608 */
555
556 mixer_store (s, AC97_Extended_Audio_ID , 0x0809);
557 mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, 0x0009);
558 mixer_store (s, AC97_PCM_Front_DAC_Rate , 0xbb80);
559 mixer_store (s, AC97_PCM_Surround_DAC_Rate , 0xbb80);
560 mixer_store (s, AC97_PCM_LFE_DAC_Rate , 0xbb80);
561 mixer_store (s, AC97_PCM_LR_ADC_Rate , 0xbb80);
562 mixer_store (s, AC97_MIC_ADC_Rate , 0xbb80);
563
564 #ifdef USE_MIXER
565 record_select (s, 0);
566 set_volume (s, AC97_Master_Volume_Mute, AUD_MIXER_VOLUME , 0x8000);
567 set_volume (s, AC97_PCM_Out_Volume_Mute, AUD_MIXER_PCM , 0x8808);
568 set_volume (s, AC97_Line_In_Volume_Mute, AUD_MIXER_LINE_IN, 0x8808);
569 #endif
570 reset_voices (s, active);
571 }
572
573 /**
574 * Native audio mixer
575 * I/O Reads
576 */
577 static uint32_t nam_readb (void *opaque, uint32_t addr)
578 {
579 AC97LinkState *s = opaque;
580 dolog ("U nam readb %#x\n", addr);
581 s->cas = 0;
582 return ~0U;
583 }
584
585 static uint32_t nam_readw (void *opaque, uint32_t addr)
586 {
587 AC97LinkState *s = opaque;
588 uint32_t val = ~0U;
589 uint32_t index = addr;
590 s->cas = 0;
591 val = mixer_load (s, index);
592 return val;
593 }
594
595 static uint32_t nam_readl (void *opaque, uint32_t addr)
596 {
597 AC97LinkState *s = opaque;
598 dolog ("U nam readl %#x\n", addr);
599 s->cas = 0;
600 return ~0U;
601 }
602
603 /**
604 * Native audio mixer
605 * I/O Writes
606 */
607 static void nam_writeb (void *opaque, uint32_t addr, uint32_t val)
608 {
609 AC97LinkState *s = opaque;
610 dolog ("U nam writeb %#x <- %#x\n", addr, val);
611 s->cas = 0;
612 }
613
614 static void nam_writew (void *opaque, uint32_t addr, uint32_t val)
615 {
616 AC97LinkState *s = opaque;
617 uint32_t index = addr;
618 s->cas = 0;
619 switch (index) {
620 case AC97_Reset:
621 mixer_reset (s);
622 break;
623 case AC97_Powerdown_Ctrl_Stat:
624 val &= ~0xf;
625 val |= mixer_load (s, index) & 0xf;
626 mixer_store (s, index, val);
627 break;
628 #ifdef USE_MIXER
629 case AC97_Master_Volume_Mute:
630 set_volume (s, index, AUD_MIXER_VOLUME, val);
631 break;
632 case AC97_PCM_Out_Volume_Mute:
633 set_volume (s, index, AUD_MIXER_PCM, val);
634 break;
635 case AC97_Line_In_Volume_Mute:
636 set_volume (s, index, AUD_MIXER_LINE_IN, val);
637 break;
638 case AC97_Record_Select:
639 record_select (s, val);
640 break;
641 #endif
642 case AC97_Vendor_ID1:
643 case AC97_Vendor_ID2:
644 dolog ("Attempt to write vendor ID to %#x\n", val);
645 break;
646 case AC97_Extended_Audio_ID:
647 dolog ("Attempt to write extended audio ID to %#x\n", val);
648 break;
649 case AC97_Extended_Audio_Ctrl_Stat:
650 if (!(val & EACS_VRA)) {
651 mixer_store (s, AC97_PCM_Front_DAC_Rate, 0xbb80);
652 mixer_store (s, AC97_PCM_LR_ADC_Rate, 0xbb80);
653 open_voice (s, PI_INDEX, 48000);
654 open_voice (s, PO_INDEX, 48000);
655 }
656 if (!(val & EACS_VRM)) {
657 mixer_store (s, AC97_MIC_ADC_Rate, 0xbb80);
658 open_voice (s, MC_INDEX, 48000);
659 }
660 dolog ("Setting extended audio control to %#x\n", val);
661 mixer_store (s, AC97_Extended_Audio_Ctrl_Stat, val);
662 break;
663 case AC97_PCM_Front_DAC_Rate:
664 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) {
665 mixer_store (s, index, val);
666 dolog ("Set front DAC rate to %d\n", val);
667 open_voice (s, PO_INDEX, val);
668 }
669 else {
670 dolog ("Attempt to set front DAC rate to %d, "
671 "but VRA is not set\n",
672 val);
673 }
674 break;
675 case AC97_MIC_ADC_Rate:
676 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRM) {
677 mixer_store (s, index, val);
678 dolog ("Set MIC ADC rate to %d\n", val);
679 open_voice (s, MC_INDEX, val);
680 }
681 else {
682 dolog ("Attempt to set MIC ADC rate to %d, "
683 "but VRM is not set\n",
684 val);
685 }
686 break;
687 case AC97_PCM_LR_ADC_Rate:
688 if (mixer_load (s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) {
689 mixer_store (s, index, val);
690 dolog ("Set front LR ADC rate to %d\n", val);
691 open_voice (s, PI_INDEX, val);
692 }
693 else {
694 dolog ("Attempt to set LR ADC rate to %d, but VRA is not set\n",
695 val);
696 }
697 break;
698 default:
699 dolog ("U nam writew %#x <- %#x\n", addr, val);
700 mixer_store (s, index, val);
701 break;
702 }
703 }
704
705 static void nam_writel (void *opaque, uint32_t addr, uint32_t val)
706 {
707 AC97LinkState *s = opaque;
708 dolog ("U nam writel %#x <- %#x\n", addr, val);
709 s->cas = 0;
710 }
711
712 /**
713 * Native audio bus master
714 * I/O Reads
715 */
716 static uint32_t nabm_readb (void *opaque, uint32_t addr)
717 {
718 AC97LinkState *s = opaque;
719 AC97BusMasterRegs *r = NULL;
720 uint32_t index = addr;
721 uint32_t val = ~0U;
722
723 switch (index) {
724 case CAS:
725 dolog ("CAS %d\n", s->cas);
726 val = s->cas;
727 s->cas = 1;
728 break;
729 case PI_CIV:
730 case PO_CIV:
731 case MC_CIV:
732 r = &s->bm_regs[GET_BM (index)];
733 val = r->civ;
734 dolog ("CIV[%d] -> %#x\n", GET_BM (index), val);
735 break;
736 case PI_LVI:
737 case PO_LVI:
738 case MC_LVI:
739 r = &s->bm_regs[GET_BM (index)];
740 val = r->lvi;
741 dolog ("LVI[%d] -> %#x\n", GET_BM (index), val);
742 break;
743 case PI_PIV:
744 case PO_PIV:
745 case MC_PIV:
746 r = &s->bm_regs[GET_BM (index)];
747 val = r->piv;
748 dolog ("PIV[%d] -> %#x\n", GET_BM (index), val);
749 break;
750 case PI_CR:
751 case PO_CR:
752 case MC_CR:
753 r = &s->bm_regs[GET_BM (index)];
754 val = r->cr;
755 dolog ("CR[%d] -> %#x\n", GET_BM (index), val);
756 break;
757 case PI_SR:
758 case PO_SR:
759 case MC_SR:
760 r = &s->bm_regs[GET_BM (index)];
761 val = r->sr & 0xff;
762 dolog ("SRb[%d] -> %#x\n", GET_BM (index), val);
763 break;
764 default:
765 dolog ("U nabm readb %#x -> %#x\n", addr, val);
766 break;
767 }
768 return val;
769 }
770
771 static uint32_t nabm_readw (void *opaque, uint32_t addr)
772 {
773 AC97LinkState *s = opaque;
774 AC97BusMasterRegs *r = NULL;
775 uint32_t index = addr;
776 uint32_t val = ~0U;
777
778 switch (index) {
779 case PI_SR:
780 case PO_SR:
781 case MC_SR:
782 r = &s->bm_regs[GET_BM (index)];
783 val = r->sr;
784 dolog ("SR[%d] -> %#x\n", GET_BM (index), val);
785 break;
786 case PI_PICB:
787 case PO_PICB:
788 case MC_PICB:
789 r = &s->bm_regs[GET_BM (index)];
790 val = r->picb;
791 dolog ("PICB[%d] -> %#x\n", GET_BM (index), val);
792 break;
793 default:
794 dolog ("U nabm readw %#x -> %#x\n", addr, val);
795 break;
796 }
797 return val;
798 }
799
800 static uint32_t nabm_readl (void *opaque, uint32_t addr)
801 {
802 AC97LinkState *s = opaque;
803 AC97BusMasterRegs *r = NULL;
804 uint32_t index = addr;
805 uint32_t val = ~0U;
806
807 switch (index) {
808 case PI_BDBAR:
809 case PO_BDBAR:
810 case MC_BDBAR:
811 r = &s->bm_regs[GET_BM (index)];
812 val = r->bdbar;
813 dolog ("BMADDR[%d] -> %#x\n", GET_BM (index), val);
814 break;
815 case PI_CIV:
816 case PO_CIV:
817 case MC_CIV:
818 r = &s->bm_regs[GET_BM (index)];
819 val = r->civ | (r->lvi << 8) | (r->sr << 16);
820 dolog ("CIV LVI SR[%d] -> %#x, %#x, %#x\n", GET_BM (index),
821 r->civ, r->lvi, r->sr);
822 break;
823 case PI_PICB:
824 case PO_PICB:
825 case MC_PICB:
826 r = &s->bm_regs[GET_BM (index)];
827 val = r->picb | (r->piv << 16) | (r->cr << 24);
828 dolog ("PICB PIV CR[%d] -> %#x %#x %#x %#x\n", GET_BM (index),
829 val, r->picb, r->piv, r->cr);
830 break;
831 case GLOB_CNT:
832 val = s->glob_cnt;
833 dolog ("glob_cnt -> %#x\n", val);
834 break;
835 case GLOB_STA:
836 val = s->glob_sta | GS_S0CR;
837 dolog ("glob_sta -> %#x\n", val);
838 break;
839 default:
840 dolog ("U nabm readl %#x -> %#x\n", addr, val);
841 break;
842 }
843 return val;
844 }
845
846 /**
847 * Native audio bus master
848 * I/O Writes
849 */
850 static void nabm_writeb (void *opaque, uint32_t addr, uint32_t val)
851 {
852 AC97LinkState *s = opaque;
853 AC97BusMasterRegs *r = NULL;
854 uint32_t index = addr;
855 switch (index) {
856 case PI_LVI:
857 case PO_LVI:
858 case MC_LVI:
859 r = &s->bm_regs[GET_BM (index)];
860 if ((r->cr & CR_RPBM) && (r->sr & SR_DCH)) {
861 r->sr &= ~(SR_DCH | SR_CELV);
862 r->civ = r->piv;
863 r->piv = (r->piv + 1) % 32;
864 fetch_bd (s, r);
865 }
866 r->lvi = val % 32;
867 dolog ("LVI[%d] <- %#x\n", GET_BM (index), val);
868 break;
869 case PI_CR:
870 case PO_CR:
871 case MC_CR:
872 r = &s->bm_regs[GET_BM (index)];
873 if (val & CR_RR) {
874 reset_bm_regs (s, r);
875 }
876 else {
877 r->cr = val & CR_VALID_MASK;
878 if (!(r->cr & CR_RPBM)) {
879 voice_set_active (s, r - s->bm_regs, 0);
880 r->sr |= SR_DCH;
881 }
882 else {
883 r->civ = r->piv;
884 r->piv = (r->piv + 1) % 32;
885 fetch_bd (s, r);
886 r->sr &= ~SR_DCH;
887 voice_set_active (s, r - s->bm_regs, 1);
888 }
889 }
890 dolog ("CR[%d] <- %#x (cr %#x)\n", GET_BM (index), val, r->cr);
891 break;
892 case PI_SR:
893 case PO_SR:
894 case MC_SR:
895 r = &s->bm_regs[GET_BM (index)];
896 r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK);
897 update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK));
898 dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr);
899 break;
900 default:
901 dolog ("U nabm writeb %#x <- %#x\n", addr, val);
902 break;
903 }
904 }
905
906 static void nabm_writew (void *opaque, uint32_t addr, uint32_t val)
907 {
908 AC97LinkState *s = opaque;
909 AC97BusMasterRegs *r = NULL;
910 uint32_t index = addr;
911 switch (index) {
912 case PI_SR:
913 case PO_SR:
914 case MC_SR:
915 r = &s->bm_regs[GET_BM (index)];
916 r->sr |= val & ~(SR_RO_MASK | SR_WCLEAR_MASK);
917 update_sr (s, r, r->sr & ~(val & SR_WCLEAR_MASK));
918 dolog ("SR[%d] <- %#x (sr %#x)\n", GET_BM (index), val, r->sr);
919 break;
920 default:
921 dolog ("U nabm writew %#x <- %#x\n", addr, val);
922 break;
923 }
924 }
925
926 static void nabm_writel (void *opaque, uint32_t addr, uint32_t val)
927 {
928 AC97LinkState *s = opaque;
929 AC97BusMasterRegs *r = NULL;
930 uint32_t index = addr;
931 switch (index) {
932 case PI_BDBAR:
933 case PO_BDBAR:
934 case MC_BDBAR:
935 r = &s->bm_regs[GET_BM (index)];
936 r->bdbar = val & ~3;
937 dolog ("BDBAR[%d] <- %#x (bdbar %#x)\n",
938 GET_BM (index), val, r->bdbar);
939 break;
940 case GLOB_CNT:
941 if (val & GC_WR)
942 warm_reset (s);
943 if (val & GC_CR)
944 cold_reset (s);
945 if (!(val & (GC_WR | GC_CR)))
946 s->glob_cnt = val & GC_VALID_MASK;
947 dolog ("glob_cnt <- %#x (glob_cnt %#x)\n", val, s->glob_cnt);
948 break;
949 case GLOB_STA:
950 s->glob_sta &= ~(val & GS_WCLEAR_MASK);
951 s->glob_sta |= (val & ~(GS_WCLEAR_MASK | GS_RO_MASK)) & GS_VALID_MASK;
952 dolog ("glob_sta <- %#x (glob_sta %#x)\n", val, s->glob_sta);
953 break;
954 default:
955 dolog ("U nabm writel %#x <- %#x\n", addr, val);
956 break;
957 }
958 }
959
960 static int write_audio (AC97LinkState *s, AC97BusMasterRegs *r,
961 int max, int *stop)
962 {
963 uint8_t tmpbuf[4096];
964 uint32_t addr = r->bd.addr;
965 uint32_t temp = r->picb << 1;
966 uint32_t written = 0;
967 int to_copy = 0;
968 temp = audio_MIN (temp, max);
969
970 if (!temp) {
971 *stop = 1;
972 return 0;
973 }
974
975 while (temp) {
976 int copied;
977 to_copy = audio_MIN (temp, sizeof (tmpbuf));
978 pci_dma_read (&s->dev, addr, tmpbuf, to_copy);
979 copied = AUD_write (s->voice_po, tmpbuf, to_copy);
980 dolog ("write_audio max=%x to_copy=%x copied=%x\n",
981 max, to_copy, copied);
982 if (!copied) {
983 *stop = 1;
984 break;
985 }
986 temp -= copied;
987 addr += copied;
988 written += copied;
989 }
990
991 if (!temp) {
992 if (to_copy < 4) {
993 dolog ("whoops\n");
994 s->last_samp = 0;
995 }
996 else {
997 s->last_samp = *(uint32_t *) &tmpbuf[to_copy - 4];
998 }
999 }
1000
1001 r->bd.addr = addr;
1002 return written;
1003 }
1004
1005 static void write_bup (AC97LinkState *s, int elapsed)
1006 {
1007 dolog ("write_bup\n");
1008 if (!(s->bup_flag & BUP_SET)) {
1009 if (s->bup_flag & BUP_LAST) {
1010 int i;
1011 uint8_t *p = s->silence;
1012 for (i = 0; i < sizeof (s->silence) / 4; i++, p += 4) {
1013 *(uint32_t *) p = s->last_samp;
1014 }
1015 }
1016 else {
1017 memset (s->silence, 0, sizeof (s->silence));
1018 }
1019 s->bup_flag |= BUP_SET;
1020 }
1021
1022 while (elapsed) {
1023 int temp = audio_MIN (elapsed, sizeof (s->silence));
1024 while (temp) {
1025 int copied = AUD_write (s->voice_po, s->silence, temp);
1026 if (!copied)
1027 return;
1028 temp -= copied;
1029 elapsed -= copied;
1030 }
1031 }
1032 }
1033
1034 static int read_audio (AC97LinkState *s, AC97BusMasterRegs *r,
1035 int max, int *stop)
1036 {
1037 uint8_t tmpbuf[4096];
1038 uint32_t addr = r->bd.addr;
1039 uint32_t temp = r->picb << 1;
1040 uint32_t nread = 0;
1041 int to_copy = 0;
1042 SWVoiceIn *voice = (r - s->bm_regs) == MC_INDEX ? s->voice_mc : s->voice_pi;
1043
1044 temp = audio_MIN (temp, max);
1045
1046 if (!temp) {
1047 *stop = 1;
1048 return 0;
1049 }
1050
1051 while (temp) {
1052 int acquired;
1053 to_copy = audio_MIN (temp, sizeof (tmpbuf));
1054 acquired = AUD_read (voice, tmpbuf, to_copy);
1055 if (!acquired) {
1056 *stop = 1;
1057 break;
1058 }
1059 pci_dma_write (&s->dev, addr, tmpbuf, acquired);
1060 temp -= acquired;
1061 addr += acquired;
1062 nread += acquired;
1063 }
1064
1065 r->bd.addr = addr;
1066 return nread;
1067 }
1068
1069 static void transfer_audio (AC97LinkState *s, int index, int elapsed)
1070 {
1071 AC97BusMasterRegs *r = &s->bm_regs[index];
1072 int stop = 0;
1073
1074 if (s->invalid_freq[index]) {
1075 AUD_log ("ac97", "attempt to use voice %d with invalid frequency %d\n",
1076 index, s->invalid_freq[index]);
1077 return;
1078 }
1079
1080 if (r->sr & SR_DCH) {
1081 if (r->cr & CR_RPBM) {
1082 switch (index) {
1083 case PO_INDEX:
1084 write_bup (s, elapsed);
1085 break;
1086 }
1087 }
1088 return;
1089 }
1090
1091 while ((elapsed >> 1) && !stop) {
1092 int temp;
1093
1094 if (!r->bd_valid) {
1095 dolog ("invalid bd\n");
1096 fetch_bd (s, r);
1097 }
1098
1099 if (!r->picb) {
1100 dolog ("fresh bd %d is empty %#x %#x\n",
1101 r->civ, r->bd.addr, r->bd.ctl_len);
1102 if (r->civ == r->lvi) {
1103 r->sr |= SR_DCH; /* CELV? */
1104 s->bup_flag = 0;
1105 break;
1106 }
1107 r->sr &= ~SR_CELV;
1108 r->civ = r->piv;
1109 r->piv = (r->piv + 1) % 32;
1110 fetch_bd (s, r);
1111 return;
1112 }
1113
1114 switch (index) {
1115 case PO_INDEX:
1116 temp = write_audio (s, r, elapsed, &stop);
1117 elapsed -= temp;
1118 r->picb -= (temp >> 1);
1119 break;
1120
1121 case PI_INDEX:
1122 case MC_INDEX:
1123 temp = read_audio (s, r, elapsed, &stop);
1124 elapsed -= temp;
1125 r->picb -= (temp >> 1);
1126 break;
1127 }
1128
1129 if (!r->picb) {
1130 uint32_t new_sr = r->sr & ~SR_CELV;
1131
1132 if (r->bd.ctl_len & BD_IOC) {
1133 new_sr |= SR_BCIS;
1134 }
1135
1136 if (r->civ == r->lvi) {
1137 dolog ("Underrun civ (%d) == lvi (%d)\n", r->civ, r->lvi);
1138
1139 new_sr |= SR_LVBCI | SR_DCH | SR_CELV;
1140 stop = 1;
1141 s->bup_flag = (r->bd.ctl_len & BD_BUP) ? BUP_LAST : 0;
1142 }
1143 else {
1144 r->civ = r->piv;
1145 r->piv = (r->piv + 1) % 32;
1146 fetch_bd (s, r);
1147 }
1148
1149 update_sr (s, r, new_sr);
1150 }
1151 }
1152 }
1153
1154 static void pi_callback (void *opaque, int avail)
1155 {
1156 transfer_audio (opaque, PI_INDEX, avail);
1157 }
1158
1159 static void mc_callback (void *opaque, int avail)
1160 {
1161 transfer_audio (opaque, MC_INDEX, avail);
1162 }
1163
1164 static void po_callback (void *opaque, int free)
1165 {
1166 transfer_audio (opaque, PO_INDEX, free);
1167 }
1168
1169 static const VMStateDescription vmstate_ac97_bm_regs = {
1170 .name = "ac97_bm_regs",
1171 .version_id = 1,
1172 .minimum_version_id = 1,
1173 .minimum_version_id_old = 1,
1174 .fields = (VMStateField []) {
1175 VMSTATE_UINT32(bdbar, AC97BusMasterRegs),
1176 VMSTATE_UINT8(civ, AC97BusMasterRegs),
1177 VMSTATE_UINT8(lvi, AC97BusMasterRegs),
1178 VMSTATE_UINT16(sr, AC97BusMasterRegs),
1179 VMSTATE_UINT16(picb, AC97BusMasterRegs),
1180 VMSTATE_UINT8(piv, AC97BusMasterRegs),
1181 VMSTATE_UINT8(cr, AC97BusMasterRegs),
1182 VMSTATE_UINT32(bd_valid, AC97BusMasterRegs),
1183 VMSTATE_UINT32(bd.addr, AC97BusMasterRegs),
1184 VMSTATE_UINT32(bd.ctl_len, AC97BusMasterRegs),
1185 VMSTATE_END_OF_LIST()
1186 }
1187 };
1188
1189 static int ac97_post_load (void *opaque, int version_id)
1190 {
1191 uint8_t active[LAST_INDEX];
1192 AC97LinkState *s = opaque;
1193
1194 #ifdef USE_MIXER
1195 record_select (s, mixer_load (s, AC97_Record_Select));
1196 #define V_(a, b) set_volume (s, a, b, mixer_load (s, a))
1197 V_ (AC97_Master_Volume_Mute, AUD_MIXER_VOLUME);
1198 V_ (AC97_PCM_Out_Volume_Mute, AUD_MIXER_PCM);
1199 V_ (AC97_Line_In_Volume_Mute, AUD_MIXER_LINE_IN);
1200 #undef V_
1201 #endif
1202 active[PI_INDEX] = !!(s->bm_regs[PI_INDEX].cr & CR_RPBM);
1203 active[PO_INDEX] = !!(s->bm_regs[PO_INDEX].cr & CR_RPBM);
1204 active[MC_INDEX] = !!(s->bm_regs[MC_INDEX].cr & CR_RPBM);
1205 reset_voices (s, active);
1206
1207 s->bup_flag = 0;
1208 s->last_samp = 0;
1209 return 0;
1210 }
1211
1212 static bool is_version_2 (void *opaque, int version_id)
1213 {
1214 return version_id == 2;
1215 }
1216
1217 static const VMStateDescription vmstate_ac97 = {
1218 .name = "ac97",
1219 .version_id = 3,
1220 .minimum_version_id = 2,
1221 .minimum_version_id_old = 2,
1222 .post_load = ac97_post_load,
1223 .fields = (VMStateField []) {
1224 VMSTATE_PCI_DEVICE(dev, AC97LinkState),
1225 VMSTATE_UINT32(glob_cnt, AC97LinkState),
1226 VMSTATE_UINT32(glob_sta, AC97LinkState),
1227 VMSTATE_UINT32(cas, AC97LinkState),
1228 VMSTATE_STRUCT_ARRAY(bm_regs, AC97LinkState, 3, 1,
1229 vmstate_ac97_bm_regs, AC97BusMasterRegs),
1230 VMSTATE_BUFFER(mixer_data, AC97LinkState),
1231 VMSTATE_UNUSED_TEST(is_version_2, 3),
1232 VMSTATE_END_OF_LIST()
1233 }
1234 };
1235
1236 static const MemoryRegionPortio nam_portio[] = {
1237 { 0, 256 * 1, 1, .read = nam_readb, },
1238 { 0, 256 * 2, 2, .read = nam_readw, },
1239 { 0, 256 * 4, 4, .read = nam_readl, },
1240 { 0, 256 * 1, 1, .write = nam_writeb, },
1241 { 0, 256 * 2, 2, .write = nam_writew, },
1242 { 0, 256 * 4, 4, .write = nam_writel, },
1243 PORTIO_END_OF_LIST(),
1244 };
1245
1246 static const MemoryRegionOps ac97_io_nam_ops = {
1247 .old_portio = nam_portio,
1248 };
1249
1250 static const MemoryRegionPortio nabm_portio[] = {
1251 { 0, 64 * 1, 1, .read = nabm_readb, },
1252 { 0, 64 * 2, 2, .read = nabm_readw, },
1253 { 0, 64 * 4, 4, .read = nabm_readl, },
1254 { 0, 64 * 1, 1, .write = nabm_writeb, },
1255 { 0, 64 * 2, 2, .write = nabm_writew, },
1256 { 0, 64 * 4, 4, .write = nabm_writel, },
1257 PORTIO_END_OF_LIST()
1258 };
1259
1260 static const MemoryRegionOps ac97_io_nabm_ops = {
1261 .old_portio = nabm_portio,
1262 };
1263
1264 static void ac97_on_reset (void *opaque)
1265 {
1266 AC97LinkState *s = opaque;
1267
1268 reset_bm_regs (s, &s->bm_regs[0]);
1269 reset_bm_regs (s, &s->bm_regs[1]);
1270 reset_bm_regs (s, &s->bm_regs[2]);
1271
1272 /*
1273 * Reset the mixer too. The Windows XP driver seems to rely on
1274 * this. At least it wants to read the vendor id before it resets
1275 * the codec manually.
1276 */
1277 mixer_reset (s);
1278 }
1279
1280 static int ac97_initfn (PCIDevice *dev)
1281 {
1282 AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, dev);
1283 uint8_t *c = s->dev.config;
1284
1285 /* TODO: no need to override */
1286 c[PCI_COMMAND] = 0x00; /* pcicmd pci command rw, ro */
1287 c[PCI_COMMAND + 1] = 0x00;
1288
1289 /* TODO: */
1290 c[PCI_STATUS] = PCI_STATUS_FAST_BACK; /* pcists pci status rwc, ro */
1291 c[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
1292
1293 c[PCI_CLASS_PROG] = 0x00; /* pi programming interface ro */
1294
1295 /* TODO set when bar is registered. no need to override. */
1296 /* nabmar native audio mixer base address rw */
1297 c[PCI_BASE_ADDRESS_0] = PCI_BASE_ADDRESS_SPACE_IO;
1298 c[PCI_BASE_ADDRESS_0 + 1] = 0x00;
1299 c[PCI_BASE_ADDRESS_0 + 2] = 0x00;
1300 c[PCI_BASE_ADDRESS_0 + 3] = 0x00;
1301
1302 /* TODO set when bar is registered. no need to override. */
1303 /* nabmbar native audio bus mastering base address rw */
1304 c[PCI_BASE_ADDRESS_0 + 4] = PCI_BASE_ADDRESS_SPACE_IO;
1305 c[PCI_BASE_ADDRESS_0 + 5] = 0x00;
1306 c[PCI_BASE_ADDRESS_0 + 6] = 0x00;
1307 c[PCI_BASE_ADDRESS_0 + 7] = 0x00;
1308
1309 if (s->use_broken_id) {
1310 c[PCI_SUBSYSTEM_VENDOR_ID] = 0x86;
1311 c[PCI_SUBSYSTEM_VENDOR_ID + 1] = 0x80;
1312 c[PCI_SUBSYSTEM_ID] = 0x00;
1313 c[PCI_SUBSYSTEM_ID + 1] = 0x00;
1314 }
1315
1316 c[PCI_INTERRUPT_LINE] = 0x00; /* intr_ln interrupt line rw */
1317 c[PCI_INTERRUPT_PIN] = 0x01; /* intr_pn interrupt pin ro */
1318
1319 memory_region_init_io (&s->io_nam, &ac97_io_nam_ops, s, "ac97-nam", 1024);
1320 memory_region_init_io (&s->io_nabm, &ac97_io_nabm_ops, s, "ac97-nabm", 256);
1321 pci_register_bar (&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nam);
1322 pci_register_bar (&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_nabm);
1323 qemu_register_reset (ac97_on_reset, s);
1324 AUD_register_card ("ac97", &s->card);
1325 ac97_on_reset (s);
1326 return 0;
1327 }
1328
1329 static int ac97_exitfn (PCIDevice *dev)
1330 {
1331 AC97LinkState *s = DO_UPCAST (AC97LinkState, dev, dev);
1332
1333 memory_region_destroy (&s->io_nam);
1334 memory_region_destroy (&s->io_nabm);
1335 return 0;
1336 }
1337
1338 int ac97_init (PCIBus *bus)
1339 {
1340 pci_create_simple (bus, -1, "AC97");
1341 return 0;
1342 }
1343
1344 static PCIDeviceInfo ac97_info = {
1345 .qdev.name = "AC97",
1346 .qdev.desc = "Intel 82801AA AC97 Audio",
1347 .qdev.size = sizeof (AC97LinkState),
1348 .qdev.vmsd = &vmstate_ac97,
1349 .init = ac97_initfn,
1350 .exit = ac97_exitfn,
1351 .vendor_id = PCI_VENDOR_ID_INTEL,
1352 .device_id = PCI_DEVICE_ID_INTEL_82801AA_5,
1353 .revision = 0x01,
1354 .class_id = PCI_CLASS_MULTIMEDIA_AUDIO,
1355 .qdev.props = (Property[]) {
1356 DEFINE_PROP_UINT32("use_broken_id", AC97LinkState, use_broken_id, 0),
1357 DEFINE_PROP_END_OF_LIST(),
1358 }
1359 };
1360
1361 static void ac97_register (void)
1362 {
1363 pci_qdev_register (&ac97_info);
1364 }
1365 device_init (ac97_register);
1366
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