hw/rc4030.c

   1 /*
   2  * QEMU JAZZ RC4030 chipset
   3  *
   4  * Copyright (c) 2007-2009 Herve Poussineau
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "mips.h"
  27 #include "qemu-timer.h"
  28
  29 /********************************************************/
  30 /* debug rc4030 */
  31
  32 //#define DEBUG_RC4030
  33 //#define DEBUG_RC4030_DMA
  34
  35 #ifdef DEBUG_RC4030
  36 #define DPRINTF(fmt, ...) \
  37 do { printf("rc4030: " fmt , ## __VA_ARGS__); } while (0)
  38 static const char* irq_names[] = { "parallel", "floppy", "sound", "video",
  39             "network", "scsi", "keyboard", "mouse", "serial0", "serial1" };
  40 #else
  41 #define DPRINTF(fmt, ...)
  42 #endif
  43
  44 #define RC4030_ERROR(fmt, ...) \
  45 do { fprintf(stderr, "rc4030 ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
  46
  47 /********************************************************/
  48 /* rc4030 emulation                                     */
  49
  50 typedef struct dma_pagetable_entry {
  51     int32_t frame;
  52     int32_t owner;
  53 } QEMU_PACKED dma_pagetable_entry;
  54
  55 #define DMA_PAGESIZE    4096
  56 #define DMA_REG_ENABLE  1
  57 #define DMA_REG_COUNT   2
  58 #define DMA_REG_ADDRESS 3
  59
  60 #define DMA_FLAG_ENABLE     0x0001
  61 #define DMA_FLAG_MEM_TO_DEV 0x0002
  62 #define DMA_FLAG_TC_INTR    0x0100
  63 #define DMA_FLAG_MEM_INTR   0x0200
  64 #define DMA_FLAG_ADDR_INTR  0x0400
  65
  66 typedef struct rc4030State
  67 {
  68     uint32_t config; /* 0x0000: RC4030 config register */
  69     uint32_t revision; /* 0x0008: RC4030 Revision register */
  70     uint32_t invalid_address_register; /* 0x0010: Invalid Address register */
  71
  72     /* DMA */
  73     uint32_t dma_regs[8][4];
  74     uint32_t dma_tl_base; /* 0x0018: DMA transl. table base */
  75     uint32_t dma_tl_limit; /* 0x0020: DMA transl. table limit */
  76
  77     /* cache */
  78     uint32_t cache_maint; /* 0x0030: Cache Maintenance */
  79     uint32_t remote_failed_address; /* 0x0038: Remote Failed Address */
  80     uint32_t memory_failed_address; /* 0x0040: Memory Failed Address */
  81     uint32_t cache_ptag; /* 0x0048: I/O Cache Physical Tag */
  82     uint32_t cache_ltag; /* 0x0050: I/O Cache Logical Tag */
  83     uint32_t cache_bmask; /* 0x0058: I/O Cache Byte Mask */
  84
  85     uint32_t nmi_interrupt; /* 0x0200: interrupt source */
  86     uint32_t offset210;
  87     uint32_t nvram_protect; /* 0x0220: NV ram protect register */
  88     uint32_t rem_speed[16];
  89     uint32_t imr_jazz; /* Local bus int enable mask */
  90     uint32_t isr_jazz; /* Local bus int source */
  91
  92     /* timer */
  93     QEMUTimer *periodic_timer;
  94     uint32_t itr; /* Interval timer reload */
  95
  96     qemu_irq timer_irq;
  97     qemu_irq jazz_bus_irq;
  98 } rc4030State;
  99
 100 static void set_next_tick(rc4030State *s)
 101 {
 102     qemu_irq_lower(s->timer_irq);
 103     uint32_t tm_hz;
 104
 105     tm_hz = 1000 / (s->itr + 1);
 106
 107     qemu_mod_timer(s->periodic_timer, qemu_get_clock_ns(vm_clock) +
 108                    get_ticks_per_sec() / tm_hz);
 109 }
 110
 111 /* called for accesses to rc4030 */
 112 static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr)
 113 {
 114     rc4030State *s = opaque;
 115     uint32_t val;
 116
 117     addr &= 0x3fff;
 118     switch (addr & ~0x3) {
 119     /* Global config register */
 120     case 0x0000:
 121         val = s->config;
 122         break;
 123     /* Revision register */
 124     case 0x0008:
 125         val = s->revision;
 126         break;
 127     /* Invalid Address register */
 128     case 0x0010:
 129         val = s->invalid_address_register;
 130         break;
 131     /* DMA transl. table base */
 132     case 0x0018:
 133         val = s->dma_tl_base;
 134         break;
 135     /* DMA transl. table limit */
 136     case 0x0020:
 137         val = s->dma_tl_limit;
 138         break;
 139     /* Remote Failed Address */
 140     case 0x0038:
 141         val = s->remote_failed_address;
 142         break;
 143     /* Memory Failed Address */
 144     case 0x0040:
 145         val = s->memory_failed_address;
 146         break;
 147     /* I/O Cache Byte Mask */
 148     case 0x0058:
 149         val = s->cache_bmask;
 150         /* HACK */
 151         if (s->cache_bmask == (uint32_t)-1)
 152             s->cache_bmask = 0;
 153         break;
 154     /* Remote Speed Registers */
 155     case 0x0070:
 156     case 0x0078:
 157     case 0x0080:
 158     case 0x0088:
 159     case 0x0090:
 160     case 0x0098:
 161     case 0x00a0:
 162     case 0x00a8:
 163     case 0x00b0:
 164     case 0x00b8:
 165     case 0x00c0:
 166     case 0x00c8:
 167     case 0x00d0:
 168     case 0x00d8:
 169     case 0x00e0:
 170     case 0x00e8:
 171         val = s->rem_speed[(addr - 0x0070) >> 3];
 172         break;
 173     /* DMA channel base address */
 174     case 0x0100:
 175     case 0x0108:
 176     case 0x0110:
 177     case 0x0118:
 178     case 0x0120:
 179     case 0x0128:
 180     case 0x0130:
 181     case 0x0138:
 182     case 0x0140:
 183     case 0x0148:
 184     case 0x0150:
 185     case 0x0158:
 186     case 0x0160:
 187     case 0x0168:
 188     case 0x0170:
 189     case 0x0178:
 190     case 0x0180:
 191     case 0x0188:
 192     case 0x0190:
 193     case 0x0198:
 194     case 0x01a0:
 195     case 0x01a8:
 196     case 0x01b0:
 197     case 0x01b8:
 198     case 0x01c0:
 199     case 0x01c8:
 200     case 0x01d0:
 201     case 0x01d8:
 202     case 0x01e0:
 203     case 0x01e8:
 204     case 0x01f0:
 205     case 0x01f8:
 206         {
 207             int entry = (addr - 0x0100) >> 5;
 208             int idx = (addr & 0x1f) >> 3;
 209             val = s->dma_regs[entry][idx];
 210         }
 211         break;
 212     /* Interrupt source */
 213     case 0x0200:
 214         val = s->nmi_interrupt;
 215         break;
 216     /* Error type */
 217     case 0x0208:
 218         val = 0;
 219         break;
 220     /* Offset 0x0210 */
 221     case 0x0210:
 222         val = s->offset210;
 223         break;
 224     /* NV ram protect register */
 225     case 0x0220:
 226         val = s->nvram_protect;
 227         break;
 228     /* Interval timer count */
 229     case 0x0230:
 230         val = 0;
 231         qemu_irq_lower(s->timer_irq);
 232         break;
 233     /* EISA interrupt */
 234     case 0x0238:
 235         val = 7; /* FIXME: should be read from EISA controller */
 236         break;
 237     default:
 238         RC4030_ERROR("invalid read [" TARGET_FMT_plx "]\n", addr);
 239         val = 0;
 240         break;
 241     }
 242
 243     if ((addr & ~3) != 0x230) {
 244         DPRINTF("read 0x%02x at " TARGET_FMT_plx "\n", val, addr);
 245     }
 246
 247     return val;
 248 }
 249
 250 static uint32_t rc4030_readw(void *opaque, target_phys_addr_t addr)
 251 {
 252     uint32_t v = rc4030_readl(opaque, addr & ~0x3);
 253     if (addr & 0x2)
 254         return v >> 16;
 255     else
 256         return v & 0xffff;
 257 }
 258
 259 static uint32_t rc4030_readb(void *opaque, target_phys_addr_t addr)
 260 {
 261     uint32_t v = rc4030_readl(opaque, addr & ~0x3);
 262     return (v >> (8 * (addr & 0x3))) & 0xff;
 263 }
 264
 265 static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 266 {
 267     rc4030State *s = opaque;
 268     addr &= 0x3fff;
 269
 270     DPRINTF("write 0x%02x at " TARGET_FMT_plx "\n", val, addr);
 271
 272     switch (addr & ~0x3) {
 273     /* Global config register */
 274     case 0x0000:
 275         s->config = val;
 276         break;
 277     /* DMA transl. table base */
 278     case 0x0018:
 279         s->dma_tl_base = val;
 280         break;
 281     /* DMA transl. table limit */
 282     case 0x0020:
 283         s->dma_tl_limit = val;
 284         break;
 285     /* DMA transl. table invalidated */
 286     case 0x0028:
 287         break;
 288     /* Cache Maintenance */
 289     case 0x0030:
 290         s->cache_maint = val;
 291         break;
 292     /* I/O Cache Physical Tag */
 293     case 0x0048:
 294         s->cache_ptag = val;
 295         break;
 296     /* I/O Cache Logical Tag */
 297     case 0x0050:
 298         s->cache_ltag = val;
 299         break;
 300     /* I/O Cache Byte Mask */
 301     case 0x0058:
 302         s->cache_bmask |= val; /* HACK */
 303         break;
 304     /* I/O Cache Buffer Window */
 305     case 0x0060:
 306         /* HACK */
 307         if (s->cache_ltag == 0x80000001 && s->cache_bmask == 0xf0f0f0f) {
 308             target_phys_addr_t dest = s->cache_ptag & ~0x1;
 309             dest += (s->cache_maint & 0x3) << 3;
 310             cpu_physical_memory_write(dest, &val, 4);
 311         }
 312         break;
 313     /* Remote Speed Registers */
 314     case 0x0070:
 315     case 0x0078:
 316     case 0x0080:
 317     case 0x0088:
 318     case 0x0090:
 319     case 0x0098:
 320     case 0x00a0:
 321     case 0x00a8:
 322     case 0x00b0:
 323     case 0x00b8:
 324     case 0x00c0:
 325     case 0x00c8:
 326     case 0x00d0:
 327     case 0x00d8:
 328     case 0x00e0:
 329     case 0x00e8:
 330         s->rem_speed[(addr - 0x0070) >> 3] = val;
 331         break;
 332     /* DMA channel base address */
 333     case 0x0100:
 334     case 0x0108:
 335     case 0x0110:
 336     case 0x0118:
 337     case 0x0120:
 338     case 0x0128:
 339     case 0x0130:
 340     case 0x0138:
 341     case 0x0140:
 342     case 0x0148:
 343     case 0x0150:
 344     case 0x0158:
 345     case 0x0160:
 346     case 0x0168:
 347     case 0x0170:
 348     case 0x0178:
 349     case 0x0180:
 350     case 0x0188:
 351     case 0x0190:
 352     case 0x0198:
 353     case 0x01a0:
 354     case 0x01a8:
 355     case 0x01b0:
 356     case 0x01b8:
 357     case 0x01c0:
 358     case 0x01c8:
 359     case 0x01d0:
 360     case 0x01d8:
 361     case 0x01e0:
 362     case 0x01e8:
 363     case 0x01f0:
 364     case 0x01f8:
 365         {
 366             int entry = (addr - 0x0100) >> 5;
 367             int idx = (addr & 0x1f) >> 3;
 368             s->dma_regs[entry][idx] = val;
 369         }
 370         break;
 371     /* Offset 0x0210 */
 372     case 0x0210:
 373         s->offset210 = val;
 374         break;
 375     /* Interval timer reload */
 376     case 0x0228:
 377         s->itr = val;
 378         qemu_irq_lower(s->timer_irq);
 379         set_next_tick(s);
 380         break;
 381     /* EISA interrupt */
 382     case 0x0238:
 383         break;
 384     default:
 385         RC4030_ERROR("invalid write of 0x%02x at [" TARGET_FMT_plx "]\n", val, addr);
 386         break;
 387     }
 388 }
 389
 390 static void rc4030_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 391 {
 392     uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
 393
 394     if (addr & 0x2)
 395         val = (val << 16) | (old_val & 0x0000ffff);
 396     else
 397         val = val | (old_val & 0xffff0000);
 398     rc4030_writel(opaque, addr & ~0x3, val);
 399 }
 400
 401 static void rc4030_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 402 {
 403     uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
 404
 405     switch (addr & 3) {
 406     case 0:
 407         val = val | (old_val & 0xffffff00);
 408         break;
 409     case 1:
 410         val = (val << 8) | (old_val & 0xffff00ff);
 411         break;
 412     case 2:
 413         val = (val << 16) | (old_val & 0xff00ffff);
 414         break;
 415     case 3:
 416         val = (val << 24) | (old_val & 0x00ffffff);
 417         break;
 418     }
 419     rc4030_writel(opaque, addr & ~0x3, val);
 420 }
 421
 422 static CPUReadMemoryFunc * const rc4030_read[3] = {
 423     rc4030_readb,
 424     rc4030_readw,
 425     rc4030_readl,
 426 };
 427
 428 static CPUWriteMemoryFunc * const rc4030_write[3] = {
 429     rc4030_writeb,
 430     rc4030_writew,
 431     rc4030_writel,
 432 };
 433
 434 static void update_jazz_irq(rc4030State *s)
 435 {
 436     uint16_t pending;
 437
 438     pending = s->isr_jazz & s->imr_jazz;
 439
 440 #ifdef DEBUG_RC4030
 441     if (s->isr_jazz != 0) {
 442         uint32_t irq = 0;
 443         DPRINTF("pending irqs:");
 444         for (irq = 0; irq < ARRAY_SIZE(irq_names); irq++) {
 445             if (s->isr_jazz & (1 << irq)) {
 446                 printf(" %s", irq_names[irq]);
 447                 if (!(s->imr_jazz & (1 << irq))) {
 448                     printf("(ignored)");
 449                 }
 450             }
 451         }
 452         printf("\n");
 453     }
 454 #endif
 455
 456     if (pending != 0)
 457         qemu_irq_raise(s->jazz_bus_irq);
 458     else
 459         qemu_irq_lower(s->jazz_bus_irq);
 460 }
 461
 462 static void rc4030_irq_jazz_request(void *opaque, int irq, int level)
 463 {
 464     rc4030State *s = opaque;
 465
 466     if (level) {
 467         s->isr_jazz |= 1 << irq;
 468     } else {
 469         s->isr_jazz &= ~(1 << irq);
 470     }
 471
 472     update_jazz_irq(s);
 473 }
 474
 475 static void rc4030_periodic_timer(void *opaque)
 476 {
 477     rc4030State *s = opaque;
 478
 479     set_next_tick(s);
 480     qemu_irq_raise(s->timer_irq);
 481 }
 482
 483 static uint32_t jazzio_readw(void *opaque, target_phys_addr_t addr)
 484 {
 485     rc4030State *s = opaque;
 486     uint32_t val;
 487     uint32_t irq;
 488     addr &= 0xfff;
 489
 490     switch (addr) {
 491     /* Local bus int source */
 492     case 0x00: {
 493         uint32_t pending = s->isr_jazz & s->imr_jazz;
 494         val = 0;
 495         irq = 0;
 496         while (pending) {
 497             if (pending & 1) {
 498                 DPRINTF("returning irq %s\n", irq_names[irq]);
 499                 val = (irq + 1) << 2;
 500                 break;
 501             }
 502             irq++;
 503             pending >>= 1;
 504         }
 505         break;
 506     }
 507     /* Local bus int enable mask */
 508     case 0x02:
 509         val = s->imr_jazz;
 510         break;
 511     default:
 512         RC4030_ERROR("(jazz io controller) invalid read [" TARGET_FMT_plx "]\n", addr);
 513         val = 0;
 514     }
 515
 516     DPRINTF("(jazz io controller) read 0x%04x at " TARGET_FMT_plx "\n", val, addr);
 517
 518     return val;
 519 }
 520
 521 static uint32_t jazzio_readb(void *opaque, target_phys_addr_t addr)
 522 {
 523     uint32_t v;
 524     v = jazzio_readw(opaque, addr & ~0x1);
 525     return (v >> (8 * (addr & 0x1))) & 0xff;
 526 }
 527
 528 static uint32_t jazzio_readl(void *opaque, target_phys_addr_t addr)
 529 {
 530     uint32_t v;
 531     v = jazzio_readw(opaque, addr);
 532     v |= jazzio_readw(opaque, addr + 2) << 16;
 533     return v;
 534 }
 535
 536 static void jazzio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 537 {
 538     rc4030State *s = opaque;
 539     addr &= 0xfff;
 540
 541     DPRINTF("(jazz io controller) write 0x%04x at " TARGET_FMT_plx "\n", val, addr);
 542
 543     switch (addr) {
 544     /* Local bus int enable mask */
 545     case 0x02:
 546         s->imr_jazz = val;
 547         update_jazz_irq(s);
 548         break;
 549     default:
 550         RC4030_ERROR("(jazz io controller) invalid write of 0x%04x at [" TARGET_FMT_plx "]\n", val, addr);
 551         break;
 552     }
 553 }
 554
 555 static void jazzio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 556 {
 557     uint32_t old_val = jazzio_readw(opaque, addr & ~0x1);
 558
 559     switch (addr & 1) {
 560     case 0:
 561         val = val | (old_val & 0xff00);
 562         break;
 563     case 1:
 564         val = (val << 8) | (old_val & 0x00ff);
 565         break;
 566     }
 567     jazzio_writew(opaque, addr & ~0x1, val);
 568 }
 569
 570 static void jazzio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 571 {
 572     jazzio_writew(opaque, addr, val & 0xffff);
 573     jazzio_writew(opaque, addr + 2, (val >> 16) & 0xffff);
 574 }
 575
 576 static CPUReadMemoryFunc * const jazzio_read[3] = {
 577     jazzio_readb,
 578     jazzio_readw,
 579     jazzio_readl,
 580 };
 581
 582 static CPUWriteMemoryFunc * const jazzio_write[3] = {
 583     jazzio_writeb,
 584     jazzio_writew,
 585     jazzio_writel,
 586 };
 587
 588 static void rc4030_reset(void *opaque)
 589 {
 590     rc4030State *s = opaque;
 591     int i;
 592
 593     s->config = 0x410; /* some boards seem to accept 0x104 too */
 594     s->revision = 1;
 595     s->invalid_address_register = 0;
 596
 597     memset(s->dma_regs, 0, sizeof(s->dma_regs));
 598     s->dma_tl_base = s->dma_tl_limit = 0;
 599
 600     s->remote_failed_address = s->memory_failed_address = 0;
 601     s->cache_maint = 0;
 602     s->cache_ptag = s->cache_ltag = 0;
 603     s->cache_bmask = 0;
 604
 605     s->offset210 = 0x18186;
 606     s->nvram_protect = 7;
 607     for (i = 0; i < 15; i++)
 608         s->rem_speed[i] = 7;
 609     s->imr_jazz = 0x10; /* XXX: required by firmware, but why? */
 610     s->isr_jazz = 0;
 611
 612     s->itr = 0;
 613
 614     qemu_irq_lower(s->timer_irq);
 615     qemu_irq_lower(s->jazz_bus_irq);
 616 }
 617
 618 static int rc4030_load(QEMUFile *f, void *opaque, int version_id)
 619 {
 620     rc4030State* s = opaque;
 621     int i, j;
 622
 623     if (version_id != 2)
 624         return -EINVAL;
 625
 626     s->config = qemu_get_be32(f);
 627     s->invalid_address_register = qemu_get_be32(f);
 628     for (i = 0; i < 8; i++)
 629         for (j = 0; j < 4; j++)
 630             s->dma_regs[i][j] = qemu_get_be32(f);
 631     s->dma_tl_base = qemu_get_be32(f);
 632     s->dma_tl_limit = qemu_get_be32(f);
 633     s->cache_maint = qemu_get_be32(f);
 634     s->remote_failed_address = qemu_get_be32(f);
 635     s->memory_failed_address = qemu_get_be32(f);
 636     s->cache_ptag = qemu_get_be32(f);
 637     s->cache_ltag = qemu_get_be32(f);
 638     s->cache_bmask = qemu_get_be32(f);
 639     s->offset210 = qemu_get_be32(f);
 640     s->nvram_protect = qemu_get_be32(f);
 641     for (i = 0; i < 15; i++)
 642         s->rem_speed[i] = qemu_get_be32(f);
 643     s->imr_jazz = qemu_get_be32(f);
 644     s->isr_jazz = qemu_get_be32(f);
 645     s->itr = qemu_get_be32(f);
 646
 647     set_next_tick(s);
 648     update_jazz_irq(s);
 649
 650     return 0;
 651 }
 652
 653 static void rc4030_save(QEMUFile *f, void *opaque)
 654 {
 655     rc4030State* s = opaque;
 656     int i, j;
 657
 658     qemu_put_be32(f, s->config);
 659     qemu_put_be32(f, s->invalid_address_register);
 660     for (i = 0; i < 8; i++)
 661         for (j = 0; j < 4; j++)
 662             qemu_put_be32(f, s->dma_regs[i][j]);
 663     qemu_put_be32(f, s->dma_tl_base);
 664     qemu_put_be32(f, s->dma_tl_limit);
 665     qemu_put_be32(f, s->cache_maint);
 666     qemu_put_be32(f, s->remote_failed_address);
 667     qemu_put_be32(f, s->memory_failed_address);
 668     qemu_put_be32(f, s->cache_ptag);
 669     qemu_put_be32(f, s->cache_ltag);
 670     qemu_put_be32(f, s->cache_bmask);
 671     qemu_put_be32(f, s->offset210);
 672     qemu_put_be32(f, s->nvram_protect);
 673     for (i = 0; i < 15; i++)
 674         qemu_put_be32(f, s->rem_speed[i]);
 675     qemu_put_be32(f, s->imr_jazz);
 676     qemu_put_be32(f, s->isr_jazz);
 677     qemu_put_be32(f, s->itr);
 678 }
 679
 680 void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write)
 681 {
 682     rc4030State *s = opaque;
 683     target_phys_addr_t entry_addr;
 684     target_phys_addr_t phys_addr;
 685     dma_pagetable_entry entry;
 686     int index;
 687     int ncpy, i;
 688
 689     i = 0;
 690     for (;;) {
 691         if (i == len) {
 692             break;
 693         }
 694
 695         ncpy = DMA_PAGESIZE - (addr & (DMA_PAGESIZE - 1));
 696         if (ncpy > len - i)
 697             ncpy = len - i;
 698
 699         /* Get DMA translation table entry */
 700         index = addr / DMA_PAGESIZE;
 701         if (index >= s->dma_tl_limit / sizeof(dma_pagetable_entry)) {
 702             break;
 703         }
 704         entry_addr = s->dma_tl_base + index * sizeof(dma_pagetable_entry);
 705         /* XXX: not sure. should we really use only lowest bits? */
 706         entry_addr &= 0x7fffffff;
 707         cpu_physical_memory_read(entry_addr, &entry, sizeof(entry));
 708
 709         /* Read/write data at right place */
 710         phys_addr = entry.frame + (addr & (DMA_PAGESIZE - 1));
 711         cpu_physical_memory_rw(phys_addr, &buf[i], ncpy, is_write);
 712
 713         i += ncpy;
 714         addr += ncpy;
 715     }
 716 }
 717
 718 static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_write)
 719 {
 720     rc4030State *s = opaque;
 721     target_phys_addr_t dma_addr;
 722     int dev_to_mem;
 723
 724     s->dma_regs[n][DMA_REG_ENABLE] &= ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR);
 725
 726     /* Check DMA channel consistency */
 727     dev_to_mem = (s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_MEM_TO_DEV) ? 0 : 1;
 728     if (!(s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_ENABLE) ||
 729         (is_write != dev_to_mem)) {
 730         s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_MEM_INTR;
 731         s->nmi_interrupt |= 1 << n;
 732         return;
 733     }
 734
 735     /* Get start address and len */
 736     if (len > s->dma_regs[n][DMA_REG_COUNT])
 737         len = s->dma_regs[n][DMA_REG_COUNT];
 738     dma_addr = s->dma_regs[n][DMA_REG_ADDRESS];
 739
 740     /* Read/write data at right place */
 741     rc4030_dma_memory_rw(opaque, dma_addr, buf, len, is_write);
 742
 743     s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_TC_INTR;
 744     s->dma_regs[n][DMA_REG_COUNT] -= len;
 745
 746 #ifdef DEBUG_RC4030_DMA
 747     {
 748         int i, j;
 749         printf("rc4030 dma: Copying %d bytes %s host %p\n",
 750             len, is_write ? "from" : "to", buf);
 751         for (i = 0; i < len; i += 16) {
 752             int n = 16;
 753             if (n > len - i) {
 754                 n = len - i;
 755             }
 756             for (j = 0; j < n; j++)
 757                 printf("%02x ", buf[i + j]);
 758             while (j++ < 16)
 759                 printf("   ");
 760             printf("| ");
 761             for (j = 0; j < n; j++)
 762                 printf("%c", isprint(buf[i + j]) ? buf[i + j] : '.');
 763             printf("\n");
 764         }
 765     }
 766 #endif
 767 }
 768
 769 struct rc4030DMAState {
 770     void *opaque;
 771     int n;
 772 };
 773
 774 void rc4030_dma_read(void *dma, uint8_t *buf, int len)
 775 {
 776     rc4030_dma s = dma;
 777     rc4030_do_dma(s->opaque, s->n, buf, len, 0);
 778 }
 779
 780 void rc4030_dma_write(void *dma, uint8_t *buf, int len)
 781 {
 782     rc4030_dma s = dma;
 783     rc4030_do_dma(s->opaque, s->n, buf, len, 1);
 784 }
 785
 786 static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n)
 787 {
 788     rc4030_dma *s;
 789     struct rc4030DMAState *p;
 790     int i;
 791
 792     s = (rc4030_dma *)g_malloc0(sizeof(rc4030_dma) * n);
 793     p = (struct rc4030DMAState *)g_malloc0(sizeof(struct rc4030DMAState) * n);
 794     for (i = 0; i < n; i++) {
 795         p->opaque = opaque;
 796         p->n = i;
 797         s[i] = p;
 798         p++;
 799     }
 800     return s;
 801 }
 802
 803 void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
 804                   qemu_irq **irqs, rc4030_dma **dmas)
 805 {
 806     rc4030State *s;
 807     int s_chipset, s_jazzio;
 808
 809     s = g_malloc0(sizeof(rc4030State));
 810
 811     *irqs = qemu_allocate_irqs(rc4030_irq_jazz_request, s, 16);
 812     *dmas = rc4030_allocate_dmas(s, 4);
 813
 814     s->periodic_timer = qemu_new_timer_ns(vm_clock, rc4030_periodic_timer, s);
 815     s->timer_irq = timer;
 816     s->jazz_bus_irq = jazz_bus;
 817
 818     qemu_register_reset(rc4030_reset, s);
 819     register_savevm(NULL, "rc4030", 0, 2, rc4030_save, rc4030_load, s);
 820     rc4030_reset(s);
 821
 822     s_chipset = cpu_register_io_memory(rc4030_read, rc4030_write, s,
 823                                        DEVICE_NATIVE_ENDIAN);
 824     cpu_register_physical_memory(0x80000000, 0x300, s_chipset);
 825     s_jazzio = cpu_register_io_memory(jazzio_read, jazzio_write, s,
 826                                       DEVICE_NATIVE_ENDIAN);
 827     cpu_register_physical_memory(0xf0000000, 0x00001000, s_jazzio);
 828
 829     return s;
 830 }