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x86/cpuid: Fix crash on -cpu ""
[qemu/opensuse.git] / hw / strongarm.c
bloba3d908051ff4d99c74fd0b36029b855a089b0a46
1 /*
2 * StrongARM SA-1100/SA-1110 emulation
3 *
4 * Copyright (C) 2011 Dmitry Eremin-Solenikov
5 *
6 * Largely based on StrongARM emulation:
7 * Copyright (c) 2006 Openedhand Ltd.
8 * Written by Andrzej Zaborowski <balrog@zabor.org>
9 *
10 * UART code based on QEMU 16550A UART emulation
11 * Copyright (c) 2003-2004 Fabrice Bellard
12 * Copyright (c) 2008 Citrix Systems, Inc.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, see <http://www.gnu.org/licenses/>.
25 */
26 #include "sysbus.h"
27 #include "strongarm.h"
28 #include "qemu-error.h"
29 #include "arm-misc.h"
30 #include "sysemu.h"
31 #include "ssi.h"
32
33 //#define DEBUG
34
35 /*
36 TODO
37 - Implement cp15, c14 ?
38 - Implement cp15, c15 !!! (idle used in L)
39 - Implement idle mode handling/DIM
40 - Implement sleep mode/Wake sources
41 - Implement reset control
42 - Implement memory control regs
43 - PCMCIA handling
44 - Maybe support MBGNT/MBREQ
45 - DMA channels
46 - GPCLK
47 - IrDA
48 - MCP
49 - Enhance UART with modem signals
50 */
51
52 #ifdef DEBUG
53 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__)
54 #else
55 # define DPRINTF(format, ...) do { } while (0)
56 #endif
57
58 static struct {
59 target_phys_addr_t io_base;
60 int irq;
61 } sa_serial[] = {
62 { 0x80010000, SA_PIC_UART1 },
63 { 0x80030000, SA_PIC_UART2 },
64 { 0x80050000, SA_PIC_UART3 },
65 { 0, 0 }
66 };
67
68 /* Interrupt Controller */
69 typedef struct {
70 SysBusDevice busdev;
71 MemoryRegion iomem;
72 qemu_irq irq;
73 qemu_irq fiq;
74
75 uint32_t pending;
76 uint32_t enabled;
77 uint32_t is_fiq;
78 uint32_t int_idle;
79 } StrongARMPICState;
80
81 #define ICIP 0x00
82 #define ICMR 0x04
83 #define ICLR 0x08
84 #define ICFP 0x10
85 #define ICPR 0x20
86 #define ICCR 0x0c
87
88 #define SA_PIC_SRCS 32
89
90
91 static void strongarm_pic_update(void *opaque)
92 {
93 StrongARMPICState *s = opaque;
94
95 /* FIXME: reflect DIM */
96 qemu_set_irq(s->fiq, s->pending & s->enabled & s->is_fiq);
97 qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq);
98 }
99
100 static void strongarm_pic_set_irq(void *opaque, int irq, int level)
101 {
102 StrongARMPICState *s = opaque;
103
104 if (level) {
105 s->pending |= 1 << irq;
106 } else {
107 s->pending &= ~(1 << irq);
108 }
109
110 strongarm_pic_update(s);
111 }
112
113 static uint64_t strongarm_pic_mem_read(void *opaque, target_phys_addr_t offset,
114 unsigned size)
115 {
116 StrongARMPICState *s = opaque;
117
118 switch (offset) {
119 case ICIP:
120 return s->pending & ~s->is_fiq & s->enabled;
121 case ICMR:
122 return s->enabled;
123 case ICLR:
124 return s->is_fiq;
125 case ICCR:
126 return s->int_idle == 0;
127 case ICFP:
128 return s->pending & s->is_fiq & s->enabled;
129 case ICPR:
130 return s->pending;
131 default:
132 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
133 __func__, offset);
134 return 0;
135 }
136 }
137
138 static void strongarm_pic_mem_write(void *opaque, target_phys_addr_t offset,
139 uint64_t value, unsigned size)
140 {
141 StrongARMPICState *s = opaque;
142
143 switch (offset) {
144 case ICMR:
145 s->enabled = value;
146 break;
147 case ICLR:
148 s->is_fiq = value;
149 break;
150 case ICCR:
151 s->int_idle = (value & 1) ? 0 : ~0;
152 break;
153 default:
154 printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
155 __func__, offset);
156 break;
157 }
158 strongarm_pic_update(s);
159 }
160
161 static const MemoryRegionOps strongarm_pic_ops = {
162 .read = strongarm_pic_mem_read,
163 .write = strongarm_pic_mem_write,
164 .endianness = DEVICE_NATIVE_ENDIAN,
165 };
166
167 static int strongarm_pic_initfn(SysBusDevice *dev)
168 {
169 StrongARMPICState *s = FROM_SYSBUS(StrongARMPICState, dev);
170
171 qdev_init_gpio_in(&dev->qdev, strongarm_pic_set_irq, SA_PIC_SRCS);
172 memory_region_init_io(&s->iomem, &strongarm_pic_ops, s, "pic", 0x1000);
173 sysbus_init_mmio_region(dev, &s->iomem);
174 sysbus_init_irq(dev, &s->irq);
175 sysbus_init_irq(dev, &s->fiq);
176
177 return 0;
178 }
179
180 static int strongarm_pic_post_load(void *opaque, int version_id)
181 {
182 strongarm_pic_update(opaque);
183 return 0;
184 }
185
186 static VMStateDescription vmstate_strongarm_pic_regs = {
187 .name = "strongarm_pic",
188 .version_id = 0,
189 .minimum_version_id = 0,
190 .minimum_version_id_old = 0,
191 .post_load = strongarm_pic_post_load,
192 .fields = (VMStateField[]) {
193 VMSTATE_UINT32(pending, StrongARMPICState),
194 VMSTATE_UINT32(enabled, StrongARMPICState),
195 VMSTATE_UINT32(is_fiq, StrongARMPICState),
196 VMSTATE_UINT32(int_idle, StrongARMPICState),
197 VMSTATE_END_OF_LIST(),
198 },
199 };
200
201 static SysBusDeviceInfo strongarm_pic_info = {
202 .init = strongarm_pic_initfn,
203 .qdev.name = "strongarm_pic",
204 .qdev.desc = "StrongARM PIC",
205 .qdev.size = sizeof(StrongARMPICState),
206 .qdev.vmsd = &vmstate_strongarm_pic_regs,
207 };
208
209 /* Real-Time Clock */
210 #define RTAR 0x00 /* RTC Alarm register */
211 #define RCNR 0x04 /* RTC Counter register */
212 #define RTTR 0x08 /* RTC Timer Trim register */
213 #define RTSR 0x10 /* RTC Status register */
214
215 #define RTSR_AL (1 << 0) /* RTC Alarm detected */
216 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */
217 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */
218 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */
219
220 /* 16 LSB of RTTR are clockdiv for internal trim logic,
221 * trim delete isn't emulated, so
222 * f = 32 768 / (RTTR_trim + 1) */
223
224 typedef struct {
225 SysBusDevice busdev;
226 MemoryRegion iomem;
227 uint32_t rttr;
228 uint32_t rtsr;
229 uint32_t rtar;
230 uint32_t last_rcnr;
231 int64_t last_hz;
232 QEMUTimer *rtc_alarm;
233 QEMUTimer *rtc_hz;
234 qemu_irq rtc_irq;
235 qemu_irq rtc_hz_irq;
236 } StrongARMRTCState;
237
238 static inline void strongarm_rtc_int_update(StrongARMRTCState *s)
239 {
240 qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL);
241 qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ);
242 }
243
244 static void strongarm_rtc_hzupdate(StrongARMRTCState *s)
245 {
246 int64_t rt = qemu_get_clock_ms(rt_clock);
247 s->last_rcnr += ((rt - s->last_hz) << 15) /
248 (1000 * ((s->rttr & 0xffff) + 1));
249 s->last_hz = rt;
250 }
251
252 static inline void strongarm_rtc_timer_update(StrongARMRTCState *s)
253 {
254 if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) {
255 qemu_mod_timer(s->rtc_hz, s->last_hz + 1000);
256 } else {
257 qemu_del_timer(s->rtc_hz);
258 }
259
260 if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) {
261 qemu_mod_timer(s->rtc_alarm, s->last_hz +
262 (((s->rtar - s->last_rcnr) * 1000 *
263 ((s->rttr & 0xffff) + 1)) >> 15));
264 } else {
265 qemu_del_timer(s->rtc_alarm);
266 }
267 }
268
269 static inline void strongarm_rtc_alarm_tick(void *opaque)
270 {
271 StrongARMRTCState *s = opaque;
272 s->rtsr |= RTSR_AL;
273 strongarm_rtc_timer_update(s);
274 strongarm_rtc_int_update(s);
275 }
276
277 static inline void strongarm_rtc_hz_tick(void *opaque)
278 {
279 StrongARMRTCState *s = opaque;
280 s->rtsr |= RTSR_HZ;
281 strongarm_rtc_timer_update(s);
282 strongarm_rtc_int_update(s);
283 }
284
285 static uint64_t strongarm_rtc_read(void *opaque, target_phys_addr_t addr,
286 unsigned size)
287 {
288 StrongARMRTCState *s = opaque;
289
290 switch (addr) {
291 case RTTR:
292 return s->rttr;
293 case RTSR:
294 return s->rtsr;
295 case RTAR:
296 return s->rtar;
297 case RCNR:
298 return s->last_rcnr +
299 ((qemu_get_clock_ms(rt_clock) - s->last_hz) << 15) /
300 (1000 * ((s->rttr & 0xffff) + 1));
301 default:
302 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
303 return 0;
304 }
305 }
306
307 static void strongarm_rtc_write(void *opaque, target_phys_addr_t addr,
308 uint64_t value, unsigned size)
309 {
310 StrongARMRTCState *s = opaque;
311 uint32_t old_rtsr;
312
313 switch (addr) {
314 case RTTR:
315 strongarm_rtc_hzupdate(s);
316 s->rttr = value;
317 strongarm_rtc_timer_update(s);
318 break;
319
320 case RTSR:
321 old_rtsr = s->rtsr;
322 s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) |
323 (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ)));
324
325 if (s->rtsr != old_rtsr) {
326 strongarm_rtc_timer_update(s);
327 }
328
329 strongarm_rtc_int_update(s);
330 break;
331
332 case RTAR:
333 s->rtar = value;
334 strongarm_rtc_timer_update(s);
335 break;
336
337 case RCNR:
338 strongarm_rtc_hzupdate(s);
339 s->last_rcnr = value;
340 strongarm_rtc_timer_update(s);
341 break;
342
343 default:
344 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
345 }
346 }
347
348 static const MemoryRegionOps strongarm_rtc_ops = {
349 .read = strongarm_rtc_read,
350 .write = strongarm_rtc_write,
351 .endianness = DEVICE_NATIVE_ENDIAN,
352 };
353
354 static int strongarm_rtc_init(SysBusDevice *dev)
355 {
356 StrongARMRTCState *s = FROM_SYSBUS(StrongARMRTCState, dev);
357 struct tm tm;
358
359 s->rttr = 0x0;
360 s->rtsr = 0;
361
362 qemu_get_timedate(&tm, 0);
363
364 s->last_rcnr = (uint32_t) mktimegm(&tm);
365 s->last_hz = qemu_get_clock_ms(rt_clock);
366
367 s->rtc_alarm = qemu_new_timer_ms(rt_clock, strongarm_rtc_alarm_tick, s);
368 s->rtc_hz = qemu_new_timer_ms(rt_clock, strongarm_rtc_hz_tick, s);
369
370 sysbus_init_irq(dev, &s->rtc_irq);
371 sysbus_init_irq(dev, &s->rtc_hz_irq);
372
373 memory_region_init_io(&s->iomem, &strongarm_rtc_ops, s, "rtc", 0x10000);
374 sysbus_init_mmio_region(dev, &s->iomem);
375
376 return 0;
377 }
378
379 static void strongarm_rtc_pre_save(void *opaque)
380 {
381 StrongARMRTCState *s = opaque;
382
383 strongarm_rtc_hzupdate(s);
384 }
385
386 static int strongarm_rtc_post_load(void *opaque, int version_id)
387 {
388 StrongARMRTCState *s = opaque;
389
390 strongarm_rtc_timer_update(s);
391 strongarm_rtc_int_update(s);
392
393 return 0;
394 }
395
396 static const VMStateDescription vmstate_strongarm_rtc_regs = {
397 .name = "strongarm-rtc",
398 .version_id = 0,
399 .minimum_version_id = 0,
400 .minimum_version_id_old = 0,
401 .pre_save = strongarm_rtc_pre_save,
402 .post_load = strongarm_rtc_post_load,
403 .fields = (VMStateField[]) {
404 VMSTATE_UINT32(rttr, StrongARMRTCState),
405 VMSTATE_UINT32(rtsr, StrongARMRTCState),
406 VMSTATE_UINT32(rtar, StrongARMRTCState),
407 VMSTATE_UINT32(last_rcnr, StrongARMRTCState),
408 VMSTATE_INT64(last_hz, StrongARMRTCState),
409 VMSTATE_END_OF_LIST(),
410 },
411 };
412
413 static SysBusDeviceInfo strongarm_rtc_sysbus_info = {
414 .init = strongarm_rtc_init,
415 .qdev.name = "strongarm-rtc",
416 .qdev.desc = "StrongARM RTC Controller",
417 .qdev.size = sizeof(StrongARMRTCState),
418 .qdev.vmsd = &vmstate_strongarm_rtc_regs,
419 };
420
421 /* GPIO */
422 #define GPLR 0x00
423 #define GPDR 0x04
424 #define GPSR 0x08
425 #define GPCR 0x0c
426 #define GRER 0x10
427 #define GFER 0x14
428 #define GEDR 0x18
429 #define GAFR 0x1c
430
431 typedef struct StrongARMGPIOInfo StrongARMGPIOInfo;
432 struct StrongARMGPIOInfo {
433 SysBusDevice busdev;
434 MemoryRegion iomem;
435 qemu_irq handler[28];
436 qemu_irq irqs[11];
437 qemu_irq irqX;
438
439 uint32_t ilevel;
440 uint32_t olevel;
441 uint32_t dir;
442 uint32_t rising;
443 uint32_t falling;
444 uint32_t status;
445 uint32_t gpsr;
446 uint32_t gafr;
447
448 uint32_t prev_level;
449 };
450
451
452 static void strongarm_gpio_irq_update(StrongARMGPIOInfo *s)
453 {
454 int i;
455 for (i = 0; i < 11; i++) {
456 qemu_set_irq(s->irqs[i], s->status & (1 << i));
457 }
458
459 qemu_set_irq(s->irqX, (s->status & ~0x7ff));
460 }
461
462 static void strongarm_gpio_set(void *opaque, int line, int level)
463 {
464 StrongARMGPIOInfo *s = opaque;
465 uint32_t mask;
466
467 mask = 1 << line;
468
469 if (level) {
470 s->status |= s->rising & mask &
471 ~s->ilevel & ~s->dir;
472 s->ilevel |= mask;
473 } else {
474 s->status |= s->falling & mask &
475 s->ilevel & ~s->dir;
476 s->ilevel &= ~mask;
477 }
478
479 if (s->status & mask) {
480 strongarm_gpio_irq_update(s);
481 }
482 }
483
484 static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s)
485 {
486 uint32_t level, diff;
487 int bit;
488
489 level = s->olevel & s->dir;
490
491 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
492 bit = ffs(diff) - 1;
493 qemu_set_irq(s->handler[bit], (level >> bit) & 1);
494 }
495
496 s->prev_level = level;
497 }
498
499 static uint64_t strongarm_gpio_read(void *opaque, target_phys_addr_t offset,
500 unsigned size)
501 {
502 StrongARMGPIOInfo *s = opaque;
503
504 switch (offset) {
505 case GPDR: /* GPIO Pin-Direction registers */
506 return s->dir;
507
508 case GPSR: /* GPIO Pin-Output Set registers */
509 DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx "\n",
510 __func__, offset);
511 return s->gpsr; /* Return last written value. */
512
513 case GPCR: /* GPIO Pin-Output Clear registers */
514 DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx "\n",
515 __func__, offset);
516 return 31337; /* Specified as unpredictable in the docs. */
517
518 case GRER: /* GPIO Rising-Edge Detect Enable registers */
519 return s->rising;
520
521 case GFER: /* GPIO Falling-Edge Detect Enable registers */
522 return s->falling;
523
524 case GAFR: /* GPIO Alternate Function registers */
525 return s->gafr;
526
527 case GPLR: /* GPIO Pin-Level registers */
528 return (s->olevel & s->dir) |
529 (s->ilevel & ~s->dir);
530
531 case GEDR: /* GPIO Edge Detect Status registers */
532 return s->status;
533
534 default:
535 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
536 }
537
538 return 0;
539 }
540
541 static void strongarm_gpio_write(void *opaque, target_phys_addr_t offset,
542 uint64_t value, unsigned size)
543 {
544 StrongARMGPIOInfo *s = opaque;
545
546 switch (offset) {
547 case GPDR: /* GPIO Pin-Direction registers */
548 s->dir = value;
549 strongarm_gpio_handler_update(s);
550 break;
551
552 case GPSR: /* GPIO Pin-Output Set registers */
553 s->olevel |= value;
554 strongarm_gpio_handler_update(s);
555 s->gpsr = value;
556 break;
557
558 case GPCR: /* GPIO Pin-Output Clear registers */
559 s->olevel &= ~value;
560 strongarm_gpio_handler_update(s);
561 break;
562
563 case GRER: /* GPIO Rising-Edge Detect Enable registers */
564 s->rising = value;
565 break;
566
567 case GFER: /* GPIO Falling-Edge Detect Enable registers */
568 s->falling = value;
569 break;
570
571 case GAFR: /* GPIO Alternate Function registers */
572 s->gafr = value;
573 break;
574
575 case GEDR: /* GPIO Edge Detect Status registers */
576 s->status &= ~value;
577 strongarm_gpio_irq_update(s);
578 break;
579
580 default:
581 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
582 }
583 }
584
585 static const MemoryRegionOps strongarm_gpio_ops = {
586 .read = strongarm_gpio_read,
587 .write = strongarm_gpio_write,
588 .endianness = DEVICE_NATIVE_ENDIAN,
589 };
590
591 static DeviceState *strongarm_gpio_init(target_phys_addr_t base,
592 DeviceState *pic)
593 {
594 DeviceState *dev;
595 int i;
596
597 dev = qdev_create(NULL, "strongarm-gpio");
598 qdev_init_nofail(dev);
599
600 sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
601 for (i = 0; i < 12; i++)
602 sysbus_connect_irq(sysbus_from_qdev(dev), i,
603 qdev_get_gpio_in(pic, SA_PIC_GPIO0_EDGE + i));
604
605 return dev;
606 }
607
608 static int strongarm_gpio_initfn(SysBusDevice *dev)
609 {
610 StrongARMGPIOInfo *s;
611 int i;
612
613 s = FROM_SYSBUS(StrongARMGPIOInfo, dev);
614
615 qdev_init_gpio_in(&dev->qdev, strongarm_gpio_set, 28);
616 qdev_init_gpio_out(&dev->qdev, s->handler, 28);
617
618 memory_region_init_io(&s->iomem, &strongarm_gpio_ops, s, "gpio", 0x1000);
619
620 sysbus_init_mmio_region(dev, &s->iomem);
621 for (i = 0; i < 11; i++) {
622 sysbus_init_irq(dev, &s->irqs[i]);
623 }
624 sysbus_init_irq(dev, &s->irqX);
625
626 return 0;
627 }
628
629 static const VMStateDescription vmstate_strongarm_gpio_regs = {
630 .name = "strongarm-gpio",
631 .version_id = 0,
632 .minimum_version_id = 0,
633 .minimum_version_id_old = 0,
634 .fields = (VMStateField[]) {
635 VMSTATE_UINT32(ilevel, StrongARMGPIOInfo),
636 VMSTATE_UINT32(olevel, StrongARMGPIOInfo),
637 VMSTATE_UINT32(dir, StrongARMGPIOInfo),
638 VMSTATE_UINT32(rising, StrongARMGPIOInfo),
639 VMSTATE_UINT32(falling, StrongARMGPIOInfo),
640 VMSTATE_UINT32(status, StrongARMGPIOInfo),
641 VMSTATE_UINT32(gafr, StrongARMGPIOInfo),
642 VMSTATE_END_OF_LIST(),
643 },
644 };
645
646 static SysBusDeviceInfo strongarm_gpio_info = {
647 .init = strongarm_gpio_initfn,
648 .qdev.name = "strongarm-gpio",
649 .qdev.desc = "StrongARM GPIO controller",
650 .qdev.size = sizeof(StrongARMGPIOInfo),
651 };
652
653 /* Peripheral Pin Controller */
654 #define PPDR 0x00
655 #define PPSR 0x04
656 #define PPAR 0x08
657 #define PSDR 0x0c
658 #define PPFR 0x10
659
660 typedef struct StrongARMPPCInfo StrongARMPPCInfo;
661 struct StrongARMPPCInfo {
662 SysBusDevice busdev;
663 MemoryRegion iomem;
664 qemu_irq handler[28];
665
666 uint32_t ilevel;
667 uint32_t olevel;
668 uint32_t dir;
669 uint32_t ppar;
670 uint32_t psdr;
671 uint32_t ppfr;
672
673 uint32_t prev_level;
674 };
675
676 static void strongarm_ppc_set(void *opaque, int line, int level)
677 {
678 StrongARMPPCInfo *s = opaque;
679
680 if (level) {
681 s->ilevel |= 1 << line;
682 } else {
683 s->ilevel &= ~(1 << line);
684 }
685 }
686
687 static void strongarm_ppc_handler_update(StrongARMPPCInfo *s)
688 {
689 uint32_t level, diff;
690 int bit;
691
692 level = s->olevel & s->dir;
693
694 for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
695 bit = ffs(diff) - 1;
696 qemu_set_irq(s->handler[bit], (level >> bit) & 1);
697 }
698
699 s->prev_level = level;
700 }
701
702 static uint64_t strongarm_ppc_read(void *opaque, target_phys_addr_t offset,
703 unsigned size)
704 {
705 StrongARMPPCInfo *s = opaque;
706
707 switch (offset) {
708 case PPDR: /* PPC Pin Direction registers */
709 return s->dir | ~0x3fffff;
710
711 case PPSR: /* PPC Pin State registers */
712 return (s->olevel & s->dir) |
713 (s->ilevel & ~s->dir) |
714 ~0x3fffff;
715
716 case PPAR:
717 return s->ppar | ~0x41000;
718
719 case PSDR:
720 return s->psdr;
721
722 case PPFR:
723 return s->ppfr | ~0x7f001;
724
725 default:
726 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
727 }
728
729 return 0;
730 }
731
732 static void strongarm_ppc_write(void *opaque, target_phys_addr_t offset,
733 uint64_t value, unsigned size)
734 {
735 StrongARMPPCInfo *s = opaque;
736
737 switch (offset) {
738 case PPDR: /* PPC Pin Direction registers */
739 s->dir = value & 0x3fffff;
740 strongarm_ppc_handler_update(s);
741 break;
742
743 case PPSR: /* PPC Pin State registers */
744 s->olevel = value & s->dir & 0x3fffff;
745 strongarm_ppc_handler_update(s);
746 break;
747
748 case PPAR:
749 s->ppar = value & 0x41000;
750 break;
751
752 case PSDR:
753 s->psdr = value & 0x3fffff;
754 break;
755
756 case PPFR:
757 s->ppfr = value & 0x7f001;
758 break;
759
760 default:
761 printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
762 }
763 }
764
765 static const MemoryRegionOps strongarm_ppc_ops = {
766 .read = strongarm_ppc_read,
767 .write = strongarm_ppc_write,
768 .endianness = DEVICE_NATIVE_ENDIAN,
769 };
770
771 static int strongarm_ppc_init(SysBusDevice *dev)
772 {
773 StrongARMPPCInfo *s;
774
775 s = FROM_SYSBUS(StrongARMPPCInfo, dev);
776
777 qdev_init_gpio_in(&dev->qdev, strongarm_ppc_set, 22);
778 qdev_init_gpio_out(&dev->qdev, s->handler, 22);
779
780 memory_region_init_io(&s->iomem, &strongarm_ppc_ops, s, "ppc", 0x1000);
781
782 sysbus_init_mmio_region(dev, &s->iomem);
783
784 return 0;
785 }
786
787 static const VMStateDescription vmstate_strongarm_ppc_regs = {
788 .name = "strongarm-ppc",
789 .version_id = 0,
790 .minimum_version_id = 0,
791 .minimum_version_id_old = 0,
792 .fields = (VMStateField[]) {
793 VMSTATE_UINT32(ilevel, StrongARMPPCInfo),
794 VMSTATE_UINT32(olevel, StrongARMPPCInfo),
795 VMSTATE_UINT32(dir, StrongARMPPCInfo),
796 VMSTATE_UINT32(ppar, StrongARMPPCInfo),
797 VMSTATE_UINT32(psdr, StrongARMPPCInfo),
798 VMSTATE_UINT32(ppfr, StrongARMPPCInfo),
799 VMSTATE_END_OF_LIST(),
800 },
801 };
802
803 static SysBusDeviceInfo strongarm_ppc_info = {
804 .init = strongarm_ppc_init,
805 .qdev.name = "strongarm-ppc",
806 .qdev.desc = "StrongARM PPC controller",
807 .qdev.size = sizeof(StrongARMPPCInfo),
808 };
809
810 /* UART Ports */
811 #define UTCR0 0x00
812 #define UTCR1 0x04
813 #define UTCR2 0x08
814 #define UTCR3 0x0c
815 #define UTDR 0x14
816 #define UTSR0 0x1c
817 #define UTSR1 0x20
818
819 #define UTCR0_PE (1 << 0) /* Parity enable */
820 #define UTCR0_OES (1 << 1) /* Even parity */
821 #define UTCR0_SBS (1 << 2) /* 2 stop bits */
822 #define UTCR0_DSS (1 << 3) /* 8-bit data */
823
824 #define UTCR3_RXE (1 << 0) /* Rx enable */
825 #define UTCR3_TXE (1 << 1) /* Tx enable */
826 #define UTCR3_BRK (1 << 2) /* Force Break */
827 #define UTCR3_RIE (1 << 3) /* Rx int enable */
828 #define UTCR3_TIE (1 << 4) /* Tx int enable */
829 #define UTCR3_LBM (1 << 5) /* Loopback */
830
831 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */
832 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */
833 #define UTSR0_RID (1 << 2) /* Receiver Idle */
834 #define UTSR0_RBB (1 << 3) /* Receiver begin break */
835 #define UTSR0_REB (1 << 4) /* Receiver end break */
836 #define UTSR0_EIF (1 << 5) /* Error in FIFO */
837
838 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */
839 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */
840 #define UTSR1_PRE (1 << 3) /* Parity error */
841 #define UTSR1_FRE (1 << 4) /* Frame error */
842 #define UTSR1_ROR (1 << 5) /* Receive Over Run */
843
844 #define RX_FIFO_PRE (1 << 8)
845 #define RX_FIFO_FRE (1 << 9)
846 #define RX_FIFO_ROR (1 << 10)
847
848 typedef struct {
849 SysBusDevice busdev;
850 MemoryRegion iomem;
851 CharDriverState *chr;
852 qemu_irq irq;
853
854 uint8_t utcr0;
855 uint16_t brd;
856 uint8_t utcr3;
857 uint8_t utsr0;
858 uint8_t utsr1;
859
860 uint8_t tx_fifo[8];
861 uint8_t tx_start;
862 uint8_t tx_len;
863 uint16_t rx_fifo[12]; /* value + error flags in high bits */
864 uint8_t rx_start;
865 uint8_t rx_len;
866
867 uint64_t char_transmit_time; /* time to transmit a char in ticks*/
868 bool wait_break_end;
869 QEMUTimer *rx_timeout_timer;
870 QEMUTimer *tx_timer;
871 } StrongARMUARTState;
872
873 static void strongarm_uart_update_status(StrongARMUARTState *s)
874 {
875 uint16_t utsr1 = 0;
876
877 if (s->tx_len != 8) {
878 utsr1 |= UTSR1_TNF;
879 }
880
881 if (s->rx_len != 0) {
882 uint16_t ent = s->rx_fifo[s->rx_start];
883
884 utsr1 |= UTSR1_RNE;
885 if (ent & RX_FIFO_PRE) {
886 s->utsr1 |= UTSR1_PRE;
887 }
888 if (ent & RX_FIFO_FRE) {
889 s->utsr1 |= UTSR1_FRE;
890 }
891 if (ent & RX_FIFO_ROR) {
892 s->utsr1 |= UTSR1_ROR;
893 }
894 }
895
896 s->utsr1 = utsr1;
897 }
898
899 static void strongarm_uart_update_int_status(StrongARMUARTState *s)
900 {
901 uint16_t utsr0 = s->utsr0 &
902 (UTSR0_REB | UTSR0_RBB | UTSR0_RID);
903 int i;
904
905 if ((s->utcr3 & UTCR3_TXE) &&
906 (s->utcr3 & UTCR3_TIE) &&
907 s->tx_len <= 4) {
908 utsr0 |= UTSR0_TFS;
909 }
910
911 if ((s->utcr3 & UTCR3_RXE) &&
912 (s->utcr3 & UTCR3_RIE) &&
913 s->rx_len > 4) {
914 utsr0 |= UTSR0_RFS;
915 }
916
917 for (i = 0; i < s->rx_len && i < 4; i++)
918 if (s->rx_fifo[(s->rx_start + i) % 12] & ~0xff) {
919 utsr0 |= UTSR0_EIF;
920 break;
921 }
922
923 s->utsr0 = utsr0;
924 qemu_set_irq(s->irq, utsr0);
925 }
926
927 static void strongarm_uart_update_parameters(StrongARMUARTState *s)
928 {
929 int speed, parity, data_bits, stop_bits, frame_size;
930 QEMUSerialSetParams ssp;
931
932 /* Start bit. */
933 frame_size = 1;
934 if (s->utcr0 & UTCR0_PE) {
935 /* Parity bit. */
936 frame_size++;
937 if (s->utcr0 & UTCR0_OES) {
938 parity = 'E';
939 } else {
940 parity = 'O';
941 }
942 } else {
943 parity = 'N';
944 }
945 if (s->utcr0 & UTCR0_SBS) {
946 stop_bits = 2;
947 } else {
948 stop_bits = 1;
949 }
950
951 data_bits = (s->utcr0 & UTCR0_DSS) ? 8 : 7;
952 frame_size += data_bits + stop_bits;
953 speed = 3686400 / 16 / (s->brd + 1);
954 ssp.speed = speed;
955 ssp.parity = parity;
956 ssp.data_bits = data_bits;
957 ssp.stop_bits = stop_bits;
958 s->char_transmit_time = (get_ticks_per_sec() / speed) * frame_size;
959 if (s->chr) {
960 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
961 }
962
963 DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label,
964 speed, parity, data_bits, stop_bits);
965 }
966
967 static void strongarm_uart_rx_to(void *opaque)
968 {
969 StrongARMUARTState *s = opaque;
970
971 if (s->rx_len) {
972 s->utsr0 |= UTSR0_RID;
973 strongarm_uart_update_int_status(s);
974 }
975 }
976
977 static void strongarm_uart_rx_push(StrongARMUARTState *s, uint16_t c)
978 {
979 if ((s->utcr3 & UTCR3_RXE) == 0) {
980 /* rx disabled */
981 return;
982 }
983
984 if (s->wait_break_end) {
985 s->utsr0 |= UTSR0_REB;
986 s->wait_break_end = false;
987 }
988
989 if (s->rx_len < 12) {
990 s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c;
991 s->rx_len++;
992 } else
993 s->rx_fifo[(s->rx_start + 11) % 12] |= RX_FIFO_ROR;
994 }
995
996 static int strongarm_uart_can_receive(void *opaque)
997 {
998 StrongARMUARTState *s = opaque;
999
1000 if (s->rx_len == 12) {
1001 return 0;
1002 }
1003 /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */
1004 if (s->rx_len < 8) {
1005 return 8 - s->rx_len;
1006 }
1007 return 1;
1008 }
1009
1010 static void strongarm_uart_receive(void *opaque, const uint8_t *buf, int size)
1011 {
1012 StrongARMUARTState *s = opaque;
1013 int i;
1014
1015 for (i = 0; i < size; i++) {
1016 strongarm_uart_rx_push(s, buf[i]);
1017 }
1018
1019 /* call the timeout receive callback in 3 char transmit time */
1020 qemu_mod_timer(s->rx_timeout_timer,
1021 qemu_get_clock_ns(vm_clock) + s->char_transmit_time * 3);
1022
1023 strongarm_uart_update_status(s);
1024 strongarm_uart_update_int_status(s);
1025 }
1026
1027 static void strongarm_uart_event(void *opaque, int event)
1028 {
1029 StrongARMUARTState *s = opaque;
1030 if (event == CHR_EVENT_BREAK) {
1031 s->utsr0 |= UTSR0_RBB;
1032 strongarm_uart_rx_push(s, RX_FIFO_FRE);
1033 s->wait_break_end = true;
1034 strongarm_uart_update_status(s);
1035 strongarm_uart_update_int_status(s);
1036 }
1037 }
1038
1039 static void strongarm_uart_tx(void *opaque)
1040 {
1041 StrongARMUARTState *s = opaque;
1042 uint64_t new_xmit_ts = qemu_get_clock_ns(vm_clock);
1043
1044 if (s->utcr3 & UTCR3_LBM) /* loopback */ {
1045 strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1);
1046 } else if (s->chr) {
1047 qemu_chr_fe_write(s->chr, &s->tx_fifo[s->tx_start], 1);
1048 }
1049
1050 s->tx_start = (s->tx_start + 1) % 8;
1051 s->tx_len--;
1052 if (s->tx_len) {
1053 qemu_mod_timer(s->tx_timer, new_xmit_ts + s->char_transmit_time);
1054 }
1055 strongarm_uart_update_status(s);
1056 strongarm_uart_update_int_status(s);
1057 }
1058
1059 static uint64_t strongarm_uart_read(void *opaque, target_phys_addr_t addr,
1060 unsigned size)
1061 {
1062 StrongARMUARTState *s = opaque;
1063 uint16_t ret;
1064
1065 switch (addr) {
1066 case UTCR0:
1067 return s->utcr0;
1068
1069 case UTCR1:
1070 return s->brd >> 8;
1071
1072 case UTCR2:
1073 return s->brd & 0xff;
1074
1075 case UTCR3:
1076 return s->utcr3;
1077
1078 case UTDR:
1079 if (s->rx_len != 0) {
1080 ret = s->rx_fifo[s->rx_start];
1081 s->rx_start = (s->rx_start + 1) % 12;
1082 s->rx_len--;
1083 strongarm_uart_update_status(s);
1084 strongarm_uart_update_int_status(s);
1085 return ret;
1086 }
1087 return 0;
1088
1089 case UTSR0:
1090 return s->utsr0;
1091
1092 case UTSR1:
1093 return s->utsr1;
1094
1095 default:
1096 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1097 return 0;
1098 }
1099 }
1100
1101 static void strongarm_uart_write(void *opaque, target_phys_addr_t addr,
1102 uint64_t value, unsigned size)
1103 {
1104 StrongARMUARTState *s = opaque;
1105
1106 switch (addr) {
1107 case UTCR0:
1108 s->utcr0 = value & 0x7f;
1109 strongarm_uart_update_parameters(s);
1110 break;
1111
1112 case UTCR1:
1113 s->brd = (s->brd & 0xff) | ((value & 0xf) << 8);
1114 strongarm_uart_update_parameters(s);
1115 break;
1116
1117 case UTCR2:
1118 s->brd = (s->brd & 0xf00) | (value & 0xff);
1119 strongarm_uart_update_parameters(s);
1120 break;
1121
1122 case UTCR3:
1123 s->utcr3 = value & 0x3f;
1124 if ((s->utcr3 & UTCR3_RXE) == 0) {
1125 s->rx_len = 0;
1126 }
1127 if ((s->utcr3 & UTCR3_TXE) == 0) {
1128 s->tx_len = 0;
1129 }
1130 strongarm_uart_update_status(s);
1131 strongarm_uart_update_int_status(s);
1132 break;
1133
1134 case UTDR:
1135 if ((s->utcr3 & UTCR3_TXE) && s->tx_len != 8) {
1136 s->tx_fifo[(s->tx_start + s->tx_len) % 8] = value;
1137 s->tx_len++;
1138 strongarm_uart_update_status(s);
1139 strongarm_uart_update_int_status(s);
1140 if (s->tx_len == 1) {
1141 strongarm_uart_tx(s);
1142 }
1143 }
1144 break;
1145
1146 case UTSR0:
1147 s->utsr0 = s->utsr0 & ~(value &
1148 (UTSR0_REB | UTSR0_RBB | UTSR0_RID));
1149 strongarm_uart_update_int_status(s);
1150 break;
1151
1152 default:
1153 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1154 }
1155 }
1156
1157 static const MemoryRegionOps strongarm_uart_ops = {
1158 .read = strongarm_uart_read,
1159 .write = strongarm_uart_write,
1160 .endianness = DEVICE_NATIVE_ENDIAN,
1161 };
1162
1163 static int strongarm_uart_init(SysBusDevice *dev)
1164 {
1165 StrongARMUARTState *s = FROM_SYSBUS(StrongARMUARTState, dev);
1166
1167 memory_region_init_io(&s->iomem, &strongarm_uart_ops, s, "uart", 0x10000);
1168 sysbus_init_mmio_region(dev, &s->iomem);
1169 sysbus_init_irq(dev, &s->irq);
1170
1171 s->rx_timeout_timer = qemu_new_timer_ns(vm_clock, strongarm_uart_rx_to, s);
1172 s->tx_timer = qemu_new_timer_ns(vm_clock, strongarm_uart_tx, s);
1173
1174 if (s->chr) {
1175 qemu_chr_add_handlers(s->chr,
1176 strongarm_uart_can_receive,
1177 strongarm_uart_receive,
1178 strongarm_uart_event,
1179 s);
1180 }
1181
1182 return 0;
1183 }
1184
1185 static void strongarm_uart_reset(DeviceState *dev)
1186 {
1187 StrongARMUARTState *s = DO_UPCAST(StrongARMUARTState, busdev.qdev, dev);
1188
1189 s->utcr0 = UTCR0_DSS; /* 8 data, no parity */
1190 s->brd = 23; /* 9600 */
1191 /* enable send & recv - this actually violates spec */
1192 s->utcr3 = UTCR3_TXE | UTCR3_RXE;
1193
1194 s->rx_len = s->tx_len = 0;
1195
1196 strongarm_uart_update_parameters(s);
1197 strongarm_uart_update_status(s);
1198 strongarm_uart_update_int_status(s);
1199 }
1200
1201 static int strongarm_uart_post_load(void *opaque, int version_id)
1202 {
1203 StrongARMUARTState *s = opaque;
1204
1205 strongarm_uart_update_parameters(s);
1206 strongarm_uart_update_status(s);
1207 strongarm_uart_update_int_status(s);
1208
1209 /* tx and restart timer */
1210 if (s->tx_len) {
1211 strongarm_uart_tx(s);
1212 }
1213
1214 /* restart rx timeout timer */
1215 if (s->rx_len) {
1216 qemu_mod_timer(s->rx_timeout_timer,
1217 qemu_get_clock_ns(vm_clock) + s->char_transmit_time * 3);
1218 }
1219
1220 return 0;
1221 }
1222
1223 static const VMStateDescription vmstate_strongarm_uart_regs = {
1224 .name = "strongarm-uart",
1225 .version_id = 0,
1226 .minimum_version_id = 0,
1227 .minimum_version_id_old = 0,
1228 .post_load = strongarm_uart_post_load,
1229 .fields = (VMStateField[]) {
1230 VMSTATE_UINT8(utcr0, StrongARMUARTState),
1231 VMSTATE_UINT16(brd, StrongARMUARTState),
1232 VMSTATE_UINT8(utcr3, StrongARMUARTState),
1233 VMSTATE_UINT8(utsr0, StrongARMUARTState),
1234 VMSTATE_UINT8_ARRAY(tx_fifo, StrongARMUARTState, 8),
1235 VMSTATE_UINT8(tx_start, StrongARMUARTState),
1236 VMSTATE_UINT8(tx_len, StrongARMUARTState),
1237 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMUARTState, 12),
1238 VMSTATE_UINT8(rx_start, StrongARMUARTState),
1239 VMSTATE_UINT8(rx_len, StrongARMUARTState),
1240 VMSTATE_BOOL(wait_break_end, StrongARMUARTState),
1241 VMSTATE_END_OF_LIST(),
1242 },
1243 };
1244
1245 static SysBusDeviceInfo strongarm_uart_info = {
1246 .init = strongarm_uart_init,
1247 .qdev.name = "strongarm-uart",
1248 .qdev.desc = "StrongARM UART controller",
1249 .qdev.size = sizeof(StrongARMUARTState),
1250 .qdev.reset = strongarm_uart_reset,
1251 .qdev.vmsd = &vmstate_strongarm_uart_regs,
1252 .qdev.props = (Property[]) {
1253 DEFINE_PROP_CHR("chardev", StrongARMUARTState, chr),
1254 DEFINE_PROP_END_OF_LIST(),
1255 }
1256 };
1257
1258 /* Synchronous Serial Ports */
1259 typedef struct {
1260 SysBusDevice busdev;
1261 MemoryRegion iomem;
1262 qemu_irq irq;
1263 SSIBus *bus;
1264
1265 uint16_t sscr[2];
1266 uint16_t sssr;
1267
1268 uint16_t rx_fifo[8];
1269 uint8_t rx_level;
1270 uint8_t rx_start;
1271 } StrongARMSSPState;
1272
1273 #define SSCR0 0x60 /* SSP Control register 0 */
1274 #define SSCR1 0x64 /* SSP Control register 1 */
1275 #define SSDR 0x6c /* SSP Data register */
1276 #define SSSR 0x74 /* SSP Status register */
1277
1278 /* Bitfields for above registers */
1279 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
1280 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
1281 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
1282 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
1283 #define SSCR0_SSE (1 << 7)
1284 #define SSCR0_DSS(x) (((x) & 0xf) + 1)
1285 #define SSCR1_RIE (1 << 0)
1286 #define SSCR1_TIE (1 << 1)
1287 #define SSCR1_LBM (1 << 2)
1288 #define SSSR_TNF (1 << 2)
1289 #define SSSR_RNE (1 << 3)
1290 #define SSSR_TFS (1 << 5)
1291 #define SSSR_RFS (1 << 6)
1292 #define SSSR_ROR (1 << 7)
1293 #define SSSR_RW 0x0080
1294
1295 static void strongarm_ssp_int_update(StrongARMSSPState *s)
1296 {
1297 int level = 0;
1298
1299 level |= (s->sssr & SSSR_ROR);
1300 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
1301 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
1302 qemu_set_irq(s->irq, level);
1303 }
1304
1305 static void strongarm_ssp_fifo_update(StrongARMSSPState *s)
1306 {
1307 s->sssr &= ~SSSR_TFS;
1308 s->sssr &= ~SSSR_TNF;
1309 if (s->sscr[0] & SSCR0_SSE) {
1310 if (s->rx_level >= 4) {
1311 s->sssr |= SSSR_RFS;
1312 } else {
1313 s->sssr &= ~SSSR_RFS;
1314 }
1315 if (s->rx_level) {
1316 s->sssr |= SSSR_RNE;
1317 } else {
1318 s->sssr &= ~SSSR_RNE;
1319 }
1320 /* TX FIFO is never filled, so it is always in underrun
1321 condition if SSP is enabled */
1322 s->sssr |= SSSR_TFS;
1323 s->sssr |= SSSR_TNF;
1324 }
1325
1326 strongarm_ssp_int_update(s);
1327 }
1328
1329 static uint64_t strongarm_ssp_read(void *opaque, target_phys_addr_t addr,
1330 unsigned size)
1331 {
1332 StrongARMSSPState *s = opaque;
1333 uint32_t retval;
1334
1335 switch (addr) {
1336 case SSCR0:
1337 return s->sscr[0];
1338 case SSCR1:
1339 return s->sscr[1];
1340 case SSSR:
1341 return s->sssr;
1342 case SSDR:
1343 if (~s->sscr[0] & SSCR0_SSE) {
1344 return 0xffffffff;
1345 }
1346 if (s->rx_level < 1) {
1347 printf("%s: SSP Rx Underrun\n", __func__);
1348 return 0xffffffff;
1349 }
1350 s->rx_level--;
1351 retval = s->rx_fifo[s->rx_start++];
1352 s->rx_start &= 0x7;
1353 strongarm_ssp_fifo_update(s);
1354 return retval;
1355 default:
1356 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1357 break;
1358 }
1359 return 0;
1360 }
1361
1362 static void strongarm_ssp_write(void *opaque, target_phys_addr_t addr,
1363 uint64_t value, unsigned size)
1364 {
1365 StrongARMSSPState *s = opaque;
1366
1367 switch (addr) {
1368 case SSCR0:
1369 s->sscr[0] = value & 0xffbf;
1370 if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) {
1371 printf("%s: Wrong data size: %i bits\n", __func__,
1372 (int)SSCR0_DSS(value));
1373 }
1374 if (!(value & SSCR0_SSE)) {
1375 s->sssr = 0;
1376 s->rx_level = 0;
1377 }
1378 strongarm_ssp_fifo_update(s);
1379 break;
1380
1381 case SSCR1:
1382 s->sscr[1] = value & 0x2f;
1383 if (value & SSCR1_LBM) {
1384 printf("%s: Attempt to use SSP LBM mode\n", __func__);
1385 }
1386 strongarm_ssp_fifo_update(s);
1387 break;
1388
1389 case SSSR:
1390 s->sssr &= ~(value & SSSR_RW);
1391 strongarm_ssp_int_update(s);
1392 break;
1393
1394 case SSDR:
1395 if (SSCR0_UWIRE(s->sscr[0])) {
1396 value &= 0xff;
1397 } else
1398 /* Note how 32bits overflow does no harm here */
1399 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
1400
1401 /* Data goes from here to the Tx FIFO and is shifted out from
1402 * there directly to the slave, no need to buffer it.
1403 */
1404 if (s->sscr[0] & SSCR0_SSE) {
1405 uint32_t readval;
1406 if (s->sscr[1] & SSCR1_LBM) {
1407 readval = value;
1408 } else {
1409 readval = ssi_transfer(s->bus, value);
1410 }
1411
1412 if (s->rx_level < 0x08) {
1413 s->rx_fifo[(s->rx_start + s->rx_level++) & 0x7] = readval;
1414 } else {
1415 s->sssr |= SSSR_ROR;
1416 }
1417 }
1418 strongarm_ssp_fifo_update(s);
1419 break;
1420
1421 default:
1422 printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1423 break;
1424 }
1425 }
1426
1427 static const MemoryRegionOps strongarm_ssp_ops = {
1428 .read = strongarm_ssp_read,
1429 .write = strongarm_ssp_write,
1430 .endianness = DEVICE_NATIVE_ENDIAN,
1431 };
1432
1433 static int strongarm_ssp_post_load(void *opaque, int version_id)
1434 {
1435 StrongARMSSPState *s = opaque;
1436
1437 strongarm_ssp_fifo_update(s);
1438
1439 return 0;
1440 }
1441
1442 static int strongarm_ssp_init(SysBusDevice *dev)
1443 {
1444 StrongARMSSPState *s = FROM_SYSBUS(StrongARMSSPState, dev);
1445
1446 sysbus_init_irq(dev, &s->irq);
1447
1448 memory_region_init_io(&s->iomem, &strongarm_ssp_ops, s, "ssp", 0x1000);
1449 sysbus_init_mmio_region(dev, &s->iomem);
1450
1451 s->bus = ssi_create_bus(&dev->qdev, "ssi");
1452 return 0;
1453 }
1454
1455 static void strongarm_ssp_reset(DeviceState *dev)
1456 {
1457 StrongARMSSPState *s = DO_UPCAST(StrongARMSSPState, busdev.qdev, dev);
1458 s->sssr = 0x03; /* 3 bit data, SPI, disabled */
1459 s->rx_start = 0;
1460 s->rx_level = 0;
1461 }
1462
1463 static const VMStateDescription vmstate_strongarm_ssp_regs = {
1464 .name = "strongarm-ssp",
1465 .version_id = 0,
1466 .minimum_version_id = 0,
1467 .minimum_version_id_old = 0,
1468 .post_load = strongarm_ssp_post_load,
1469 .fields = (VMStateField[]) {
1470 VMSTATE_UINT16_ARRAY(sscr, StrongARMSSPState, 2),
1471 VMSTATE_UINT16(sssr, StrongARMSSPState),
1472 VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMSSPState, 8),
1473 VMSTATE_UINT8(rx_start, StrongARMSSPState),
1474 VMSTATE_UINT8(rx_level, StrongARMSSPState),
1475 VMSTATE_END_OF_LIST(),
1476 },
1477 };
1478
1479 static SysBusDeviceInfo strongarm_ssp_info = {
1480 .init = strongarm_ssp_init,
1481 .qdev.name = "strongarm-ssp",
1482 .qdev.desc = "StrongARM SSP controller",
1483 .qdev.size = sizeof(StrongARMSSPState),
1484 .qdev.reset = strongarm_ssp_reset,
1485 .qdev.vmsd = &vmstate_strongarm_ssp_regs,
1486 };
1487
1488 /* Main CPU functions */
1489 StrongARMState *sa1110_init(MemoryRegion *sysmem,
1490 unsigned int sdram_size, const char *rev)
1491 {
1492 StrongARMState *s;
1493 qemu_irq *pic;
1494 int i;
1495
1496 s = g_malloc0(sizeof(StrongARMState));
1497
1498 if (!rev) {
1499 rev = "sa1110-b5";
1500 }
1501
1502 if (strncmp(rev, "sa1110", 6)) {
1503 error_report("Machine requires a SA1110 processor.");
1504 exit(1);
1505 }
1506
1507 s->env = cpu_init(rev);
1508
1509 if (!s->env) {
1510 error_report("Unable to find CPU definition");
1511 exit(1);
1512 }
1513
1514 memory_region_init_ram(&s->sdram, NULL, "strongarm.sdram", sdram_size);
1515 memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram);
1516
1517 pic = arm_pic_init_cpu(s->env);
1518 s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000,
1519 pic[ARM_PIC_CPU_IRQ], pic[ARM_PIC_CPU_FIQ], NULL);
1520
1521 sysbus_create_varargs("pxa25x-timer", 0x90000000,
1522 qdev_get_gpio_in(s->pic, SA_PIC_OSTC0),
1523 qdev_get_gpio_in(s->pic, SA_PIC_OSTC1),
1524 qdev_get_gpio_in(s->pic, SA_PIC_OSTC2),
1525 qdev_get_gpio_in(s->pic, SA_PIC_OSTC3),
1526 NULL);
1527
1528 sysbus_create_simple("strongarm-rtc", 0x90010000,
1529 qdev_get_gpio_in(s->pic, SA_PIC_RTC_ALARM));
1530
1531 s->gpio = strongarm_gpio_init(0x90040000, s->pic);
1532
1533 s->ppc = sysbus_create_varargs("strongarm-ppc", 0x90060000, NULL);
1534
1535 for (i = 0; sa_serial[i].io_base; i++) {
1536 DeviceState *dev = qdev_create(NULL, "strongarm-uart");
1537 qdev_prop_set_chr(dev, "chardev", serial_hds[i]);
1538 qdev_init_nofail(dev);
1539 sysbus_mmio_map(sysbus_from_qdev(dev), 0,
1540 sa_serial[i].io_base);
1541 sysbus_connect_irq(sysbus_from_qdev(dev), 0,
1542 qdev_get_gpio_in(s->pic, sa_serial[i].irq));
1543 }
1544
1545 s->ssp = sysbus_create_varargs("strongarm-ssp", 0x80070000,
1546 qdev_get_gpio_in(s->pic, SA_PIC_SSP), NULL);
1547 s->ssp_bus = (SSIBus *)qdev_get_child_bus(s->ssp, "ssi");
1548
1549 return s;
1550 }
1551
1552 static void strongarm_register_devices(void)
1553 {
1554 sysbus_register_withprop(&strongarm_pic_info);
1555 sysbus_register_withprop(&strongarm_rtc_sysbus_info);
1556 sysbus_register_withprop(&strongarm_gpio_info);
1557 sysbus_register_withprop(&strongarm_ppc_info);
1558 sysbus_register_withprop(&strongarm_uart_info);
1559 sysbus_register_withprop(&strongarm_ssp_info);
1560 }
1561 device_init(strongarm_register_devices)
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