hw/xilinx_zynq.c

   1 /*
   2  * Xilinx Zynq Baseboard System emulation.
   3  *
   4  * Copyright (c) 2010 Xilinx.
   5  * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com)
   6  * Copyright (c) 2012 Petalogix Pty Ltd.
   7  * Written by Haibing Ma
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include "sysbus.h"
  19 #include "arm-misc.h"
  20 #include "net.h"
  21 #include "exec-memory.h"
  22 #include "sysemu.h"
  23 #include "boards.h"
  24 #include "flash.h"
  25 #include "blockdev.h"
  26 #include "loader.h"
  27
  28 #define FLASH_SIZE (64 * 1024 * 1024)
  29 #define FLASH_SECTOR_SIZE (128 * 1024)
  30
  31 #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
  32
  33 static struct arm_boot_info zynq_binfo = {};
  34
  35 static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
  36 {
  37     DeviceState *dev;
  38     SysBusDevice *s;
  39
  40     qemu_check_nic_model(nd, "cadence_gem");
  41     dev = qdev_create(NULL, "cadence_gem");
  42     qdev_set_nic_properties(dev, nd);
  43     qdev_init_nofail(dev);
  44     s = sysbus_from_qdev(dev);
  45     sysbus_mmio_map(s, 0, base);
  46     sysbus_connect_irq(s, 0, irq);
  47 }
  48
  49 static void zynq_init(ram_addr_t ram_size, const char *boot_device,
  50                         const char *kernel_filename, const char *kernel_cmdline,
  51                         const char *initrd_filename, const char *cpu_model)
  52 {
  53     ARMCPU *cpu;
  54     MemoryRegion *address_space_mem = get_system_memory();
  55     MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
  56     MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
  57     DeviceState *dev;
  58     SysBusDevice *busdev;
  59     qemu_irq *irqp;
  60     qemu_irq pic[64];
  61     NICInfo *nd;
  62     int n;
  63     qemu_irq cpu_irq;
  64
  65     if (!cpu_model) {
  66         cpu_model = "cortex-a9";
  67     }
  68
  69     cpu = cpu_arm_init(cpu_model);
  70     if (!cpu) {
  71         fprintf(stderr, "Unable to find CPU definition\n");
  72         exit(1);
  73     }
  74     irqp = arm_pic_init_cpu(cpu);
  75     cpu_irq = irqp[ARM_PIC_CPU_IRQ];
  76
  77     /* max 2GB ram */
  78     if (ram_size > 0x80000000) {
  79         ram_size = 0x80000000;
  80     }
  81
  82     /* DDR remapped to address zero.  */
  83     memory_region_init_ram(ext_ram, "zynq.ext_ram", ram_size);
  84     vmstate_register_ram_global(ext_ram);
  85     memory_region_add_subregion(address_space_mem, 0, ext_ram);
  86
  87     /* 256K of on-chip memory */
  88     memory_region_init_ram(ocm_ram, "zynq.ocm_ram", 256 << 10);
  89     vmstate_register_ram_global(ocm_ram);
  90     memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);
  91
  92     DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
  93
  94     /* AMD */
  95     pflash_cfi02_register(0xe2000000, NULL, "zynq.pflash", FLASH_SIZE,
  96                           dinfo ? dinfo->bdrv : NULL, FLASH_SECTOR_SIZE,
  97                           FLASH_SIZE/FLASH_SECTOR_SIZE, 1,
  98                           1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
  99                               0);
 100
 101     dev = qdev_create(NULL, "xilinx,zynq_slcr");
 102     qdev_init_nofail(dev);
 103     sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xF8000000);
 104
 105     dev = qdev_create(NULL, "a9mpcore_priv");
 106     qdev_prop_set_uint32(dev, "num-cpu", 1);
 107     qdev_init_nofail(dev);
 108     busdev = sysbus_from_qdev(dev);
 109     sysbus_mmio_map(busdev, 0, 0xF8F00000);
 110     sysbus_connect_irq(busdev, 0, cpu_irq);
 111
 112     for (n = 0; n < 64; n++) {
 113         pic[n] = qdev_get_gpio_in(dev, n);
 114     }
 115
 116     sysbus_create_simple("cadence_uart", 0xE0000000, pic[59-IRQ_OFFSET]);
 117     sysbus_create_simple("cadence_uart", 0xE0001000, pic[82-IRQ_OFFSET]);
 118
 119     sysbus_create_varargs("cadence_ttc", 0xF8001000,
 120             pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
 121     sysbus_create_varargs("cadence_ttc", 0xF8002000,
 122             pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL);
 123
 124     for (n = 0; n < nb_nics; n++) {
 125         nd = &nd_table[n];
 126         if (n == 0) {
 127             gem_init(nd, 0xE000B000, pic[54-IRQ_OFFSET]);
 128         } else if (n == 1) {
 129             gem_init(nd, 0xE000C000, pic[77-IRQ_OFFSET]);
 130         }
 131     }
 132
 133     zynq_binfo.ram_size = ram_size;
 134     zynq_binfo.kernel_filename = kernel_filename;
 135     zynq_binfo.kernel_cmdline = kernel_cmdline;
 136     zynq_binfo.initrd_filename = initrd_filename;
 137     zynq_binfo.nb_cpus = 1;
 138     zynq_binfo.board_id = 0xd32;
 139     zynq_binfo.loader_start = 0;
 140     arm_load_kernel(arm_env_get_cpu(first_cpu), &zynq_binfo);
 141 }
 142
 143 static QEMUMachine zynq_machine = {
 144     .name = "xilinx-zynq-a9",
 145     .desc = "Xilinx Zynq Platform Baseboard for Cortex-A9",
 146     .init = zynq_init,
 147     .use_scsi = 1,
 148     .max_cpus = 1,
 149     .no_sdcard = 1
 150 };
 151
 152 static void zynq_machine_init(void)
 153 {
 154     qemu_register_machine(&zynq_machine);
 155 }
 156
 157 machine_init(zynq_machine_init);