hw/musicpal.c

   1 /*
   2  * Marvell MV88W8618 / Freecom MusicPal emulation.
   3  *
   4  * Copyright (c) 2008 Jan Kiszka
   5  *
   6  * This code is licensed under the GNU GPL v2.
   7  *
   8  * Contributions after 2012-01-13 are licensed under the terms of the
   9  * GNU GPL, version 2 or (at your option) any later version.
  10  */
  11
  12 #include "sysbus.h"
  13 #include "arm-misc.h"
  14 #include "devices.h"
  15 #include "net/net.h"
  16 #include "sysemu.h"
  17 #include "boards.h"
  18 #include "serial.h"
  19 #include "qemu-timer.h"
  20 #include "ptimer.h"
  21 #include "block.h"
  22 #include "flash.h"
  23 #include "ui/console.h"
  24 #include "i2c.h"
  25 #include "blockdev.h"
  26 #include "exec-memory.h"
  27 #include "ui/pixel_ops.h"
  28
  29 #define MP_MISC_BASE            0x80002000
  30 #define MP_MISC_SIZE            0x00001000
  31
  32 #define MP_ETH_BASE             0x80008000
  33 #define MP_ETH_SIZE             0x00001000
  34
  35 #define MP_WLAN_BASE            0x8000C000
  36 #define MP_WLAN_SIZE            0x00000800
  37
  38 #define MP_UART1_BASE           0x8000C840
  39 #define MP_UART2_BASE           0x8000C940
  40
  41 #define MP_GPIO_BASE            0x8000D000
  42 #define MP_GPIO_SIZE            0x00001000
  43
  44 #define MP_FLASHCFG_BASE        0x90006000
  45 #define MP_FLASHCFG_SIZE        0x00001000
  46
  47 #define MP_AUDIO_BASE           0x90007000
  48
  49 #define MP_PIC_BASE             0x90008000
  50 #define MP_PIC_SIZE             0x00001000
  51
  52 #define MP_PIT_BASE             0x90009000
  53 #define MP_PIT_SIZE             0x00001000
  54
  55 #define MP_LCD_BASE             0x9000c000
  56 #define MP_LCD_SIZE             0x00001000
  57
  58 #define MP_SRAM_BASE            0xC0000000
  59 #define MP_SRAM_SIZE            0x00020000
  60
  61 #define MP_RAM_DEFAULT_SIZE     32*1024*1024
  62 #define MP_FLASH_SIZE_MAX       32*1024*1024
  63
  64 #define MP_TIMER1_IRQ           4
  65 #define MP_TIMER2_IRQ           5
  66 #define MP_TIMER3_IRQ           6
  67 #define MP_TIMER4_IRQ           7
  68 #define MP_EHCI_IRQ             8
  69 #define MP_ETH_IRQ              9
  70 #define MP_UART1_IRQ            11
  71 #define MP_UART2_IRQ            11
  72 #define MP_GPIO_IRQ             12
  73 #define MP_RTC_IRQ              28
  74 #define MP_AUDIO_IRQ            30
  75
  76 /* Wolfson 8750 I2C address */
  77 #define MP_WM_ADDR              0x1A
  78
  79 /* Ethernet register offsets */
  80 #define MP_ETH_SMIR             0x010
  81 #define MP_ETH_PCXR             0x408
  82 #define MP_ETH_SDCMR            0x448
  83 #define MP_ETH_ICR              0x450
  84 #define MP_ETH_IMR              0x458
  85 #define MP_ETH_FRDP0            0x480
  86 #define MP_ETH_FRDP1            0x484
  87 #define MP_ETH_FRDP2            0x488
  88 #define MP_ETH_FRDP3            0x48C
  89 #define MP_ETH_CRDP0            0x4A0
  90 #define MP_ETH_CRDP1            0x4A4
  91 #define MP_ETH_CRDP2            0x4A8
  92 #define MP_ETH_CRDP3            0x4AC
  93 #define MP_ETH_CTDP0            0x4E0
  94 #define MP_ETH_CTDP1            0x4E4
  95 #define MP_ETH_CTDP2            0x4E8
  96 #define MP_ETH_CTDP3            0x4EC
  97
  98 /* MII PHY access */
  99 #define MP_ETH_SMIR_DATA        0x0000FFFF
 100 #define MP_ETH_SMIR_ADDR        0x03FF0000
 101 #define MP_ETH_SMIR_OPCODE      (1 << 26) /* Read value */
 102 #define MP_ETH_SMIR_RDVALID     (1 << 27)
 103
 104 /* PHY registers */
 105 #define MP_ETH_PHY1_BMSR        0x00210000
 106 #define MP_ETH_PHY1_PHYSID1     0x00410000
 107 #define MP_ETH_PHY1_PHYSID2     0x00610000
 108
 109 #define MP_PHY_BMSR_LINK        0x0004
 110 #define MP_PHY_BMSR_AUTONEG     0x0008
 111
 112 #define MP_PHY_88E3015          0x01410E20
 113
 114 /* TX descriptor status */
 115 #define MP_ETH_TX_OWN           (1 << 31)
 116
 117 /* RX descriptor status */
 118 #define MP_ETH_RX_OWN           (1 << 31)
 119
 120 /* Interrupt cause/mask bits */
 121 #define MP_ETH_IRQ_RX_BIT       0
 122 #define MP_ETH_IRQ_RX           (1 << MP_ETH_IRQ_RX_BIT)
 123 #define MP_ETH_IRQ_TXHI_BIT     2
 124 #define MP_ETH_IRQ_TXLO_BIT     3
 125
 126 /* Port config bits */
 127 #define MP_ETH_PCXR_2BSM_BIT    28 /* 2-byte incoming suffix */
 128
 129 /* SDMA command bits */
 130 #define MP_ETH_CMD_TXHI         (1 << 23)
 131 #define MP_ETH_CMD_TXLO         (1 << 22)
 132
 133 typedef struct mv88w8618_tx_desc {
 134     uint32_t cmdstat;
 135     uint16_t res;
 136     uint16_t bytes;
 137     uint32_t buffer;
 138     uint32_t next;
 139 } mv88w8618_tx_desc;
 140
 141 typedef struct mv88w8618_rx_desc {
 142     uint32_t cmdstat;
 143     uint16_t bytes;
 144     uint16_t buffer_size;
 145     uint32_t buffer;
 146     uint32_t next;
 147 } mv88w8618_rx_desc;
 148
 149 typedef struct mv88w8618_eth_state {
 150     SysBusDevice busdev;
 151     MemoryRegion iomem;
 152     qemu_irq irq;
 153     uint32_t smir;
 154     uint32_t icr;
 155     uint32_t imr;
 156     int mmio_index;
 157     uint32_t vlan_header;
 158     uint32_t tx_queue[2];
 159     uint32_t rx_queue[4];
 160     uint32_t frx_queue[4];
 161     uint32_t cur_rx[4];
 162     NICState *nic;
 163     NICConf conf;
 164 } mv88w8618_eth_state;
 165
 166 static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc)
 167 {
 168     cpu_to_le32s(&desc->cmdstat);
 169     cpu_to_le16s(&desc->bytes);
 170     cpu_to_le16s(&desc->buffer_size);
 171     cpu_to_le32s(&desc->buffer);
 172     cpu_to_le32s(&desc->next);
 173     cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
 174 }
 175
 176 static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc)
 177 {
 178     cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
 179     le32_to_cpus(&desc->cmdstat);
 180     le16_to_cpus(&desc->bytes);
 181     le16_to_cpus(&desc->buffer_size);
 182     le32_to_cpus(&desc->buffer);
 183     le32_to_cpus(&desc->next);
 184 }
 185
 186 static int eth_can_receive(NetClientState *nc)
 187 {
 188     return 1;
 189 }
 190
 191 static ssize_t eth_receive(NetClientState *nc, const uint8_t *buf, size_t size)
 192 {
 193     mv88w8618_eth_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
 194     uint32_t desc_addr;
 195     mv88w8618_rx_desc desc;
 196     int i;
 197
 198     for (i = 0; i < 4; i++) {
 199         desc_addr = s->cur_rx[i];
 200         if (!desc_addr) {
 201             continue;
 202         }
 203         do {
 204             eth_rx_desc_get(desc_addr, &desc);
 205             if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) {
 206                 cpu_physical_memory_write(desc.buffer + s->vlan_header,
 207                                           buf, size);
 208                 desc.bytes = size + s->vlan_header;
 209                 desc.cmdstat &= ~MP_ETH_RX_OWN;
 210                 s->cur_rx[i] = desc.next;
 211
 212                 s->icr |= MP_ETH_IRQ_RX;
 213                 if (s->icr & s->imr) {
 214                     qemu_irq_raise(s->irq);
 215                 }
 216                 eth_rx_desc_put(desc_addr, &desc);
 217                 return size;
 218             }
 219             desc_addr = desc.next;
 220         } while (desc_addr != s->rx_queue[i]);
 221     }
 222     return size;
 223 }
 224
 225 static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc)
 226 {
 227     cpu_to_le32s(&desc->cmdstat);
 228     cpu_to_le16s(&desc->res);
 229     cpu_to_le16s(&desc->bytes);
 230     cpu_to_le32s(&desc->buffer);
 231     cpu_to_le32s(&desc->next);
 232     cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
 233 }
 234
 235 static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc)
 236 {
 237     cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
 238     le32_to_cpus(&desc->cmdstat);
 239     le16_to_cpus(&desc->res);
 240     le16_to_cpus(&desc->bytes);
 241     le32_to_cpus(&desc->buffer);
 242     le32_to_cpus(&desc->next);
 243 }
 244
 245 static void eth_send(mv88w8618_eth_state *s, int queue_index)
 246 {
 247     uint32_t desc_addr = s->tx_queue[queue_index];
 248     mv88w8618_tx_desc desc;
 249     uint32_t next_desc;
 250     uint8_t buf[2048];
 251     int len;
 252
 253     do {
 254         eth_tx_desc_get(desc_addr, &desc);
 255         next_desc = desc.next;
 256         if (desc.cmdstat & MP_ETH_TX_OWN) {
 257             len = desc.bytes;
 258             if (len < 2048) {
 259                 cpu_physical_memory_read(desc.buffer, buf, len);
 260                 qemu_send_packet(&s->nic->nc, buf, len);
 261             }
 262             desc.cmdstat &= ~MP_ETH_TX_OWN;
 263             s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
 264             eth_tx_desc_put(desc_addr, &desc);
 265         }
 266         desc_addr = next_desc;
 267     } while (desc_addr != s->tx_queue[queue_index]);
 268 }
 269
 270 static uint64_t mv88w8618_eth_read(void *opaque, hwaddr offset,
 271                                    unsigned size)
 272 {
 273     mv88w8618_eth_state *s = opaque;
 274
 275     switch (offset) {
 276     case MP_ETH_SMIR:
 277         if (s->smir & MP_ETH_SMIR_OPCODE) {
 278             switch (s->smir & MP_ETH_SMIR_ADDR) {
 279             case MP_ETH_PHY1_BMSR:
 280                 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
 281                        MP_ETH_SMIR_RDVALID;
 282             case MP_ETH_PHY1_PHYSID1:
 283                 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID;
 284             case MP_ETH_PHY1_PHYSID2:
 285                 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID;
 286             default:
 287                 return MP_ETH_SMIR_RDVALID;
 288             }
 289         }
 290         return 0;
 291
 292     case MP_ETH_ICR:
 293         return s->icr;
 294
 295     case MP_ETH_IMR:
 296         return s->imr;
 297
 298     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 299         return s->frx_queue[(offset - MP_ETH_FRDP0)/4];
 300
 301     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 302         return s->rx_queue[(offset - MP_ETH_CRDP0)/4];
 303
 304     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 305         return s->tx_queue[(offset - MP_ETH_CTDP0)/4];
 306
 307     default:
 308         return 0;
 309     }
 310 }
 311
 312 static void mv88w8618_eth_write(void *opaque, hwaddr offset,
 313                                 uint64_t value, unsigned size)
 314 {
 315     mv88w8618_eth_state *s = opaque;
 316
 317     switch (offset) {
 318     case MP_ETH_SMIR:
 319         s->smir = value;
 320         break;
 321
 322     case MP_ETH_PCXR:
 323         s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2;
 324         break;
 325
 326     case MP_ETH_SDCMR:
 327         if (value & MP_ETH_CMD_TXHI) {
 328             eth_send(s, 1);
 329         }
 330         if (value & MP_ETH_CMD_TXLO) {
 331             eth_send(s, 0);
 332         }
 333         if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr) {
 334             qemu_irq_raise(s->irq);
 335         }
 336         break;
 337
 338     case MP_ETH_ICR:
 339         s->icr &= value;
 340         break;
 341
 342     case MP_ETH_IMR:
 343         s->imr = value;
 344         if (s->icr & s->imr) {
 345             qemu_irq_raise(s->irq);
 346         }
 347         break;
 348
 349     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 350         s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value;
 351         break;
 352
 353     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 354         s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
 355             s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value;
 356         break;
 357
 358     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 359         s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value;
 360         break;
 361     }
 362 }
 363
 364 static const MemoryRegionOps mv88w8618_eth_ops = {
 365     .read = mv88w8618_eth_read,
 366     .write = mv88w8618_eth_write,
 367     .endianness = DEVICE_NATIVE_ENDIAN,
 368 };
 369
 370 static void eth_cleanup(NetClientState *nc)
 371 {
 372     mv88w8618_eth_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
 373
 374     s->nic = NULL;
 375 }
 376
 377 static NetClientInfo net_mv88w8618_info = {
 378     .type = NET_CLIENT_OPTIONS_KIND_NIC,
 379     .size = sizeof(NICState),
 380     .can_receive = eth_can_receive,
 381     .receive = eth_receive,
 382     .cleanup = eth_cleanup,
 383 };
 384
 385 static int mv88w8618_eth_init(SysBusDevice *dev)
 386 {
 387     mv88w8618_eth_state *s = FROM_SYSBUS(mv88w8618_eth_state, dev);
 388
 389     sysbus_init_irq(dev, &s->irq);
 390     s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf,
 391                           object_get_typename(OBJECT(dev)), dev->qdev.id, s);
 392     memory_region_init_io(&s->iomem, &mv88w8618_eth_ops, s, "mv88w8618-eth",
 393                           MP_ETH_SIZE);
 394     sysbus_init_mmio(dev, &s->iomem);
 395     return 0;
 396 }
 397
 398 static const VMStateDescription mv88w8618_eth_vmsd = {
 399     .name = "mv88w8618_eth",
 400     .version_id = 1,
 401     .minimum_version_id = 1,
 402     .minimum_version_id_old = 1,
 403     .fields = (VMStateField[]) {
 404         VMSTATE_UINT32(smir, mv88w8618_eth_state),
 405         VMSTATE_UINT32(icr, mv88w8618_eth_state),
 406         VMSTATE_UINT32(imr, mv88w8618_eth_state),
 407         VMSTATE_UINT32(vlan_header, mv88w8618_eth_state),
 408         VMSTATE_UINT32_ARRAY(tx_queue, mv88w8618_eth_state, 2),
 409         VMSTATE_UINT32_ARRAY(rx_queue, mv88w8618_eth_state, 4),
 410         VMSTATE_UINT32_ARRAY(frx_queue, mv88w8618_eth_state, 4),
 411         VMSTATE_UINT32_ARRAY(cur_rx, mv88w8618_eth_state, 4),
 412         VMSTATE_END_OF_LIST()
 413     }
 414 };
 415
 416 static Property mv88w8618_eth_properties[] = {
 417     DEFINE_NIC_PROPERTIES(mv88w8618_eth_state, conf),
 418     DEFINE_PROP_END_OF_LIST(),
 419 };
 420
 421 static void mv88w8618_eth_class_init(ObjectClass *klass, void *data)
 422 {
 423     DeviceClass *dc = DEVICE_CLASS(klass);
 424     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 425
 426     k->init = mv88w8618_eth_init;
 427     dc->vmsd = &mv88w8618_eth_vmsd;
 428     dc->props = mv88w8618_eth_properties;
 429 }
 430
 431 static TypeInfo mv88w8618_eth_info = {
 432     .name          = "mv88w8618_eth",
 433     .parent        = TYPE_SYS_BUS_DEVICE,
 434     .instance_size = sizeof(mv88w8618_eth_state),
 435     .class_init    = mv88w8618_eth_class_init,
 436 };
 437
 438 /* LCD register offsets */
 439 #define MP_LCD_IRQCTRL          0x180
 440 #define MP_LCD_IRQSTAT          0x184
 441 #define MP_LCD_SPICTRL          0x1ac
 442 #define MP_LCD_INST             0x1bc
 443 #define MP_LCD_DATA             0x1c0
 444
 445 /* Mode magics */
 446 #define MP_LCD_SPI_DATA         0x00100011
 447 #define MP_LCD_SPI_CMD          0x00104011
 448 #define MP_LCD_SPI_INVALID      0x00000000
 449
 450 /* Commmands */
 451 #define MP_LCD_INST_SETPAGE0    0xB0
 452 /* ... */
 453 #define MP_LCD_INST_SETPAGE7    0xB7
 454
 455 #define MP_LCD_TEXTCOLOR        0xe0e0ff /* RRGGBB */
 456
 457 typedef struct musicpal_lcd_state {
 458     SysBusDevice busdev;
 459     MemoryRegion iomem;
 460     uint32_t brightness;
 461     uint32_t mode;
 462     uint32_t irqctrl;
 463     uint32_t page;
 464     uint32_t page_off;
 465     DisplayState *ds;
 466     uint8_t video_ram[128*64/8];
 467 } musicpal_lcd_state;
 468
 469 static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col)
 470 {
 471     switch (s->brightness) {
 472     case 7:
 473         return col;
 474     case 0:
 475         return 0;
 476     default:
 477         return (col * s->brightness) / 7;
 478     }
 479 }
 480
 481 #define SET_LCD_PIXEL(depth, type) \
 482 static inline void glue(set_lcd_pixel, depth) \
 483         (musicpal_lcd_state *s, int x, int y, type col) \
 484 { \
 485     int dx, dy; \
 486     type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \
 487 \
 488     for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
 489         for (dx = 0; dx < 3; dx++, pixel++) \
 490             *pixel = col; \
 491 }
 492 SET_LCD_PIXEL(8, uint8_t)
 493 SET_LCD_PIXEL(16, uint16_t)
 494 SET_LCD_PIXEL(32, uint32_t)
 495
 496 static void lcd_refresh(void *opaque)
 497 {
 498     musicpal_lcd_state *s = opaque;
 499     int x, y, col;
 500
 501     switch (ds_get_bits_per_pixel(s->ds)) {
 502     case 0:
 503         return;
 504 #define LCD_REFRESH(depth, func) \
 505     case depth: \
 506         col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \
 507                    scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \
 508                    scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \
 509         for (x = 0; x < 128; x++) { \
 510             for (y = 0; y < 64; y++) { \
 511                 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \
 512                     glue(set_lcd_pixel, depth)(s, x, y, col); \
 513                 } else { \
 514                     glue(set_lcd_pixel, depth)(s, x, y, 0); \
 515                 } \
 516             } \
 517         } \
 518         break;
 519     LCD_REFRESH(8, rgb_to_pixel8)
 520     LCD_REFRESH(16, rgb_to_pixel16)
 521     LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ?
 522                      rgb_to_pixel32bgr : rgb_to_pixel32))
 523     default:
 524         hw_error("unsupported colour depth %i\n",
 525                   ds_get_bits_per_pixel(s->ds));
 526     }
 527
 528     dpy_gfx_update(s->ds, 0, 0, 128*3, 64*3);
 529 }
 530
 531 static void lcd_invalidate(void *opaque)
 532 {
 533 }
 534
 535 static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level)
 536 {
 537     musicpal_lcd_state *s = opaque;
 538     s->brightness &= ~(1 << irq);
 539     s->brightness |= level << irq;
 540 }
 541
 542 static uint64_t musicpal_lcd_read(void *opaque, hwaddr offset,
 543                                   unsigned size)
 544 {
 545     musicpal_lcd_state *s = opaque;
 546
 547     switch (offset) {
 548     case MP_LCD_IRQCTRL:
 549         return s->irqctrl;
 550
 551     default:
 552         return 0;
 553     }
 554 }
 555
 556 static void musicpal_lcd_write(void *opaque, hwaddr offset,
 557                                uint64_t value, unsigned size)
 558 {
 559     musicpal_lcd_state *s = opaque;
 560
 561     switch (offset) {
 562     case MP_LCD_IRQCTRL:
 563         s->irqctrl = value;
 564         break;
 565
 566     case MP_LCD_SPICTRL:
 567         if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD) {
 568             s->mode = value;
 569         } else {
 570             s->mode = MP_LCD_SPI_INVALID;
 571         }
 572         break;
 573
 574     case MP_LCD_INST:
 575         if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
 576             s->page = value - MP_LCD_INST_SETPAGE0;
 577             s->page_off = 0;
 578         }
 579         break;
 580
 581     case MP_LCD_DATA:
 582         if (s->mode == MP_LCD_SPI_CMD) {
 583             if (value >= MP_LCD_INST_SETPAGE0 &&
 584                 value <= MP_LCD_INST_SETPAGE7) {
 585                 s->page = value - MP_LCD_INST_SETPAGE0;
 586                 s->page_off = 0;
 587             }
 588         } else if (s->mode == MP_LCD_SPI_DATA) {
 589             s->video_ram[s->page*128 + s->page_off] = value;
 590             s->page_off = (s->page_off + 1) & 127;
 591         }
 592         break;
 593     }
 594 }
 595
 596 static const MemoryRegionOps musicpal_lcd_ops = {
 597     .read = musicpal_lcd_read,
 598     .write = musicpal_lcd_write,
 599     .endianness = DEVICE_NATIVE_ENDIAN,
 600 };
 601
 602 static int musicpal_lcd_init(SysBusDevice *dev)
 603 {
 604     musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev);
 605
 606     s->brightness = 7;
 607
 608     memory_region_init_io(&s->iomem, &musicpal_lcd_ops, s,
 609                           "musicpal-lcd", MP_LCD_SIZE);
 610     sysbus_init_mmio(dev, &s->iomem);
 611
 612     s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
 613                                  NULL, NULL, s);
 614     qemu_console_resize(s->ds, 128*3, 64*3);
 615
 616     qdev_init_gpio_in(&dev->qdev, musicpal_lcd_gpio_brigthness_in, 3);
 617
 618     return 0;
 619 }
 620
 621 static const VMStateDescription musicpal_lcd_vmsd = {
 622     .name = "musicpal_lcd",
 623     .version_id = 1,
 624     .minimum_version_id = 1,
 625     .minimum_version_id_old = 1,
 626     .fields = (VMStateField[]) {
 627         VMSTATE_UINT32(brightness, musicpal_lcd_state),
 628         VMSTATE_UINT32(mode, musicpal_lcd_state),
 629         VMSTATE_UINT32(irqctrl, musicpal_lcd_state),
 630         VMSTATE_UINT32(page, musicpal_lcd_state),
 631         VMSTATE_UINT32(page_off, musicpal_lcd_state),
 632         VMSTATE_BUFFER(video_ram, musicpal_lcd_state),
 633         VMSTATE_END_OF_LIST()
 634     }
 635 };
 636
 637 static void musicpal_lcd_class_init(ObjectClass *klass, void *data)
 638 {
 639     DeviceClass *dc = DEVICE_CLASS(klass);
 640     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 641
 642     k->init = musicpal_lcd_init;
 643     dc->vmsd = &musicpal_lcd_vmsd;
 644 }
 645
 646 static TypeInfo musicpal_lcd_info = {
 647     .name          = "musicpal_lcd",
 648     .parent        = TYPE_SYS_BUS_DEVICE,
 649     .instance_size = sizeof(musicpal_lcd_state),
 650     .class_init    = musicpal_lcd_class_init,
 651 };
 652
 653 /* PIC register offsets */
 654 #define MP_PIC_STATUS           0x00
 655 #define MP_PIC_ENABLE_SET       0x08
 656 #define MP_PIC_ENABLE_CLR       0x0C
 657
 658 typedef struct mv88w8618_pic_state
 659 {
 660     SysBusDevice busdev;
 661     MemoryRegion iomem;
 662     uint32_t level;
 663     uint32_t enabled;
 664     qemu_irq parent_irq;
 665 } mv88w8618_pic_state;
 666
 667 static void mv88w8618_pic_update(mv88w8618_pic_state *s)
 668 {
 669     qemu_set_irq(s->parent_irq, (s->level & s->enabled));
 670 }
 671
 672 static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
 673 {
 674     mv88w8618_pic_state *s = opaque;
 675
 676     if (level) {
 677         s->level |= 1 << irq;
 678     } else {
 679         s->level &= ~(1 << irq);
 680     }
 681     mv88w8618_pic_update(s);
 682 }
 683
 684 static uint64_t mv88w8618_pic_read(void *opaque, hwaddr offset,
 685                                    unsigned size)
 686 {
 687     mv88w8618_pic_state *s = opaque;
 688
 689     switch (offset) {
 690     case MP_PIC_STATUS:
 691         return s->level & s->enabled;
 692
 693     default:
 694         return 0;
 695     }
 696 }
 697
 698 static void mv88w8618_pic_write(void *opaque, hwaddr offset,
 699                                 uint64_t value, unsigned size)
 700 {
 701     mv88w8618_pic_state *s = opaque;
 702
 703     switch (offset) {
 704     case MP_PIC_ENABLE_SET:
 705         s->enabled |= value;
 706         break;
 707
 708     case MP_PIC_ENABLE_CLR:
 709         s->enabled &= ~value;
 710         s->level &= ~value;
 711         break;
 712     }
 713     mv88w8618_pic_update(s);
 714 }
 715
 716 static void mv88w8618_pic_reset(DeviceState *d)
 717 {
 718     mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state,
 719                                          sysbus_from_qdev(d));
 720
 721     s->level = 0;
 722     s->enabled = 0;
 723 }
 724
 725 static const MemoryRegionOps mv88w8618_pic_ops = {
 726     .read = mv88w8618_pic_read,
 727     .write = mv88w8618_pic_write,
 728     .endianness = DEVICE_NATIVE_ENDIAN,
 729 };
 730
 731 static int mv88w8618_pic_init(SysBusDevice *dev)
 732 {
 733     mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, dev);
 734
 735     qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);
 736     sysbus_init_irq(dev, &s->parent_irq);
 737     memory_region_init_io(&s->iomem, &mv88w8618_pic_ops, s,
 738                           "musicpal-pic", MP_PIC_SIZE);
 739     sysbus_init_mmio(dev, &s->iomem);
 740     return 0;
 741 }
 742
 743 static const VMStateDescription mv88w8618_pic_vmsd = {
 744     .name = "mv88w8618_pic",
 745     .version_id = 1,
 746     .minimum_version_id = 1,
 747     .minimum_version_id_old = 1,
 748     .fields = (VMStateField[]) {
 749         VMSTATE_UINT32(level, mv88w8618_pic_state),
 750         VMSTATE_UINT32(enabled, mv88w8618_pic_state),
 751         VMSTATE_END_OF_LIST()
 752     }
 753 };
 754
 755 static void mv88w8618_pic_class_init(ObjectClass *klass, void *data)
 756 {
 757     DeviceClass *dc = DEVICE_CLASS(klass);
 758     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 759
 760     k->init = mv88w8618_pic_init;
 761     dc->reset = mv88w8618_pic_reset;
 762     dc->vmsd = &mv88w8618_pic_vmsd;
 763 }
 764
 765 static TypeInfo mv88w8618_pic_info = {
 766     .name          = "mv88w8618_pic",
 767     .parent        = TYPE_SYS_BUS_DEVICE,
 768     .instance_size = sizeof(mv88w8618_pic_state),
 769     .class_init    = mv88w8618_pic_class_init,
 770 };
 771
 772 /* PIT register offsets */
 773 #define MP_PIT_TIMER1_LENGTH    0x00
 774 /* ... */
 775 #define MP_PIT_TIMER4_LENGTH    0x0C
 776 #define MP_PIT_CONTROL          0x10
 777 #define MP_PIT_TIMER1_VALUE     0x14
 778 /* ... */
 779 #define MP_PIT_TIMER4_VALUE     0x20
 780 #define MP_BOARD_RESET          0x34
 781
 782 /* Magic board reset value (probably some watchdog behind it) */
 783 #define MP_BOARD_RESET_MAGIC    0x10000
 784
 785 typedef struct mv88w8618_timer_state {
 786     ptimer_state *ptimer;
 787     uint32_t limit;
 788     int freq;
 789     qemu_irq irq;
 790 } mv88w8618_timer_state;
 791
 792 typedef struct mv88w8618_pit_state {
 793     SysBusDevice busdev;
 794     MemoryRegion iomem;
 795     mv88w8618_timer_state timer[4];
 796 } mv88w8618_pit_state;
 797
 798 static void mv88w8618_timer_tick(void *opaque)
 799 {
 800     mv88w8618_timer_state *s = opaque;
 801
 802     qemu_irq_raise(s->irq);
 803 }
 804
 805 static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s,
 806                                  uint32_t freq)
 807 {
 808     QEMUBH *bh;
 809
 810     sysbus_init_irq(dev, &s->irq);
 811     s->freq = freq;
 812
 813     bh = qemu_bh_new(mv88w8618_timer_tick, s);
 814     s->ptimer = ptimer_init(bh);
 815 }
 816
 817 static uint64_t mv88w8618_pit_read(void *opaque, hwaddr offset,
 818                                    unsigned size)
 819 {
 820     mv88w8618_pit_state *s = opaque;
 821     mv88w8618_timer_state *t;
 822
 823     switch (offset) {
 824     case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
 825         t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
 826         return ptimer_get_count(t->ptimer);
 827
 828     default:
 829         return 0;
 830     }
 831 }
 832
 833 static void mv88w8618_pit_write(void *opaque, hwaddr offset,
 834                                 uint64_t value, unsigned size)
 835 {
 836     mv88w8618_pit_state *s = opaque;
 837     mv88w8618_timer_state *t;
 838     int i;
 839
 840     switch (offset) {
 841     case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
 842         t = &s->timer[offset >> 2];
 843         t->limit = value;
 844         if (t->limit > 0) {
 845             ptimer_set_limit(t->ptimer, t->limit, 1);
 846         } else {
 847             ptimer_stop(t->ptimer);
 848         }
 849         break;
 850
 851     case MP_PIT_CONTROL:
 852         for (i = 0; i < 4; i++) {
 853             t = &s->timer[i];
 854             if (value & 0xf && t->limit > 0) {
 855                 ptimer_set_limit(t->ptimer, t->limit, 0);
 856                 ptimer_set_freq(t->ptimer, t->freq);
 857                 ptimer_run(t->ptimer, 0);
 858             } else {
 859                 ptimer_stop(t->ptimer);
 860             }
 861             value >>= 4;
 862         }
 863         break;
 864
 865     case MP_BOARD_RESET:
 866         if (value == MP_BOARD_RESET_MAGIC) {
 867             qemu_system_reset_request();
 868         }
 869         break;
 870     }
 871 }
 872
 873 static void mv88w8618_pit_reset(DeviceState *d)
 874 {
 875     mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state,
 876                                          sysbus_from_qdev(d));
 877     int i;
 878
 879     for (i = 0; i < 4; i++) {
 880         ptimer_stop(s->timer[i].ptimer);
 881         s->timer[i].limit = 0;
 882     }
 883 }
 884
 885 static const MemoryRegionOps mv88w8618_pit_ops = {
 886     .read = mv88w8618_pit_read,
 887     .write = mv88w8618_pit_write,
 888     .endianness = DEVICE_NATIVE_ENDIAN,
 889 };
 890
 891 static int mv88w8618_pit_init(SysBusDevice *dev)
 892 {
 893     mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, dev);
 894     int i;
 895
 896     /* Letting them all run at 1 MHz is likely just a pragmatic
 897      * simplification. */
 898     for (i = 0; i < 4; i++) {
 899         mv88w8618_timer_init(dev, &s->timer[i], 1000000);
 900     }
 901
 902     memory_region_init_io(&s->iomem, &mv88w8618_pit_ops, s,
 903                           "musicpal-pit", MP_PIT_SIZE);
 904     sysbus_init_mmio(dev, &s->iomem);
 905     return 0;
 906 }
 907
 908 static const VMStateDescription mv88w8618_timer_vmsd = {
 909     .name = "timer",
 910     .version_id = 1,
 911     .minimum_version_id = 1,
 912     .minimum_version_id_old = 1,
 913     .fields = (VMStateField[]) {
 914         VMSTATE_PTIMER(ptimer, mv88w8618_timer_state),
 915         VMSTATE_UINT32(limit, mv88w8618_timer_state),
 916         VMSTATE_END_OF_LIST()
 917     }
 918 };
 919
 920 static const VMStateDescription mv88w8618_pit_vmsd = {
 921     .name = "mv88w8618_pit",
 922     .version_id = 1,
 923     .minimum_version_id = 1,
 924     .minimum_version_id_old = 1,
 925     .fields = (VMStateField[]) {
 926         VMSTATE_STRUCT_ARRAY(timer, mv88w8618_pit_state, 4, 1,
 927                              mv88w8618_timer_vmsd, mv88w8618_timer_state),
 928         VMSTATE_END_OF_LIST()
 929     }
 930 };
 931
 932 static void mv88w8618_pit_class_init(ObjectClass *klass, void *data)
 933 {
 934     DeviceClass *dc = DEVICE_CLASS(klass);
 935     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 936
 937     k->init = mv88w8618_pit_init;
 938     dc->reset = mv88w8618_pit_reset;
 939     dc->vmsd = &mv88w8618_pit_vmsd;
 940 }
 941
 942 static TypeInfo mv88w8618_pit_info = {
 943     .name          = "mv88w8618_pit",
 944     .parent        = TYPE_SYS_BUS_DEVICE,
 945     .instance_size = sizeof(mv88w8618_pit_state),
 946     .class_init    = mv88w8618_pit_class_init,
 947 };
 948
 949 /* Flash config register offsets */
 950 #define MP_FLASHCFG_CFGR0    0x04
 951
 952 typedef struct mv88w8618_flashcfg_state {
 953     SysBusDevice busdev;
 954     MemoryRegion iomem;
 955     uint32_t cfgr0;
 956 } mv88w8618_flashcfg_state;
 957
 958 static uint64_t mv88w8618_flashcfg_read(void *opaque,
 959                                         hwaddr offset,
 960                                         unsigned size)
 961 {
 962     mv88w8618_flashcfg_state *s = opaque;
 963
 964     switch (offset) {
 965     case MP_FLASHCFG_CFGR0:
 966         return s->cfgr0;
 967
 968     default:
 969         return 0;
 970     }
 971 }
 972
 973 static void mv88w8618_flashcfg_write(void *opaque, hwaddr offset,
 974                                      uint64_t value, unsigned size)
 975 {
 976     mv88w8618_flashcfg_state *s = opaque;
 977
 978     switch (offset) {
 979     case MP_FLASHCFG_CFGR0:
 980         s->cfgr0 = value;
 981         break;
 982     }
 983 }
 984
 985 static const MemoryRegionOps mv88w8618_flashcfg_ops = {
 986     .read = mv88w8618_flashcfg_read,
 987     .write = mv88w8618_flashcfg_write,
 988     .endianness = DEVICE_NATIVE_ENDIAN,
 989 };
 990
 991 static int mv88w8618_flashcfg_init(SysBusDevice *dev)
 992 {
 993     mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev);
 994
 995     s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
 996     memory_region_init_io(&s->iomem, &mv88w8618_flashcfg_ops, s,
 997                           "musicpal-flashcfg", MP_FLASHCFG_SIZE);
 998     sysbus_init_mmio(dev, &s->iomem);
 999     return 0;
1000 }
1001
1002 static const VMStateDescription mv88w8618_flashcfg_vmsd = {
1003     .name = "mv88w8618_flashcfg",
1004     .version_id = 1,
1005     .minimum_version_id = 1,
1006     .minimum_version_id_old = 1,
1007     .fields = (VMStateField[]) {
1008         VMSTATE_UINT32(cfgr0, mv88w8618_flashcfg_state),
1009         VMSTATE_END_OF_LIST()
1010     }
1011 };
1012
1013 static void mv88w8618_flashcfg_class_init(ObjectClass *klass, void *data)
1014 {
1015     DeviceClass *dc = DEVICE_CLASS(klass);
1016     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1017
1018     k->init = mv88w8618_flashcfg_init;
1019     dc->vmsd = &mv88w8618_flashcfg_vmsd;
1020 }
1021
1022 static TypeInfo mv88w8618_flashcfg_info = {
1023     .name          = "mv88w8618_flashcfg",
1024     .parent        = TYPE_SYS_BUS_DEVICE,
1025     .instance_size = sizeof(mv88w8618_flashcfg_state),
1026     .class_init    = mv88w8618_flashcfg_class_init,
1027 };
1028
1029 /* Misc register offsets */
1030 #define MP_MISC_BOARD_REVISION  0x18
1031
1032 #define MP_BOARD_REVISION       0x31
1033
1034 static uint64_t musicpal_misc_read(void *opaque, hwaddr offset,
1035                                    unsigned size)
1036 {
1037     switch (offset) {
1038     case MP_MISC_BOARD_REVISION:
1039         return MP_BOARD_REVISION;
1040
1041     default:
1042         return 0;
1043     }
1044 }
1045
1046 static void musicpal_misc_write(void *opaque, hwaddr offset,
1047                                 uint64_t value, unsigned size)
1048 {
1049 }
1050
1051 static const MemoryRegionOps musicpal_misc_ops = {
1052     .read = musicpal_misc_read,
1053     .write = musicpal_misc_write,
1054     .endianness = DEVICE_NATIVE_ENDIAN,
1055 };
1056
1057 static void musicpal_misc_init(SysBusDevice *dev)
1058 {
1059     MemoryRegion *iomem = g_new(MemoryRegion, 1);
1060
1061     memory_region_init_io(iomem, &musicpal_misc_ops, NULL,
1062                           "musicpal-misc", MP_MISC_SIZE);
1063     sysbus_add_memory(dev, MP_MISC_BASE, iomem);
1064 }
1065
1066 /* WLAN register offsets */
1067 #define MP_WLAN_MAGIC1          0x11c
1068 #define MP_WLAN_MAGIC2          0x124
1069
1070 static uint64_t mv88w8618_wlan_read(void *opaque, hwaddr offset,
1071                                     unsigned size)
1072 {
1073     switch (offset) {
1074     /* Workaround to allow loading the binary-only wlandrv.ko crap
1075      * from the original Freecom firmware. */
1076     case MP_WLAN_MAGIC1:
1077         return ~3;
1078     case MP_WLAN_MAGIC2:
1079         return -1;
1080
1081     default:
1082         return 0;
1083     }
1084 }
1085
1086 static void mv88w8618_wlan_write(void *opaque, hwaddr offset,
1087                                  uint64_t value, unsigned size)
1088 {
1089 }
1090
1091 static const MemoryRegionOps mv88w8618_wlan_ops = {
1092     .read = mv88w8618_wlan_read,
1093     .write =mv88w8618_wlan_write,
1094     .endianness = DEVICE_NATIVE_ENDIAN,
1095 };
1096
1097 static int mv88w8618_wlan_init(SysBusDevice *dev)
1098 {
1099     MemoryRegion *iomem = g_new(MemoryRegion, 1);
1100
1101     memory_region_init_io(iomem, &mv88w8618_wlan_ops, NULL,
1102                           "musicpal-wlan", MP_WLAN_SIZE);
1103     sysbus_init_mmio(dev, iomem);
1104     return 0;
1105 }
1106
1107 /* GPIO register offsets */
1108 #define MP_GPIO_OE_LO           0x008
1109 #define MP_GPIO_OUT_LO          0x00c
1110 #define MP_GPIO_IN_LO           0x010
1111 #define MP_GPIO_IER_LO          0x014
1112 #define MP_GPIO_IMR_LO          0x018
1113 #define MP_GPIO_ISR_LO          0x020
1114 #define MP_GPIO_OE_HI           0x508
1115 #define MP_GPIO_OUT_HI          0x50c
1116 #define MP_GPIO_IN_HI           0x510
1117 #define MP_GPIO_IER_HI          0x514
1118 #define MP_GPIO_IMR_HI          0x518
1119 #define MP_GPIO_ISR_HI          0x520
1120
1121 /* GPIO bits & masks */
1122 #define MP_GPIO_LCD_BRIGHTNESS  0x00070000
1123 #define MP_GPIO_I2C_DATA_BIT    29
1124 #define MP_GPIO_I2C_CLOCK_BIT   30
1125
1126 /* LCD brightness bits in GPIO_OE_HI */
1127 #define MP_OE_LCD_BRIGHTNESS    0x0007
1128
1129 typedef struct musicpal_gpio_state {
1130     SysBusDevice busdev;
1131     MemoryRegion iomem;
1132     uint32_t lcd_brightness;
1133     uint32_t out_state;
1134     uint32_t in_state;
1135     uint32_t ier;
1136     uint32_t imr;
1137     uint32_t isr;
1138     qemu_irq irq;
1139     qemu_irq out[5]; /* 3 brightness out + 2 lcd (data and clock ) */
1140 } musicpal_gpio_state;
1141
1142 static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) {
1143     int i;
1144     uint32_t brightness;
1145
1146     /* compute brightness ratio */
1147     switch (s->lcd_brightness) {
1148     case 0x00000007:
1149         brightness = 0;
1150         break;
1151
1152     case 0x00020000:
1153         brightness = 1;
1154         break;
1155
1156     case 0x00020001:
1157         brightness = 2;
1158         break;
1159
1160     case 0x00040000:
1161         brightness = 3;
1162         break;
1163
1164     case 0x00010006:
1165         brightness = 4;
1166         break;
1167
1168     case 0x00020005:
1169         brightness = 5;
1170         break;
1171
1172     case 0x00040003:
1173         brightness = 6;
1174         break;
1175
1176     case 0x00030004:
1177     default:
1178         brightness = 7;
1179     }
1180
1181     /* set lcd brightness GPIOs  */
1182     for (i = 0; i <= 2; i++) {
1183         qemu_set_irq(s->out[i], (brightness >> i) & 1);
1184     }
1185 }
1186
1187 static void musicpal_gpio_pin_event(void *opaque, int pin, int level)
1188 {
1189     musicpal_gpio_state *s = opaque;
1190     uint32_t mask = 1 << pin;
1191     uint32_t delta = level << pin;
1192     uint32_t old = s->in_state & mask;
1193
1194     s->in_state &= ~mask;
1195     s->in_state |= delta;
1196
1197     if ((old ^ delta) &&
1198         ((level && (s->imr & mask)) || (!level && (s->ier & mask)))) {
1199         s->isr = mask;
1200         qemu_irq_raise(s->irq);
1201     }
1202 }
1203
1204 static uint64_t musicpal_gpio_read(void *opaque, hwaddr offset,
1205                                    unsigned size)
1206 {
1207     musicpal_gpio_state *s = opaque;
1208
1209     switch (offset) {
1210     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1211         return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS;
1212
1213     case MP_GPIO_OUT_LO:
1214         return s->out_state & 0xFFFF;
1215     case MP_GPIO_OUT_HI:
1216         return s->out_state >> 16;
1217
1218     case MP_GPIO_IN_LO:
1219         return s->in_state & 0xFFFF;
1220     case MP_GPIO_IN_HI:
1221         return s->in_state >> 16;
1222
1223     case MP_GPIO_IER_LO:
1224         return s->ier & 0xFFFF;
1225     case MP_GPIO_IER_HI:
1226         return s->ier >> 16;
1227
1228     case MP_GPIO_IMR_LO:
1229         return s->imr & 0xFFFF;
1230     case MP_GPIO_IMR_HI:
1231         return s->imr >> 16;
1232
1233     case MP_GPIO_ISR_LO:
1234         return s->isr & 0xFFFF;
1235     case MP_GPIO_ISR_HI:
1236         return s->isr >> 16;
1237
1238     default:
1239         return 0;
1240     }
1241 }
1242
1243 static void musicpal_gpio_write(void *opaque, hwaddr offset,
1244                                 uint64_t value, unsigned size)
1245 {
1246     musicpal_gpio_state *s = opaque;
1247     switch (offset) {
1248     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1249         s->lcd_brightness = (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) |
1250                          (value & MP_OE_LCD_BRIGHTNESS);
1251         musicpal_gpio_brightness_update(s);
1252         break;
1253
1254     case MP_GPIO_OUT_LO:
1255         s->out_state = (s->out_state & 0xFFFF0000) | (value & 0xFFFF);
1256         break;
1257     case MP_GPIO_OUT_HI:
1258         s->out_state = (s->out_state & 0xFFFF) | (value << 16);
1259         s->lcd_brightness = (s->lcd_brightness & 0xFFFF) |
1260                             (s->out_state & MP_GPIO_LCD_BRIGHTNESS);
1261         musicpal_gpio_brightness_update(s);
1262         qemu_set_irq(s->out[3], (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1);
1263         qemu_set_irq(s->out[4], (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1);
1264         break;
1265
1266     case MP_GPIO_IER_LO:
1267         s->ier = (s->ier & 0xFFFF0000) | (value & 0xFFFF);
1268         break;
1269     case MP_GPIO_IER_HI:
1270         s->ier = (s->ier & 0xFFFF) | (value << 16);
1271         break;
1272
1273     case MP_GPIO_IMR_LO:
1274         s->imr = (s->imr & 0xFFFF0000) | (value & 0xFFFF);
1275         break;
1276     case MP_GPIO_IMR_HI:
1277         s->imr = (s->imr & 0xFFFF) | (value << 16);
1278         break;
1279     }
1280 }
1281
1282 static const MemoryRegionOps musicpal_gpio_ops = {
1283     .read = musicpal_gpio_read,
1284     .write = musicpal_gpio_write,
1285     .endianness = DEVICE_NATIVE_ENDIAN,
1286 };
1287
1288 static void musicpal_gpio_reset(DeviceState *d)
1289 {
1290     musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state,
1291                                          sysbus_from_qdev(d));
1292
1293     s->lcd_brightness = 0;
1294     s->out_state = 0;
1295     s->in_state = 0xffffffff;
1296     s->ier = 0;
1297     s->imr = 0;
1298     s->isr = 0;
1299 }
1300
1301 static int musicpal_gpio_init(SysBusDevice *dev)
1302 {
1303     musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state, dev);
1304
1305     sysbus_init_irq(dev, &s->irq);
1306
1307     memory_region_init_io(&s->iomem, &musicpal_gpio_ops, s,
1308                           "musicpal-gpio", MP_GPIO_SIZE);
1309     sysbus_init_mmio(dev, &s->iomem);
1310
1311     qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));
1312
1313     qdev_init_gpio_in(&dev->qdev, musicpal_gpio_pin_event, 32);
1314
1315     return 0;
1316 }
1317
1318 static const VMStateDescription musicpal_gpio_vmsd = {
1319     .name = "musicpal_gpio",
1320     .version_id = 1,
1321     .minimum_version_id = 1,
1322     .minimum_version_id_old = 1,
1323     .fields = (VMStateField[]) {
1324         VMSTATE_UINT32(lcd_brightness, musicpal_gpio_state),
1325         VMSTATE_UINT32(out_state, musicpal_gpio_state),
1326         VMSTATE_UINT32(in_state, musicpal_gpio_state),
1327         VMSTATE_UINT32(ier, musicpal_gpio_state),
1328         VMSTATE_UINT32(imr, musicpal_gpio_state),
1329         VMSTATE_UINT32(isr, musicpal_gpio_state),
1330         VMSTATE_END_OF_LIST()
1331     }
1332 };
1333
1334 static void musicpal_gpio_class_init(ObjectClass *klass, void *data)
1335 {
1336     DeviceClass *dc = DEVICE_CLASS(klass);
1337     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1338
1339     k->init = musicpal_gpio_init;
1340     dc->reset = musicpal_gpio_reset;
1341     dc->vmsd = &musicpal_gpio_vmsd;
1342 }
1343
1344 static TypeInfo musicpal_gpio_info = {
1345     .name          = "musicpal_gpio",
1346     .parent        = TYPE_SYS_BUS_DEVICE,
1347     .instance_size = sizeof(musicpal_gpio_state),
1348     .class_init    = musicpal_gpio_class_init,
1349 };
1350
1351 /* Keyboard codes & masks */
1352 #define KEY_RELEASED            0x80
1353 #define KEY_CODE                0x7f
1354
1355 #define KEYCODE_TAB             0x0f
1356 #define KEYCODE_ENTER           0x1c
1357 #define KEYCODE_F               0x21
1358 #define KEYCODE_M               0x32
1359
1360 #define KEYCODE_EXTENDED        0xe0
1361 #define KEYCODE_UP              0x48
1362 #define KEYCODE_DOWN            0x50
1363 #define KEYCODE_LEFT            0x4b
1364 #define KEYCODE_RIGHT           0x4d
1365
1366 #define MP_KEY_WHEEL_VOL       (1 << 0)
1367 #define MP_KEY_WHEEL_VOL_INV   (1 << 1)
1368 #define MP_KEY_WHEEL_NAV       (1 << 2)
1369 #define MP_KEY_WHEEL_NAV_INV   (1 << 3)
1370 #define MP_KEY_BTN_FAVORITS    (1 << 4)
1371 #define MP_KEY_BTN_MENU        (1 << 5)
1372 #define MP_KEY_BTN_VOLUME      (1 << 6)
1373 #define MP_KEY_BTN_NAVIGATION  (1 << 7)
1374
1375 typedef struct musicpal_key_state {
1376     SysBusDevice busdev;
1377     MemoryRegion iomem;
1378     uint32_t kbd_extended;
1379     uint32_t pressed_keys;
1380     qemu_irq out[8];
1381 } musicpal_key_state;
1382
1383 static void musicpal_key_event(void *opaque, int keycode)
1384 {
1385     musicpal_key_state *s = opaque;
1386     uint32_t event = 0;
1387     int i;
1388
1389     if (keycode == KEYCODE_EXTENDED) {
1390         s->kbd_extended = 1;
1391         return;
1392     }
1393
1394     if (s->kbd_extended) {
1395         switch (keycode & KEY_CODE) {
1396         case KEYCODE_UP:
1397             event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV;
1398             break;
1399
1400         case KEYCODE_DOWN:
1401             event = MP_KEY_WHEEL_NAV;
1402             break;
1403
1404         case KEYCODE_LEFT:
1405             event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV;
1406             break;
1407
1408         case KEYCODE_RIGHT:
1409             event = MP_KEY_WHEEL_VOL;
1410             break;
1411         }
1412     } else {
1413         switch (keycode & KEY_CODE) {
1414         case KEYCODE_F:
1415             event = MP_KEY_BTN_FAVORITS;
1416             break;
1417
1418         case KEYCODE_TAB:
1419             event = MP_KEY_BTN_VOLUME;
1420             break;
1421
1422         case KEYCODE_ENTER:
1423             event = MP_KEY_BTN_NAVIGATION;
1424             break;
1425
1426         case KEYCODE_M:
1427             event = MP_KEY_BTN_MENU;
1428             break;
1429         }
1430         /* Do not repeat already pressed buttons */
1431         if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
1432             event = 0;
1433         }
1434     }
1435
1436     if (event) {
1437         /* Raise GPIO pin first if repeating a key */
1438         if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
1439             for (i = 0; i <= 7; i++) {
1440                 if (event & (1 << i)) {
1441                     qemu_set_irq(s->out[i], 1);
1442                 }
1443             }
1444         }
1445         for (i = 0; i <= 7; i++) {
1446             if (event & (1 << i)) {
1447                 qemu_set_irq(s->out[i], !!(keycode & KEY_RELEASED));
1448             }
1449         }
1450         if (keycode & KEY_RELEASED) {
1451             s->pressed_keys &= ~event;
1452         } else {
1453             s->pressed_keys |= event;
1454         }
1455     }
1456
1457     s->kbd_extended = 0;
1458 }
1459
1460 static int musicpal_key_init(SysBusDevice *dev)
1461 {
1462     musicpal_key_state *s = FROM_SYSBUS(musicpal_key_state, dev);
1463
1464     memory_region_init(&s->iomem, "dummy", 0);
1465     sysbus_init_mmio(dev, &s->iomem);
1466
1467     s->kbd_extended = 0;
1468     s->pressed_keys = 0;
1469
1470     qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));
1471
1472     qemu_add_kbd_event_handler(musicpal_key_event, s);
1473
1474     return 0;
1475 }
1476
1477 static const VMStateDescription musicpal_key_vmsd = {
1478     .name = "musicpal_key",
1479     .version_id = 1,
1480     .minimum_version_id = 1,
1481     .minimum_version_id_old = 1,
1482     .fields = (VMStateField[]) {
1483         VMSTATE_UINT32(kbd_extended, musicpal_key_state),
1484         VMSTATE_UINT32(pressed_keys, musicpal_key_state),
1485         VMSTATE_END_OF_LIST()
1486     }
1487 };
1488
1489 static void musicpal_key_class_init(ObjectClass *klass, void *data)
1490 {
1491     DeviceClass *dc = DEVICE_CLASS(klass);
1492     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1493
1494     k->init = musicpal_key_init;
1495     dc->vmsd = &musicpal_key_vmsd;
1496 }
1497
1498 static TypeInfo musicpal_key_info = {
1499     .name          = "musicpal_key",
1500     .parent        = TYPE_SYS_BUS_DEVICE,
1501     .instance_size = sizeof(musicpal_key_state),
1502     .class_init    = musicpal_key_class_init,
1503 };
1504
1505 static struct arm_boot_info musicpal_binfo = {
1506     .loader_start = 0x0,
1507     .board_id = 0x20e,
1508 };
1509
1510 static void musicpal_init(QEMUMachineInitArgs *args)
1511 {
1512     const char *cpu_model = args->cpu_model;
1513     const char *kernel_filename = args->kernel_filename;
1514     const char *kernel_cmdline = args->kernel_cmdline;
1515     const char *initrd_filename = args->initrd_filename;
1516     ARMCPU *cpu;
1517     qemu_irq *cpu_pic;
1518     qemu_irq pic[32];
1519     DeviceState *dev;
1520     DeviceState *i2c_dev;
1521     DeviceState *lcd_dev;
1522     DeviceState *key_dev;
1523     DeviceState *wm8750_dev;
1524     SysBusDevice *s;
1525     i2c_bus *i2c;
1526     int i;
1527     unsigned long flash_size;
1528     DriveInfo *dinfo;
1529     MemoryRegion *address_space_mem = get_system_memory();
1530     MemoryRegion *ram = g_new(MemoryRegion, 1);
1531     MemoryRegion *sram = g_new(MemoryRegion, 1);
1532
1533     if (!cpu_model) {
1534         cpu_model = "arm926";
1535     }
1536     cpu = cpu_arm_init(cpu_model);
1537     if (!cpu) {
1538         fprintf(stderr, "Unable to find CPU definition\n");
1539         exit(1);
1540     }
1541     cpu_pic = arm_pic_init_cpu(cpu);
1542
1543     /* For now we use a fixed - the original - RAM size */
1544     memory_region_init_ram(ram, "musicpal.ram", MP_RAM_DEFAULT_SIZE);
1545     vmstate_register_ram_global(ram);
1546     memory_region_add_subregion(address_space_mem, 0, ram);
1547
1548     memory_region_init_ram(sram, "musicpal.sram", MP_SRAM_SIZE);
1549     vmstate_register_ram_global(sram);
1550     memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram);
1551
1552     dev = sysbus_create_simple("mv88w8618_pic", MP_PIC_BASE,
1553                                cpu_pic[ARM_PIC_CPU_IRQ]);
1554     for (i = 0; i < 32; i++) {
1555         pic[i] = qdev_get_gpio_in(dev, i);
1556     }
1557     sysbus_create_varargs("mv88w8618_pit", MP_PIT_BASE, pic[MP_TIMER1_IRQ],
1558                           pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
1559                           pic[MP_TIMER4_IRQ], NULL);
1560
1561     if (serial_hds[0]) {
1562         serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
1563                        1825000, serial_hds[0], DEVICE_NATIVE_ENDIAN);
1564     }
1565     if (serial_hds[1]) {
1566         serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
1567                        1825000, serial_hds[1], DEVICE_NATIVE_ENDIAN);
1568     }
1569
1570     /* Register flash */
1571     dinfo = drive_get(IF_PFLASH, 0, 0);
1572     if (dinfo) {
1573         flash_size = bdrv_getlength(dinfo->bdrv);
1574         if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
1575             flash_size != 32*1024*1024) {
1576             fprintf(stderr, "Invalid flash image size\n");
1577             exit(1);
1578         }
1579
1580         /*
1581          * The original U-Boot accesses the flash at 0xFE000000 instead of
1582          * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1583          * image is smaller than 32 MB.
1584          */
1585 #ifdef TARGET_WORDS_BIGENDIAN
1586         pflash_cfi02_register(0x100000000ULL-MP_FLASH_SIZE_MAX, NULL,
1587                               "musicpal.flash", flash_size,
1588                               dinfo->bdrv, 0x10000,
1589                               (flash_size + 0xffff) >> 16,
1590                               MP_FLASH_SIZE_MAX / flash_size,
1591                               2, 0x00BF, 0x236D, 0x0000, 0x0000,
1592                               0x5555, 0x2AAA, 1);
1593 #else
1594         pflash_cfi02_register(0x100000000ULL-MP_FLASH_SIZE_MAX, NULL,
1595                               "musicpal.flash", flash_size,
1596                               dinfo->bdrv, 0x10000,
1597                               (flash_size + 0xffff) >> 16,
1598                               MP_FLASH_SIZE_MAX / flash_size,
1599                               2, 0x00BF, 0x236D, 0x0000, 0x0000,
1600                               0x5555, 0x2AAA, 0);
1601 #endif
1602
1603     }
1604     sysbus_create_simple("mv88w8618_flashcfg", MP_FLASHCFG_BASE, NULL);
1605
1606     qemu_check_nic_model(&nd_table[0], "mv88w8618");
1607     dev = qdev_create(NULL, "mv88w8618_eth");
1608     qdev_set_nic_properties(dev, &nd_table[0]);
1609     qdev_init_nofail(dev);
1610     sysbus_mmio_map(sysbus_from_qdev(dev), 0, MP_ETH_BASE);
1611     sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[MP_ETH_IRQ]);
1612
1613     sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
1614
1615     musicpal_misc_init(sysbus_from_qdev(dev));
1616
1617     dev = sysbus_create_simple("musicpal_gpio", MP_GPIO_BASE, pic[MP_GPIO_IRQ]);
1618     i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL);
1619     i2c = (i2c_bus *)qdev_get_child_bus(i2c_dev, "i2c");
1620
1621     lcd_dev = sysbus_create_simple("musicpal_lcd", MP_LCD_BASE, NULL);
1622     key_dev = sysbus_create_simple("musicpal_key", -1, NULL);
1623
1624     /* I2C read data */
1625     qdev_connect_gpio_out(i2c_dev, 0,
1626                           qdev_get_gpio_in(dev, MP_GPIO_I2C_DATA_BIT));
1627     /* I2C data */
1628     qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0));
1629     /* I2C clock */
1630     qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1));
1631
1632     for (i = 0; i < 3; i++) {
1633         qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i));
1634     }
1635     for (i = 0; i < 4; i++) {
1636         qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 8));
1637     }
1638     for (i = 4; i < 8; i++) {
1639         qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 15));
1640     }
1641
1642     wm8750_dev = i2c_create_slave(i2c, "wm8750", MP_WM_ADDR);
1643     dev = qdev_create(NULL, "mv88w8618_audio");
1644     s = sysbus_from_qdev(dev);
1645     qdev_prop_set_ptr(dev, "wm8750", wm8750_dev);
1646     qdev_init_nofail(dev);
1647     sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
1648     sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
1649
1650     musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
1651     musicpal_binfo.kernel_filename = kernel_filename;
1652     musicpal_binfo.kernel_cmdline = kernel_cmdline;
1653     musicpal_binfo.initrd_filename = initrd_filename;
1654     arm_load_kernel(cpu, &musicpal_binfo);
1655 }
1656
1657 static QEMUMachine musicpal_machine = {
1658     .name = "musicpal",
1659     .desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
1660     .init = musicpal_init,
1661 };
1662
1663 static void musicpal_machine_init(void)
1664 {
1665     qemu_register_machine(&musicpal_machine);
1666 }
1667
1668 machine_init(musicpal_machine_init);
1669
1670 static void mv88w8618_wlan_class_init(ObjectClass *klass, void *data)
1671 {
1672     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
1673
1674     sdc->init = mv88w8618_wlan_init;
1675 }
1676
1677 static TypeInfo mv88w8618_wlan_info = {
1678     .name          = "mv88w8618_wlan",
1679     .parent        = TYPE_SYS_BUS_DEVICE,
1680     .instance_size = sizeof(SysBusDevice),
1681     .class_init    = mv88w8618_wlan_class_init,
1682 };
1683
1684 static void musicpal_register_types(void)
1685 {
1686     type_register_static(&mv88w8618_pic_info);
1687     type_register_static(&mv88w8618_pit_info);
1688     type_register_static(&mv88w8618_flashcfg_info);
1689     type_register_static(&mv88w8618_eth_info);
1690     type_register_static(&mv88w8618_wlan_info);
1691     type_register_static(&musicpal_lcd_info);
1692     type_register_static(&musicpal_gpio_info);
1693     type_register_static(&musicpal_key_info);
1694 }
1695
1696 type_init(musicpal_register_types)