target-sparc/int32_helper.c

   1 /*
   2  * Sparc32 interrupt helpers
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21 #include "trace.h"
  22 #include "sysemu.h"
  23
  24 #define DEBUG_PCALL
  25
  26 #ifdef DEBUG_PCALL
  27 static const char * const excp_names[0x80] = {
  28     [TT_TFAULT] = "Instruction Access Fault",
  29     [TT_ILL_INSN] = "Illegal Instruction",
  30     [TT_PRIV_INSN] = "Privileged Instruction",
  31     [TT_NFPU_INSN] = "FPU Disabled",
  32     [TT_WIN_OVF] = "Window Overflow",
  33     [TT_WIN_UNF] = "Window Underflow",
  34     [TT_UNALIGNED] = "Unaligned Memory Access",
  35     [TT_FP_EXCP] = "FPU Exception",
  36     [TT_DFAULT] = "Data Access Fault",
  37     [TT_TOVF] = "Tag Overflow",
  38     [TT_EXTINT | 0x1] = "External Interrupt 1",
  39     [TT_EXTINT | 0x2] = "External Interrupt 2",
  40     [TT_EXTINT | 0x3] = "External Interrupt 3",
  41     [TT_EXTINT | 0x4] = "External Interrupt 4",
  42     [TT_EXTINT | 0x5] = "External Interrupt 5",
  43     [TT_EXTINT | 0x6] = "External Interrupt 6",
  44     [TT_EXTINT | 0x7] = "External Interrupt 7",
  45     [TT_EXTINT | 0x8] = "External Interrupt 8",
  46     [TT_EXTINT | 0x9] = "External Interrupt 9",
  47     [TT_EXTINT | 0xa] = "External Interrupt 10",
  48     [TT_EXTINT | 0xb] = "External Interrupt 11",
  49     [TT_EXTINT | 0xc] = "External Interrupt 12",
  50     [TT_EXTINT | 0xd] = "External Interrupt 13",
  51     [TT_EXTINT | 0xe] = "External Interrupt 14",
  52     [TT_EXTINT | 0xf] = "External Interrupt 15",
  53     [TT_TOVF] = "Tag Overflow",
  54     [TT_CODE_ACCESS] = "Instruction Access Error",
  55     [TT_DATA_ACCESS] = "Data Access Error",
  56     [TT_DIV_ZERO] = "Division By Zero",
  57     [TT_NCP_INSN] = "Coprocessor Disabled",
  58 };
  59 #endif
  60
  61 void do_interrupt(CPUSPARCState *env)
  62 {
  63     int cwp, intno = env->exception_index;
  64
  65     /* Compute PSR before exposing state.  */
  66     if (env->cc_op != CC_OP_FLAGS) {
  67         cpu_get_psr(env);
  68     }
  69
  70 #ifdef DEBUG_PCALL
  71     if (qemu_loglevel_mask(CPU_LOG_INT)) {
  72         static int count;
  73         const char *name;
  74
  75         if (intno < 0 || intno >= 0x100) {
  76             name = "Unknown";
  77         } else if (intno >= 0x80) {
  78             name = "Trap Instruction";
  79         } else {
  80             name = excp_names[intno];
  81             if (!name) {
  82                 name = "Unknown";
  83             }
  84         }
  85
  86         qemu_log("%6d: %s (v=%02x)\n", count, name, intno);
  87         log_cpu_state(env, 0);
  88 #if 0
  89         {
  90             int i;
  91             uint8_t *ptr;
  92
  93             qemu_log("       code=");
  94             ptr = (uint8_t *)env->pc;
  95             for (i = 0; i < 16; i++) {
  96                 qemu_log(" %02x", ldub(ptr + i));
  97             }
  98             qemu_log("\n");
  99         }
 100 #endif
 101         count++;
 102     }
 103 #endif
 104 #if !defined(CONFIG_USER_ONLY)
 105     if (env->psret == 0) {
 106         if (env->exception_index == 0x80 &&
 107             env->def->features & CPU_FEATURE_TA0_SHUTDOWN) {
 108             qemu_system_shutdown_request();
 109         } else {
 110             cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
 111                       env->exception_index);
 112         }
 113         return;
 114     }
 115 #endif
 116     env->psret = 0;
 117     cwp = cpu_cwp_dec(env, env->cwp - 1);
 118     cpu_set_cwp(env, cwp);
 119     env->regwptr[9] = env->pc;
 120     env->regwptr[10] = env->npc;
 121     env->psrps = env->psrs;
 122     env->psrs = 1;
 123     env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
 124     env->pc = env->tbr;
 125     env->npc = env->pc + 4;
 126     env->exception_index = -1;
 127
 128 #if !defined(CONFIG_USER_ONLY)
 129     /* IRQ acknowledgment */
 130     if ((intno & ~15) == TT_EXTINT && env->qemu_irq_ack != NULL) {
 131         env->qemu_irq_ack(env, env->irq_manager, intno);
 132     }
 133 #endif
 134 }
 135
 136 #if !defined(CONFIG_USER_ONLY)
 137 static void leon3_cache_control_int(CPUSPARCState *env)
 138 {
 139     uint32_t state = 0;
 140
 141     if (env->cache_control & CACHE_CTRL_IF) {
 142         /* Instruction cache state */
 143         state = env->cache_control & CACHE_STATE_MASK;
 144         if (state == CACHE_ENABLED) {
 145             state = CACHE_FROZEN;
 146             trace_int_helper_icache_freeze();
 147         }
 148
 149         env->cache_control &= ~CACHE_STATE_MASK;
 150         env->cache_control |= state;
 151     }
 152
 153     if (env->cache_control & CACHE_CTRL_DF) {
 154         /* Data cache state */
 155         state = (env->cache_control >> 2) & CACHE_STATE_MASK;
 156         if (state == CACHE_ENABLED) {
 157             state = CACHE_FROZEN;
 158             trace_int_helper_dcache_freeze();
 159         }
 160
 161         env->cache_control &= ~(CACHE_STATE_MASK << 2);
 162         env->cache_control |= (state << 2);
 163     }
 164 }
 165
 166 void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno)
 167 {
 168     leon3_irq_ack(irq_manager, intno);
 169     leon3_cache_control_int(env);
 170 }
 171 #endif