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qemu-log: fix x86 and user logging
[qemu/opensuse.git] / hw / fdc.c
blobedf07063b2492426431e13a14a16a0ce2f65d907
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "hw.h"
31 #include "fdc.h"
32 #include "qemu-error.h"
33 #include "qemu-timer.h"
34 #include "isa.h"
35 #include "sysbus.h"
36 #include "qdev-addr.h"
37 #include "blockdev.h"
38 #include "sysemu.h"
39 #include "qemu-log.h"
40
41 /********************************************************/
42 /* debug Floppy devices */
43 //#define DEBUG_FLOPPY
44
45 #ifdef DEBUG_FLOPPY
46 #define FLOPPY_DPRINTF(fmt, ...) \
47 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
48 #else
49 #define FLOPPY_DPRINTF(fmt, ...)
50 #endif
51
52 /********************************************************/
53 /* Floppy drive emulation */
54
55 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
56 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
57
58 /* Will always be a fixed parameter for us */
59 #define FD_SECTOR_LEN 512
60 #define FD_SECTOR_SC 2 /* Sector size code */
61 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
62
63 typedef struct FDCtrl FDCtrl;
64
65 /* Floppy disk drive emulation */
66 typedef enum FDiskFlags {
67 FDISK_DBL_SIDES = 0x01,
68 } FDiskFlags;
69
70 typedef struct FDrive {
71 FDCtrl *fdctrl;
72 BlockDriverState *bs;
73 /* Drive status */
74 FDriveType drive;
75 uint8_t perpendicular; /* 2.88 MB access mode */
76 /* Position */
77 uint8_t head;
78 uint8_t track;
79 uint8_t sect;
80 /* Media */
81 FDiskFlags flags;
82 uint8_t last_sect; /* Nb sector per track */
83 uint8_t max_track; /* Nb of tracks */
84 uint16_t bps; /* Bytes per sector */
85 uint8_t ro; /* Is read-only */
86 uint8_t media_changed; /* Is media changed */
87 uint8_t media_rate; /* Data rate of medium */
88 } FDrive;
89
90 static void fd_init(FDrive *drv)
91 {
92 /* Drive */
93 drv->drive = FDRIVE_DRV_NONE;
94 drv->perpendicular = 0;
95 /* Disk */
96 drv->last_sect = 0;
97 drv->max_track = 0;
98 }
99
100 #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1)
101
102 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
103 uint8_t last_sect, uint8_t num_sides)
104 {
105 return (((track * num_sides) + head) * last_sect) + sect - 1;
106 }
107
108 /* Returns current position, in sectors, for given drive */
109 static int fd_sector(FDrive *drv)
110 {
111 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect,
112 NUM_SIDES(drv));
113 }
114
115 /* Seek to a new position:
116 * returns 0 if already on right track
117 * returns 1 if track changed
118 * returns 2 if track is invalid
119 * returns 3 if sector is invalid
120 * returns 4 if seek is disabled
121 */
122 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
123 int enable_seek)
124 {
125 uint32_t sector;
126 int ret;
127
128 if (track > drv->max_track ||
129 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
130 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
131 head, track, sect, 1,
132 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
133 drv->max_track, drv->last_sect);
134 return 2;
135 }
136 if (sect > drv->last_sect) {
137 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
138 head, track, sect, 1,
139 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
140 drv->max_track, drv->last_sect);
141 return 3;
142 }
143 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv));
144 ret = 0;
145 if (sector != fd_sector(drv)) {
146 #if 0
147 if (!enable_seek) {
148 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x"
149 " (max=%d %02x %02x)\n",
150 head, track, sect, 1, drv->max_track,
151 drv->last_sect);
152 return 4;
153 }
154 #endif
155 drv->head = head;
156 if (drv->track != track) {
157 if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
158 drv->media_changed = 0;
159 }
160 ret = 1;
161 }
162 drv->track = track;
163 drv->sect = sect;
164 }
165
166 if (drv->bs == NULL || !bdrv_is_inserted(drv->bs)) {
167 ret = 2;
168 }
169
170 return ret;
171 }
172
173 /* Set drive back to track 0 */
174 static void fd_recalibrate(FDrive *drv)
175 {
176 FLOPPY_DPRINTF("recalibrate\n");
177 fd_seek(drv, 0, 0, 1, 1);
178 }
179
180 /* Revalidate a disk drive after a disk change */
181 static void fd_revalidate(FDrive *drv)
182 {
183 int nb_heads, max_track, last_sect, ro;
184 FDriveType drive;
185 FDriveRate rate;
186
187 FLOPPY_DPRINTF("revalidate\n");
188 if (drv->bs != NULL) {
189 ro = bdrv_is_read_only(drv->bs);
190 bdrv_get_floppy_geometry_hint(drv->bs, &nb_heads, &max_track,
191 &last_sect, drv->drive, &drive, &rate);
192 if (!bdrv_is_inserted(drv->bs)) {
193 FLOPPY_DPRINTF("No disk in drive\n");
194 } else {
195 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", nb_heads,
196 max_track, last_sect, ro ? "ro" : "rw");
197 }
198 if (nb_heads == 1) {
199 drv->flags &= ~FDISK_DBL_SIDES;
200 } else {
201 drv->flags |= FDISK_DBL_SIDES;
202 }
203 drv->max_track = max_track;
204 drv->last_sect = last_sect;
205 drv->ro = ro;
206 drv->drive = drive;
207 drv->media_rate = rate;
208 } else {
209 FLOPPY_DPRINTF("No drive connected\n");
210 drv->last_sect = 0;
211 drv->max_track = 0;
212 drv->flags &= ~FDISK_DBL_SIDES;
213 }
214 }
215
216 /********************************************************/
217 /* Intel 82078 floppy disk controller emulation */
218
219 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
220 static void fdctrl_reset_fifo(FDCtrl *fdctrl);
221 static int fdctrl_transfer_handler (void *opaque, int nchan,
222 int dma_pos, int dma_len);
223 static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0);
224 static FDrive *get_cur_drv(FDCtrl *fdctrl);
225
226 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
227 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
228 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
229 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
230 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
231 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
232 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
233 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
234 static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
235 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
236 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
237 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value);
238
239 enum {
240 FD_DIR_WRITE = 0,
241 FD_DIR_READ = 1,
242 FD_DIR_SCANE = 2,
243 FD_DIR_SCANL = 3,
244 FD_DIR_SCANH = 4,
245 };
246
247 enum {
248 FD_STATE_MULTI = 0x01, /* multi track flag */
249 FD_STATE_FORMAT = 0x02, /* format flag */
250 FD_STATE_SEEK = 0x04, /* seek flag */
251 };
252
253 enum {
254 FD_REG_SRA = 0x00,
255 FD_REG_SRB = 0x01,
256 FD_REG_DOR = 0x02,
257 FD_REG_TDR = 0x03,
258 FD_REG_MSR = 0x04,
259 FD_REG_DSR = 0x04,
260 FD_REG_FIFO = 0x05,
261 FD_REG_DIR = 0x07,
262 FD_REG_CCR = 0x07,
263 };
264
265 enum {
266 FD_CMD_READ_TRACK = 0x02,
267 FD_CMD_SPECIFY = 0x03,
268 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
269 FD_CMD_WRITE = 0x05,
270 FD_CMD_READ = 0x06,
271 FD_CMD_RECALIBRATE = 0x07,
272 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
273 FD_CMD_WRITE_DELETED = 0x09,
274 FD_CMD_READ_ID = 0x0a,
275 FD_CMD_READ_DELETED = 0x0c,
276 FD_CMD_FORMAT_TRACK = 0x0d,
277 FD_CMD_DUMPREG = 0x0e,
278 FD_CMD_SEEK = 0x0f,
279 FD_CMD_VERSION = 0x10,
280 FD_CMD_SCAN_EQUAL = 0x11,
281 FD_CMD_PERPENDICULAR_MODE = 0x12,
282 FD_CMD_CONFIGURE = 0x13,
283 FD_CMD_LOCK = 0x14,
284 FD_CMD_VERIFY = 0x16,
285 FD_CMD_POWERDOWN_MODE = 0x17,
286 FD_CMD_PART_ID = 0x18,
287 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
288 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
289 FD_CMD_SAVE = 0x2e,
290 FD_CMD_OPTION = 0x33,
291 FD_CMD_RESTORE = 0x4e,
292 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
293 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
294 FD_CMD_FORMAT_AND_WRITE = 0xcd,
295 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
296 };
297
298 enum {
299 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
300 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
301 FD_CONFIG_POLL = 0x10, /* Poll enabled */
302 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
303 FD_CONFIG_EIS = 0x40, /* No implied seeks */
304 };
305
306 enum {
307 FD_SR0_DS0 = 0x01,
308 FD_SR0_DS1 = 0x02,
309 FD_SR0_HEAD = 0x04,
310 FD_SR0_EQPMT = 0x10,
311 FD_SR0_SEEK = 0x20,
312 FD_SR0_ABNTERM = 0x40,
313 FD_SR0_INVCMD = 0x80,
314 FD_SR0_RDYCHG = 0xc0,
315 };
316
317 enum {
318 FD_SR1_MA = 0x01, /* Missing address mark */
319 FD_SR1_NW = 0x02, /* Not writable */
320 FD_SR1_EC = 0x80, /* End of cylinder */
321 };
322
323 enum {
324 FD_SR2_SNS = 0x04, /* Scan not satisfied */
325 FD_SR2_SEH = 0x08, /* Scan equal hit */
326 };
327
328 enum {
329 FD_SRA_DIR = 0x01,
330 FD_SRA_nWP = 0x02,
331 FD_SRA_nINDX = 0x04,
332 FD_SRA_HDSEL = 0x08,
333 FD_SRA_nTRK0 = 0x10,
334 FD_SRA_STEP = 0x20,
335 FD_SRA_nDRV2 = 0x40,
336 FD_SRA_INTPEND = 0x80,
337 };
338
339 enum {
340 FD_SRB_MTR0 = 0x01,
341 FD_SRB_MTR1 = 0x02,
342 FD_SRB_WGATE = 0x04,
343 FD_SRB_RDATA = 0x08,
344 FD_SRB_WDATA = 0x10,
345 FD_SRB_DR0 = 0x20,
346 };
347
348 enum {
349 #if MAX_FD == 4
350 FD_DOR_SELMASK = 0x03,
351 #else
352 FD_DOR_SELMASK = 0x01,
353 #endif
354 FD_DOR_nRESET = 0x04,
355 FD_DOR_DMAEN = 0x08,
356 FD_DOR_MOTEN0 = 0x10,
357 FD_DOR_MOTEN1 = 0x20,
358 FD_DOR_MOTEN2 = 0x40,
359 FD_DOR_MOTEN3 = 0x80,
360 };
361
362 enum {
363 #if MAX_FD == 4
364 FD_TDR_BOOTSEL = 0x0c,
365 #else
366 FD_TDR_BOOTSEL = 0x04,
367 #endif
368 };
369
370 enum {
371 FD_DSR_DRATEMASK= 0x03,
372 FD_DSR_PWRDOWN = 0x40,
373 FD_DSR_SWRESET = 0x80,
374 };
375
376 enum {
377 FD_MSR_DRV0BUSY = 0x01,
378 FD_MSR_DRV1BUSY = 0x02,
379 FD_MSR_DRV2BUSY = 0x04,
380 FD_MSR_DRV3BUSY = 0x08,
381 FD_MSR_CMDBUSY = 0x10,
382 FD_MSR_NONDMA = 0x20,
383 FD_MSR_DIO = 0x40,
384 FD_MSR_RQM = 0x80,
385 };
386
387 enum {
388 FD_DIR_DSKCHG = 0x80,
389 };
390
391 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
392 #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
393 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
394
395 struct FDCtrl {
396 MemoryRegion iomem;
397 qemu_irq irq;
398 /* Controller state */
399 QEMUTimer *result_timer;
400 int dma_chann;
401 /* Controller's identification */
402 uint8_t version;
403 /* HW */
404 uint8_t sra;
405 uint8_t srb;
406 uint8_t dor;
407 uint8_t dor_vmstate; /* only used as temp during vmstate */
408 uint8_t tdr;
409 uint8_t dsr;
410 uint8_t msr;
411 uint8_t cur_drv;
412 uint8_t status0;
413 uint8_t status1;
414 uint8_t status2;
415 /* Command FIFO */
416 uint8_t *fifo;
417 int32_t fifo_size;
418 uint32_t data_pos;
419 uint32_t data_len;
420 uint8_t data_state;
421 uint8_t data_dir;
422 uint8_t eot; /* last wanted sector */
423 /* States kept only to be returned back */
424 /* precompensation */
425 uint8_t precomp_trk;
426 uint8_t config;
427 uint8_t lock;
428 /* Power down config (also with status regB access mode */
429 uint8_t pwrd;
430 /* Floppy drives */
431 uint8_t num_floppies;
432 /* Sun4m quirks? */
433 int sun4m;
434 FDrive drives[MAX_FD];
435 int reset_sensei;
436 uint32_t check_media_rate;
437 /* Timers state */
438 uint8_t timer0;
439 uint8_t timer1;
440 };
441
442 typedef struct FDCtrlSysBus {
443 SysBusDevice busdev;
444 struct FDCtrl state;
445 } FDCtrlSysBus;
446
447 typedef struct FDCtrlISABus {
448 ISADevice busdev;
449 uint32_t iobase;
450 uint32_t irq;
451 uint32_t dma;
452 struct FDCtrl state;
453 int32_t bootindexA;
454 int32_t bootindexB;
455 } FDCtrlISABus;
456
457 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
458 {
459 FDCtrl *fdctrl = opaque;
460 uint32_t retval;
461
462 reg &= 7;
463 switch (reg) {
464 case FD_REG_SRA:
465 retval = fdctrl_read_statusA(fdctrl);
466 break;
467 case FD_REG_SRB:
468 retval = fdctrl_read_statusB(fdctrl);
469 break;
470 case FD_REG_DOR:
471 retval = fdctrl_read_dor(fdctrl);
472 break;
473 case FD_REG_TDR:
474 retval = fdctrl_read_tape(fdctrl);
475 break;
476 case FD_REG_MSR:
477 retval = fdctrl_read_main_status(fdctrl);
478 break;
479 case FD_REG_FIFO:
480 retval = fdctrl_read_data(fdctrl);
481 break;
482 case FD_REG_DIR:
483 retval = fdctrl_read_dir(fdctrl);
484 break;
485 default:
486 retval = (uint32_t)(-1);
487 break;
488 }
489 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
490
491 return retval;
492 }
493
494 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
495 {
496 FDCtrl *fdctrl = opaque;
497
498 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
499
500 reg &= 7;
501 switch (reg) {
502 case FD_REG_DOR:
503 fdctrl_write_dor(fdctrl, value);
504 break;
505 case FD_REG_TDR:
506 fdctrl_write_tape(fdctrl, value);
507 break;
508 case FD_REG_DSR:
509 fdctrl_write_rate(fdctrl, value);
510 break;
511 case FD_REG_FIFO:
512 fdctrl_write_data(fdctrl, value);
513 break;
514 case FD_REG_CCR:
515 fdctrl_write_ccr(fdctrl, value);
516 break;
517 default:
518 break;
519 }
520 }
521
522 static uint64_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg,
523 unsigned ize)
524 {
525 return fdctrl_read(opaque, (uint32_t)reg);
526 }
527
528 static void fdctrl_write_mem (void *opaque, target_phys_addr_t reg,
529 uint64_t value, unsigned size)
530 {
531 fdctrl_write(opaque, (uint32_t)reg, value);
532 }
533
534 static const MemoryRegionOps fdctrl_mem_ops = {
535 .read = fdctrl_read_mem,
536 .write = fdctrl_write_mem,
537 .endianness = DEVICE_NATIVE_ENDIAN,
538 };
539
540 static const MemoryRegionOps fdctrl_mem_strict_ops = {
541 .read = fdctrl_read_mem,
542 .write = fdctrl_write_mem,
543 .endianness = DEVICE_NATIVE_ENDIAN,
544 .valid = {
545 .min_access_size = 1,
546 .max_access_size = 1,
547 },
548 };
549
550 static bool fdrive_media_changed_needed(void *opaque)
551 {
552 FDrive *drive = opaque;
553
554 return (drive->bs != NULL && drive->media_changed != 1);
555 }
556
557 static const VMStateDescription vmstate_fdrive_media_changed = {
558 .name = "fdrive/media_changed",
559 .version_id = 1,
560 .minimum_version_id = 1,
561 .minimum_version_id_old = 1,
562 .fields = (VMStateField[]) {
563 VMSTATE_UINT8(media_changed, FDrive),
564 VMSTATE_END_OF_LIST()
565 }
566 };
567
568 static bool fdrive_media_rate_needed(void *opaque)
569 {
570 FDrive *drive = opaque;
571
572 return drive->fdctrl->check_media_rate;
573 }
574
575 static const VMStateDescription vmstate_fdrive_media_rate = {
576 .name = "fdrive/media_rate",
577 .version_id = 1,
578 .minimum_version_id = 1,
579 .minimum_version_id_old = 1,
580 .fields = (VMStateField[]) {
581 VMSTATE_UINT8(media_rate, FDrive),
582 VMSTATE_END_OF_LIST()
583 }
584 };
585
586 static const VMStateDescription vmstate_fdrive = {
587 .name = "fdrive",
588 .version_id = 1,
589 .minimum_version_id = 1,
590 .minimum_version_id_old = 1,
591 .fields = (VMStateField[]) {
592 VMSTATE_UINT8(head, FDrive),
593 VMSTATE_UINT8(track, FDrive),
594 VMSTATE_UINT8(sect, FDrive),
595 VMSTATE_END_OF_LIST()
596 },
597 .subsections = (VMStateSubsection[]) {
598 {
599 .vmsd = &vmstate_fdrive_media_changed,
600 .needed = &fdrive_media_changed_needed,
601 } , {
602 .vmsd = &vmstate_fdrive_media_rate,
603 .needed = &fdrive_media_rate_needed,
604 } , {
605 /* empty */
606 }
607 }
608 };
609
610 static void fdc_pre_save(void *opaque)
611 {
612 FDCtrl *s = opaque;
613
614 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
615 }
616
617 static int fdc_post_load(void *opaque, int version_id)
618 {
619 FDCtrl *s = opaque;
620
621 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
622 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
623 return 0;
624 }
625
626 static const VMStateDescription vmstate_fdc = {
627 .name = "fdc",
628 .version_id = 2,
629 .minimum_version_id = 2,
630 .minimum_version_id_old = 2,
631 .pre_save = fdc_pre_save,
632 .post_load = fdc_post_load,
633 .fields = (VMStateField []) {
634 /* Controller State */
635 VMSTATE_UINT8(sra, FDCtrl),
636 VMSTATE_UINT8(srb, FDCtrl),
637 VMSTATE_UINT8(dor_vmstate, FDCtrl),
638 VMSTATE_UINT8(tdr, FDCtrl),
639 VMSTATE_UINT8(dsr, FDCtrl),
640 VMSTATE_UINT8(msr, FDCtrl),
641 VMSTATE_UINT8(status0, FDCtrl),
642 VMSTATE_UINT8(status1, FDCtrl),
643 VMSTATE_UINT8(status2, FDCtrl),
644 /* Command FIFO */
645 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
646 uint8_t),
647 VMSTATE_UINT32(data_pos, FDCtrl),
648 VMSTATE_UINT32(data_len, FDCtrl),
649 VMSTATE_UINT8(data_state, FDCtrl),
650 VMSTATE_UINT8(data_dir, FDCtrl),
651 VMSTATE_UINT8(eot, FDCtrl),
652 /* States kept only to be returned back */
653 VMSTATE_UINT8(timer0, FDCtrl),
654 VMSTATE_UINT8(timer1, FDCtrl),
655 VMSTATE_UINT8(precomp_trk, FDCtrl),
656 VMSTATE_UINT8(config, FDCtrl),
657 VMSTATE_UINT8(lock, FDCtrl),
658 VMSTATE_UINT8(pwrd, FDCtrl),
659 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
660 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
661 vmstate_fdrive, FDrive),
662 VMSTATE_END_OF_LIST()
663 }
664 };
665
666 static void fdctrl_external_reset_sysbus(DeviceState *d)
667 {
668 FDCtrlSysBus *sys = container_of(d, FDCtrlSysBus, busdev.qdev);
669 FDCtrl *s = &sys->state;
670
671 fdctrl_reset(s, 0);
672 }
673
674 static void fdctrl_external_reset_isa(DeviceState *d)
675 {
676 FDCtrlISABus *isa = container_of(d, FDCtrlISABus, busdev.qdev);
677 FDCtrl *s = &isa->state;
678
679 fdctrl_reset(s, 0);
680 }
681
682 static void fdctrl_handle_tc(void *opaque, int irq, int level)
683 {
684 //FDCtrl *s = opaque;
685
686 if (level) {
687 // XXX
688 FLOPPY_DPRINTF("TC pulsed\n");
689 }
690 }
691
692 /* Change IRQ state */
693 static void fdctrl_reset_irq(FDCtrl *fdctrl)
694 {
695 if (!(fdctrl->sra & FD_SRA_INTPEND))
696 return;
697 FLOPPY_DPRINTF("Reset interrupt\n");
698 qemu_set_irq(fdctrl->irq, 0);
699 fdctrl->sra &= ~FD_SRA_INTPEND;
700 }
701
702 static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0)
703 {
704 /* Sparc mutation */
705 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
706 /* XXX: not sure */
707 fdctrl->msr &= ~FD_MSR_CMDBUSY;
708 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
709 fdctrl->status0 = status0;
710 return;
711 }
712 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
713 qemu_set_irq(fdctrl->irq, 1);
714 fdctrl->sra |= FD_SRA_INTPEND;
715 }
716
717 fdctrl->reset_sensei = 0;
718 fdctrl->status0 = status0;
719 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
720 }
721
722 /* Reset controller */
723 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
724 {
725 int i;
726
727 FLOPPY_DPRINTF("reset controller\n");
728 fdctrl_reset_irq(fdctrl);
729 /* Initialise controller */
730 fdctrl->sra = 0;
731 fdctrl->srb = 0xc0;
732 if (!fdctrl->drives[1].bs)
733 fdctrl->sra |= FD_SRA_nDRV2;
734 fdctrl->cur_drv = 0;
735 fdctrl->dor = FD_DOR_nRESET;
736 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
737 fdctrl->msr = FD_MSR_RQM;
738 /* FIFO state */
739 fdctrl->data_pos = 0;
740 fdctrl->data_len = 0;
741 fdctrl->data_state = 0;
742 fdctrl->data_dir = FD_DIR_WRITE;
743 for (i = 0; i < MAX_FD; i++)
744 fd_recalibrate(&fdctrl->drives[i]);
745 fdctrl_reset_fifo(fdctrl);
746 if (do_irq) {
747 fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
748 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
749 }
750 }
751
752 static inline FDrive *drv0(FDCtrl *fdctrl)
753 {
754 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
755 }
756
757 static inline FDrive *drv1(FDCtrl *fdctrl)
758 {
759 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
760 return &fdctrl->drives[1];
761 else
762 return &fdctrl->drives[0];
763 }
764
765 #if MAX_FD == 4
766 static inline FDrive *drv2(FDCtrl *fdctrl)
767 {
768 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
769 return &fdctrl->drives[2];
770 else
771 return &fdctrl->drives[1];
772 }
773
774 static inline FDrive *drv3(FDCtrl *fdctrl)
775 {
776 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
777 return &fdctrl->drives[3];
778 else
779 return &fdctrl->drives[2];
780 }
781 #endif
782
783 static FDrive *get_cur_drv(FDCtrl *fdctrl)
784 {
785 switch (fdctrl->cur_drv) {
786 case 0: return drv0(fdctrl);
787 case 1: return drv1(fdctrl);
788 #if MAX_FD == 4
789 case 2: return drv2(fdctrl);
790 case 3: return drv3(fdctrl);
791 #endif
792 default: return NULL;
793 }
794 }
795
796 /* Status A register : 0x00 (read-only) */
797 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
798 {
799 uint32_t retval = fdctrl->sra;
800
801 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
802
803 return retval;
804 }
805
806 /* Status B register : 0x01 (read-only) */
807 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
808 {
809 uint32_t retval = fdctrl->srb;
810
811 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
812
813 return retval;
814 }
815
816 /* Digital output register : 0x02 */
817 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
818 {
819 uint32_t retval = fdctrl->dor;
820
821 /* Selected drive */
822 retval |= fdctrl->cur_drv;
823 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
824
825 return retval;
826 }
827
828 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
829 {
830 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
831
832 /* Motors */
833 if (value & FD_DOR_MOTEN0)
834 fdctrl->srb |= FD_SRB_MTR0;
835 else
836 fdctrl->srb &= ~FD_SRB_MTR0;
837 if (value & FD_DOR_MOTEN1)
838 fdctrl->srb |= FD_SRB_MTR1;
839 else
840 fdctrl->srb &= ~FD_SRB_MTR1;
841
842 /* Drive */
843 if (value & 1)
844 fdctrl->srb |= FD_SRB_DR0;
845 else
846 fdctrl->srb &= ~FD_SRB_DR0;
847
848 /* Reset */
849 if (!(value & FD_DOR_nRESET)) {
850 if (fdctrl->dor & FD_DOR_nRESET) {
851 FLOPPY_DPRINTF("controller enter RESET state\n");
852 }
853 } else {
854 if (!(fdctrl->dor & FD_DOR_nRESET)) {
855 FLOPPY_DPRINTF("controller out of RESET state\n");
856 fdctrl_reset(fdctrl, 1);
857 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
858 }
859 }
860 /* Selected drive */
861 fdctrl->cur_drv = value & FD_DOR_SELMASK;
862
863 fdctrl->dor = value;
864 }
865
866 /* Tape drive register : 0x03 */
867 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
868 {
869 uint32_t retval = fdctrl->tdr;
870
871 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
872
873 return retval;
874 }
875
876 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
877 {
878 /* Reset mode */
879 if (!(fdctrl->dor & FD_DOR_nRESET)) {
880 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
881 return;
882 }
883 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
884 /* Disk boot selection indicator */
885 fdctrl->tdr = value & FD_TDR_BOOTSEL;
886 /* Tape indicators: never allow */
887 }
888
889 /* Main status register : 0x04 (read) */
890 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
891 {
892 uint32_t retval = fdctrl->msr;
893
894 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
895 fdctrl->dor |= FD_DOR_nRESET;
896
897 /* Sparc mutation */
898 if (fdctrl->sun4m) {
899 retval |= FD_MSR_DIO;
900 fdctrl_reset_irq(fdctrl);
901 };
902
903 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
904
905 return retval;
906 }
907
908 /* Data select rate register : 0x04 (write) */
909 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
910 {
911 /* Reset mode */
912 if (!(fdctrl->dor & FD_DOR_nRESET)) {
913 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
914 return;
915 }
916 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
917 /* Reset: autoclear */
918 if (value & FD_DSR_SWRESET) {
919 fdctrl->dor &= ~FD_DOR_nRESET;
920 fdctrl_reset(fdctrl, 1);
921 fdctrl->dor |= FD_DOR_nRESET;
922 }
923 if (value & FD_DSR_PWRDOWN) {
924 fdctrl_reset(fdctrl, 1);
925 }
926 fdctrl->dsr = value;
927 }
928
929 /* Configuration control register: 0x07 (write) */
930 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value)
931 {
932 /* Reset mode */
933 if (!(fdctrl->dor & FD_DOR_nRESET)) {
934 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
935 return;
936 }
937 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value);
938
939 /* Only the rate selection bits used in AT mode, and we
940 * store those in the DSR.
941 */
942 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) |
943 (value & FD_DSR_DRATEMASK);
944 }
945
946 static int fdctrl_media_changed(FDrive *drv)
947 {
948 return drv->media_changed;
949 }
950
951 /* Digital input register : 0x07 (read-only) */
952 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
953 {
954 uint32_t retval = 0;
955
956 if (fdctrl_media_changed(get_cur_drv(fdctrl))) {
957 retval |= FD_DIR_DSKCHG;
958 }
959 if (retval != 0) {
960 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
961 }
962
963 return retval;
964 }
965
966 /* FIFO state control */
967 static void fdctrl_reset_fifo(FDCtrl *fdctrl)
968 {
969 fdctrl->data_dir = FD_DIR_WRITE;
970 fdctrl->data_pos = 0;
971 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
972 }
973
974 /* Set FIFO status for the host to read */
975 static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len, uint8_t status0)
976 {
977 fdctrl->data_dir = FD_DIR_READ;
978 fdctrl->data_len = fifo_len;
979 fdctrl->data_pos = 0;
980 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
981 if (status0) {
982 fdctrl_raise_irq(fdctrl, status0);
983 }
984 }
985
986 /* Set an error: unimplemented/unknown command */
987 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
988 {
989 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n",
990 fdctrl->fifo[0]);
991 fdctrl->fifo[0] = FD_SR0_INVCMD;
992 fdctrl_set_fifo(fdctrl, 1, 0);
993 }
994
995 /* Seek to next sector
996 * returns 0 when end of track reached (for DBL_SIDES on head 1)
997 * otherwise returns 1
998 */
999 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
1000 {
1001 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1002 cur_drv->head, cur_drv->track, cur_drv->sect,
1003 fd_sector(cur_drv));
1004 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1005 error in fact */
1006 uint8_t new_head = cur_drv->head;
1007 uint8_t new_track = cur_drv->track;
1008 uint8_t new_sect = cur_drv->sect;
1009
1010 int ret = 1;
1011
1012 if (new_sect >= cur_drv->last_sect ||
1013 new_sect == fdctrl->eot) {
1014 new_sect = 1;
1015 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1016 if (new_head == 0 &&
1017 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1018 new_head = 1;
1019 } else {
1020 new_head = 0;
1021 new_track++;
1022 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) {
1023 ret = 0;
1024 }
1025 }
1026 } else {
1027 new_track++;
1028 ret = 0;
1029 }
1030 if (ret == 1) {
1031 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1032 new_head, new_track, new_sect, fd_sector(cur_drv));
1033 }
1034 } else {
1035 new_sect++;
1036 }
1037 fd_seek(cur_drv, new_head, new_track, new_sect, 1);
1038 return ret;
1039 }
1040
1041 /* Callback for transfer end (stop or abort) */
1042 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1043 uint8_t status1, uint8_t status2)
1044 {
1045 FDrive *cur_drv;
1046
1047 cur_drv = get_cur_drv(fdctrl);
1048 fdctrl->status0 = status0 | FD_SR0_SEEK | (cur_drv->head << 2) |
1049 GET_CUR_DRV(fdctrl);
1050
1051 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1052 status0, status1, status2, fdctrl->status0);
1053 fdctrl->fifo[0] = fdctrl->status0;
1054 fdctrl->fifo[1] = status1;
1055 fdctrl->fifo[2] = status2;
1056 fdctrl->fifo[3] = cur_drv->track;
1057 fdctrl->fifo[4] = cur_drv->head;
1058 fdctrl->fifo[5] = cur_drv->sect;
1059 fdctrl->fifo[6] = FD_SECTOR_SC;
1060 fdctrl->data_dir = FD_DIR_READ;
1061 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1062 DMA_release_DREQ(fdctrl->dma_chann);
1063 }
1064 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1065 fdctrl->msr &= ~FD_MSR_NONDMA;
1066 fdctrl_set_fifo(fdctrl, 7, fdctrl->status0);
1067 }
1068
1069 /* Prepare a data transfer (either DMA or FIFO) */
1070 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
1071 {
1072 FDrive *cur_drv;
1073 uint8_t kh, kt, ks;
1074 int did_seek = 0;
1075
1076 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1077 cur_drv = get_cur_drv(fdctrl);
1078 kt = fdctrl->fifo[2];
1079 kh = fdctrl->fifo[3];
1080 ks = fdctrl->fifo[4];
1081 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1082 GET_CUR_DRV(fdctrl), kh, kt, ks,
1083 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1084 NUM_SIDES(cur_drv)));
1085 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1086 case 2:
1087 /* sect too big */
1088 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1089 fdctrl->fifo[3] = kt;
1090 fdctrl->fifo[4] = kh;
1091 fdctrl->fifo[5] = ks;
1092 return;
1093 case 3:
1094 /* track too big */
1095 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1096 fdctrl->fifo[3] = kt;
1097 fdctrl->fifo[4] = kh;
1098 fdctrl->fifo[5] = ks;
1099 return;
1100 case 4:
1101 /* No seek enabled */
1102 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1103 fdctrl->fifo[3] = kt;
1104 fdctrl->fifo[4] = kh;
1105 fdctrl->fifo[5] = ks;
1106 return;
1107 case 1:
1108 did_seek = 1;
1109 break;
1110 default:
1111 break;
1112 }
1113
1114 /* Check the data rate. If the programmed data rate does not match
1115 * the currently inserted medium, the operation has to fail. */
1116 if (fdctrl->check_media_rate &&
1117 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1118 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n",
1119 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1120 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1121 fdctrl->fifo[3] = kt;
1122 fdctrl->fifo[4] = kh;
1123 fdctrl->fifo[5] = ks;
1124 return;
1125 }
1126
1127 /* Set the FIFO state */
1128 fdctrl->data_dir = direction;
1129 fdctrl->data_pos = 0;
1130 fdctrl->msr |= FD_MSR_CMDBUSY;
1131 if (fdctrl->fifo[0] & 0x80)
1132 fdctrl->data_state |= FD_STATE_MULTI;
1133 else
1134 fdctrl->data_state &= ~FD_STATE_MULTI;
1135 if (did_seek)
1136 fdctrl->data_state |= FD_STATE_SEEK;
1137 else
1138 fdctrl->data_state &= ~FD_STATE_SEEK;
1139 if (fdctrl->fifo[5] == 00) {
1140 fdctrl->data_len = fdctrl->fifo[8];
1141 } else {
1142 int tmp;
1143 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1144 tmp = (fdctrl->fifo[6] - ks + 1);
1145 if (fdctrl->fifo[0] & 0x80)
1146 tmp += fdctrl->fifo[6];
1147 fdctrl->data_len *= tmp;
1148 }
1149 fdctrl->eot = fdctrl->fifo[6];
1150 if (fdctrl->dor & FD_DOR_DMAEN) {
1151 int dma_mode;
1152 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1153 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1154 dma_mode = (dma_mode >> 2) & 3;
1155 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1156 dma_mode, direction,
1157 (128 << fdctrl->fifo[5]) *
1158 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1159 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1160 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1161 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1162 (direction == FD_DIR_READ && dma_mode == 1)) {
1163 /* No access is allowed until DMA transfer has completed */
1164 fdctrl->msr &= ~FD_MSR_RQM;
1165 /* Now, we just have to wait for the DMA controller to
1166 * recall us...
1167 */
1168 DMA_hold_DREQ(fdctrl->dma_chann);
1169 DMA_schedule(fdctrl->dma_chann);
1170 return;
1171 } else {
1172 FLOPPY_DPRINTF("bad dma_mode=%d direction=%d\n", dma_mode,
1173 direction);
1174 }
1175 }
1176 FLOPPY_DPRINTF("start non-DMA transfer\n");
1177 fdctrl->msr |= FD_MSR_NONDMA;
1178 if (direction != FD_DIR_WRITE)
1179 fdctrl->msr |= FD_MSR_DIO;
1180 /* IO based transfer: calculate len */
1181 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1182
1183 return;
1184 }
1185
1186 /* Prepare a transfer of deleted data */
1187 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
1188 {
1189 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n");
1190
1191 /* We don't handle deleted data,
1192 * so we don't return *ANYTHING*
1193 */
1194 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1195 }
1196
1197 /* handlers for DMA transfers */
1198 static int fdctrl_transfer_handler (void *opaque, int nchan,
1199 int dma_pos, int dma_len)
1200 {
1201 FDCtrl *fdctrl;
1202 FDrive *cur_drv;
1203 int len, start_pos, rel_pos;
1204 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1205
1206 fdctrl = opaque;
1207 if (fdctrl->msr & FD_MSR_RQM) {
1208 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1209 return 0;
1210 }
1211 cur_drv = get_cur_drv(fdctrl);
1212 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1213 fdctrl->data_dir == FD_DIR_SCANH)
1214 status2 = FD_SR2_SNS;
1215 if (dma_len > fdctrl->data_len)
1216 dma_len = fdctrl->data_len;
1217 if (cur_drv->bs == NULL) {
1218 if (fdctrl->data_dir == FD_DIR_WRITE)
1219 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1220 else
1221 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1222 len = 0;
1223 goto transfer_error;
1224 }
1225 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1226 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1227 len = dma_len - fdctrl->data_pos;
1228 if (len + rel_pos > FD_SECTOR_LEN)
1229 len = FD_SECTOR_LEN - rel_pos;
1230 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1231 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1232 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1233 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1234 fd_sector(cur_drv) * FD_SECTOR_LEN);
1235 if (fdctrl->data_dir != FD_DIR_WRITE ||
1236 len < FD_SECTOR_LEN || rel_pos != 0) {
1237 /* READ & SCAN commands and realign to a sector for WRITE */
1238 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1239 fdctrl->fifo, 1) < 0) {
1240 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1241 fd_sector(cur_drv));
1242 /* Sure, image size is too small... */
1243 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1244 }
1245 }
1246 switch (fdctrl->data_dir) {
1247 case FD_DIR_READ:
1248 /* READ commands */
1249 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1250 fdctrl->data_pos, len);
1251 break;
1252 case FD_DIR_WRITE:
1253 /* WRITE commands */
1254 if (cur_drv->ro) {
1255 /* Handle readonly medium early, no need to do DMA, touch the
1256 * LED or attempt any writes. A real floppy doesn't attempt
1257 * to write to readonly media either. */
1258 fdctrl_stop_transfer(fdctrl,
1259 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW,
1260 0x00);
1261 goto transfer_error;
1262 }
1263
1264 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1265 fdctrl->data_pos, len);
1266 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1267 fdctrl->fifo, 1) < 0) {
1268 FLOPPY_DPRINTF("error writing sector %d\n",
1269 fd_sector(cur_drv));
1270 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1271 goto transfer_error;
1272 }
1273 break;
1274 default:
1275 /* SCAN commands */
1276 {
1277 uint8_t tmpbuf[FD_SECTOR_LEN];
1278 int ret;
1279 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1280 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1281 if (ret == 0) {
1282 status2 = FD_SR2_SEH;
1283 goto end_transfer;
1284 }
1285 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1286 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1287 status2 = 0x00;
1288 goto end_transfer;
1289 }
1290 }
1291 break;
1292 }
1293 fdctrl->data_pos += len;
1294 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1295 if (rel_pos == 0) {
1296 /* Seek to next sector */
1297 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1298 break;
1299 }
1300 }
1301 end_transfer:
1302 len = fdctrl->data_pos - start_pos;
1303 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1304 fdctrl->data_pos, len, fdctrl->data_len);
1305 if (fdctrl->data_dir == FD_DIR_SCANE ||
1306 fdctrl->data_dir == FD_DIR_SCANL ||
1307 fdctrl->data_dir == FD_DIR_SCANH)
1308 status2 = FD_SR2_SEH;
1309 if (FD_DID_SEEK(fdctrl->data_state))
1310 status0 |= FD_SR0_SEEK;
1311 fdctrl->data_len -= len;
1312 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1313 transfer_error:
1314
1315 return len;
1316 }
1317
1318 /* Data register : 0x05 */
1319 static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
1320 {
1321 FDrive *cur_drv;
1322 uint32_t retval = 0;
1323 int pos;
1324
1325 cur_drv = get_cur_drv(fdctrl);
1326 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1327 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1328 FLOPPY_DPRINTF("error: controller not ready for reading\n");
1329 return 0;
1330 }
1331 pos = fdctrl->data_pos;
1332 if (fdctrl->msr & FD_MSR_NONDMA) {
1333 pos %= FD_SECTOR_LEN;
1334 if (pos == 0) {
1335 if (fdctrl->data_pos != 0)
1336 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1337 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1338 fd_sector(cur_drv));
1339 return 0;
1340 }
1341 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1342 FLOPPY_DPRINTF("error getting sector %d\n",
1343 fd_sector(cur_drv));
1344 /* Sure, image size is too small... */
1345 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1346 }
1347 }
1348 }
1349 retval = fdctrl->fifo[pos];
1350 if (++fdctrl->data_pos == fdctrl->data_len) {
1351 fdctrl->data_pos = 0;
1352 /* Switch from transfer mode to status mode
1353 * then from status mode to command mode
1354 */
1355 if (fdctrl->msr & FD_MSR_NONDMA) {
1356 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1357 } else {
1358 fdctrl_reset_fifo(fdctrl);
1359 fdctrl_reset_irq(fdctrl);
1360 }
1361 }
1362 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1363
1364 return retval;
1365 }
1366
1367 static void fdctrl_format_sector(FDCtrl *fdctrl)
1368 {
1369 FDrive *cur_drv;
1370 uint8_t kh, kt, ks;
1371
1372 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1373 cur_drv = get_cur_drv(fdctrl);
1374 kt = fdctrl->fifo[6];
1375 kh = fdctrl->fifo[7];
1376 ks = fdctrl->fifo[8];
1377 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1378 GET_CUR_DRV(fdctrl), kh, kt, ks,
1379 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1380 NUM_SIDES(cur_drv)));
1381 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1382 case 2:
1383 /* sect too big */
1384 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1385 fdctrl->fifo[3] = kt;
1386 fdctrl->fifo[4] = kh;
1387 fdctrl->fifo[5] = ks;
1388 return;
1389 case 3:
1390 /* track too big */
1391 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1392 fdctrl->fifo[3] = kt;
1393 fdctrl->fifo[4] = kh;
1394 fdctrl->fifo[5] = ks;
1395 return;
1396 case 4:
1397 /* No seek enabled */
1398 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1399 fdctrl->fifo[3] = kt;
1400 fdctrl->fifo[4] = kh;
1401 fdctrl->fifo[5] = ks;
1402 return;
1403 case 1:
1404 fdctrl->data_state |= FD_STATE_SEEK;
1405 break;
1406 default:
1407 break;
1408 }
1409 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1410 if (cur_drv->bs == NULL ||
1411 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1412 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv));
1413 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1414 } else {
1415 if (cur_drv->sect == cur_drv->last_sect) {
1416 fdctrl->data_state &= ~FD_STATE_FORMAT;
1417 /* Last sector done */
1418 if (FD_DID_SEEK(fdctrl->data_state))
1419 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1420 else
1421 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1422 } else {
1423 /* More to do */
1424 fdctrl->data_pos = 0;
1425 fdctrl->data_len = 4;
1426 }
1427 }
1428 }
1429
1430 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
1431 {
1432 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1433 fdctrl->fifo[0] = fdctrl->lock << 4;
1434 fdctrl_set_fifo(fdctrl, 1, 0);
1435 }
1436
1437 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
1438 {
1439 FDrive *cur_drv = get_cur_drv(fdctrl);
1440
1441 /* Drives position */
1442 fdctrl->fifo[0] = drv0(fdctrl)->track;
1443 fdctrl->fifo[1] = drv1(fdctrl)->track;
1444 #if MAX_FD == 4
1445 fdctrl->fifo[2] = drv2(fdctrl)->track;
1446 fdctrl->fifo[3] = drv3(fdctrl)->track;
1447 #else
1448 fdctrl->fifo[2] = 0;
1449 fdctrl->fifo[3] = 0;
1450 #endif
1451 /* timers */
1452 fdctrl->fifo[4] = fdctrl->timer0;
1453 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1454 fdctrl->fifo[6] = cur_drv->last_sect;
1455 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1456 (cur_drv->perpendicular << 2);
1457 fdctrl->fifo[8] = fdctrl->config;
1458 fdctrl->fifo[9] = fdctrl->precomp_trk;
1459 fdctrl_set_fifo(fdctrl, 10, 0);
1460 }
1461
1462 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
1463 {
1464 /* Controller's version */
1465 fdctrl->fifo[0] = fdctrl->version;
1466 fdctrl_set_fifo(fdctrl, 1, 0);
1467 }
1468
1469 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
1470 {
1471 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1472 fdctrl_set_fifo(fdctrl, 1, 0);
1473 }
1474
1475 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
1476 {
1477 FDrive *cur_drv = get_cur_drv(fdctrl);
1478
1479 /* Drives position */
1480 drv0(fdctrl)->track = fdctrl->fifo[3];
1481 drv1(fdctrl)->track = fdctrl->fifo[4];
1482 #if MAX_FD == 4
1483 drv2(fdctrl)->track = fdctrl->fifo[5];
1484 drv3(fdctrl)->track = fdctrl->fifo[6];
1485 #endif
1486 /* timers */
1487 fdctrl->timer0 = fdctrl->fifo[7];
1488 fdctrl->timer1 = fdctrl->fifo[8];
1489 cur_drv->last_sect = fdctrl->fifo[9];
1490 fdctrl->lock = fdctrl->fifo[10] >> 7;
1491 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1492 fdctrl->config = fdctrl->fifo[11];
1493 fdctrl->precomp_trk = fdctrl->fifo[12];
1494 fdctrl->pwrd = fdctrl->fifo[13];
1495 fdctrl_reset_fifo(fdctrl);
1496 }
1497
1498 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
1499 {
1500 FDrive *cur_drv = get_cur_drv(fdctrl);
1501
1502 fdctrl->fifo[0] = 0;
1503 fdctrl->fifo[1] = 0;
1504 /* Drives position */
1505 fdctrl->fifo[2] = drv0(fdctrl)->track;
1506 fdctrl->fifo[3] = drv1(fdctrl)->track;
1507 #if MAX_FD == 4
1508 fdctrl->fifo[4] = drv2(fdctrl)->track;
1509 fdctrl->fifo[5] = drv3(fdctrl)->track;
1510 #else
1511 fdctrl->fifo[4] = 0;
1512 fdctrl->fifo[5] = 0;
1513 #endif
1514 /* timers */
1515 fdctrl->fifo[6] = fdctrl->timer0;
1516 fdctrl->fifo[7] = fdctrl->timer1;
1517 fdctrl->fifo[8] = cur_drv->last_sect;
1518 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1519 (cur_drv->perpendicular << 2);
1520 fdctrl->fifo[10] = fdctrl->config;
1521 fdctrl->fifo[11] = fdctrl->precomp_trk;
1522 fdctrl->fifo[12] = fdctrl->pwrd;
1523 fdctrl->fifo[13] = 0;
1524 fdctrl->fifo[14] = 0;
1525 fdctrl_set_fifo(fdctrl, 15, 0);
1526 }
1527
1528 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
1529 {
1530 FDrive *cur_drv = get_cur_drv(fdctrl);
1531
1532 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1533 qemu_mod_timer(fdctrl->result_timer,
1534 qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 50));
1535 }
1536
1537 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
1538 {
1539 FDrive *cur_drv;
1540
1541 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1542 cur_drv = get_cur_drv(fdctrl);
1543 fdctrl->data_state |= FD_STATE_FORMAT;
1544 if (fdctrl->fifo[0] & 0x80)
1545 fdctrl->data_state |= FD_STATE_MULTI;
1546 else
1547 fdctrl->data_state &= ~FD_STATE_MULTI;
1548 fdctrl->data_state &= ~FD_STATE_SEEK;
1549 cur_drv->bps =
1550 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1551 #if 0
1552 cur_drv->last_sect =
1553 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1554 fdctrl->fifo[3] / 2;
1555 #else
1556 cur_drv->last_sect = fdctrl->fifo[3];
1557 #endif
1558 /* TODO: implement format using DMA expected by the Bochs BIOS
1559 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1560 * the sector with the specified fill byte
1561 */
1562 fdctrl->data_state &= ~FD_STATE_FORMAT;
1563 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1564 }
1565
1566 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
1567 {
1568 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1569 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1570 if (fdctrl->fifo[2] & 1)
1571 fdctrl->dor &= ~FD_DOR_DMAEN;
1572 else
1573 fdctrl->dor |= FD_DOR_DMAEN;
1574 /* No result back */
1575 fdctrl_reset_fifo(fdctrl);
1576 }
1577
1578 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
1579 {
1580 FDrive *cur_drv;
1581
1582 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1583 cur_drv = get_cur_drv(fdctrl);
1584 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1585 /* 1 Byte status back */
1586 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1587 (cur_drv->track == 0 ? 0x10 : 0x00) |
1588 (cur_drv->head << 2) |
1589 GET_CUR_DRV(fdctrl) |
1590 0x28;
1591 fdctrl_set_fifo(fdctrl, 1, 0);
1592 }
1593
1594 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
1595 {
1596 FDrive *cur_drv;
1597
1598 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1599 cur_drv = get_cur_drv(fdctrl);
1600 fd_recalibrate(cur_drv);
1601 fdctrl_reset_fifo(fdctrl);
1602 /* Raise Interrupt */
1603 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1604 }
1605
1606 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
1607 {
1608 FDrive *cur_drv = get_cur_drv(fdctrl);
1609
1610 if (fdctrl->reset_sensei > 0) {
1611 fdctrl->fifo[0] =
1612 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1613 fdctrl->reset_sensei--;
1614 } else if (!(fdctrl->sra & FD_SRA_INTPEND)) {
1615 fdctrl->fifo[0] = FD_SR0_INVCMD;
1616 fdctrl_set_fifo(fdctrl, 1, 0);
1617 return;
1618 } else {
1619 fdctrl->fifo[0] =
1620 (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0))
1621 | GET_CUR_DRV(fdctrl);
1622 }
1623
1624 fdctrl->fifo[1] = cur_drv->track;
1625 fdctrl_set_fifo(fdctrl, 2, 0);
1626 fdctrl_reset_irq(fdctrl);
1627 fdctrl->status0 = FD_SR0_RDYCHG;
1628 }
1629
1630 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
1631 {
1632 FDrive *cur_drv;
1633
1634 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1635 cur_drv = get_cur_drv(fdctrl);
1636 fdctrl_reset_fifo(fdctrl);
1637 /* The seek command just sends step pulses to the drive and doesn't care if
1638 * there is a medium inserted of if it's banging the head against the drive.
1639 */
1640 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1);
1641 /* Raise Interrupt */
1642 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1643 }
1644
1645 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
1646 {
1647 FDrive *cur_drv = get_cur_drv(fdctrl);
1648
1649 if (fdctrl->fifo[1] & 0x80)
1650 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1651 /* No result back */
1652 fdctrl_reset_fifo(fdctrl);
1653 }
1654
1655 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
1656 {
1657 fdctrl->config = fdctrl->fifo[2];
1658 fdctrl->precomp_trk = fdctrl->fifo[3];
1659 /* No result back */
1660 fdctrl_reset_fifo(fdctrl);
1661 }
1662
1663 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
1664 {
1665 fdctrl->pwrd = fdctrl->fifo[1];
1666 fdctrl->fifo[0] = fdctrl->fifo[1];
1667 fdctrl_set_fifo(fdctrl, 1, 0);
1668 }
1669
1670 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
1671 {
1672 /* No result back */
1673 fdctrl_reset_fifo(fdctrl);
1674 }
1675
1676 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
1677 {
1678 FDrive *cur_drv = get_cur_drv(fdctrl);
1679
1680 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1681 /* Command parameters done */
1682 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1683 fdctrl->fifo[0] = fdctrl->fifo[1];
1684 fdctrl->fifo[2] = 0;
1685 fdctrl->fifo[3] = 0;
1686 fdctrl_set_fifo(fdctrl, 4, 0);
1687 } else {
1688 fdctrl_reset_fifo(fdctrl);
1689 }
1690 } else if (fdctrl->data_len > 7) {
1691 /* ERROR */
1692 fdctrl->fifo[0] = 0x80 |
1693 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1694 fdctrl_set_fifo(fdctrl, 1, 0);
1695 }
1696 }
1697
1698 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
1699 {
1700 FDrive *cur_drv;
1701
1702 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1703 cur_drv = get_cur_drv(fdctrl);
1704 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1705 fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1,
1706 cur_drv->sect, 1);
1707 } else {
1708 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1);
1709 }
1710 fdctrl_reset_fifo(fdctrl);
1711 /* Raise Interrupt */
1712 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1713 }
1714
1715 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
1716 {
1717 FDrive *cur_drv;
1718
1719 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1720 cur_drv = get_cur_drv(fdctrl);
1721 if (fdctrl->fifo[2] > cur_drv->track) {
1722 fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1);
1723 } else {
1724 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1);
1725 }
1726 fdctrl_reset_fifo(fdctrl);
1727 /* Raise Interrupt */
1728 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1729 }
1730
1731 static const struct {
1732 uint8_t value;
1733 uint8_t mask;
1734 const char* name;
1735 int parameters;
1736 void (*handler)(FDCtrl *fdctrl, int direction);
1737 int direction;
1738 } handlers[] = {
1739 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1740 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1741 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1742 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1743 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1744 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1745 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1746 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1747 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1748 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1749 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1750 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1751 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1752 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1753 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1754 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1755 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1756 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1757 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1758 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1759 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1760 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1761 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1762 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1763 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1764 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1765 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1766 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1767 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1768 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1769 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1770 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1771 };
1772 /* Associate command to an index in the 'handlers' array */
1773 static uint8_t command_to_handler[256];
1774
1775 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
1776 {
1777 FDrive *cur_drv;
1778 int pos;
1779
1780 /* Reset mode */
1781 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1782 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1783 return;
1784 }
1785 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1786 FLOPPY_DPRINTF("error: controller not ready for writing\n");
1787 return;
1788 }
1789 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1790 /* Is it write command time ? */
1791 if (fdctrl->msr & FD_MSR_NONDMA) {
1792 /* FIFO data write */
1793 pos = fdctrl->data_pos++;
1794 pos %= FD_SECTOR_LEN;
1795 fdctrl->fifo[pos] = value;
1796 if (pos == FD_SECTOR_LEN - 1 ||
1797 fdctrl->data_pos == fdctrl->data_len) {
1798 cur_drv = get_cur_drv(fdctrl);
1799 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1800 FLOPPY_DPRINTF("error writing sector %d\n",
1801 fd_sector(cur_drv));
1802 return;
1803 }
1804 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1805 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1806 fd_sector(cur_drv));
1807 return;
1808 }
1809 }
1810 /* Switch from transfer mode to status mode
1811 * then from status mode to command mode
1812 */
1813 if (fdctrl->data_pos == fdctrl->data_len)
1814 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1815 return;
1816 }
1817 if (fdctrl->data_pos == 0) {
1818 /* Command */
1819 pos = command_to_handler[value & 0xff];
1820 FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1821 fdctrl->data_len = handlers[pos].parameters + 1;
1822 fdctrl->msr |= FD_MSR_CMDBUSY;
1823 }
1824
1825 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1826 fdctrl->fifo[fdctrl->data_pos++] = value;
1827 if (fdctrl->data_pos == fdctrl->data_len) {
1828 /* We now have all parameters
1829 * and will be able to treat the command
1830 */
1831 if (fdctrl->data_state & FD_STATE_FORMAT) {
1832 fdctrl_format_sector(fdctrl);
1833 return;
1834 }
1835
1836 pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1837 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1838 (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1839 }
1840 }
1841
1842 static void fdctrl_result_timer(void *opaque)
1843 {
1844 FDCtrl *fdctrl = opaque;
1845 FDrive *cur_drv = get_cur_drv(fdctrl);
1846
1847 /* Pretend we are spinning.
1848 * This is needed for Coherent, which uses READ ID to check for
1849 * sector interleaving.
1850 */
1851 if (cur_drv->last_sect != 0) {
1852 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1853 }
1854 /* READ_ID can't automatically succeed! */
1855 if (fdctrl->check_media_rate &&
1856 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1857 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n",
1858 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1859 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1860 } else {
1861 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1862 }
1863 }
1864
1865 static void fdctrl_change_cb(void *opaque, bool load)
1866 {
1867 FDrive *drive = opaque;
1868
1869 drive->media_changed = 1;
1870 fd_revalidate(drive);
1871 }
1872
1873 static const BlockDevOps fdctrl_block_ops = {
1874 .change_media_cb = fdctrl_change_cb,
1875 };
1876
1877 /* Init functions */
1878 static int fdctrl_connect_drives(FDCtrl *fdctrl)
1879 {
1880 unsigned int i;
1881 FDrive *drive;
1882
1883 for (i = 0; i < MAX_FD; i++) {
1884 drive = &fdctrl->drives[i];
1885 drive->fdctrl = fdctrl;
1886
1887 if (drive->bs) {
1888 if (bdrv_get_on_error(drive->bs, 0) != BLOCK_ERR_STOP_ENOSPC) {
1889 error_report("fdc doesn't support drive option werror");
1890 return -1;
1891 }
1892 if (bdrv_get_on_error(drive->bs, 1) != BLOCK_ERR_REPORT) {
1893 error_report("fdc doesn't support drive option rerror");
1894 return -1;
1895 }
1896 }
1897
1898 fd_init(drive);
1899 fdctrl_change_cb(drive, 0);
1900 if (drive->bs) {
1901 bdrv_set_dev_ops(drive->bs, &fdctrl_block_ops, drive);
1902 }
1903 }
1904 return 0;
1905 }
1906
1907 ISADevice *fdctrl_init_isa(ISABus *bus, DriveInfo **fds)
1908 {
1909 ISADevice *dev;
1910
1911 dev = isa_try_create(bus, "isa-fdc");
1912 if (!dev) {
1913 return NULL;
1914 }
1915
1916 if (fds[0]) {
1917 qdev_prop_set_drive_nofail(&dev->qdev, "driveA", fds[0]->bdrv);
1918 }
1919 if (fds[1]) {
1920 qdev_prop_set_drive_nofail(&dev->qdev, "driveB", fds[1]->bdrv);
1921 }
1922 qdev_init_nofail(&dev->qdev);
1923
1924 return dev;
1925 }
1926
1927 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
1928 target_phys_addr_t mmio_base, DriveInfo **fds)
1929 {
1930 FDCtrl *fdctrl;
1931 DeviceState *dev;
1932 FDCtrlSysBus *sys;
1933
1934 dev = qdev_create(NULL, "sysbus-fdc");
1935 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1936 fdctrl = &sys->state;
1937 fdctrl->dma_chann = dma_chann; /* FIXME */
1938 if (fds[0]) {
1939 qdev_prop_set_drive_nofail(dev, "driveA", fds[0]->bdrv);
1940 }
1941 if (fds[1]) {
1942 qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv);
1943 }
1944 qdev_init_nofail(dev);
1945 sysbus_connect_irq(&sys->busdev, 0, irq);
1946 sysbus_mmio_map(&sys->busdev, 0, mmio_base);
1947 }
1948
1949 void sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
1950 DriveInfo **fds, qemu_irq *fdc_tc)
1951 {
1952 DeviceState *dev;
1953 FDCtrlSysBus *sys;
1954
1955 dev = qdev_create(NULL, "SUNW,fdtwo");
1956 if (fds[0]) {
1957 qdev_prop_set_drive_nofail(dev, "drive", fds[0]->bdrv);
1958 }
1959 qdev_init_nofail(dev);
1960 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1961 sysbus_connect_irq(&sys->busdev, 0, irq);
1962 sysbus_mmio_map(&sys->busdev, 0, io_base);
1963 *fdc_tc = qdev_get_gpio_in(dev, 0);
1964 }
1965
1966 static int fdctrl_init_common(FDCtrl *fdctrl)
1967 {
1968 int i, j;
1969 static int command_tables_inited = 0;
1970
1971 /* Fill 'command_to_handler' lookup table */
1972 if (!command_tables_inited) {
1973 command_tables_inited = 1;
1974 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
1975 for (j = 0; j < sizeof(command_to_handler); j++) {
1976 if ((j & handlers[i].mask) == handlers[i].value) {
1977 command_to_handler[j] = i;
1978 }
1979 }
1980 }
1981 }
1982
1983 FLOPPY_DPRINTF("init controller\n");
1984 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1985 fdctrl->fifo_size = 512;
1986 fdctrl->result_timer = qemu_new_timer_ns(vm_clock,
1987 fdctrl_result_timer, fdctrl);
1988
1989 fdctrl->version = 0x90; /* Intel 82078 controller */
1990 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1991 fdctrl->num_floppies = MAX_FD;
1992
1993 if (fdctrl->dma_chann != -1)
1994 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
1995 return fdctrl_connect_drives(fdctrl);
1996 }
1997
1998 static const MemoryRegionPortio fdc_portio_list[] = {
1999 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
2000 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
2001 PORTIO_END_OF_LIST(),
2002 };
2003
2004 static int isabus_fdc_init1(ISADevice *dev)
2005 {
2006 FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
2007 FDCtrl *fdctrl = &isa->state;
2008 int ret;
2009
2010 isa_register_portio_list(dev, isa->iobase, fdc_portio_list, fdctrl, "fdc");
2011
2012 isa_init_irq(&isa->busdev, &fdctrl->irq, isa->irq);
2013 fdctrl->dma_chann = isa->dma;
2014
2015 qdev_set_legacy_instance_id(&dev->qdev, isa->iobase, 2);
2016 ret = fdctrl_init_common(fdctrl);
2017
2018 add_boot_device_path(isa->bootindexA, &dev->qdev, "/floppy@0");
2019 add_boot_device_path(isa->bootindexB, &dev->qdev, "/floppy@1");
2020
2021 return ret;
2022 }
2023
2024 static int sysbus_fdc_init1(SysBusDevice *dev)
2025 {
2026 FDCtrlSysBus *sys = DO_UPCAST(FDCtrlSysBus, busdev, dev);
2027 FDCtrl *fdctrl = &sys->state;
2028 int ret;
2029
2030 memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_ops, fdctrl, "fdc", 0x08);
2031 sysbus_init_mmio(dev, &fdctrl->iomem);
2032 sysbus_init_irq(dev, &fdctrl->irq);
2033 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
2034 fdctrl->dma_chann = -1;
2035
2036 qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */
2037 ret = fdctrl_init_common(fdctrl);
2038
2039 return ret;
2040 }
2041
2042 static int sun4m_fdc_init1(SysBusDevice *dev)
2043 {
2044 FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state);
2045
2046 memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_strict_ops, fdctrl,
2047 "fdctrl", 0x08);
2048 sysbus_init_mmio(dev, &fdctrl->iomem);
2049 sysbus_init_irq(dev, &fdctrl->irq);
2050 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
2051
2052 fdctrl->sun4m = 1;
2053 qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */
2054 return fdctrl_init_common(fdctrl);
2055 }
2056
2057 void fdc_get_bs(BlockDriverState *bs[], ISADevice *dev)
2058 {
2059 FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
2060 FDCtrl *fdctrl = &isa->state;
2061 int i;
2062
2063 for (i = 0; i < MAX_FD; i++) {
2064 bs[i] = fdctrl->drives[i].bs;
2065 }
2066 }
2067
2068
2069 static const VMStateDescription vmstate_isa_fdc ={
2070 .name = "fdc",
2071 .version_id = 2,
2072 .minimum_version_id = 2,
2073 .fields = (VMStateField []) {
2074 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2075 VMSTATE_END_OF_LIST()
2076 }
2077 };
2078
2079 static Property isa_fdc_properties[] = {
2080 DEFINE_PROP_HEX32("iobase", FDCtrlISABus, iobase, 0x3f0),
2081 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6),
2082 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2),
2083 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].bs),
2084 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].bs),
2085 DEFINE_PROP_INT32("bootindexA", FDCtrlISABus, bootindexA, -1),
2086 DEFINE_PROP_INT32("bootindexB", FDCtrlISABus, bootindexB, -1),
2087 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate,
2088 0, true),
2089 DEFINE_PROP_END_OF_LIST(),
2090 };
2091
2092 static void isabus_fdc_class_init1(ObjectClass *klass, void *data)
2093 {
2094 DeviceClass *dc = DEVICE_CLASS(klass);
2095 ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
2096 ic->init = isabus_fdc_init1;
2097 dc->fw_name = "fdc";
2098 dc->no_user = 1;
2099 dc->reset = fdctrl_external_reset_isa;
2100 dc->vmsd = &vmstate_isa_fdc;
2101 dc->props = isa_fdc_properties;
2102 }
2103
2104 static TypeInfo isa_fdc_info = {
2105 .name = "isa-fdc",
2106 .parent = TYPE_ISA_DEVICE,
2107 .instance_size = sizeof(FDCtrlISABus),
2108 .class_init = isabus_fdc_class_init1,
2109 };
2110
2111 static const VMStateDescription vmstate_sysbus_fdc ={
2112 .name = "fdc",
2113 .version_id = 2,
2114 .minimum_version_id = 2,
2115 .fields = (VMStateField []) {
2116 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2117 VMSTATE_END_OF_LIST()
2118 }
2119 };
2120
2121 static Property sysbus_fdc_properties[] = {
2122 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].bs),
2123 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].bs),
2124 DEFINE_PROP_END_OF_LIST(),
2125 };
2126
2127 static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
2128 {
2129 DeviceClass *dc = DEVICE_CLASS(klass);
2130 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
2131
2132 k->init = sysbus_fdc_init1;
2133 dc->reset = fdctrl_external_reset_sysbus;
2134 dc->vmsd = &vmstate_sysbus_fdc;
2135 dc->props = sysbus_fdc_properties;
2136 }
2137
2138 static TypeInfo sysbus_fdc_info = {
2139 .name = "sysbus-fdc",
2140 .parent = TYPE_SYS_BUS_DEVICE,
2141 .instance_size = sizeof(FDCtrlSysBus),
2142 .class_init = sysbus_fdc_class_init,
2143 };
2144
2145 static Property sun4m_fdc_properties[] = {
2146 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].bs),
2147 DEFINE_PROP_END_OF_LIST(),
2148 };
2149
2150 static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
2151 {
2152 DeviceClass *dc = DEVICE_CLASS(klass);
2153 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
2154
2155 k->init = sun4m_fdc_init1;
2156 dc->reset = fdctrl_external_reset_sysbus;
2157 dc->vmsd = &vmstate_sysbus_fdc;
2158 dc->props = sun4m_fdc_properties;
2159 }
2160
2161 static TypeInfo sun4m_fdc_info = {
2162 .name = "SUNW,fdtwo",
2163 .parent = TYPE_SYS_BUS_DEVICE,
2164 .instance_size = sizeof(FDCtrlSysBus),
2165 .class_init = sun4m_fdc_class_init,
2166 };
2167
2168 static void fdc_register_types(void)
2169 {
2170 type_register_static(&isa_fdc_info);
2171 type_register_static(&sysbus_fdc_info);
2172 type_register_static(&sun4m_fdc_info);
2173 }
2174
2175 type_init(fdc_register_types)
Patch queue for openSUSE QEMU