hw/m48t59.c

   1 /*
   2  * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
   3  *
   4  * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "nvram.h"
  26 #include "qemu-timer.h"
  27 #include "sysemu.h"
  28 #include "sysbus.h"
  29 #include "isa.h"
  30
  31 //#define DEBUG_NVRAM
  32
  33 #if defined(DEBUG_NVRAM)
  34 #define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
  35 #else
  36 #define NVRAM_PRINTF(fmt, ...) do { } while (0)
  37 #endif
  38
  39 /*
  40  * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
  41  * alarm and a watchdog timer and related control registers. In the
  42  * PPC platform there is also a nvram lock function.
  43  */
  44
  45 /*
  46  * Chipset docs:
  47  * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
  48  * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
  49  * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
  50  */
  51
  52 struct M48t59State {
  53     /* Hardware parameters */
  54     qemu_irq IRQ;
  55     MemoryRegion iomem;
  56     uint32_t io_base;
  57     uint32_t size;
  58     /* RTC management */
  59     time_t   time_offset;
  60     time_t   stop_time;
  61     /* Alarm & watchdog */
  62     struct tm alarm;
  63     struct QEMUTimer *alrm_timer;
  64     struct QEMUTimer *wd_timer;
  65     /* NVRAM storage */
  66     uint8_t *buffer;
  67     /* Model parameters */
  68     uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
  69     /* NVRAM storage */
  70     uint16_t addr;
  71     uint8_t  lock;
  72 };
  73
  74 typedef struct M48t59ISAState {
  75     ISADevice busdev;
  76     M48t59State state;
  77     MemoryRegion io;
  78 } M48t59ISAState;
  79
  80 typedef struct M48t59SysBusState {
  81     SysBusDevice busdev;
  82     M48t59State state;
  83 } M48t59SysBusState;
  84
  85 /* Fake timer functions */
  86
  87 /* Alarm management */
  88 static void alarm_cb (void *opaque)
  89 {
  90     struct tm tm;
  91     uint64_t next_time;
  92     M48t59State *NVRAM = opaque;
  93
  94     qemu_set_irq(NVRAM->IRQ, 1);
  95     if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
  96         (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
  97         (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
  98         (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
  99         /* Repeat once a month */
 100         qemu_get_timedate(&tm, NVRAM->time_offset);
 101         tm.tm_mon++;
 102         if (tm.tm_mon == 13) {
 103             tm.tm_mon = 1;
 104             tm.tm_year++;
 105         }
 106         next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset;
 107     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 108                (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
 109                (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
 110                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 111         /* Repeat once a day */
 112         next_time = 24 * 60 * 60;
 113     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 114                (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
 115                (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
 116                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 117         /* Repeat once an hour */
 118         next_time = 60 * 60;
 119     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 120                (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
 121                (NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
 122                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 123         /* Repeat once a minute */
 124         next_time = 60;
 125     } else {
 126         /* Repeat once a second */
 127         next_time = 1;
 128     }
 129     qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock_ns(rtc_clock) +
 130                     next_time * 1000);
 131     qemu_set_irq(NVRAM->IRQ, 0);
 132 }
 133
 134 static void set_alarm(M48t59State *NVRAM)
 135 {
 136     int diff;
 137     if (NVRAM->alrm_timer != NULL) {
 138         qemu_del_timer(NVRAM->alrm_timer);
 139         diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
 140         if (diff > 0)
 141             qemu_mod_timer(NVRAM->alrm_timer, diff * 1000);
 142     }
 143 }
 144
 145 /* RTC management helpers */
 146 static inline void get_time(M48t59State *NVRAM, struct tm *tm)
 147 {
 148     qemu_get_timedate(tm, NVRAM->time_offset);
 149 }
 150
 151 static void set_time(M48t59State *NVRAM, struct tm *tm)
 152 {
 153     NVRAM->time_offset = qemu_timedate_diff(tm);
 154     set_alarm(NVRAM);
 155 }
 156
 157 /* Watchdog management */
 158 static void watchdog_cb (void *opaque)
 159 {
 160     M48t59State *NVRAM = opaque;
 161
 162     NVRAM->buffer[0x1FF0] |= 0x80;
 163     if (NVRAM->buffer[0x1FF7] & 0x80) {
 164         NVRAM->buffer[0x1FF7] = 0x00;
 165         NVRAM->buffer[0x1FFC] &= ~0x40;
 166         /* May it be a hw CPU Reset instead ? */
 167         qemu_system_reset_request();
 168     } else {
 169         qemu_set_irq(NVRAM->IRQ, 1);
 170         qemu_set_irq(NVRAM->IRQ, 0);
 171     }
 172 }
 173
 174 static void set_up_watchdog(M48t59State *NVRAM, uint8_t value)
 175 {
 176     uint64_t interval; /* in 1/16 seconds */
 177
 178     NVRAM->buffer[0x1FF0] &= ~0x80;
 179     if (NVRAM->wd_timer != NULL) {
 180         qemu_del_timer(NVRAM->wd_timer);
 181         if (value != 0) {
 182             interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
 183             qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
 184                            ((interval * 1000) >> 4));
 185         }
 186     }
 187 }
 188
 189 /* Direct access to NVRAM */
 190 void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
 191 {
 192     M48t59State *NVRAM = opaque;
 193     struct tm tm;
 194     int tmp;
 195
 196     if (addr > 0x1FF8 && addr < 0x2000)
 197         NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
 198
 199     /* check for NVRAM access */
 200     if ((NVRAM->model == 2 && addr < 0x7f8) ||
 201         (NVRAM->model == 8 && addr < 0x1ff8) ||
 202         (NVRAM->model == 59 && addr < 0x1ff0)) {
 203         goto do_write;
 204     }
 205
 206     /* TOD access */
 207     switch (addr) {
 208     case 0x1FF0:
 209         /* flags register : read-only */
 210         break;
 211     case 0x1FF1:
 212         /* unused */
 213         break;
 214     case 0x1FF2:
 215         /* alarm seconds */
 216         tmp = from_bcd(val & 0x7F);
 217         if (tmp >= 0 && tmp <= 59) {
 218             NVRAM->alarm.tm_sec = tmp;
 219             NVRAM->buffer[0x1FF2] = val;
 220             set_alarm(NVRAM);
 221         }
 222         break;
 223     case 0x1FF3:
 224         /* alarm minutes */
 225         tmp = from_bcd(val & 0x7F);
 226         if (tmp >= 0 && tmp <= 59) {
 227             NVRAM->alarm.tm_min = tmp;
 228             NVRAM->buffer[0x1FF3] = val;
 229             set_alarm(NVRAM);
 230         }
 231         break;
 232     case 0x1FF4:
 233         /* alarm hours */
 234         tmp = from_bcd(val & 0x3F);
 235         if (tmp >= 0 && tmp <= 23) {
 236             NVRAM->alarm.tm_hour = tmp;
 237             NVRAM->buffer[0x1FF4] = val;
 238             set_alarm(NVRAM);
 239         }
 240         break;
 241     case 0x1FF5:
 242         /* alarm date */
 243         tmp = from_bcd(val & 0x3F);
 244         if (tmp != 0) {
 245             NVRAM->alarm.tm_mday = tmp;
 246             NVRAM->buffer[0x1FF5] = val;
 247             set_alarm(NVRAM);
 248         }
 249         break;
 250     case 0x1FF6:
 251         /* interrupts */
 252         NVRAM->buffer[0x1FF6] = val;
 253         break;
 254     case 0x1FF7:
 255         /* watchdog */
 256         NVRAM->buffer[0x1FF7] = val;
 257         set_up_watchdog(NVRAM, val);
 258         break;
 259     case 0x1FF8:
 260     case 0x07F8:
 261         /* control */
 262        NVRAM->buffer[addr] = (val & ~0xA0) | 0x90;
 263         break;
 264     case 0x1FF9:
 265     case 0x07F9:
 266         /* seconds (BCD) */
 267         tmp = from_bcd(val & 0x7F);
 268         if (tmp >= 0 && tmp <= 59) {
 269             get_time(NVRAM, &tm);
 270             tm.tm_sec = tmp;
 271             set_time(NVRAM, &tm);
 272         }
 273         if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) {
 274             if (val & 0x80) {
 275                 NVRAM->stop_time = time(NULL);
 276             } else {
 277                 NVRAM->time_offset += NVRAM->stop_time - time(NULL);
 278                 NVRAM->stop_time = 0;
 279             }
 280         }
 281         NVRAM->buffer[addr] = val & 0x80;
 282         break;
 283     case 0x1FFA:
 284     case 0x07FA:
 285         /* minutes (BCD) */
 286         tmp = from_bcd(val & 0x7F);
 287         if (tmp >= 0 && tmp <= 59) {
 288             get_time(NVRAM, &tm);
 289             tm.tm_min = tmp;
 290             set_time(NVRAM, &tm);
 291         }
 292         break;
 293     case 0x1FFB:
 294     case 0x07FB:
 295         /* hours (BCD) */
 296         tmp = from_bcd(val & 0x3F);
 297         if (tmp >= 0 && tmp <= 23) {
 298             get_time(NVRAM, &tm);
 299             tm.tm_hour = tmp;
 300             set_time(NVRAM, &tm);
 301         }
 302         break;
 303     case 0x1FFC:
 304     case 0x07FC:
 305         /* day of the week / century */
 306         tmp = from_bcd(val & 0x07);
 307         get_time(NVRAM, &tm);
 308         tm.tm_wday = tmp;
 309         set_time(NVRAM, &tm);
 310         NVRAM->buffer[addr] = val & 0x40;
 311         break;
 312     case 0x1FFD:
 313     case 0x07FD:
 314         /* date (BCD) */
 315        tmp = from_bcd(val & 0x3F);
 316         if (tmp != 0) {
 317             get_time(NVRAM, &tm);
 318             tm.tm_mday = tmp;
 319             set_time(NVRAM, &tm);
 320         }
 321         break;
 322     case 0x1FFE:
 323     case 0x07FE:
 324         /* month */
 325         tmp = from_bcd(val & 0x1F);
 326         if (tmp >= 1 && tmp <= 12) {
 327             get_time(NVRAM, &tm);
 328             tm.tm_mon = tmp - 1;
 329             set_time(NVRAM, &tm);
 330         }
 331         break;
 332     case 0x1FFF:
 333     case 0x07FF:
 334         /* year */
 335         tmp = from_bcd(val);
 336         if (tmp >= 0 && tmp <= 99) {
 337             get_time(NVRAM, &tm);
 338             if (NVRAM->model == 8) {
 339                 tm.tm_year = from_bcd(val) + 68; // Base year is 1968
 340             } else {
 341                 tm.tm_year = from_bcd(val);
 342             }
 343             set_time(NVRAM, &tm);
 344         }
 345         break;
 346     default:
 347         /* Check lock registers state */
 348         if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
 349             break;
 350         if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
 351             break;
 352     do_write:
 353         if (addr < NVRAM->size) {
 354             NVRAM->buffer[addr] = val & 0xFF;
 355         }
 356         break;
 357     }
 358 }
 359
 360 uint32_t m48t59_read (void *opaque, uint32_t addr)
 361 {
 362     M48t59State *NVRAM = opaque;
 363     struct tm tm;
 364     uint32_t retval = 0xFF;
 365
 366     /* check for NVRAM access */
 367     if ((NVRAM->model == 2 && addr < 0x078f) ||
 368         (NVRAM->model == 8 && addr < 0x1ff8) ||
 369         (NVRAM->model == 59 && addr < 0x1ff0)) {
 370         goto do_read;
 371     }
 372
 373     /* TOD access */
 374     switch (addr) {
 375     case 0x1FF0:
 376         /* flags register */
 377         goto do_read;
 378     case 0x1FF1:
 379         /* unused */
 380         retval = 0;
 381         break;
 382     case 0x1FF2:
 383         /* alarm seconds */
 384         goto do_read;
 385     case 0x1FF3:
 386         /* alarm minutes */
 387         goto do_read;
 388     case 0x1FF4:
 389         /* alarm hours */
 390         goto do_read;
 391     case 0x1FF5:
 392         /* alarm date */
 393         goto do_read;
 394     case 0x1FF6:
 395         /* interrupts */
 396         goto do_read;
 397     case 0x1FF7:
 398         /* A read resets the watchdog */
 399         set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
 400         goto do_read;
 401     case 0x1FF8:
 402     case 0x07F8:
 403         /* control */
 404         goto do_read;
 405     case 0x1FF9:
 406     case 0x07F9:
 407         /* seconds (BCD) */
 408         get_time(NVRAM, &tm);
 409         retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec);
 410         break;
 411     case 0x1FFA:
 412     case 0x07FA:
 413         /* minutes (BCD) */
 414         get_time(NVRAM, &tm);
 415         retval = to_bcd(tm.tm_min);
 416         break;
 417     case 0x1FFB:
 418     case 0x07FB:
 419         /* hours (BCD) */
 420         get_time(NVRAM, &tm);
 421         retval = to_bcd(tm.tm_hour);
 422         break;
 423     case 0x1FFC:
 424     case 0x07FC:
 425         /* day of the week / century */
 426         get_time(NVRAM, &tm);
 427         retval = NVRAM->buffer[addr] | tm.tm_wday;
 428         break;
 429     case 0x1FFD:
 430     case 0x07FD:
 431         /* date */
 432         get_time(NVRAM, &tm);
 433         retval = to_bcd(tm.tm_mday);
 434         break;
 435     case 0x1FFE:
 436     case 0x07FE:
 437         /* month */
 438         get_time(NVRAM, &tm);
 439         retval = to_bcd(tm.tm_mon + 1);
 440         break;
 441     case 0x1FFF:
 442     case 0x07FF:
 443         /* year */
 444         get_time(NVRAM, &tm);
 445         if (NVRAM->model == 8) {
 446             retval = to_bcd(tm.tm_year - 68); // Base year is 1968
 447         } else {
 448             retval = to_bcd(tm.tm_year);
 449         }
 450         break;
 451     default:
 452         /* Check lock registers state */
 453         if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
 454             break;
 455         if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
 456             break;
 457     do_read:
 458         if (addr < NVRAM->size) {
 459             retval = NVRAM->buffer[addr];
 460         }
 461         break;
 462     }
 463     if (addr > 0x1FF9 && addr < 0x2000)
 464        NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
 465
 466     return retval;
 467 }
 468
 469 void m48t59_set_addr (void *opaque, uint32_t addr)
 470 {
 471     M48t59State *NVRAM = opaque;
 472
 473     NVRAM->addr = addr;
 474 }
 475
 476 void m48t59_toggle_lock (void *opaque, int lock)
 477 {
 478     M48t59State *NVRAM = opaque;
 479
 480     NVRAM->lock ^= 1 << lock;
 481 }
 482
 483 /* IO access to NVRAM */
 484 static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
 485 {
 486     M48t59State *NVRAM = opaque;
 487
 488     NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
 489     switch (addr) {
 490     case 0:
 491         NVRAM->addr &= ~0x00FF;
 492         NVRAM->addr |= val;
 493         break;
 494     case 1:
 495         NVRAM->addr &= ~0xFF00;
 496         NVRAM->addr |= val << 8;
 497         break;
 498     case 3:
 499         m48t59_write(NVRAM, NVRAM->addr, val);
 500         NVRAM->addr = 0x0000;
 501         break;
 502     default:
 503         break;
 504     }
 505 }
 506
 507 static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
 508 {
 509     M48t59State *NVRAM = opaque;
 510     uint32_t retval;
 511
 512     switch (addr) {
 513     case 3:
 514         retval = m48t59_read(NVRAM, NVRAM->addr);
 515         break;
 516     default:
 517         retval = -1;
 518         break;
 519     }
 520     NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
 521
 522     return retval;
 523 }
 524
 525 static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
 526 {
 527     M48t59State *NVRAM = opaque;
 528
 529     m48t59_write(NVRAM, addr, value & 0xff);
 530 }
 531
 532 static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
 533 {
 534     M48t59State *NVRAM = opaque;
 535
 536     m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
 537     m48t59_write(NVRAM, addr + 1, value & 0xff);
 538 }
 539
 540 static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
 541 {
 542     M48t59State *NVRAM = opaque;
 543
 544     m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
 545     m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
 546     m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
 547     m48t59_write(NVRAM, addr + 3, value & 0xff);
 548 }
 549
 550 static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
 551 {
 552     M48t59State *NVRAM = opaque;
 553     uint32_t retval;
 554
 555     retval = m48t59_read(NVRAM, addr);
 556     return retval;
 557 }
 558
 559 static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
 560 {
 561     M48t59State *NVRAM = opaque;
 562     uint32_t retval;
 563
 564     retval = m48t59_read(NVRAM, addr) << 8;
 565     retval |= m48t59_read(NVRAM, addr + 1);
 566     return retval;
 567 }
 568
 569 static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
 570 {
 571     M48t59State *NVRAM = opaque;
 572     uint32_t retval;
 573
 574     retval = m48t59_read(NVRAM, addr) << 24;
 575     retval |= m48t59_read(NVRAM, addr + 1) << 16;
 576     retval |= m48t59_read(NVRAM, addr + 2) << 8;
 577     retval |= m48t59_read(NVRAM, addr + 3);
 578     return retval;
 579 }
 580
 581 static const MemoryRegionOps nvram_ops = {
 582     .old_mmio = {
 583         .read = { nvram_readb, nvram_readw, nvram_readl, },
 584         .write = { nvram_writeb, nvram_writew, nvram_writel, },
 585     },
 586     .endianness = DEVICE_NATIVE_ENDIAN,
 587 };
 588
 589 static const VMStateDescription vmstate_m48t59 = {
 590     .name = "m48t59",
 591     .version_id = 1,
 592     .minimum_version_id = 1,
 593     .minimum_version_id_old = 1,
 594     .fields      = (VMStateField[]) {
 595         VMSTATE_UINT8(lock, M48t59State),
 596         VMSTATE_UINT16(addr, M48t59State),
 597         VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, 0, size),
 598         VMSTATE_END_OF_LIST()
 599     }
 600 };
 601
 602 static void m48t59_reset_common(M48t59State *NVRAM)
 603 {
 604     NVRAM->addr = 0;
 605     NVRAM->lock = 0;
 606     if (NVRAM->alrm_timer != NULL)
 607         qemu_del_timer(NVRAM->alrm_timer);
 608
 609     if (NVRAM->wd_timer != NULL)
 610         qemu_del_timer(NVRAM->wd_timer);
 611 }
 612
 613 static void m48t59_reset_isa(DeviceState *d)
 614 {
 615     M48t59ISAState *isa = container_of(d, M48t59ISAState, busdev.qdev);
 616     M48t59State *NVRAM = &isa->state;
 617
 618     m48t59_reset_common(NVRAM);
 619 }
 620
 621 static void m48t59_reset_sysbus(DeviceState *d)
 622 {
 623     M48t59SysBusState *sys = container_of(d, M48t59SysBusState, busdev.qdev);
 624     M48t59State *NVRAM = &sys->state;
 625
 626     m48t59_reset_common(NVRAM);
 627 }
 628
 629 static const MemoryRegionPortio m48t59_portio[] = {
 630     {0, 4, 1, .read = NVRAM_readb, .write = NVRAM_writeb },
 631     PORTIO_END_OF_LIST(),
 632 };
 633
 634 static const MemoryRegionOps m48t59_io_ops = {
 635     .old_portio = m48t59_portio,
 636 };
 637
 638 /* Initialisation routine */
 639 M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base,
 640                          uint32_t io_base, uint16_t size, int model)
 641 {
 642     DeviceState *dev;
 643     SysBusDevice *s;
 644     M48t59SysBusState *d;
 645     M48t59State *state;
 646
 647     dev = qdev_create(NULL, "m48t59");
 648     qdev_prop_set_uint32(dev, "model", model);
 649     qdev_prop_set_uint32(dev, "size", size);
 650     qdev_prop_set_uint32(dev, "io_base", io_base);
 651     qdev_init_nofail(dev);
 652     s = sysbus_from_qdev(dev);
 653     d = FROM_SYSBUS(M48t59SysBusState, s);
 654     state = &d->state;
 655     sysbus_connect_irq(s, 0, IRQ);
 656     if (io_base != 0) {
 657         register_ioport_read(io_base, 0x04, 1, NVRAM_readb, state);
 658         register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, state);
 659     }
 660     if (mem_base != 0) {
 661         sysbus_mmio_map(s, 0, mem_base);
 662     }
 663
 664     return state;
 665 }
 666
 667 M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
 668                              int model)
 669 {
 670     M48t59ISAState *d;
 671     ISADevice *dev;
 672     M48t59State *s;
 673
 674     dev = isa_create(bus, "m48t59_isa");
 675     qdev_prop_set_uint32(&dev->qdev, "model", model);
 676     qdev_prop_set_uint32(&dev->qdev, "size", size);
 677     qdev_prop_set_uint32(&dev->qdev, "io_base", io_base);
 678     qdev_init_nofail(&dev->qdev);
 679     d = DO_UPCAST(M48t59ISAState, busdev, dev);
 680     s = &d->state;
 681
 682     memory_region_init_io(&d->io, &m48t59_io_ops, s, "m48t59", 4);
 683     if (io_base != 0) {
 684         isa_register_ioport(dev, &d->io, io_base);
 685     }
 686
 687     return s;
 688 }
 689
 690 static void m48t59_init_common(M48t59State *s)
 691 {
 692     s->buffer = g_malloc0(s->size);
 693     if (s->model == 59) {
 694         s->alrm_timer = qemu_new_timer_ns(rtc_clock, &alarm_cb, s);
 695         s->wd_timer = qemu_new_timer_ns(vm_clock, &watchdog_cb, s);
 696     }
 697     qemu_get_timedate(&s->alarm, 0);
 698
 699     vmstate_register(NULL, -1, &vmstate_m48t59, s);
 700 }
 701
 702 static int m48t59_init_isa1(ISADevice *dev)
 703 {
 704     M48t59ISAState *d = DO_UPCAST(M48t59ISAState, busdev, dev);
 705     M48t59State *s = &d->state;
 706
 707     isa_init_irq(dev, &s->IRQ, 8);
 708     m48t59_init_common(s);
 709
 710     return 0;
 711 }
 712
 713 static int m48t59_init1(SysBusDevice *dev)
 714 {
 715     M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev);
 716     M48t59State *s = &d->state;
 717
 718     sysbus_init_irq(dev, &s->IRQ);
 719
 720     memory_region_init_io(&s->iomem, &nvram_ops, s, "m48t59.nvram", s->size);
 721     sysbus_init_mmio(dev, &s->iomem);
 722     m48t59_init_common(s);
 723
 724     return 0;
 725 }
 726
 727 static Property m48t59_isa_properties[] = {
 728     DEFINE_PROP_UINT32("size",    M48t59ISAState, state.size,    -1),
 729     DEFINE_PROP_UINT32("model",   M48t59ISAState, state.model,   -1),
 730     DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base,  0),
 731     DEFINE_PROP_END_OF_LIST(),
 732 };
 733
 734 static void m48t59_init_class_isa1(ObjectClass *klass, void *data)
 735 {
 736     DeviceClass *dc = DEVICE_CLASS(klass);
 737     ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
 738     ic->init = m48t59_init_isa1;
 739     dc->no_user = 1;
 740     dc->reset = m48t59_reset_isa;
 741     dc->props = m48t59_isa_properties;
 742 }
 743
 744 static TypeInfo m48t59_isa_info = {
 745     .name          = "m48t59_isa",
 746     .parent        = TYPE_ISA_DEVICE,
 747     .instance_size = sizeof(M48t59ISAState),
 748     .class_init    = m48t59_init_class_isa1,
 749 };
 750
 751 static Property m48t59_properties[] = {
 752     DEFINE_PROP_UINT32("size",    M48t59SysBusState, state.size,    -1),
 753     DEFINE_PROP_UINT32("model",   M48t59SysBusState, state.model,   -1),
 754     DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base,  0),
 755     DEFINE_PROP_END_OF_LIST(),
 756 };
 757
 758 static void m48t59_class_init(ObjectClass *klass, void *data)
 759 {
 760     DeviceClass *dc = DEVICE_CLASS(klass);
 761     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 762
 763     k->init = m48t59_init1;
 764     dc->reset = m48t59_reset_sysbus;
 765     dc->props = m48t59_properties;
 766 }
 767
 768 static TypeInfo m48t59_info = {
 769     .name          = "m48t59",
 770     .parent        = TYPE_SYS_BUS_DEVICE,
 771     .instance_size = sizeof(M48t59SysBusState),
 772     .class_init    = m48t59_class_init,
 773 };
 774
 775 static void m48t59_register_types(void)
 776 {
 777     type_register_static(&m48t59_info);
 778     type_register_static(&m48t59_isa_info);
 779 }
 780
 781 type_init(m48t59_register_types)