target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21 #include <linux/kvm_para.h>
  22
  23 #include "qemu-common.h"
  24 #include "sysemu/sysemu.h"
  25 #include "sysemu/kvm.h"
  26 #include "kvm_i386.h"
  27 #include "cpu.h"
  28 #include "exec/gdbstub.h"
  29 #include "qemu/host-utils.h"
  30 #include "qemu/config-file.h"
  31 #include "hw/pc.h"
  32 #include "hw/apic.h"
  33 #include "exec/ioport.h"
  34 #include "hyperv.h"
  35 #include "hw/pci/pci.h"
  36
  37 //#define DEBUG_KVM
  38
  39 #ifdef DEBUG_KVM
  40 #define DPRINTF(fmt, ...) \
  41     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  42 #else
  43 #define DPRINTF(fmt, ...) \
  44     do { } while (0)
  45 #endif
  46
  47 #define MSR_KVM_WALL_CLOCK  0x11
  48 #define MSR_KVM_SYSTEM_TIME 0x12
  49
  50 #ifndef BUS_MCEERR_AR
  51 #define BUS_MCEERR_AR 4
  52 #endif
  53 #ifndef BUS_MCEERR_AO
  54 #define BUS_MCEERR_AO 5
  55 #endif
  56
  57 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  58     KVM_CAP_INFO(SET_TSS_ADDR),
  59     KVM_CAP_INFO(EXT_CPUID),
  60     KVM_CAP_INFO(MP_STATE),
  61     KVM_CAP_LAST_INFO
  62 };
  63
  64 static bool has_msr_star;
  65 static bool has_msr_hsave_pa;
  66 static bool has_msr_tsc_adjust;
  67 static bool has_msr_tsc_deadline;
  68 static bool has_msr_async_pf_en;
  69 static bool has_msr_pv_eoi_en;
  70 static bool has_msr_misc_enable;
  71 static int lm_capable_kernel;
  72
  73 bool kvm_allows_irq0_override(void)
  74 {
  75     return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
  76 }
  77
  78 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  79 {
  80     struct kvm_cpuid2 *cpuid;
  81     int r, size;
  82
  83     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  84     cpuid = (struct kvm_cpuid2 *)g_malloc0(size);
  85     cpuid->nent = max;
  86     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  87     if (r == 0 && cpuid->nent >= max) {
  88         r = -E2BIG;
  89     }
  90     if (r < 0) {
  91         if (r == -E2BIG) {
  92             g_free(cpuid);
  93             return NULL;
  94         } else {
  95             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  96                     strerror(-r));
  97             exit(1);
  98         }
  99     }
 100     return cpuid;
 101 }
 102
 103 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
 104  * for all entries.
 105  */
 106 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
 107 {
 108     struct kvm_cpuid2 *cpuid;
 109     int max = 1;
 110     while ((cpuid = try_get_cpuid(s, max)) == NULL) {
 111         max *= 2;
 112     }
 113     return cpuid;
 114 }
 115
 116 struct kvm_para_features {
 117     int cap;
 118     int feature;
 119 } para_features[] = {
 120     { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 121     { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 122     { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 123     { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
 124     { -1, -1 }
 125 };
 126
 127 static int get_para_features(KVMState *s)
 128 {
 129     int i, features = 0;
 130
 131     for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 132         if (kvm_check_extension(s, para_features[i].cap)) {
 133             features |= (1 << para_features[i].feature);
 134         }
 135     }
 136
 137     return features;
 138 }
 139
 140
 141 /* Returns the value for a specific register on the cpuid entry
 142  */
 143 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
 144 {
 145     uint32_t ret = 0;
 146     switch (reg) {
 147     case R_EAX:
 148         ret = entry->eax;
 149         break;
 150     case R_EBX:
 151         ret = entry->ebx;
 152         break;
 153     case R_ECX:
 154         ret = entry->ecx;
 155         break;
 156     case R_EDX:
 157         ret = entry->edx;
 158         break;
 159     }
 160     return ret;
 161 }
 162
 163 /* Find matching entry for function/index on kvm_cpuid2 struct
 164  */
 165 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
 166                                                  uint32_t function,
 167                                                  uint32_t index)
 168 {
 169     int i;
 170     for (i = 0; i < cpuid->nent; ++i) {
 171         if (cpuid->entries[i].function == function &&
 172             cpuid->entries[i].index == index) {
 173             return &cpuid->entries[i];
 174         }
 175     }
 176     /* not found: */
 177     return NULL;
 178 }
 179
 180 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
 181                                       uint32_t index, int reg)
 182 {
 183     struct kvm_cpuid2 *cpuid;
 184     uint32_t ret = 0;
 185     uint32_t cpuid_1_edx;
 186     bool found = false;
 187
 188     cpuid = get_supported_cpuid(s);
 189
 190     struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
 191     if (entry) {
 192         found = true;
 193         ret = cpuid_entry_get_reg(entry, reg);
 194     }
 195
 196     /* Fixups for the data returned by KVM, below */
 197
 198     if (function == 1 && reg == R_EDX) {
 199         /* KVM before 2.6.30 misreports the following features */
 200         ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 201     } else if (function == 1 && reg == R_ECX) {
 202         /* We can set the hypervisor flag, even if KVM does not return it on
 203          * GET_SUPPORTED_CPUID
 204          */
 205         ret |= CPUID_EXT_HYPERVISOR;
 206         /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
 207          * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
 208          * and the irqchip is in the kernel.
 209          */
 210         if (kvm_irqchip_in_kernel() &&
 211                 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
 212             ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
 213         }
 214
 215         /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
 216          * without the in-kernel irqchip
 217          */
 218         if (!kvm_irqchip_in_kernel()) {
 219             ret &= ~CPUID_EXT_X2APIC;
 220         }
 221     } else if (function == 0x80000001 && reg == R_EDX) {
 222         /* On Intel, kvm returns cpuid according to the Intel spec,
 223          * so add missing bits according to the AMD spec:
 224          */
 225         cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 226         ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
 227     }
 228
 229     g_free(cpuid);
 230
 231     /* fallback for older kernels */
 232     if ((function == KVM_CPUID_FEATURES) && !found) {
 233         ret = get_para_features(s);
 234     }
 235
 236     return ret;
 237 }
 238
 239 typedef struct HWPoisonPage {
 240     ram_addr_t ram_addr;
 241     QLIST_ENTRY(HWPoisonPage) list;
 242 } HWPoisonPage;
 243
 244 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
 245     QLIST_HEAD_INITIALIZER(hwpoison_page_list);
 246
 247 static void kvm_unpoison_all(void *param)
 248 {
 249     HWPoisonPage *page, *next_page;
 250
 251     QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
 252         QLIST_REMOVE(page, list);
 253         qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
 254         g_free(page);
 255     }
 256 }
 257
 258 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
 259 {
 260     HWPoisonPage *page;
 261
 262     QLIST_FOREACH(page, &hwpoison_page_list, list) {
 263         if (page->ram_addr == ram_addr) {
 264             return;
 265         }
 266     }
 267     page = g_malloc(sizeof(HWPoisonPage));
 268     page->ram_addr = ram_addr;
 269     QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
 270 }
 271
 272 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 273                                      int *max_banks)
 274 {
 275     int r;
 276
 277     r = kvm_check_extension(s, KVM_CAP_MCE);
 278     if (r > 0) {
 279         *max_banks = r;
 280         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 281     }
 282     return -ENOSYS;
 283 }
 284
 285 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
 286 {
 287     CPUX86State *env = &cpu->env;
 288     uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
 289                       MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
 290     uint64_t mcg_status = MCG_STATUS_MCIP;
 291
 292     if (code == BUS_MCEERR_AR) {
 293         status |= MCI_STATUS_AR | 0x134;
 294         mcg_status |= MCG_STATUS_EIPV;
 295     } else {
 296         status |= 0xc0;
 297         mcg_status |= MCG_STATUS_RIPV;
 298     }
 299     cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
 300                        (MCM_ADDR_PHYS << 6) | 0xc,
 301                        cpu_x86_support_mca_broadcast(env) ?
 302                        MCE_INJECT_BROADCAST : 0);
 303 }
 304
 305 static void hardware_memory_error(void)
 306 {
 307     fprintf(stderr, "Hardware memory error!\n");
 308     exit(1);
 309 }
 310
 311 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
 312 {
 313     X86CPU *cpu = X86_CPU(c);
 314     CPUX86State *env = &cpu->env;
 315     ram_addr_t ram_addr;
 316     hwaddr paddr;
 317
 318     if ((env->mcg_cap & MCG_SER_P) && addr
 319         && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
 320         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 321             !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
 322             fprintf(stderr, "Hardware memory error for memory used by "
 323                     "QEMU itself instead of guest system!\n");
 324             /* Hope we are lucky for AO MCE */
 325             if (code == BUS_MCEERR_AO) {
 326                 return 0;
 327             } else {
 328                 hardware_memory_error();
 329             }
 330         }
 331         kvm_hwpoison_page_add(ram_addr);
 332         kvm_mce_inject(cpu, paddr, code);
 333     } else {
 334         if (code == BUS_MCEERR_AO) {
 335             return 0;
 336         } else if (code == BUS_MCEERR_AR) {
 337             hardware_memory_error();
 338         } else {
 339             return 1;
 340         }
 341     }
 342     return 0;
 343 }
 344
 345 int kvm_arch_on_sigbus(int code, void *addr)
 346 {
 347     if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
 348         ram_addr_t ram_addr;
 349         hwaddr paddr;
 350
 351         /* Hope we are lucky for AO MCE */
 352         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 353             !kvm_physical_memory_addr_from_host(CPU(first_cpu)->kvm_state,
 354                                                 addr, &paddr)) {
 355             fprintf(stderr, "Hardware memory error for memory used by "
 356                     "QEMU itself instead of guest system!: %p\n", addr);
 357             return 0;
 358         }
 359         kvm_hwpoison_page_add(ram_addr);
 360         kvm_mce_inject(x86_env_get_cpu(first_cpu), paddr, code);
 361     } else {
 362         if (code == BUS_MCEERR_AO) {
 363             return 0;
 364         } else if (code == BUS_MCEERR_AR) {
 365             hardware_memory_error();
 366         } else {
 367             return 1;
 368         }
 369     }
 370     return 0;
 371 }
 372
 373 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
 374 {
 375     CPUX86State *env = &cpu->env;
 376
 377     if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
 378         unsigned int bank, bank_num = env->mcg_cap & 0xff;
 379         struct kvm_x86_mce mce;
 380
 381         env->exception_injected = -1;
 382
 383         /*
 384          * There must be at least one bank in use if an MCE is pending.
 385          * Find it and use its values for the event injection.
 386          */
 387         for (bank = 0; bank < bank_num; bank++) {
 388             if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
 389                 break;
 390             }
 391         }
 392         assert(bank < bank_num);
 393
 394         mce.bank = bank;
 395         mce.status = env->mce_banks[bank * 4 + 1];
 396         mce.mcg_status = env->mcg_status;
 397         mce.addr = env->mce_banks[bank * 4 + 2];
 398         mce.misc = env->mce_banks[bank * 4 + 3];
 399
 400         return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
 401     }
 402     return 0;
 403 }
 404
 405 static void cpu_update_state(void *opaque, int running, RunState state)
 406 {
 407     CPUX86State *env = opaque;
 408
 409     if (running) {
 410         env->tsc_valid = false;
 411     }
 412 }
 413
 414 int kvm_arch_init_vcpu(CPUState *cs)
 415 {
 416     struct {
 417         struct kvm_cpuid2 cpuid;
 418         struct kvm_cpuid_entry2 entries[100];
 419     } QEMU_PACKED cpuid_data;
 420     X86CPU *cpu = X86_CPU(cs);
 421     CPUX86State *env = &cpu->env;
 422     uint32_t limit, i, j, cpuid_i;
 423     uint32_t unused;
 424     struct kvm_cpuid_entry2 *c;
 425     uint32_t signature[3];
 426     int r;
 427
 428     cpuid_i = 0;
 429
 430     /* Paravirtualization CPUIDs */
 431     c = &cpuid_data.entries[cpuid_i++];
 432     memset(c, 0, sizeof(*c));
 433     c->function = KVM_CPUID_SIGNATURE;
 434     if (!hyperv_enabled()) {
 435         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 436         c->eax = 0;
 437     } else {
 438         memcpy(signature, "Microsoft Hv", 12);
 439         c->eax = HYPERV_CPUID_MIN;
 440     }
 441     c->ebx = signature[0];
 442     c->ecx = signature[1];
 443     c->edx = signature[2];
 444
 445     c = &cpuid_data.entries[cpuid_i++];
 446     memset(c, 0, sizeof(*c));
 447     c->function = KVM_CPUID_FEATURES;
 448     c->eax = env->cpuid_kvm_features;
 449
 450     if (hyperv_enabled()) {
 451         memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
 452         c->eax = signature[0];
 453
 454         c = &cpuid_data.entries[cpuid_i++];
 455         memset(c, 0, sizeof(*c));
 456         c->function = HYPERV_CPUID_VERSION;
 457         c->eax = 0x00001bbc;
 458         c->ebx = 0x00060001;
 459
 460         c = &cpuid_data.entries[cpuid_i++];
 461         memset(c, 0, sizeof(*c));
 462         c->function = HYPERV_CPUID_FEATURES;
 463         if (hyperv_relaxed_timing_enabled()) {
 464             c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
 465         }
 466         if (hyperv_vapic_recommended()) {
 467             c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
 468             c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
 469         }
 470
 471         c = &cpuid_data.entries[cpuid_i++];
 472         memset(c, 0, sizeof(*c));
 473         c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
 474         if (hyperv_relaxed_timing_enabled()) {
 475             c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
 476         }
 477         if (hyperv_vapic_recommended()) {
 478             c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
 479         }
 480         c->ebx = hyperv_get_spinlock_retries();
 481
 482         c = &cpuid_data.entries[cpuid_i++];
 483         memset(c, 0, sizeof(*c));
 484         c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
 485         c->eax = 0x40;
 486         c->ebx = 0x40;
 487
 488         c = &cpuid_data.entries[cpuid_i++];
 489         memset(c, 0, sizeof(*c));
 490         c->function = KVM_CPUID_SIGNATURE_NEXT;
 491         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 492         c->eax = 0;
 493         c->ebx = signature[0];
 494         c->ecx = signature[1];
 495         c->edx = signature[2];
 496     }
 497
 498     has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
 499
 500     has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
 501
 502     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 503
 504     for (i = 0; i <= limit; i++) {
 505         c = &cpuid_data.entries[cpuid_i++];
 506
 507         switch (i) {
 508         case 2: {
 509             /* Keep reading function 2 till all the input is received */
 510             int times;
 511
 512             c->function = i;
 513             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 514                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 515             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 516             times = c->eax & 0xff;
 517
 518             for (j = 1; j < times; ++j) {
 519                 c = &cpuid_data.entries[cpuid_i++];
 520                 c->function = i;
 521                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 522                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 523             }
 524             break;
 525         }
 526         case 4:
 527         case 0xb:
 528         case 0xd:
 529             for (j = 0; ; j++) {
 530                 if (i == 0xd && j == 64) {
 531                     break;
 532                 }
 533                 c->function = i;
 534                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 535                 c->index = j;
 536                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 537
 538                 if (i == 4 && c->eax == 0) {
 539                     break;
 540                 }
 541                 if (i == 0xb && !(c->ecx & 0xff00)) {
 542                     break;
 543                 }
 544                 if (i == 0xd && c->eax == 0) {
 545                     continue;
 546                 }
 547                 c = &cpuid_data.entries[cpuid_i++];
 548             }
 549             break;
 550         default:
 551             c->function = i;
 552             c->flags = 0;
 553             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 554             break;
 555         }
 556     }
 557     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 558
 559     for (i = 0x80000000; i <= limit; i++) {
 560         c = &cpuid_data.entries[cpuid_i++];
 561
 562         c->function = i;
 563         c->flags = 0;
 564         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 565     }
 566
 567     /* Call Centaur's CPUID instructions they are supported. */
 568     if (env->cpuid_xlevel2 > 0) {
 569         cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
 570
 571         for (i = 0xC0000000; i <= limit; i++) {
 572             c = &cpuid_data.entries[cpuid_i++];
 573
 574             c->function = i;
 575             c->flags = 0;
 576             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 577         }
 578     }
 579
 580     cpuid_data.cpuid.nent = cpuid_i;
 581
 582     if (((env->cpuid_version >> 8)&0xF) >= 6
 583         && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
 584         && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
 585         uint64_t mcg_cap;
 586         int banks;
 587         int ret;
 588
 589         ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
 590         if (ret < 0) {
 591             fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
 592             return ret;
 593         }
 594
 595         if (banks > MCE_BANKS_DEF) {
 596             banks = MCE_BANKS_DEF;
 597         }
 598         mcg_cap &= MCE_CAP_DEF;
 599         mcg_cap |= banks;
 600         ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &mcg_cap);
 601         if (ret < 0) {
 602             fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
 603             return ret;
 604         }
 605
 606         env->mcg_cap = mcg_cap;
 607     }
 608
 609     qemu_add_vm_change_state_handler(cpu_update_state, env);
 610
 611     cpuid_data.cpuid.padding = 0;
 612     r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
 613     if (r) {
 614         return r;
 615     }
 616
 617     r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL);
 618     if (r && env->tsc_khz) {
 619         r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz);
 620         if (r < 0) {
 621             fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
 622             return r;
 623         }
 624     }
 625
 626     if (kvm_has_xsave()) {
 627         env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
 628     }
 629
 630     return 0;
 631 }
 632
 633 void kvm_arch_reset_vcpu(CPUState *cs)
 634 {
 635     X86CPU *cpu = X86_CPU(cs);
 636     CPUX86State *env = &cpu->env;
 637
 638     env->exception_injected = -1;
 639     env->interrupt_injected = -1;
 640     env->xcr0 = 1;
 641     if (kvm_irqchip_in_kernel()) {
 642         env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
 643                                           KVM_MP_STATE_UNINITIALIZED;
 644     } else {
 645         env->mp_state = KVM_MP_STATE_RUNNABLE;
 646     }
 647 }
 648
 649 static int kvm_get_supported_msrs(KVMState *s)
 650 {
 651     static int kvm_supported_msrs;
 652     int ret = 0;
 653
 654     /* first time */
 655     if (kvm_supported_msrs == 0) {
 656         struct kvm_msr_list msr_list, *kvm_msr_list;
 657
 658         kvm_supported_msrs = -1;
 659
 660         /* Obtain MSR list from KVM.  These are the MSRs that we must
 661          * save/restore */
 662         msr_list.nmsrs = 0;
 663         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
 664         if (ret < 0 && ret != -E2BIG) {
 665             return ret;
 666         }
 667         /* Old kernel modules had a bug and could write beyond the provided
 668            memory. Allocate at least a safe amount of 1K. */
 669         kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
 670                                               msr_list.nmsrs *
 671                                               sizeof(msr_list.indices[0])));
 672
 673         kvm_msr_list->nmsrs = msr_list.nmsrs;
 674         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 675         if (ret >= 0) {
 676             int i;
 677
 678             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 679                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 680                     has_msr_star = true;
 681                     continue;
 682                 }
 683                 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
 684                     has_msr_hsave_pa = true;
 685                     continue;
 686                 }
 687                 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
 688                     has_msr_tsc_adjust = true;
 689                     continue;
 690                 }
 691                 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
 692                     has_msr_tsc_deadline = true;
 693                     continue;
 694                 }
 695                 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
 696                     has_msr_misc_enable = true;
 697                     continue;
 698                 }
 699             }
 700         }
 701
 702         g_free(kvm_msr_list);
 703     }
 704
 705     return ret;
 706 }
 707
 708 int kvm_arch_init(KVMState *s)
 709 {
 710     QemuOptsList *list = qemu_find_opts("machine");
 711     uint64_t identity_base = 0xfffbc000;
 712     uint64_t shadow_mem;
 713     int ret;
 714     struct utsname utsname;
 715
 716     ret = kvm_get_supported_msrs(s);
 717     if (ret < 0) {
 718         return ret;
 719     }
 720
 721     uname(&utsname);
 722     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
 723
 724     /*
 725      * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
 726      * In order to use vm86 mode, an EPT identity map and a TSS  are needed.
 727      * Since these must be part of guest physical memory, we need to allocate
 728      * them, both by setting their start addresses in the kernel and by
 729      * creating a corresponding e820 entry. We need 4 pages before the BIOS.
 730      *
 731      * Older KVM versions may not support setting the identity map base. In
 732      * that case we need to stick with the default, i.e. a 256K maximum BIOS
 733      * size.
 734      */
 735     if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 736         /* Allows up to 16M BIOSes. */
 737         identity_base = 0xfeffc000;
 738
 739         ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
 740         if (ret < 0) {
 741             return ret;
 742         }
 743     }
 744
 745     /* Set TSS base one page after EPT identity map. */
 746     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
 747     if (ret < 0) {
 748         return ret;
 749     }
 750
 751     /* Tell fw_cfg to notify the BIOS to reserve the range. */
 752     ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
 753     if (ret < 0) {
 754         fprintf(stderr, "e820_add_entry() table is full\n");
 755         return ret;
 756     }
 757     qemu_register_reset(kvm_unpoison_all, NULL);
 758
 759     if (!QTAILQ_EMPTY(&list->head)) {
 760         shadow_mem = qemu_opt_get_size(QTAILQ_FIRST(&list->head),
 761                                        "kvm_shadow_mem", -1);
 762         if (shadow_mem != -1) {
 763             shadow_mem /= 4096;
 764             ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
 765             if (ret < 0) {
 766                 return ret;
 767             }
 768         }
 769     }
 770     return 0;
 771 }
 772
 773 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 774 {
 775     lhs->selector = rhs->selector;
 776     lhs->base = rhs->base;
 777     lhs->limit = rhs->limit;
 778     lhs->type = 3;
 779     lhs->present = 1;
 780     lhs->dpl = 3;
 781     lhs->db = 0;
 782     lhs->s = 1;
 783     lhs->l = 0;
 784     lhs->g = 0;
 785     lhs->avl = 0;
 786     lhs->unusable = 0;
 787 }
 788
 789 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 790 {
 791     unsigned flags = rhs->flags;
 792     lhs->selector = rhs->selector;
 793     lhs->base = rhs->base;
 794     lhs->limit = rhs->limit;
 795     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 796     lhs->present = (flags & DESC_P_MASK) != 0;
 797     lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
 798     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 799     lhs->s = (flags & DESC_S_MASK) != 0;
 800     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 801     lhs->g = (flags & DESC_G_MASK) != 0;
 802     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 803     lhs->unusable = 0;
 804     lhs->padding = 0;
 805 }
 806
 807 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 808 {
 809     lhs->selector = rhs->selector;
 810     lhs->base = rhs->base;
 811     lhs->limit = rhs->limit;
 812     lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
 813                  (rhs->present * DESC_P_MASK) |
 814                  (rhs->dpl << DESC_DPL_SHIFT) |
 815                  (rhs->db << DESC_B_SHIFT) |
 816                  (rhs->s * DESC_S_MASK) |
 817                  (rhs->l << DESC_L_SHIFT) |
 818                  (rhs->g * DESC_G_MASK) |
 819                  (rhs->avl * DESC_AVL_MASK);
 820 }
 821
 822 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 823 {
 824     if (set) {
 825         *kvm_reg = *qemu_reg;
 826     } else {
 827         *qemu_reg = *kvm_reg;
 828     }
 829 }
 830
 831 static int kvm_getput_regs(X86CPU *cpu, int set)
 832 {
 833     CPUX86State *env = &cpu->env;
 834     struct kvm_regs regs;
 835     int ret = 0;
 836
 837     if (!set) {
 838         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
 839         if (ret < 0) {
 840             return ret;
 841         }
 842     }
 843
 844     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 845     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 846     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 847     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 848     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 849     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 850     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 851     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 852 #ifdef TARGET_X86_64
 853     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 854     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 855     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 856     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 857     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 858     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 859     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 860     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 861 #endif
 862
 863     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 864     kvm_getput_reg(&regs.rip, &env->eip, set);
 865
 866     if (set) {
 867         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
 868     }
 869
 870     return ret;
 871 }
 872
 873 static int kvm_put_fpu(X86CPU *cpu)
 874 {
 875     CPUX86State *env = &cpu->env;
 876     struct kvm_fpu fpu;
 877     int i;
 878
 879     memset(&fpu, 0, sizeof fpu);
 880     fpu.fsw = env->fpus & ~(7 << 11);
 881     fpu.fsw |= (env->fpstt & 7) << 11;
 882     fpu.fcw = env->fpuc;
 883     fpu.last_opcode = env->fpop;
 884     fpu.last_ip = env->fpip;
 885     fpu.last_dp = env->fpdp;
 886     for (i = 0; i < 8; ++i) {
 887         fpu.ftwx |= (!env->fptags[i]) << i;
 888     }
 889     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 890     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 891     fpu.mxcsr = env->mxcsr;
 892
 893     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
 894 }
 895
 896 #define XSAVE_FCW_FSW     0
 897 #define XSAVE_FTW_FOP     1
 898 #define XSAVE_CWD_RIP     2
 899 #define XSAVE_CWD_RDP     4
 900 #define XSAVE_MXCSR       6
 901 #define XSAVE_ST_SPACE    8
 902 #define XSAVE_XMM_SPACE   40
 903 #define XSAVE_XSTATE_BV   128
 904 #define XSAVE_YMMH_SPACE  144
 905
 906 static int kvm_put_xsave(X86CPU *cpu)
 907 {
 908     CPUX86State *env = &cpu->env;
 909     struct kvm_xsave* xsave = env->kvm_xsave_buf;
 910     uint16_t cwd, swd, twd;
 911     int i, r;
 912
 913     if (!kvm_has_xsave()) {
 914         return kvm_put_fpu(cpu);
 915     }
 916
 917     memset(xsave, 0, sizeof(struct kvm_xsave));
 918     twd = 0;
 919     swd = env->fpus & ~(7 << 11);
 920     swd |= (env->fpstt & 7) << 11;
 921     cwd = env->fpuc;
 922     for (i = 0; i < 8; ++i) {
 923         twd |= (!env->fptags[i]) << i;
 924     }
 925     xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
 926     xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
 927     memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
 928     memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
 929     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 930             sizeof env->fpregs);
 931     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 932             sizeof env->xmm_regs);
 933     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 934     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 935     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 936             sizeof env->ymmh_regs);
 937     r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
 938     return r;
 939 }
 940
 941 static int kvm_put_xcrs(X86CPU *cpu)
 942 {
 943     CPUX86State *env = &cpu->env;
 944     struct kvm_xcrs xcrs;
 945
 946     if (!kvm_has_xcrs()) {
 947         return 0;
 948     }
 949
 950     xcrs.nr_xcrs = 1;
 951     xcrs.flags = 0;
 952     xcrs.xcrs[0].xcr = 0;
 953     xcrs.xcrs[0].value = env->xcr0;
 954     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
 955 }
 956
 957 static int kvm_put_sregs(X86CPU *cpu)
 958 {
 959     CPUX86State *env = &cpu->env;
 960     struct kvm_sregs sregs;
 961
 962     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 963     if (env->interrupt_injected >= 0) {
 964         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 965                 (uint64_t)1 << (env->interrupt_injected % 64);
 966     }
 967
 968     if ((env->eflags & VM_MASK)) {
 969         set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 970         set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 971         set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 972         set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 973         set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 974         set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 975     } else {
 976         set_seg(&sregs.cs, &env->segs[R_CS]);
 977         set_seg(&sregs.ds, &env->segs[R_DS]);
 978         set_seg(&sregs.es, &env->segs[R_ES]);
 979         set_seg(&sregs.fs, &env->segs[R_FS]);
 980         set_seg(&sregs.gs, &env->segs[R_GS]);
 981         set_seg(&sregs.ss, &env->segs[R_SS]);
 982     }
 983
 984     set_seg(&sregs.tr, &env->tr);
 985     set_seg(&sregs.ldt, &env->ldt);
 986
 987     sregs.idt.limit = env->idt.limit;
 988     sregs.idt.base = env->idt.base;
 989     memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
 990     sregs.gdt.limit = env->gdt.limit;
 991     sregs.gdt.base = env->gdt.base;
 992     memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
 993
 994     sregs.cr0 = env->cr[0];
 995     sregs.cr2 = env->cr[2];
 996     sregs.cr3 = env->cr[3];
 997     sregs.cr4 = env->cr[4];
 998
 999     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
1000     sregs.apic_base = cpu_get_apic_base(env->apic_state);
1001
1002     sregs.efer = env->efer;
1003
1004     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1005 }
1006
1007 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1008                               uint32_t index, uint64_t value)
1009 {
1010     entry->index = index;
1011     entry->data = value;
1012 }
1013
1014 static int kvm_put_msrs(X86CPU *cpu, int level)
1015 {
1016     CPUX86State *env = &cpu->env;
1017     struct {
1018         struct kvm_msrs info;
1019         struct kvm_msr_entry entries[100];
1020     } msr_data;
1021     struct kvm_msr_entry *msrs = msr_data.entries;
1022     int n = 0;
1023
1024     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1025     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1026     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1027     kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1028     if (has_msr_star) {
1029         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1030     }
1031     if (has_msr_hsave_pa) {
1032         kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1033     }
1034     if (has_msr_tsc_adjust) {
1035         kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1036     }
1037     if (has_msr_tsc_deadline) {
1038         kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1039     }
1040     if (has_msr_misc_enable) {
1041         kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1042                           env->msr_ia32_misc_enable);
1043     }
1044 #ifdef TARGET_X86_64
1045     if (lm_capable_kernel) {
1046         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1047         kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1048         kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1049         kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1050     }
1051 #endif
1052     if (level == KVM_PUT_FULL_STATE) {
1053         /*
1054          * KVM is yet unable to synchronize TSC values of multiple VCPUs on
1055          * writeback. Until this is fixed, we only write the offset to SMP
1056          * guests after migration, desynchronizing the VCPUs, but avoiding
1057          * huge jump-backs that would occur without any writeback at all.
1058          */
1059         if (smp_cpus == 1 || env->tsc != 0) {
1060             kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1061         }
1062     }
1063     /*
1064      * The following paravirtual MSRs have side effects on the guest or are
1065      * too heavy for normal writeback. Limit them to reset or full state
1066      * updates.
1067      */
1068     if (level >= KVM_PUT_RESET_STATE) {
1069         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1070                           env->system_time_msr);
1071         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1072         if (has_msr_async_pf_en) {
1073             kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1074                               env->async_pf_en_msr);
1075         }
1076         if (has_msr_pv_eoi_en) {
1077             kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1078                               env->pv_eoi_en_msr);
1079         }
1080         if (hyperv_hypercall_available()) {
1081             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID, 0);
1082             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL, 0);
1083         }
1084         if (hyperv_vapic_recommended()) {
1085             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, 0);
1086         }
1087     }
1088     if (env->mcg_cap) {
1089         int i;
1090
1091         kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1092         kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1093         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1094             kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1095         }
1096     }
1097
1098     msr_data.info.nmsrs = n;
1099
1100     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1101
1102 }
1103
1104
1105 static int kvm_get_fpu(X86CPU *cpu)
1106 {
1107     CPUX86State *env = &cpu->env;
1108     struct kvm_fpu fpu;
1109     int i, ret;
1110
1111     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1112     if (ret < 0) {
1113         return ret;
1114     }
1115
1116     env->fpstt = (fpu.fsw >> 11) & 7;
1117     env->fpus = fpu.fsw;
1118     env->fpuc = fpu.fcw;
1119     env->fpop = fpu.last_opcode;
1120     env->fpip = fpu.last_ip;
1121     env->fpdp = fpu.last_dp;
1122     for (i = 0; i < 8; ++i) {
1123         env->fptags[i] = !((fpu.ftwx >> i) & 1);
1124     }
1125     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1126     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1127     env->mxcsr = fpu.mxcsr;
1128
1129     return 0;
1130 }
1131
1132 static int kvm_get_xsave(X86CPU *cpu)
1133 {
1134     CPUX86State *env = &cpu->env;
1135     struct kvm_xsave* xsave = env->kvm_xsave_buf;
1136     int ret, i;
1137     uint16_t cwd, swd, twd;
1138
1139     if (!kvm_has_xsave()) {
1140         return kvm_get_fpu(cpu);
1141     }
1142
1143     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1144     if (ret < 0) {
1145         return ret;
1146     }
1147
1148     cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1149     swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1150     twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1151     env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1152     env->fpstt = (swd >> 11) & 7;
1153     env->fpus = swd;
1154     env->fpuc = cwd;
1155     for (i = 0; i < 8; ++i) {
1156         env->fptags[i] = !((twd >> i) & 1);
1157     }
1158     memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1159     memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1160     env->mxcsr = xsave->region[XSAVE_MXCSR];
1161     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1162             sizeof env->fpregs);
1163     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1164             sizeof env->xmm_regs);
1165     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1166     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1167             sizeof env->ymmh_regs);
1168     return 0;
1169 }
1170
1171 static int kvm_get_xcrs(X86CPU *cpu)
1172 {
1173     CPUX86State *env = &cpu->env;
1174     int i, ret;
1175     struct kvm_xcrs xcrs;
1176
1177     if (!kvm_has_xcrs()) {
1178         return 0;
1179     }
1180
1181     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1182     if (ret < 0) {
1183         return ret;
1184     }
1185
1186     for (i = 0; i < xcrs.nr_xcrs; i++) {
1187         /* Only support xcr0 now */
1188         if (xcrs.xcrs[0].xcr == 0) {
1189             env->xcr0 = xcrs.xcrs[0].value;
1190             break;
1191         }
1192     }
1193     return 0;
1194 }
1195
1196 static int kvm_get_sregs(X86CPU *cpu)
1197 {
1198     CPUX86State *env = &cpu->env;
1199     struct kvm_sregs sregs;
1200     uint32_t hflags;
1201     int bit, i, ret;
1202
1203     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1204     if (ret < 0) {
1205         return ret;
1206     }
1207
1208     /* There can only be one pending IRQ set in the bitmap at a time, so try
1209        to find it and save its number instead (-1 for none). */
1210     env->interrupt_injected = -1;
1211     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1212         if (sregs.interrupt_bitmap[i]) {
1213             bit = ctz64(sregs.interrupt_bitmap[i]);
1214             env->interrupt_injected = i * 64 + bit;
1215             break;
1216         }
1217     }
1218
1219     get_seg(&env->segs[R_CS], &sregs.cs);
1220     get_seg(&env->segs[R_DS], &sregs.ds);
1221     get_seg(&env->segs[R_ES], &sregs.es);
1222     get_seg(&env->segs[R_FS], &sregs.fs);
1223     get_seg(&env->segs[R_GS], &sregs.gs);
1224     get_seg(&env->segs[R_SS], &sregs.ss);
1225
1226     get_seg(&env->tr, &sregs.tr);
1227     get_seg(&env->ldt, &sregs.ldt);
1228
1229     env->idt.limit = sregs.idt.limit;
1230     env->idt.base = sregs.idt.base;
1231     env->gdt.limit = sregs.gdt.limit;
1232     env->gdt.base = sregs.gdt.base;
1233
1234     env->cr[0] = sregs.cr0;
1235     env->cr[2] = sregs.cr2;
1236     env->cr[3] = sregs.cr3;
1237     env->cr[4] = sregs.cr4;
1238
1239     env->efer = sregs.efer;
1240
1241     /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1242
1243 #define HFLAG_COPY_MASK \
1244     ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1245        HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1246        HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1247        HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1248
1249     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1250     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1251     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1252                 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1253     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1254     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1255                 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1256
1257     if (env->efer & MSR_EFER_LMA) {
1258         hflags |= HF_LMA_MASK;
1259     }
1260
1261     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1262         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1263     } else {
1264         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1265                     (DESC_B_SHIFT - HF_CS32_SHIFT);
1266         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1267                     (DESC_B_SHIFT - HF_SS32_SHIFT);
1268         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1269             !(hflags & HF_CS32_MASK)) {
1270             hflags |= HF_ADDSEG_MASK;
1271         } else {
1272             hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1273                         env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1274         }
1275     }
1276     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1277
1278     return 0;
1279 }
1280
1281 static int kvm_get_msrs(X86CPU *cpu)
1282 {
1283     CPUX86State *env = &cpu->env;
1284     struct {
1285         struct kvm_msrs info;
1286         struct kvm_msr_entry entries[100];
1287     } msr_data;
1288     struct kvm_msr_entry *msrs = msr_data.entries;
1289     int ret, i, n;
1290
1291     n = 0;
1292     msrs[n++].index = MSR_IA32_SYSENTER_CS;
1293     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1294     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1295     msrs[n++].index = MSR_PAT;
1296     if (has_msr_star) {
1297         msrs[n++].index = MSR_STAR;
1298     }
1299     if (has_msr_hsave_pa) {
1300         msrs[n++].index = MSR_VM_HSAVE_PA;
1301     }
1302     if (has_msr_tsc_adjust) {
1303         msrs[n++].index = MSR_TSC_ADJUST;
1304     }
1305     if (has_msr_tsc_deadline) {
1306         msrs[n++].index = MSR_IA32_TSCDEADLINE;
1307     }
1308     if (has_msr_misc_enable) {
1309         msrs[n++].index = MSR_IA32_MISC_ENABLE;
1310     }
1311
1312     if (!env->tsc_valid) {
1313         msrs[n++].index = MSR_IA32_TSC;
1314         env->tsc_valid = !runstate_is_running();
1315     }
1316
1317 #ifdef TARGET_X86_64
1318     if (lm_capable_kernel) {
1319         msrs[n++].index = MSR_CSTAR;
1320         msrs[n++].index = MSR_KERNELGSBASE;
1321         msrs[n++].index = MSR_FMASK;
1322         msrs[n++].index = MSR_LSTAR;
1323     }
1324 #endif
1325     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1326     msrs[n++].index = MSR_KVM_WALL_CLOCK;
1327     if (has_msr_async_pf_en) {
1328         msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1329     }
1330     if (has_msr_pv_eoi_en) {
1331         msrs[n++].index = MSR_KVM_PV_EOI_EN;
1332     }
1333
1334     if (env->mcg_cap) {
1335         msrs[n++].index = MSR_MCG_STATUS;
1336         msrs[n++].index = MSR_MCG_CTL;
1337         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1338             msrs[n++].index = MSR_MC0_CTL + i;
1339         }
1340     }
1341
1342     msr_data.info.nmsrs = n;
1343     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
1344     if (ret < 0) {
1345         return ret;
1346     }
1347
1348     for (i = 0; i < ret; i++) {
1349         switch (msrs[i].index) {
1350         case MSR_IA32_SYSENTER_CS:
1351             env->sysenter_cs = msrs[i].data;
1352             break;
1353         case MSR_IA32_SYSENTER_ESP:
1354             env->sysenter_esp = msrs[i].data;
1355             break;
1356         case MSR_IA32_SYSENTER_EIP:
1357             env->sysenter_eip = msrs[i].data;
1358             break;
1359         case MSR_PAT:
1360             env->pat = msrs[i].data;
1361             break;
1362         case MSR_STAR:
1363             env->star = msrs[i].data;
1364             break;
1365 #ifdef TARGET_X86_64
1366         case MSR_CSTAR:
1367             env->cstar = msrs[i].data;
1368             break;
1369         case MSR_KERNELGSBASE:
1370             env->kernelgsbase = msrs[i].data;
1371             break;
1372         case MSR_FMASK:
1373             env->fmask = msrs[i].data;
1374             break;
1375         case MSR_LSTAR:
1376             env->lstar = msrs[i].data;
1377             break;
1378 #endif
1379         case MSR_IA32_TSC:
1380             env->tsc = msrs[i].data;
1381             break;
1382         case MSR_TSC_ADJUST:
1383             env->tsc_adjust = msrs[i].data;
1384             break;
1385         case MSR_IA32_TSCDEADLINE:
1386             env->tsc_deadline = msrs[i].data;
1387             break;
1388         case MSR_VM_HSAVE_PA:
1389             env->vm_hsave = msrs[i].data;
1390             break;
1391         case MSR_KVM_SYSTEM_TIME:
1392             env->system_time_msr = msrs[i].data;
1393             break;
1394         case MSR_KVM_WALL_CLOCK:
1395             env->wall_clock_msr = msrs[i].data;
1396             break;
1397         case MSR_MCG_STATUS:
1398             env->mcg_status = msrs[i].data;
1399             break;
1400         case MSR_MCG_CTL:
1401             env->mcg_ctl = msrs[i].data;
1402             break;
1403         case MSR_IA32_MISC_ENABLE:
1404             env->msr_ia32_misc_enable = msrs[i].data;
1405             break;
1406         default:
1407             if (msrs[i].index >= MSR_MC0_CTL &&
1408                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1409                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1410             }
1411             break;
1412         case MSR_KVM_ASYNC_PF_EN:
1413             env->async_pf_en_msr = msrs[i].data;
1414             break;
1415         case MSR_KVM_PV_EOI_EN:
1416             env->pv_eoi_en_msr = msrs[i].data;
1417             break;
1418         }
1419     }
1420
1421     return 0;
1422 }
1423
1424 static int kvm_put_mp_state(X86CPU *cpu)
1425 {
1426     struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
1427
1428     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
1429 }
1430
1431 static int kvm_get_mp_state(X86CPU *cpu)
1432 {
1433     CPUX86State *env = &cpu->env;
1434     struct kvm_mp_state mp_state;
1435     int ret;
1436
1437     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MP_STATE, &mp_state);
1438     if (ret < 0) {
1439         return ret;
1440     }
1441     env->mp_state = mp_state.mp_state;
1442     if (kvm_irqchip_in_kernel()) {
1443         env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1444     }
1445     return 0;
1446 }
1447
1448 static int kvm_get_apic(X86CPU *cpu)
1449 {
1450     CPUX86State *env = &cpu->env;
1451     DeviceState *apic = env->apic_state;
1452     struct kvm_lapic_state kapic;
1453     int ret;
1454
1455     if (apic && kvm_irqchip_in_kernel()) {
1456         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
1457         if (ret < 0) {
1458             return ret;
1459         }
1460
1461         kvm_get_apic_state(apic, &kapic);
1462     }
1463     return 0;
1464 }
1465
1466 static int kvm_put_apic(X86CPU *cpu)
1467 {
1468     CPUX86State *env = &cpu->env;
1469     DeviceState *apic = env->apic_state;
1470     struct kvm_lapic_state kapic;
1471
1472     if (apic && kvm_irqchip_in_kernel()) {
1473         kvm_put_apic_state(apic, &kapic);
1474
1475         return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
1476     }
1477     return 0;
1478 }
1479
1480 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
1481 {
1482     CPUX86State *env = &cpu->env;
1483     struct kvm_vcpu_events events;
1484
1485     if (!kvm_has_vcpu_events()) {
1486         return 0;
1487     }
1488
1489     events.exception.injected = (env->exception_injected >= 0);
1490     events.exception.nr = env->exception_injected;
1491     events.exception.has_error_code = env->has_error_code;
1492     events.exception.error_code = env->error_code;
1493     events.exception.pad = 0;
1494
1495     events.interrupt.injected = (env->interrupt_injected >= 0);
1496     events.interrupt.nr = env->interrupt_injected;
1497     events.interrupt.soft = env->soft_interrupt;
1498
1499     events.nmi.injected = env->nmi_injected;
1500     events.nmi.pending = env->nmi_pending;
1501     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1502     events.nmi.pad = 0;
1503
1504     events.sipi_vector = env->sipi_vector;
1505
1506     events.flags = 0;
1507     if (level >= KVM_PUT_RESET_STATE) {
1508         events.flags |=
1509             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1510     }
1511
1512     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
1513 }
1514
1515 static int kvm_get_vcpu_events(X86CPU *cpu)
1516 {
1517     CPUX86State *env = &cpu->env;
1518     struct kvm_vcpu_events events;
1519     int ret;
1520
1521     if (!kvm_has_vcpu_events()) {
1522         return 0;
1523     }
1524
1525     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
1526     if (ret < 0) {
1527        return ret;
1528     }
1529     env->exception_injected =
1530        events.exception.injected ? events.exception.nr : -1;
1531     env->has_error_code = events.exception.has_error_code;
1532     env->error_code = events.exception.error_code;
1533
1534     env->interrupt_injected =
1535         events.interrupt.injected ? events.interrupt.nr : -1;
1536     env->soft_interrupt = events.interrupt.soft;
1537
1538     env->nmi_injected = events.nmi.injected;
1539     env->nmi_pending = events.nmi.pending;
1540     if (events.nmi.masked) {
1541         env->hflags2 |= HF2_NMI_MASK;
1542     } else {
1543         env->hflags2 &= ~HF2_NMI_MASK;
1544     }
1545
1546     env->sipi_vector = events.sipi_vector;
1547
1548     return 0;
1549 }
1550
1551 static int kvm_guest_debug_workarounds(X86CPU *cpu)
1552 {
1553     CPUX86State *env = &cpu->env;
1554     int ret = 0;
1555     unsigned long reinject_trap = 0;
1556
1557     if (!kvm_has_vcpu_events()) {
1558         if (env->exception_injected == 1) {
1559             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1560         } else if (env->exception_injected == 3) {
1561             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1562         }
1563         env->exception_injected = -1;
1564     }
1565
1566     /*
1567      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1568      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1569      * by updating the debug state once again if single-stepping is on.
1570      * Another reason to call kvm_update_guest_debug here is a pending debug
1571      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1572      * reinject them via SET_GUEST_DEBUG.
1573      */
1574     if (reinject_trap ||
1575         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1576         ret = kvm_update_guest_debug(env, reinject_trap);
1577     }
1578     return ret;
1579 }
1580
1581 static int kvm_put_debugregs(X86CPU *cpu)
1582 {
1583     CPUX86State *env = &cpu->env;
1584     struct kvm_debugregs dbgregs;
1585     int i;
1586
1587     if (!kvm_has_debugregs()) {
1588         return 0;
1589     }
1590
1591     for (i = 0; i < 4; i++) {
1592         dbgregs.db[i] = env->dr[i];
1593     }
1594     dbgregs.dr6 = env->dr[6];
1595     dbgregs.dr7 = env->dr[7];
1596     dbgregs.flags = 0;
1597
1598     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
1599 }
1600
1601 static int kvm_get_debugregs(X86CPU *cpu)
1602 {
1603     CPUX86State *env = &cpu->env;
1604     struct kvm_debugregs dbgregs;
1605     int i, ret;
1606
1607     if (!kvm_has_debugregs()) {
1608         return 0;
1609     }
1610
1611     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
1612     if (ret < 0) {
1613         return ret;
1614     }
1615     for (i = 0; i < 4; i++) {
1616         env->dr[i] = dbgregs.db[i];
1617     }
1618     env->dr[4] = env->dr[6] = dbgregs.dr6;
1619     env->dr[5] = env->dr[7] = dbgregs.dr7;
1620
1621     return 0;
1622 }
1623
1624 int kvm_arch_put_registers(CPUState *cpu, int level)
1625 {
1626     X86CPU *x86_cpu = X86_CPU(cpu);
1627     int ret;
1628
1629     assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
1630
1631     ret = kvm_getput_regs(x86_cpu, 1);
1632     if (ret < 0) {
1633         return ret;
1634     }
1635     ret = kvm_put_xsave(x86_cpu);
1636     if (ret < 0) {
1637         return ret;
1638     }
1639     ret = kvm_put_xcrs(x86_cpu);
1640     if (ret < 0) {
1641         return ret;
1642     }
1643     ret = kvm_put_sregs(x86_cpu);
1644     if (ret < 0) {
1645         return ret;
1646     }
1647     /* must be before kvm_put_msrs */
1648     ret = kvm_inject_mce_oldstyle(x86_cpu);
1649     if (ret < 0) {
1650         return ret;
1651     }
1652     ret = kvm_put_msrs(x86_cpu, level);
1653     if (ret < 0) {
1654         return ret;
1655     }
1656     if (level >= KVM_PUT_RESET_STATE) {
1657         ret = kvm_put_mp_state(x86_cpu);
1658         if (ret < 0) {
1659             return ret;
1660         }
1661         ret = kvm_put_apic(x86_cpu);
1662         if (ret < 0) {
1663             return ret;
1664         }
1665     }
1666     ret = kvm_put_vcpu_events(x86_cpu, level);
1667     if (ret < 0) {
1668         return ret;
1669     }
1670     ret = kvm_put_debugregs(x86_cpu);
1671     if (ret < 0) {
1672         return ret;
1673     }
1674     /* must be last */
1675     ret = kvm_guest_debug_workarounds(x86_cpu);
1676     if (ret < 0) {
1677         return ret;
1678     }
1679     return 0;
1680 }
1681
1682 int kvm_arch_get_registers(CPUState *cs)
1683 {
1684     X86CPU *cpu = X86_CPU(cs);
1685     int ret;
1686
1687     assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
1688
1689     ret = kvm_getput_regs(cpu, 0);
1690     if (ret < 0) {
1691         return ret;
1692     }
1693     ret = kvm_get_xsave(cpu);
1694     if (ret < 0) {
1695         return ret;
1696     }
1697     ret = kvm_get_xcrs(cpu);
1698     if (ret < 0) {
1699         return ret;
1700     }
1701     ret = kvm_get_sregs(cpu);
1702     if (ret < 0) {
1703         return ret;
1704     }
1705     ret = kvm_get_msrs(cpu);
1706     if (ret < 0) {
1707         return ret;
1708     }
1709     ret = kvm_get_mp_state(cpu);
1710     if (ret < 0) {
1711         return ret;
1712     }
1713     ret = kvm_get_apic(cpu);
1714     if (ret < 0) {
1715         return ret;
1716     }
1717     ret = kvm_get_vcpu_events(cpu);
1718     if (ret < 0) {
1719         return ret;
1720     }
1721     ret = kvm_get_debugregs(cpu);
1722     if (ret < 0) {
1723         return ret;
1724     }
1725     return 0;
1726 }
1727
1728 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
1729 {
1730     X86CPU *x86_cpu = X86_CPU(cpu);
1731     CPUX86State *env = &x86_cpu->env;
1732     int ret;
1733
1734     /* Inject NMI */
1735     if (env->interrupt_request & CPU_INTERRUPT_NMI) {
1736         env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1737         DPRINTF("injected NMI\n");
1738         ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
1739         if (ret < 0) {
1740             fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
1741                     strerror(-ret));
1742         }
1743     }
1744
1745     if (!kvm_irqchip_in_kernel()) {
1746         /* Force the VCPU out of its inner loop to process any INIT requests
1747          * or pending TPR access reports. */
1748         if (env->interrupt_request &
1749             (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
1750             env->exit_request = 1;
1751         }
1752
1753         /* Try to inject an interrupt if the guest can accept it */
1754         if (run->ready_for_interrupt_injection &&
1755             (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1756             (env->eflags & IF_MASK)) {
1757             int irq;
1758
1759             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1760             irq = cpu_get_pic_interrupt(env);
1761             if (irq >= 0) {
1762                 struct kvm_interrupt intr;
1763
1764                 intr.irq = irq;
1765                 DPRINTF("injected interrupt %d\n", irq);
1766                 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
1767                 if (ret < 0) {
1768                     fprintf(stderr,
1769                             "KVM: injection failed, interrupt lost (%s)\n",
1770                             strerror(-ret));
1771                 }
1772             }
1773         }
1774
1775         /* If we have an interrupt but the guest is not ready to receive an
1776          * interrupt, request an interrupt window exit.  This will
1777          * cause a return to userspace as soon as the guest is ready to
1778          * receive interrupts. */
1779         if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
1780             run->request_interrupt_window = 1;
1781         } else {
1782             run->request_interrupt_window = 0;
1783         }
1784
1785         DPRINTF("setting tpr\n");
1786         run->cr8 = cpu_get_apic_tpr(env->apic_state);
1787     }
1788 }
1789
1790 void kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
1791 {
1792     X86CPU *x86_cpu = X86_CPU(cpu);
1793     CPUX86State *env = &x86_cpu->env;
1794
1795     if (run->if_flag) {
1796         env->eflags |= IF_MASK;
1797     } else {
1798         env->eflags &= ~IF_MASK;
1799     }
1800     cpu_set_apic_tpr(env->apic_state, run->cr8);
1801     cpu_set_apic_base(env->apic_state, run->apic_base);
1802 }
1803
1804 int kvm_arch_process_async_events(CPUState *cs)
1805 {
1806     X86CPU *cpu = X86_CPU(cs);
1807     CPUX86State *env = &cpu->env;
1808
1809     if (env->interrupt_request & CPU_INTERRUPT_MCE) {
1810         /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
1811         assert(env->mcg_cap);
1812
1813         env->interrupt_request &= ~CPU_INTERRUPT_MCE;
1814
1815         kvm_cpu_synchronize_state(env);
1816
1817         if (env->exception_injected == EXCP08_DBLE) {
1818             /* this means triple fault */
1819             qemu_system_reset_request();
1820             env->exit_request = 1;
1821             return 0;
1822         }
1823         env->exception_injected = EXCP12_MCHK;
1824         env->has_error_code = 0;
1825
1826         env->halted = 0;
1827         if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
1828             env->mp_state = KVM_MP_STATE_RUNNABLE;
1829         }
1830     }
1831
1832     if (kvm_irqchip_in_kernel()) {
1833         return 0;
1834     }
1835
1836     if (env->interrupt_request & CPU_INTERRUPT_POLL) {
1837         env->interrupt_request &= ~CPU_INTERRUPT_POLL;
1838         apic_poll_irq(env->apic_state);
1839     }
1840     if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1841          (env->eflags & IF_MASK)) ||
1842         (env->interrupt_request & CPU_INTERRUPT_NMI)) {
1843         env->halted = 0;
1844     }
1845     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1846         kvm_cpu_synchronize_state(env);
1847         do_cpu_init(cpu);
1848     }
1849     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1850         kvm_cpu_synchronize_state(env);
1851         do_cpu_sipi(cpu);
1852     }
1853     if (env->interrupt_request & CPU_INTERRUPT_TPR) {
1854         env->interrupt_request &= ~CPU_INTERRUPT_TPR;
1855         kvm_cpu_synchronize_state(env);
1856         apic_handle_tpr_access_report(env->apic_state, env->eip,
1857                                       env->tpr_access_type);
1858     }
1859
1860     return env->halted;
1861 }
1862
1863 static int kvm_handle_halt(X86CPU *cpu)
1864 {
1865     CPUX86State *env = &cpu->env;
1866
1867     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1868           (env->eflags & IF_MASK)) &&
1869         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1870         env->halted = 1;
1871         return EXCP_HLT;
1872     }
1873
1874     return 0;
1875 }
1876
1877 static int kvm_handle_tpr_access(X86CPU *cpu)
1878 {
1879     CPUX86State *env = &cpu->env;
1880     CPUState *cs = CPU(cpu);
1881     struct kvm_run *run = cs->kvm_run;
1882
1883     apic_handle_tpr_access_report(env->apic_state, run->tpr_access.rip,
1884                                   run->tpr_access.is_write ? TPR_ACCESS_WRITE
1885                                                            : TPR_ACCESS_READ);
1886     return 1;
1887 }
1888
1889 int kvm_arch_insert_sw_breakpoint(CPUState *cpu, struct kvm_sw_breakpoint *bp)
1890 {
1891     CPUX86State *env = &X86_CPU(cpu)->env;
1892     static const uint8_t int3 = 0xcc;
1893
1894     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1895         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
1896         return -EINVAL;
1897     }
1898     return 0;
1899 }
1900
1901 int kvm_arch_remove_sw_breakpoint(CPUState *cpu, struct kvm_sw_breakpoint *bp)
1902 {
1903     CPUX86State *env = &X86_CPU(cpu)->env;
1904     uint8_t int3;
1905
1906     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1907         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
1908         return -EINVAL;
1909     }
1910     return 0;
1911 }
1912
1913 static struct {
1914     target_ulong addr;
1915     int len;
1916     int type;
1917 } hw_breakpoint[4];
1918
1919 static int nb_hw_breakpoint;
1920
1921 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1922 {
1923     int n;
1924
1925     for (n = 0; n < nb_hw_breakpoint; n++) {
1926         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1927             (hw_breakpoint[n].len == len || len == -1)) {
1928             return n;
1929         }
1930     }
1931     return -1;
1932 }
1933
1934 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1935                                   target_ulong len, int type)
1936 {
1937     switch (type) {
1938     case GDB_BREAKPOINT_HW:
1939         len = 1;
1940         break;
1941     case GDB_WATCHPOINT_WRITE:
1942     case GDB_WATCHPOINT_ACCESS:
1943         switch (len) {
1944         case 1:
1945             break;
1946         case 2:
1947         case 4:
1948         case 8:
1949             if (addr & (len - 1)) {
1950                 return -EINVAL;
1951             }
1952             break;
1953         default:
1954             return -EINVAL;
1955         }
1956         break;
1957     default:
1958         return -ENOSYS;
1959     }
1960
1961     if (nb_hw_breakpoint == 4) {
1962         return -ENOBUFS;
1963     }
1964     if (find_hw_breakpoint(addr, len, type) >= 0) {
1965         return -EEXIST;
1966     }
1967     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1968     hw_breakpoint[nb_hw_breakpoint].len = len;
1969     hw_breakpoint[nb_hw_breakpoint].type = type;
1970     nb_hw_breakpoint++;
1971
1972     return 0;
1973 }
1974
1975 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1976                                   target_ulong len, int type)
1977 {
1978     int n;
1979
1980     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1981     if (n < 0) {
1982         return -ENOENT;
1983     }
1984     nb_hw_breakpoint--;
1985     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1986
1987     return 0;
1988 }
1989
1990 void kvm_arch_remove_all_hw_breakpoints(void)
1991 {
1992     nb_hw_breakpoint = 0;
1993 }
1994
1995 static CPUWatchpoint hw_watchpoint;
1996
1997 static int kvm_handle_debug(X86CPU *cpu,
1998                             struct kvm_debug_exit_arch *arch_info)
1999 {
2000     CPUX86State *env = &cpu->env;
2001     int ret = 0;
2002     int n;
2003
2004     if (arch_info->exception == 1) {
2005         if (arch_info->dr6 & (1 << 14)) {
2006             if (env->singlestep_enabled) {
2007                 ret = EXCP_DEBUG;
2008             }
2009         } else {
2010             for (n = 0; n < 4; n++) {
2011                 if (arch_info->dr6 & (1 << n)) {
2012                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2013                     case 0x0:
2014                         ret = EXCP_DEBUG;
2015                         break;
2016                     case 0x1:
2017                         ret = EXCP_DEBUG;
2018                         env->watchpoint_hit = &hw_watchpoint;
2019                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2020                         hw_watchpoint.flags = BP_MEM_WRITE;
2021                         break;
2022                     case 0x3:
2023                         ret = EXCP_DEBUG;
2024                         env->watchpoint_hit = &hw_watchpoint;
2025                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2026                         hw_watchpoint.flags = BP_MEM_ACCESS;
2027                         break;
2028                     }
2029                 }
2030             }
2031         }
2032     } else if (kvm_find_sw_breakpoint(CPU(cpu), arch_info->pc)) {
2033         ret = EXCP_DEBUG;
2034     }
2035     if (ret == 0) {
2036         cpu_synchronize_state(env);
2037         assert(env->exception_injected == -1);
2038
2039         /* pass to guest */
2040         env->exception_injected = arch_info->exception;
2041         env->has_error_code = 0;
2042     }
2043
2044     return ret;
2045 }
2046
2047 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
2048 {
2049     const uint8_t type_code[] = {
2050         [GDB_BREAKPOINT_HW] = 0x0,
2051         [GDB_WATCHPOINT_WRITE] = 0x1,
2052         [GDB_WATCHPOINT_ACCESS] = 0x3
2053     };
2054     const uint8_t len_code[] = {
2055         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2056     };
2057     int n;
2058
2059     if (kvm_sw_breakpoints_active(cpu)) {
2060         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
2061     }
2062     if (nb_hw_breakpoint > 0) {
2063         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2064         dbg->arch.debugreg[7] = 0x0600;
2065         for (n = 0; n < nb_hw_breakpoint; n++) {
2066             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2067             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2068                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
2069                 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
2070         }
2071     }
2072 }
2073
2074 static bool host_supports_vmx(void)
2075 {
2076     uint32_t ecx, unused;
2077
2078     host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2079     return ecx & CPUID_EXT_VMX;
2080 }
2081
2082 #define VMX_INVALID_GUEST_STATE 0x80000021
2083
2084 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2085 {
2086     X86CPU *cpu = X86_CPU(cs);
2087     uint64_t code;
2088     int ret;
2089
2090     switch (run->exit_reason) {
2091     case KVM_EXIT_HLT:
2092         DPRINTF("handle_hlt\n");
2093         ret = kvm_handle_halt(cpu);
2094         break;
2095     case KVM_EXIT_SET_TPR:
2096         ret = 0;
2097         break;
2098     case KVM_EXIT_TPR_ACCESS:
2099         ret = kvm_handle_tpr_access(cpu);
2100         break;
2101     case KVM_EXIT_FAIL_ENTRY:
2102         code = run->fail_entry.hardware_entry_failure_reason;
2103         fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2104                 code);
2105         if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2106             fprintf(stderr,
2107                     "\nIf you're running a guest on an Intel machine without "
2108                         "unrestricted mode\n"
2109                     "support, the failure can be most likely due to the guest "
2110                         "entering an invalid\n"
2111                     "state for Intel VT. For example, the guest maybe running "
2112                         "in big real mode\n"
2113                     "which is not supported on less recent Intel processors."
2114                         "\n\n");
2115         }
2116         ret = -1;
2117         break;
2118     case KVM_EXIT_EXCEPTION:
2119         fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2120                 run->ex.exception, run->ex.error_code);
2121         ret = -1;
2122         break;
2123     case KVM_EXIT_DEBUG:
2124         DPRINTF("kvm_exit_debug\n");
2125         ret = kvm_handle_debug(cpu, &run->debug.arch);
2126         break;
2127     default:
2128         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2129         ret = -1;
2130         break;
2131     }
2132
2133     return ret;
2134 }
2135
2136 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
2137 {
2138     X86CPU *cpu = X86_CPU(cs);
2139     CPUX86State *env = &cpu->env;
2140
2141     kvm_cpu_synchronize_state(env);
2142     return !(env->cr[0] & CR0_PE_MASK) ||
2143            ((env->segs[R_CS].selector  & 3) != 3);
2144 }
2145
2146 void kvm_arch_init_irq_routing(KVMState *s)
2147 {
2148     if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2149         /* If kernel can't do irq routing, interrupt source
2150          * override 0->2 cannot be set up as required by HPET.
2151          * So we have to disable it.
2152          */
2153         no_hpet = 1;
2154     }
2155     /* We know at this point that we're using the in-kernel
2156      * irqchip, so we can use irqfds, and on x86 we know
2157      * we can use msi via irqfd and GSI routing.
2158      */
2159     kvm_irqfds_allowed = true;
2160     kvm_msi_via_irqfd_allowed = true;
2161     kvm_gsi_routing_allowed = true;
2162 }
2163
2164 /* Classic KVM device assignment interface. Will remain x86 only. */
2165 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2166                           uint32_t flags, uint32_t *dev_id)
2167 {
2168     struct kvm_assigned_pci_dev dev_data = {
2169         .segnr = dev_addr->domain,
2170         .busnr = dev_addr->bus,
2171         .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2172         .flags = flags,
2173     };
2174     int ret;
2175
2176     dev_data.assigned_dev_id =
2177         (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2178
2179     ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2180     if (ret < 0) {
2181         return ret;
2182     }
2183
2184     *dev_id = dev_data.assigned_dev_id;
2185
2186     return 0;
2187 }
2188
2189 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2190 {
2191     struct kvm_assigned_pci_dev dev_data = {
2192         .assigned_dev_id = dev_id,
2193     };
2194
2195     return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2196 }
2197
2198 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2199                                    uint32_t irq_type, uint32_t guest_irq)
2200 {
2201     struct kvm_assigned_irq assigned_irq = {
2202         .assigned_dev_id = dev_id,
2203         .guest_irq = guest_irq,
2204         .flags = irq_type,
2205     };
2206
2207     if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2208         return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2209     } else {
2210         return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2211     }
2212 }
2213
2214 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2215                            uint32_t guest_irq)
2216 {
2217     uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2218         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2219
2220     return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2221 }
2222
2223 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2224 {
2225     struct kvm_assigned_pci_dev dev_data = {
2226         .assigned_dev_id = dev_id,
2227         .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2228     };
2229
2230     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
2231 }
2232
2233 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
2234                                      uint32_t type)
2235 {
2236     struct kvm_assigned_irq assigned_irq = {
2237         .assigned_dev_id = dev_id,
2238         .flags = type,
2239     };
2240
2241     return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
2242 }
2243
2244 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
2245 {
2246     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
2247         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
2248 }
2249
2250 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
2251 {
2252     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
2253                                               KVM_DEV_IRQ_GUEST_MSI, virq);
2254 }
2255
2256 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
2257 {
2258     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
2259                                                 KVM_DEV_IRQ_HOST_MSI);
2260 }
2261
2262 bool kvm_device_msix_supported(KVMState *s)
2263 {
2264     /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2265      * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2266     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
2267 }
2268
2269 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
2270                                  uint32_t nr_vectors)
2271 {
2272     struct kvm_assigned_msix_nr msix_nr = {
2273         .assigned_dev_id = dev_id,
2274         .entry_nr = nr_vectors,
2275     };
2276
2277     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
2278 }
2279
2280 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
2281                                int virq)
2282 {
2283     struct kvm_assigned_msix_entry msix_entry = {
2284         .assigned_dev_id = dev_id,
2285         .gsi = virq,
2286         .entry = vector,
2287     };
2288
2289     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
2290 }
2291
2292 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
2293 {
2294     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
2295                                               KVM_DEV_IRQ_GUEST_MSIX, 0);
2296 }
2297
2298 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
2299 {
2300     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
2301                                                 KVM_DEV_IRQ_HOST_MSIX);
2302 }