target-ppc/machine.c

   1 #include "hw/hw.h"
   2 #include "hw/boards.h"
   3 #include "kvm.h"
   4
   5 void cpu_save(QEMUFile *f, void *opaque)
   6 {
   7     CPUPPCState *env = (CPUPPCState *)opaque;
   8     unsigned int i, j;
   9
  10     for (i = 0; i < 32; i++)
  11         qemu_put_betls(f, &env->gpr[i]);
  12 #if !defined(TARGET_PPC64)
  13     for (i = 0; i < 32; i++)
  14         qemu_put_betls(f, &env->gprh[i]);
  15 #endif
  16     qemu_put_betls(f, &env->lr);
  17     qemu_put_betls(f, &env->ctr);
  18     for (i = 0; i < 8; i++)
  19         qemu_put_be32s(f, &env->crf[i]);
  20     qemu_put_betls(f, &env->xer);
  21     qemu_put_betls(f, &env->reserve_addr);
  22     qemu_put_betls(f, &env->msr);
  23     for (i = 0; i < 4; i++)
  24         qemu_put_betls(f, &env->tgpr[i]);
  25     for (i = 0; i < 32; i++) {
  26         union {
  27             float64 d;
  28             uint64_t l;
  29         } u;
  30         u.d = env->fpr[i];
  31         qemu_put_be64(f, u.l);
  32     }
  33     qemu_put_be32s(f, &env->fpscr);
  34     qemu_put_sbe32s(f, &env->access_type);
  35 #if defined(TARGET_PPC64)
  36     qemu_put_betls(f, &env->asr);
  37     qemu_put_sbe32s(f, &env->slb_nr);
  38 #endif
  39     qemu_put_betls(f, &env->spr[SPR_SDR1]);
  40     for (i = 0; i < 32; i++)
  41         qemu_put_betls(f, &env->sr[i]);
  42     for (i = 0; i < 2; i++)
  43         for (j = 0; j < 8; j++)
  44             qemu_put_betls(f, &env->DBAT[i][j]);
  45     for (i = 0; i < 2; i++)
  46         for (j = 0; j < 8; j++)
  47             qemu_put_betls(f, &env->IBAT[i][j]);
  48     qemu_put_sbe32s(f, &env->nb_tlb);
  49     qemu_put_sbe32s(f, &env->tlb_per_way);
  50     qemu_put_sbe32s(f, &env->nb_ways);
  51     qemu_put_sbe32s(f, &env->last_way);
  52     qemu_put_sbe32s(f, &env->id_tlbs);
  53     qemu_put_sbe32s(f, &env->nb_pids);
  54     if (env->tlb.tlb6) {
  55         // XXX assumes 6xx
  56         for (i = 0; i < env->nb_tlb; i++) {
  57             qemu_put_betls(f, &env->tlb.tlb6[i].pte0);
  58             qemu_put_betls(f, &env->tlb.tlb6[i].pte1);
  59             qemu_put_betls(f, &env->tlb.tlb6[i].EPN);
  60         }
  61     }
  62     for (i = 0; i < 4; i++)
  63         qemu_put_betls(f, &env->pb[i]);
  64     for (i = 0; i < 1024; i++)
  65         qemu_put_betls(f, &env->spr[i]);
  66     qemu_put_be32s(f, &env->vscr);
  67     qemu_put_be64s(f, &env->spe_acc);
  68     qemu_put_be32s(f, &env->spe_fscr);
  69     qemu_put_betls(f, &env->msr_mask);
  70     qemu_put_be32s(f, &env->flags);
  71     qemu_put_sbe32s(f, &env->error_code);
  72     qemu_put_be32s(f, &env->pending_interrupts);
  73     qemu_put_be32s(f, &env->irq_input_state);
  74     for (i = 0; i < POWERPC_EXCP_NB; i++)
  75         qemu_put_betls(f, &env->excp_vectors[i]);
  76     qemu_put_betls(f, &env->excp_prefix);
  77     qemu_put_betls(f, &env->hreset_excp_prefix);
  78     qemu_put_betls(f, &env->ivor_mask);
  79     qemu_put_betls(f, &env->ivpr_mask);
  80     qemu_put_betls(f, &env->hreset_vector);
  81     qemu_put_betls(f, &env->nip);
  82     qemu_put_betls(f, &env->hflags);
  83     qemu_put_betls(f, &env->hflags_nmsr);
  84     qemu_put_sbe32s(f, &env->mmu_idx);
  85     qemu_put_sbe32s(f, &env->power_mode);
  86 }
  87
  88 int cpu_load(QEMUFile *f, void *opaque, int version_id)
  89 {
  90     CPUPPCState *env = (CPUPPCState *)opaque;
  91     unsigned int i, j;
  92     target_ulong sdr1;
  93
  94     for (i = 0; i < 32; i++)
  95         qemu_get_betls(f, &env->gpr[i]);
  96 #if !defined(TARGET_PPC64)
  97     for (i = 0; i < 32; i++)
  98         qemu_get_betls(f, &env->gprh[i]);
  99 #endif
 100     qemu_get_betls(f, &env->lr);
 101     qemu_get_betls(f, &env->ctr);
 102     for (i = 0; i < 8; i++)
 103         qemu_get_be32s(f, &env->crf[i]);
 104     qemu_get_betls(f, &env->xer);
 105     qemu_get_betls(f, &env->reserve_addr);
 106     qemu_get_betls(f, &env->msr);
 107     for (i = 0; i < 4; i++)
 108         qemu_get_betls(f, &env->tgpr[i]);
 109     for (i = 0; i < 32; i++) {
 110         union {
 111             float64 d;
 112             uint64_t l;
 113         } u;
 114         u.l = qemu_get_be64(f);
 115         env->fpr[i] = u.d;
 116     }
 117     qemu_get_be32s(f, &env->fpscr);
 118     qemu_get_sbe32s(f, &env->access_type);
 119 #if defined(TARGET_PPC64)
 120     qemu_get_betls(f, &env->asr);
 121     qemu_get_sbe32s(f, &env->slb_nr);
 122 #endif
 123     qemu_get_betls(f, &sdr1);
 124     for (i = 0; i < 32; i++)
 125         qemu_get_betls(f, &env->sr[i]);
 126     for (i = 0; i < 2; i++)
 127         for (j = 0; j < 8; j++)
 128             qemu_get_betls(f, &env->DBAT[i][j]);
 129     for (i = 0; i < 2; i++)
 130         for (j = 0; j < 8; j++)
 131             qemu_get_betls(f, &env->IBAT[i][j]);
 132     qemu_get_sbe32s(f, &env->nb_tlb);
 133     qemu_get_sbe32s(f, &env->tlb_per_way);
 134     qemu_get_sbe32s(f, &env->nb_ways);
 135     qemu_get_sbe32s(f, &env->last_way);
 136     qemu_get_sbe32s(f, &env->id_tlbs);
 137     qemu_get_sbe32s(f, &env->nb_pids);
 138     if (env->tlb.tlb6) {
 139         // XXX assumes 6xx
 140         for (i = 0; i < env->nb_tlb; i++) {
 141             qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
 142             qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
 143             qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
 144         }
 145     }
 146     for (i = 0; i < 4; i++)
 147         qemu_get_betls(f, &env->pb[i]);
 148     for (i = 0; i < 1024; i++)
 149         qemu_get_betls(f, &env->spr[i]);
 150     ppc_store_sdr1(env, sdr1);
 151     qemu_get_be32s(f, &env->vscr);
 152     qemu_get_be64s(f, &env->spe_acc);
 153     qemu_get_be32s(f, &env->spe_fscr);
 154     qemu_get_betls(f, &env->msr_mask);
 155     qemu_get_be32s(f, &env->flags);
 156     qemu_get_sbe32s(f, &env->error_code);
 157     qemu_get_be32s(f, &env->pending_interrupts);
 158     qemu_get_be32s(f, &env->irq_input_state);
 159     for (i = 0; i < POWERPC_EXCP_NB; i++)
 160         qemu_get_betls(f, &env->excp_vectors[i]);
 161     qemu_get_betls(f, &env->excp_prefix);
 162     qemu_get_betls(f, &env->hreset_excp_prefix);
 163     qemu_get_betls(f, &env->ivor_mask);
 164     qemu_get_betls(f, &env->ivpr_mask);
 165     qemu_get_betls(f, &env->hreset_vector);
 166     qemu_get_betls(f, &env->nip);
 167     qemu_get_betls(f, &env->hflags);
 168     qemu_get_betls(f, &env->hflags_nmsr);
 169     qemu_get_sbe32s(f, &env->mmu_idx);
 170     qemu_get_sbe32s(f, &env->power_mode);
 171
 172     return 0;
 173 }