target-ppc/cpu.h

   1 /*
   2  *  PowerPC emulation cpu definitions for qemu.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #if !defined (__CPU_PPC_H__)
  20 #define __CPU_PPC_H__
  21
  22 #include "config.h"
  23 #include "qemu-common.h"
  24
  25 //#define PPC_EMULATE_32BITS_HYPV
  26
  27 #if defined (TARGET_PPC64)
  28 /* PowerPC 64 definitions */
  29 #define TARGET_LONG_BITS 64
  30 #define TARGET_PAGE_BITS 12
  31
  32 /* Note that the official physical address space bits is 62-M where M
  33    is implementation dependent.  I've not looked up M for the set of
  34    cpus we emulate at the system level.  */
  35 #define TARGET_PHYS_ADDR_SPACE_BITS 62
  36
  37 /* Note that the PPC environment architecture talks about 80 bit virtual
  38    addresses, with segmentation.  Obviously that's not all visible to a
  39    single process, which is all we're concerned with here.  */
  40 #ifdef TARGET_ABI32
  41 # define TARGET_VIRT_ADDR_SPACE_BITS 32
  42 #else
  43 # define TARGET_VIRT_ADDR_SPACE_BITS 64
  44 #endif
  45
  46 #define TARGET_PAGE_BITS_16M 24
  47
  48 #else /* defined (TARGET_PPC64) */
  49 /* PowerPC 32 definitions */
  50 #define TARGET_LONG_BITS 32
  51
  52 #if defined(TARGET_PPCEMB)
  53 /* Specific definitions for PowerPC embedded */
  54 /* BookE have 36 bits physical address space */
  55 #if defined(CONFIG_USER_ONLY)
  56 /* It looks like a lot of Linux programs assume page size
  57  * is 4kB long. This is evil, but we have to deal with it...
  58  */
  59 #define TARGET_PAGE_BITS 12
  60 #else /* defined(CONFIG_USER_ONLY) */
  61 /* Pages can be 1 kB small */
  62 #define TARGET_PAGE_BITS 10
  63 #endif /* defined(CONFIG_USER_ONLY) */
  64 #else /* defined(TARGET_PPCEMB) */
  65 /* "standard" PowerPC 32 definitions */
  66 #define TARGET_PAGE_BITS 12
  67 #endif /* defined(TARGET_PPCEMB) */
  68
  69 #define TARGET_PHYS_ADDR_SPACE_BITS 36
  70 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  71
  72 #endif /* defined (TARGET_PPC64) */
  73
  74 #define CPUArchState struct CPUPPCState
  75
  76 #include "cpu-defs.h"
  77
  78 #include "softfloat.h"
  79
  80 #define TARGET_HAS_ICE 1
  81
  82 #if defined (TARGET_PPC64)
  83 #define ELF_MACHINE     EM_PPC64
  84 #else
  85 #define ELF_MACHINE     EM_PPC
  86 #endif
  87
  88 /*****************************************************************************/
  89 /* MMU model                                                                 */
  90 typedef enum powerpc_mmu_t powerpc_mmu_t;
  91 enum powerpc_mmu_t {
  92     POWERPC_MMU_UNKNOWN    = 0x00000000,
  93     /* Standard 32 bits PowerPC MMU                            */
  94     POWERPC_MMU_32B        = 0x00000001,
  95     /* PowerPC 6xx MMU with software TLB                       */
  96     POWERPC_MMU_SOFT_6xx   = 0x00000002,
  97     /* PowerPC 74xx MMU with software TLB                      */
  98     POWERPC_MMU_SOFT_74xx  = 0x00000003,
  99     /* PowerPC 4xx MMU with software TLB                       */
 100     POWERPC_MMU_SOFT_4xx   = 0x00000004,
 101     /* PowerPC 4xx MMU with software TLB and zones protections */
 102     POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
 103     /* PowerPC MMU in real mode only                           */
 104     POWERPC_MMU_REAL       = 0x00000006,
 105     /* Freescale MPC8xx MMU model                              */
 106     POWERPC_MMU_MPC8xx     = 0x00000007,
 107     /* BookE MMU model                                         */
 108     POWERPC_MMU_BOOKE      = 0x00000008,
 109     /* BookE 2.06 MMU model                                    */
 110     POWERPC_MMU_BOOKE206   = 0x00000009,
 111     /* PowerPC 601 MMU model (specific BATs format)            */
 112     POWERPC_MMU_601        = 0x0000000A,
 113 #if defined(TARGET_PPC64)
 114 #define POWERPC_MMU_64       0x00010000
 115 #define POWERPC_MMU_1TSEG    0x00020000
 116     /* 64 bits PowerPC MMU                                     */
 117     POWERPC_MMU_64B        = POWERPC_MMU_64 | 0x00000001,
 118     /* 620 variant (no segment exceptions)                     */
 119     POWERPC_MMU_620        = POWERPC_MMU_64 | 0x00000002,
 120     /* Architecture 2.06 variant                               */
 121     POWERPC_MMU_2_06       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | 0x00000003,
 122     /* Architecture 2.06 "degraded" (no 1T segments)           */
 123     POWERPC_MMU_2_06d      = POWERPC_MMU_64 | 0x00000003,
 124 #endif /* defined(TARGET_PPC64) */
 125 };
 126
 127 /*****************************************************************************/
 128 /* Exception model                                                           */
 129 typedef enum powerpc_excp_t powerpc_excp_t;
 130 enum powerpc_excp_t {
 131     POWERPC_EXCP_UNKNOWN   = 0,
 132     /* Standard PowerPC exception model */
 133     POWERPC_EXCP_STD,
 134     /* PowerPC 40x exception model      */
 135     POWERPC_EXCP_40x,
 136     /* PowerPC 601 exception model      */
 137     POWERPC_EXCP_601,
 138     /* PowerPC 602 exception model      */
 139     POWERPC_EXCP_602,
 140     /* PowerPC 603 exception model      */
 141     POWERPC_EXCP_603,
 142     /* PowerPC 603e exception model     */
 143     POWERPC_EXCP_603E,
 144     /* PowerPC G2 exception model       */
 145     POWERPC_EXCP_G2,
 146     /* PowerPC 604 exception model      */
 147     POWERPC_EXCP_604,
 148     /* PowerPC 7x0 exception model      */
 149     POWERPC_EXCP_7x0,
 150     /* PowerPC 7x5 exception model      */
 151     POWERPC_EXCP_7x5,
 152     /* PowerPC 74xx exception model     */
 153     POWERPC_EXCP_74xx,
 154     /* BookE exception model            */
 155     POWERPC_EXCP_BOOKE,
 156 #if defined(TARGET_PPC64)
 157     /* PowerPC 970 exception model      */
 158     POWERPC_EXCP_970,
 159     /* POWER7 exception model           */
 160     POWERPC_EXCP_POWER7,
 161 #endif /* defined(TARGET_PPC64) */
 162 };
 163
 164 /*****************************************************************************/
 165 /* Exception vectors definitions                                             */
 166 enum {
 167     POWERPC_EXCP_NONE    = -1,
 168     /* The 64 first entries are used by the PowerPC embedded specification   */
 169     POWERPC_EXCP_CRITICAL = 0,  /* Critical input                            */
 170     POWERPC_EXCP_MCHECK   = 1,  /* Machine check exception                   */
 171     POWERPC_EXCP_DSI      = 2,  /* Data storage exception                    */
 172     POWERPC_EXCP_ISI      = 3,  /* Instruction storage exception             */
 173     POWERPC_EXCP_EXTERNAL = 4,  /* External input                            */
 174     POWERPC_EXCP_ALIGN    = 5,  /* Alignment exception                       */
 175     POWERPC_EXCP_PROGRAM  = 6,  /* Program exception                         */
 176     POWERPC_EXCP_FPU      = 7,  /* Floating-point unavailable exception      */
 177     POWERPC_EXCP_SYSCALL  = 8,  /* System call exception                     */
 178     POWERPC_EXCP_APU      = 9,  /* Auxiliary processor unavailable           */
 179     POWERPC_EXCP_DECR     = 10, /* Decrementer exception                     */
 180     POWERPC_EXCP_FIT      = 11, /* Fixed-interval timer interrupt            */
 181     POWERPC_EXCP_WDT      = 12, /* Watchdog timer interrupt                  */
 182     POWERPC_EXCP_DTLB     = 13, /* Data TLB miss                             */
 183     POWERPC_EXCP_ITLB     = 14, /* Instruction TLB miss                      */
 184     POWERPC_EXCP_DEBUG    = 15, /* Debug interrupt                           */
 185     /* Vectors 16 to 31 are reserved                                         */
 186     POWERPC_EXCP_SPEU     = 32, /* SPE/embedded floating-point unavailable   */
 187     POWERPC_EXCP_EFPDI    = 33, /* Embedded floating-point data interrupt    */
 188     POWERPC_EXCP_EFPRI    = 34, /* Embedded floating-point round interrupt   */
 189     POWERPC_EXCP_EPERFM   = 35, /* Embedded performance monitor interrupt    */
 190     POWERPC_EXCP_DOORI    = 36, /* Embedded doorbell interrupt               */
 191     POWERPC_EXCP_DOORCI   = 37, /* Embedded doorbell critical interrupt      */
 192     POWERPC_EXCP_GDOORI   = 38, /* Embedded guest doorbell interrupt         */
 193     POWERPC_EXCP_GDOORCI  = 39, /* Embedded guest doorbell critical interrupt*/
 194     POWERPC_EXCP_HYPPRIV  = 41, /* Embedded hypervisor priv instruction      */
 195     /* Vectors 42 to 63 are reserved                                         */
 196     /* Exceptions defined in the PowerPC server specification                */
 197     POWERPC_EXCP_RESET    = 64, /* System reset exception                    */
 198     POWERPC_EXCP_DSEG     = 65, /* Data segment exception                    */
 199     POWERPC_EXCP_ISEG     = 66, /* Instruction segment exception             */
 200     POWERPC_EXCP_HDECR    = 67, /* Hypervisor decrementer exception          */
 201     POWERPC_EXCP_TRACE    = 68, /* Trace exception                           */
 202     POWERPC_EXCP_HDSI     = 69, /* Hypervisor data storage exception         */
 203     POWERPC_EXCP_HISI     = 70, /* Hypervisor instruction storage exception  */
 204     POWERPC_EXCP_HDSEG    = 71, /* Hypervisor data segment exception         */
 205     POWERPC_EXCP_HISEG    = 72, /* Hypervisor instruction segment exception  */
 206     POWERPC_EXCP_VPU      = 73, /* Vector unavailable exception              */
 207     /* 40x specific exceptions                                               */
 208     POWERPC_EXCP_PIT      = 74, /* Programmable interval timer interrupt     */
 209     /* 601 specific exceptions                                               */
 210     POWERPC_EXCP_IO       = 75, /* IO error exception                        */
 211     POWERPC_EXCP_RUNM     = 76, /* Run mode exception                        */
 212     /* 602 specific exceptions                                               */
 213     POWERPC_EXCP_EMUL     = 77, /* Emulation trap exception                  */
 214     /* 602/603 specific exceptions                                           */
 215     POWERPC_EXCP_IFTLB    = 78, /* Instruction fetch TLB miss                */
 216     POWERPC_EXCP_DLTLB    = 79, /* Data load TLB miss                        */
 217     POWERPC_EXCP_DSTLB    = 80, /* Data store TLB miss                       */
 218     /* Exceptions available on most PowerPC                                  */
 219     POWERPC_EXCP_FPA      = 81, /* Floating-point assist exception           */
 220     POWERPC_EXCP_DABR     = 82, /* Data address breakpoint                   */
 221     POWERPC_EXCP_IABR     = 83, /* Instruction address breakpoint            */
 222     POWERPC_EXCP_SMI      = 84, /* System management interrupt               */
 223     POWERPC_EXCP_PERFM    = 85, /* Embedded performance monitor interrupt    */
 224     /* 7xx/74xx specific exceptions                                          */
 225     POWERPC_EXCP_THERM    = 86, /* Thermal interrupt                         */
 226     /* 74xx specific exceptions                                              */
 227     POWERPC_EXCP_VPUA     = 87, /* Vector assist exception                   */
 228     /* 970FX specific exceptions                                             */
 229     POWERPC_EXCP_SOFTP    = 88, /* Soft patch exception                      */
 230     POWERPC_EXCP_MAINT    = 89, /* Maintenance exception                     */
 231     /* Freescale embedded cores specific exceptions                          */
 232     POWERPC_EXCP_MEXTBR   = 90, /* Maskable external breakpoint              */
 233     POWERPC_EXCP_NMEXTBR  = 91, /* Non maskable external breakpoint          */
 234     POWERPC_EXCP_ITLBE    = 92, /* Instruction TLB error                     */
 235     POWERPC_EXCP_DTLBE    = 93, /* Data TLB error                            */
 236     /* EOL                                                                   */
 237     POWERPC_EXCP_NB       = 96,
 238     /* QEMU exceptions: used internally during code translation              */
 239     POWERPC_EXCP_STOP         = 0x200, /* stop translation                   */
 240     POWERPC_EXCP_BRANCH       = 0x201, /* branch instruction                 */
 241     /* QEMU exceptions: special cases we want to stop translation            */
 242     POWERPC_EXCP_SYNC         = 0x202, /* context synchronizing instruction  */
 243     POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only      */
 244     POWERPC_EXCP_STCX         = 0x204 /* Conditional stores in user mode     */
 245 };
 246
 247 /* Exceptions error codes                                                    */
 248 enum {
 249     /* Exception subtypes for POWERPC_EXCP_ALIGN                             */
 250     POWERPC_EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception            */
 251     POWERPC_EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store  */
 252     POWERPC_EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access     */
 253     POWERPC_EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary  */
 254     POWERPC_EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary   */
 255     POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access            */
 256     /* Exception subtypes for POWERPC_EXCP_PROGRAM                           */
 257     /* FP exceptions                                                         */
 258     POWERPC_EXCP_FP            = 0x10,
 259     POWERPC_EXCP_FP_OX         = 0x01,  /* FP overflow                       */
 260     POWERPC_EXCP_FP_UX         = 0x02,  /* FP underflow                      */
 261     POWERPC_EXCP_FP_ZX         = 0x03,  /* FP divide by zero                 */
 262     POWERPC_EXCP_FP_XX         = 0x04,  /* FP inexact                        */
 263     POWERPC_EXCP_FP_VXSNAN     = 0x05,  /* FP invalid SNaN op                */
 264     POWERPC_EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite subtraction   */
 265     POWERPC_EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide        */
 266     POWERPC_EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide            */
 267     POWERPC_EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero        */
 268     POWERPC_EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare                */
 269     POWERPC_EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation              */
 270     POWERPC_EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root            */
 271     POWERPC_EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion     */
 272     /* Invalid instruction                                                   */
 273     POWERPC_EXCP_INVAL         = 0x20,
 274     POWERPC_EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction               */
 275     POWERPC_EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction          */
 276     POWERPC_EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access                */
 277     POWERPC_EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr  */
 278     /* Privileged instruction                                                */
 279     POWERPC_EXCP_PRIV          = 0x30,
 280     POWERPC_EXCP_PRIV_OPC      = 0x01,  /* Privileged operation exception    */
 281     POWERPC_EXCP_PRIV_REG      = 0x02,  /* Privileged register exception     */
 282     /* Trap                                                                  */
 283     POWERPC_EXCP_TRAP          = 0x40,
 284 };
 285
 286 /*****************************************************************************/
 287 /* Input pins model                                                          */
 288 typedef enum powerpc_input_t powerpc_input_t;
 289 enum powerpc_input_t {
 290     PPC_FLAGS_INPUT_UNKNOWN = 0,
 291     /* PowerPC 6xx bus                  */
 292     PPC_FLAGS_INPUT_6xx,
 293     /* BookE bus                        */
 294     PPC_FLAGS_INPUT_BookE,
 295     /* PowerPC 405 bus                  */
 296     PPC_FLAGS_INPUT_405,
 297     /* PowerPC 970 bus                  */
 298     PPC_FLAGS_INPUT_970,
 299     /* PowerPC POWER7 bus               */
 300     PPC_FLAGS_INPUT_POWER7,
 301     /* PowerPC 401 bus                  */
 302     PPC_FLAGS_INPUT_401,
 303     /* Freescale RCPU bus               */
 304     PPC_FLAGS_INPUT_RCPU,
 305 };
 306
 307 #define PPC_INPUT(env) (env->bus_model)
 308
 309 /*****************************************************************************/
 310 typedef struct ppc_def_t ppc_def_t;
 311 typedef struct opc_handler_t opc_handler_t;
 312
 313 /*****************************************************************************/
 314 /* Types used to describe some PowerPC registers */
 315 typedef struct CPUPPCState CPUPPCState;
 316 typedef struct ppc_tb_t ppc_tb_t;
 317 typedef struct ppc_spr_t ppc_spr_t;
 318 typedef struct ppc_dcr_t ppc_dcr_t;
 319 typedef union ppc_avr_t ppc_avr_t;
 320 typedef union ppc_tlb_t ppc_tlb_t;
 321
 322 /* SPR access micro-ops generations callbacks */
 323 struct ppc_spr_t {
 324     void (*uea_read)(void *opaque, int gpr_num, int spr_num);
 325     void (*uea_write)(void *opaque, int spr_num, int gpr_num);
 326 #if !defined(CONFIG_USER_ONLY)
 327     void (*oea_read)(void *opaque, int gpr_num, int spr_num);
 328     void (*oea_write)(void *opaque, int spr_num, int gpr_num);
 329     void (*hea_read)(void *opaque, int gpr_num, int spr_num);
 330     void (*hea_write)(void *opaque, int spr_num, int gpr_num);
 331 #endif
 332     const char *name;
 333 };
 334
 335 /* Altivec registers (128 bits) */
 336 union ppc_avr_t {
 337     float32 f[4];
 338     uint8_t u8[16];
 339     uint16_t u16[8];
 340     uint32_t u32[4];
 341     int8_t s8[16];
 342     int16_t s16[8];
 343     int32_t s32[4];
 344     uint64_t u64[2];
 345 };
 346
 347 #if !defined(CONFIG_USER_ONLY)
 348 /* Software TLB cache */
 349 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
 350 struct ppc6xx_tlb_t {
 351     target_ulong pte0;
 352     target_ulong pte1;
 353     target_ulong EPN;
 354 };
 355
 356 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
 357 struct ppcemb_tlb_t {
 358     uint64_t RPN;
 359     target_ulong EPN;
 360     target_ulong PID;
 361     target_ulong size;
 362     uint32_t prot;
 363     uint32_t attr; /* Storage attributes */
 364 };
 365
 366 typedef struct ppcmas_tlb_t {
 367      uint32_t mas8;
 368      uint32_t mas1;
 369      uint64_t mas2;
 370      uint64_t mas7_3;
 371 } ppcmas_tlb_t;
 372
 373 union ppc_tlb_t {
 374     ppc6xx_tlb_t *tlb6;
 375     ppcemb_tlb_t *tlbe;
 376     ppcmas_tlb_t *tlbm;
 377 };
 378
 379 /* possible TLB variants */
 380 #define TLB_NONE               0
 381 #define TLB_6XX                1
 382 #define TLB_EMB                2
 383 #define TLB_MAS                3
 384 #endif
 385
 386 #define SDR_32_HTABORG         0xFFFF0000UL
 387 #define SDR_32_HTABMASK        0x000001FFUL
 388
 389 #if defined(TARGET_PPC64)
 390 #define SDR_64_HTABORG         0xFFFFFFFFFFFC0000ULL
 391 #define SDR_64_HTABSIZE        0x000000000000001FULL
 392 #endif /* defined(TARGET_PPC64 */
 393
 394 #define HASH_PTE_SIZE_32       8
 395 #define HASH_PTE_SIZE_64       16
 396
 397 typedef struct ppc_slb_t ppc_slb_t;
 398 struct ppc_slb_t {
 399     uint64_t esid;
 400     uint64_t vsid;
 401 };
 402
 403 /* Bits in the SLB ESID word */
 404 #define SLB_ESID_ESID           0xFFFFFFFFF0000000ULL
 405 #define SLB_ESID_V              0x0000000008000000ULL /* valid */
 406
 407 /* Bits in the SLB VSID word */
 408 #define SLB_VSID_SHIFT          12
 409 #define SLB_VSID_SHIFT_1T       24
 410 #define SLB_VSID_SSIZE_SHIFT    62
 411 #define SLB_VSID_B              0xc000000000000000ULL
 412 #define SLB_VSID_B_256M         0x0000000000000000ULL
 413 #define SLB_VSID_B_1T           0x4000000000000000ULL
 414 #define SLB_VSID_VSID           0x3FFFFFFFFFFFF000ULL
 415 #define SLB_VSID_PTEM           (SLB_VSID_B | SLB_VSID_VSID)
 416 #define SLB_VSID_KS             0x0000000000000800ULL
 417 #define SLB_VSID_KP             0x0000000000000400ULL
 418 #define SLB_VSID_N              0x0000000000000200ULL /* no-execute */
 419 #define SLB_VSID_L              0x0000000000000100ULL
 420 #define SLB_VSID_C              0x0000000000000080ULL /* class */
 421 #define SLB_VSID_LP             0x0000000000000030ULL
 422 #define SLB_VSID_ATTR           0x0000000000000FFFULL
 423
 424 #define SEGMENT_SHIFT_256M      28
 425 #define SEGMENT_MASK_256M       (~((1ULL << SEGMENT_SHIFT_256M) - 1))
 426
 427 #define SEGMENT_SHIFT_1T        40
 428 #define SEGMENT_MASK_1T         (~((1ULL << SEGMENT_SHIFT_1T) - 1))
 429
 430
 431 /*****************************************************************************/
 432 /* Machine state register bits definition                                    */
 433 #define MSR_SF   63 /* Sixty-four-bit mode                            hflags */
 434 #define MSR_TAG  62 /* Tag-active mode (POWERx ?)                            */
 435 #define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */
 436 #define MSR_SHV  60 /* hypervisor state                               hflags */
 437 #define MSR_CM   31 /* Computation mode for BookE                     hflags */
 438 #define MSR_ICM  30 /* Interrupt computation mode for BookE                  */
 439 #define MSR_THV  29 /* hypervisor state for 32 bits PowerPC           hflags */
 440 #define MSR_GS   28 /* guest state for BookE                                 */
 441 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE                 */
 442 #define MSR_VR   25 /* altivec available                            x hflags */
 443 #define MSR_SPE  25 /* SPE enable for BookE                         x hflags */
 444 #define MSR_AP   23 /* Access privilege state on 602                  hflags */
 445 #define MSR_SA   22 /* Supervisor access mode on 602                  hflags */
 446 #define MSR_KEY  19 /* key bit on 603e                                       */
 447 #define MSR_POW  18 /* Power management                                      */
 448 #define MSR_TGPR 17 /* TGPR usage on 602/603                        x        */
 449 #define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC x       */
 450 #define MSR_ILE  16 /* Interrupt little-endian mode                          */
 451 #define MSR_EE   15 /* External interrupt enable                             */
 452 #define MSR_PR   14 /* Problem state                                  hflags */
 453 #define MSR_FP   13 /* Floating point available                       hflags */
 454 #define MSR_ME   12 /* Machine check interrupt enable                        */
 455 #define MSR_FE0  11 /* Floating point exception mode 0                hflags */
 456 #define MSR_SE   10 /* Single-step trace enable                     x hflags */
 457 #define MSR_DWE  10 /* Debug wait enable on 405                     x        */
 458 #define MSR_UBLE 10 /* User BTB lock enable on e500                 x        */
 459 #define MSR_BE   9  /* Branch trace enable                          x hflags */
 460 #define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC  x        */
 461 #define MSR_FE1  8  /* Floating point exception mode 1                hflags */
 462 #define MSR_AL   7  /* AL bit on POWER                                       */
 463 #define MSR_EP   6  /* Exception prefix on 601                               */
 464 #define MSR_IR   5  /* Instruction relocate                                  */
 465 #define MSR_DR   4  /* Data relocate                                         */
 466 #define MSR_PE   3  /* Protection enable on 403                              */
 467 #define MSR_PX   2  /* Protection exclusive on 403                  x        */
 468 #define MSR_PMM  2  /* Performance monitor mark on POWER            x        */
 469 #define MSR_RI   1  /* Recoverable interrupt                        1        */
 470 #define MSR_LE   0  /* Little-endian mode                           1 hflags */
 471
 472 #define msr_sf   ((env->msr >> MSR_SF)   & 1)
 473 #define msr_isf  ((env->msr >> MSR_ISF)  & 1)
 474 #define msr_shv  ((env->msr >> MSR_SHV)  & 1)
 475 #define msr_cm   ((env->msr >> MSR_CM)   & 1)
 476 #define msr_icm  ((env->msr >> MSR_ICM)  & 1)
 477 #define msr_thv  ((env->msr >> MSR_THV)  & 1)
 478 #define msr_gs   ((env->msr >> MSR_GS)   & 1)
 479 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
 480 #define msr_vr   ((env->msr >> MSR_VR)   & 1)
 481 #define msr_spe  ((env->msr >> MSR_SPE)  & 1)
 482 #define msr_ap   ((env->msr >> MSR_AP)   & 1)
 483 #define msr_sa   ((env->msr >> MSR_SA)   & 1)
 484 #define msr_key  ((env->msr >> MSR_KEY)  & 1)
 485 #define msr_pow  ((env->msr >> MSR_POW)  & 1)
 486 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
 487 #define msr_ce   ((env->msr >> MSR_CE)   & 1)
 488 #define msr_ile  ((env->msr >> MSR_ILE)  & 1)
 489 #define msr_ee   ((env->msr >> MSR_EE)   & 1)
 490 #define msr_pr   ((env->msr >> MSR_PR)   & 1)
 491 #define msr_fp   ((env->msr >> MSR_FP)   & 1)
 492 #define msr_me   ((env->msr >> MSR_ME)   & 1)
 493 #define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
 494 #define msr_se   ((env->msr >> MSR_SE)   & 1)
 495 #define msr_dwe  ((env->msr >> MSR_DWE)  & 1)
 496 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
 497 #define msr_be   ((env->msr >> MSR_BE)   & 1)
 498 #define msr_de   ((env->msr >> MSR_DE)   & 1)
 499 #define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
 500 #define msr_al   ((env->msr >> MSR_AL)   & 1)
 501 #define msr_ep   ((env->msr >> MSR_EP)   & 1)
 502 #define msr_ir   ((env->msr >> MSR_IR)   & 1)
 503 #define msr_dr   ((env->msr >> MSR_DR)   & 1)
 504 #define msr_pe   ((env->msr >> MSR_PE)   & 1)
 505 #define msr_px   ((env->msr >> MSR_PX)   & 1)
 506 #define msr_pmm  ((env->msr >> MSR_PMM)  & 1)
 507 #define msr_ri   ((env->msr >> MSR_RI)   & 1)
 508 #define msr_le   ((env->msr >> MSR_LE)   & 1)
 509 /* Hypervisor bit is more specific */
 510 #if defined(TARGET_PPC64)
 511 #define MSR_HVB (1ULL << MSR_SHV)
 512 #define msr_hv  msr_shv
 513 #else
 514 #if defined(PPC_EMULATE_32BITS_HYPV)
 515 #define MSR_HVB (1ULL << MSR_THV)
 516 #define msr_hv  msr_thv
 517 #else
 518 #define MSR_HVB (0ULL)
 519 #define msr_hv  (0)
 520 #endif
 521 #endif
 522
 523 /* Exception state register bits definition                                  */
 524 #define ESR_PIL   (1 << (63 - 36)) /* Illegal Instruction                    */
 525 #define ESR_PPR   (1 << (63 - 37)) /* Privileged Instruction                 */
 526 #define ESR_PTR   (1 << (63 - 38)) /* Trap                                   */
 527 #define ESR_FP    (1 << (63 - 39)) /* Floating-Point Operation               */
 528 #define ESR_ST    (1 << (63 - 40)) /* Store Operation                        */
 529 #define ESR_AP    (1 << (63 - 44)) /* Auxiliary Processor Operation          */
 530 #define ESR_PUO   (1 << (63 - 45)) /* Unimplemented Operation                */
 531 #define ESR_BO    (1 << (63 - 46)) /* Byte Ordering                          */
 532 #define ESR_PIE   (1 << (63 - 47)) /* Imprecise exception                    */
 533 #define ESR_DATA  (1 << (63 - 53)) /* Data Access (Embedded page table)      */
 534 #define ESR_TLBI  (1 << (63 - 54)) /* TLB Ineligible (Embedded page table)   */
 535 #define ESR_PT    (1 << (63 - 55)) /* Page Table (Embedded page table)       */
 536 #define ESR_SPV   (1 << (63 - 56)) /* SPE/VMX operation                      */
 537 #define ESR_EPID  (1 << (63 - 57)) /* External Process ID operation          */
 538 #define ESR_VLEMI (1 << (63 - 58)) /* VLE operation                          */
 539 #define ESR_MIF   (1 << (63 - 62)) /* Misaligned instruction (VLE)           */
 540
 541 enum {
 542     POWERPC_FLAG_NONE     = 0x00000000,
 543     /* Flag for MSR bit 25 signification (VRE/SPE)                           */
 544     POWERPC_FLAG_SPE      = 0x00000001,
 545     POWERPC_FLAG_VRE      = 0x00000002,
 546     /* Flag for MSR bit 17 signification (TGPR/CE)                           */
 547     POWERPC_FLAG_TGPR     = 0x00000004,
 548     POWERPC_FLAG_CE       = 0x00000008,
 549     /* Flag for MSR bit 10 signification (SE/DWE/UBLE)                       */
 550     POWERPC_FLAG_SE       = 0x00000010,
 551     POWERPC_FLAG_DWE      = 0x00000020,
 552     POWERPC_FLAG_UBLE     = 0x00000040,
 553     /* Flag for MSR bit 9 signification (BE/DE)                              */
 554     POWERPC_FLAG_BE       = 0x00000080,
 555     POWERPC_FLAG_DE       = 0x00000100,
 556     /* Flag for MSR bit 2 signification (PX/PMM)                             */
 557     POWERPC_FLAG_PX       = 0x00000200,
 558     POWERPC_FLAG_PMM      = 0x00000400,
 559     /* Flag for special features                                             */
 560     /* Decrementer clock: RTC clock (POWER, 601) or bus clock                */
 561     POWERPC_FLAG_RTC_CLK  = 0x00010000,
 562     POWERPC_FLAG_BUS_CLK  = 0x00020000,
 563     /* Has CFAR                                                              */
 564     POWERPC_FLAG_CFAR     = 0x00040000,
 565 };
 566
 567 /*****************************************************************************/
 568 /* Floating point status and control register                                */
 569 #define FPSCR_FX     31 /* Floating-point exception summary                  */
 570 #define FPSCR_FEX    30 /* Floating-point enabled exception summary          */
 571 #define FPSCR_VX     29 /* Floating-point invalid operation exception summ.  */
 572 #define FPSCR_OX     28 /* Floating-point overflow exception                 */
 573 #define FPSCR_UX     27 /* Floating-point underflow exception                */
 574 #define FPSCR_ZX     26 /* Floating-point zero divide exception              */
 575 #define FPSCR_XX     25 /* Floating-point inexact exception                  */
 576 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
 577 #define FPSCR_VXISI  23 /* Floating-point invalid operation exception (inf)  */
 578 #define FPSCR_VXIDI  22 /* Floating-point invalid operation exception (inf)  */
 579 #define FPSCR_VXZDZ  21 /* Floating-point invalid operation exception (zero) */
 580 #define FPSCR_VXIMZ  20 /* Floating-point invalid operation exception (inf)  */
 581 #define FPSCR_VXVC   19 /* Floating-point invalid operation exception (comp) */
 582 #define FPSCR_FR     18 /* Floating-point fraction rounded                   */
 583 #define FPSCR_FI     17 /* Floating-point fraction inexact                   */
 584 #define FPSCR_C      16 /* Floating-point result class descriptor            */
 585 #define FPSCR_FL     15 /* Floating-point less than or negative              */
 586 #define FPSCR_FG     14 /* Floating-point greater than or negative           */
 587 #define FPSCR_FE     13 /* Floating-point equal or zero                      */
 588 #define FPSCR_FU     12 /* Floating-point unordered or NaN                   */
 589 #define FPSCR_FPCC   12 /* Floating-point condition code                     */
 590 #define FPSCR_FPRF   12 /* Floating-point result flags                       */
 591 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
 592 #define FPSCR_VXSQRT 9  /* Floating-point invalid operation exception (sqrt) */
 593 #define FPSCR_VXCVI  8  /* Floating-point invalid operation exception (int)  */
 594 #define FPSCR_VE     7  /* Floating-point invalid operation exception enable */
 595 #define FPSCR_OE     6  /* Floating-point overflow exception enable          */
 596 #define FPSCR_UE     5  /* Floating-point undeflow exception enable          */
 597 #define FPSCR_ZE     4  /* Floating-point zero divide exception enable       */
 598 #define FPSCR_XE     3  /* Floating-point inexact exception enable           */
 599 #define FPSCR_NI     2  /* Floating-point non-IEEE mode                      */
 600 #define FPSCR_RN1    1
 601 #define FPSCR_RN     0  /* Floating-point rounding control                   */
 602 #define fpscr_fex    (((env->fpscr) >> FPSCR_FEX)    & 0x1)
 603 #define fpscr_vx     (((env->fpscr) >> FPSCR_VX)     & 0x1)
 604 #define fpscr_ox     (((env->fpscr) >> FPSCR_OX)     & 0x1)
 605 #define fpscr_ux     (((env->fpscr) >> FPSCR_UX)     & 0x1)
 606 #define fpscr_zx     (((env->fpscr) >> FPSCR_ZX)     & 0x1)
 607 #define fpscr_xx     (((env->fpscr) >> FPSCR_XX)     & 0x1)
 608 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
 609 #define fpscr_vxisi  (((env->fpscr) >> FPSCR_VXISI)  & 0x1)
 610 #define fpscr_vxidi  (((env->fpscr) >> FPSCR_VXIDI)  & 0x1)
 611 #define fpscr_vxzdz  (((env->fpscr) >> FPSCR_VXZDZ)  & 0x1)
 612 #define fpscr_vximz  (((env->fpscr) >> FPSCR_VXIMZ)  & 0x1)
 613 #define fpscr_vxvc   (((env->fpscr) >> FPSCR_VXVC)   & 0x1)
 614 #define fpscr_fpcc   (((env->fpscr) >> FPSCR_FPCC)   & 0xF)
 615 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
 616 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
 617 #define fpscr_vxcvi  (((env->fpscr) >> FPSCR_VXCVI)  & 0x1)
 618 #define fpscr_ve     (((env->fpscr) >> FPSCR_VE)     & 0x1)
 619 #define fpscr_oe     (((env->fpscr) >> FPSCR_OE)     & 0x1)
 620 #define fpscr_ue     (((env->fpscr) >> FPSCR_UE)     & 0x1)
 621 #define fpscr_ze     (((env->fpscr) >> FPSCR_ZE)     & 0x1)
 622 #define fpscr_xe     (((env->fpscr) >> FPSCR_XE)     & 0x1)
 623 #define fpscr_ni     (((env->fpscr) >> FPSCR_NI)     & 0x1)
 624 #define fpscr_rn     (((env->fpscr) >> FPSCR_RN)     & 0x3)
 625 /* Invalid operation exception summary */
 626 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI)  | \
 627                                   (1 << FPSCR_VXIDI)  | (1 << FPSCR_VXZDZ)  | \
 628                                   (1 << FPSCR_VXIMZ)  | (1 << FPSCR_VXVC)   | \
 629                                   (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
 630                                   (1 << FPSCR_VXCVI)))
 631 /* exception summary */
 632 #define fpscr_ex  (((env->fpscr) >> FPSCR_XX) & 0x1F)
 633 /* enabled exception summary */
 634 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) &  \
 635                    0x1F)
 636
 637 /*****************************************************************************/
 638 /* Vector status and control register */
 639 #define VSCR_NJ         16 /* Vector non-java */
 640 #define VSCR_SAT        0 /* Vector saturation */
 641 #define vscr_nj         (((env->vscr) >> VSCR_NJ)       & 0x1)
 642 #define vscr_sat        (((env->vscr) >> VSCR_SAT)      & 0x1)
 643
 644 /*****************************************************************************/
 645 /* BookE e500 MMU registers */
 646
 647 #define MAS0_NV_SHIFT      0
 648 #define MAS0_NV_MASK       (0xfff << MAS0_NV_SHIFT)
 649
 650 #define MAS0_WQ_SHIFT      12
 651 #define MAS0_WQ_MASK       (3 << MAS0_WQ_SHIFT)
 652 /* Write TLB entry regardless of reservation */
 653 #define MAS0_WQ_ALWAYS     (0 << MAS0_WQ_SHIFT)
 654 /* Write TLB entry only already in use */
 655 #define MAS0_WQ_COND       (1 << MAS0_WQ_SHIFT)
 656 /* Clear TLB entry */
 657 #define MAS0_WQ_CLR_RSRV   (2 << MAS0_WQ_SHIFT)
 658
 659 #define MAS0_HES_SHIFT     14
 660 #define MAS0_HES           (1 << MAS0_HES_SHIFT)
 661
 662 #define MAS0_ESEL_SHIFT    16
 663 #define MAS0_ESEL_MASK     (0xfff << MAS0_ESEL_SHIFT)
 664
 665 #define MAS0_TLBSEL_SHIFT  28
 666 #define MAS0_TLBSEL_MASK   (3 << MAS0_TLBSEL_SHIFT)
 667 #define MAS0_TLBSEL_TLB0   (0 << MAS0_TLBSEL_SHIFT)
 668 #define MAS0_TLBSEL_TLB1   (1 << MAS0_TLBSEL_SHIFT)
 669 #define MAS0_TLBSEL_TLB2   (2 << MAS0_TLBSEL_SHIFT)
 670 #define MAS0_TLBSEL_TLB3   (3 << MAS0_TLBSEL_SHIFT)
 671
 672 #define MAS0_ATSEL_SHIFT   31
 673 #define MAS0_ATSEL         (1 << MAS0_ATSEL_SHIFT)
 674 #define MAS0_ATSEL_TLB     0
 675 #define MAS0_ATSEL_LRAT    MAS0_ATSEL
 676
 677 #define MAS1_TSIZE_SHIFT   7
 678 #define MAS1_TSIZE_MASK    (0x1f << MAS1_TSIZE_SHIFT)
 679
 680 #define MAS1_TS_SHIFT      12
 681 #define MAS1_TS            (1 << MAS1_TS_SHIFT)
 682
 683 #define MAS1_IND_SHIFT     13
 684 #define MAS1_IND           (1 << MAS1_IND_SHIFT)
 685
 686 #define MAS1_TID_SHIFT     16
 687 #define MAS1_TID_MASK      (0x3fff << MAS1_TID_SHIFT)
 688
 689 #define MAS1_IPROT_SHIFT   30
 690 #define MAS1_IPROT         (1 << MAS1_IPROT_SHIFT)
 691
 692 #define MAS1_VALID_SHIFT   31
 693 #define MAS1_VALID         0x80000000
 694
 695 #define MAS2_EPN_SHIFT     12
 696 #define MAS2_EPN_MASK      (~0ULL << MAS2_EPN_SHIFT)
 697
 698 #define MAS2_ACM_SHIFT     6
 699 #define MAS2_ACM           (1 << MAS2_ACM_SHIFT)
 700
 701 #define MAS2_VLE_SHIFT     5
 702 #define MAS2_VLE           (1 << MAS2_VLE_SHIFT)
 703
 704 #define MAS2_W_SHIFT       4
 705 #define MAS2_W             (1 << MAS2_W_SHIFT)
 706
 707 #define MAS2_I_SHIFT       3
 708 #define MAS2_I             (1 << MAS2_I_SHIFT)
 709
 710 #define MAS2_M_SHIFT       2
 711 #define MAS2_M             (1 << MAS2_M_SHIFT)
 712
 713 #define MAS2_G_SHIFT       1
 714 #define MAS2_G             (1 << MAS2_G_SHIFT)
 715
 716 #define MAS2_E_SHIFT       0
 717 #define MAS2_E             (1 << MAS2_E_SHIFT)
 718
 719 #define MAS3_RPN_SHIFT     12
 720 #define MAS3_RPN_MASK      (0xfffff << MAS3_RPN_SHIFT)
 721
 722 #define MAS3_U0                 0x00000200
 723 #define MAS3_U1                 0x00000100
 724 #define MAS3_U2                 0x00000080
 725 #define MAS3_U3                 0x00000040
 726 #define MAS3_UX                 0x00000020
 727 #define MAS3_SX                 0x00000010
 728 #define MAS3_UW                 0x00000008
 729 #define MAS3_SW                 0x00000004
 730 #define MAS3_UR                 0x00000002
 731 #define MAS3_SR                 0x00000001
 732 #define MAS3_SPSIZE_SHIFT       1
 733 #define MAS3_SPSIZE_MASK        (0x3e << MAS3_SPSIZE_SHIFT)
 734
 735 #define MAS4_TLBSELD_SHIFT      MAS0_TLBSEL_SHIFT
 736 #define MAS4_TLBSELD_MASK       MAS0_TLBSEL_MASK
 737 #define MAS4_TIDSELD_MASK       0x00030000
 738 #define MAS4_TIDSELD_PID0       0x00000000
 739 #define MAS4_TIDSELD_PID1       0x00010000
 740 #define MAS4_TIDSELD_PID2       0x00020000
 741 #define MAS4_TIDSELD_PIDZ       0x00030000
 742 #define MAS4_INDD               0x00008000      /* Default IND */
 743 #define MAS4_TSIZED_SHIFT       MAS1_TSIZE_SHIFT
 744 #define MAS4_TSIZED_MASK        MAS1_TSIZE_MASK
 745 #define MAS4_ACMD               0x00000040
 746 #define MAS4_VLED               0x00000020
 747 #define MAS4_WD                 0x00000010
 748 #define MAS4_ID                 0x00000008
 749 #define MAS4_MD                 0x00000004
 750 #define MAS4_GD                 0x00000002
 751 #define MAS4_ED                 0x00000001
 752 #define MAS4_WIMGED_MASK        0x0000001f      /* Default WIMGE */
 753 #define MAS4_WIMGED_SHIFT       0
 754
 755 #define MAS5_SGS                0x80000000
 756 #define MAS5_SLPID_MASK         0x00000fff
 757
 758 #define MAS6_SPID0              0x3fff0000
 759 #define MAS6_SPID1              0x00007ffe
 760 #define MAS6_ISIZE(x)           MAS1_TSIZE(x)
 761 #define MAS6_SAS                0x00000001
 762 #define MAS6_SPID               MAS6_SPID0
 763 #define MAS6_SIND               0x00000002      /* Indirect page */
 764 #define MAS6_SIND_SHIFT         1
 765 #define MAS6_SPID_MASK          0x3fff0000
 766 #define MAS6_SPID_SHIFT         16
 767 #define MAS6_ISIZE_MASK         0x00000f80
 768 #define MAS6_ISIZE_SHIFT        7
 769
 770 #define MAS7_RPN                0xffffffff
 771
 772 #define MAS8_TGS                0x80000000
 773 #define MAS8_VF                 0x40000000
 774 #define MAS8_TLBPID             0x00000fff
 775
 776 /* Bit definitions for MMUCFG */
 777 #define MMUCFG_MAVN     0x00000003      /* MMU Architecture Version Number */
 778 #define MMUCFG_MAVN_V1  0x00000000      /* v1.0 */
 779 #define MMUCFG_MAVN_V2  0x00000001      /* v2.0 */
 780 #define MMUCFG_NTLBS    0x0000000c      /* Number of TLBs */
 781 #define MMUCFG_PIDSIZE  0x000007c0      /* PID Reg Size */
 782 #define MMUCFG_TWC      0x00008000      /* TLB Write Conditional (v2.0) */
 783 #define MMUCFG_LRAT     0x00010000      /* LRAT Supported (v2.0) */
 784 #define MMUCFG_RASIZE   0x00fe0000      /* Real Addr Size */
 785 #define MMUCFG_LPIDSIZE 0x0f000000      /* LPID Reg Size */
 786
 787 /* Bit definitions for MMUCSR0 */
 788 #define MMUCSR0_TLB1FI  0x00000002      /* TLB1 Flash invalidate */
 789 #define MMUCSR0_TLB0FI  0x00000004      /* TLB0 Flash invalidate */
 790 #define MMUCSR0_TLB2FI  0x00000040      /* TLB2 Flash invalidate */
 791 #define MMUCSR0_TLB3FI  0x00000020      /* TLB3 Flash invalidate */
 792 #define MMUCSR0_TLBFI   (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
 793                          MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
 794 #define MMUCSR0_TLB0PS  0x00000780      /* TLB0 Page Size */
 795 #define MMUCSR0_TLB1PS  0x00007800      /* TLB1 Page Size */
 796 #define MMUCSR0_TLB2PS  0x00078000      /* TLB2 Page Size */
 797 #define MMUCSR0_TLB3PS  0x00780000      /* TLB3 Page Size */
 798
 799 /* TLBnCFG encoding */
 800 #define TLBnCFG_N_ENTRY         0x00000fff      /* number of entries */
 801 #define TLBnCFG_HES             0x00002000      /* HW select supported */
 802 #define TLBnCFG_AVAIL           0x00004000      /* variable page size */
 803 #define TLBnCFG_IPROT           0x00008000      /* IPROT supported */
 804 #define TLBnCFG_GTWE            0x00010000      /* Guest can write */
 805 #define TLBnCFG_IND             0x00020000      /* IND entries supported */
 806 #define TLBnCFG_PT              0x00040000      /* Can load from page table */
 807 #define TLBnCFG_MINSIZE         0x00f00000      /* Minimum Page Size (v1.0) */
 808 #define TLBnCFG_MINSIZE_SHIFT   20
 809 #define TLBnCFG_MAXSIZE         0x000f0000      /* Maximum Page Size (v1.0) */
 810 #define TLBnCFG_MAXSIZE_SHIFT   16
 811 #define TLBnCFG_ASSOC           0xff000000      /* Associativity */
 812 #define TLBnCFG_ASSOC_SHIFT     24
 813
 814 /* TLBnPS encoding */
 815 #define TLBnPS_4K               0x00000004
 816 #define TLBnPS_8K               0x00000008
 817 #define TLBnPS_16K              0x00000010
 818 #define TLBnPS_32K              0x00000020
 819 #define TLBnPS_64K              0x00000040
 820 #define TLBnPS_128K             0x00000080
 821 #define TLBnPS_256K             0x00000100
 822 #define TLBnPS_512K             0x00000200
 823 #define TLBnPS_1M               0x00000400
 824 #define TLBnPS_2M               0x00000800
 825 #define TLBnPS_4M               0x00001000
 826 #define TLBnPS_8M               0x00002000
 827 #define TLBnPS_16M              0x00004000
 828 #define TLBnPS_32M              0x00008000
 829 #define TLBnPS_64M              0x00010000
 830 #define TLBnPS_128M             0x00020000
 831 #define TLBnPS_256M             0x00040000
 832 #define TLBnPS_512M             0x00080000
 833 #define TLBnPS_1G               0x00100000
 834 #define TLBnPS_2G               0x00200000
 835 #define TLBnPS_4G               0x00400000
 836 #define TLBnPS_8G               0x00800000
 837 #define TLBnPS_16G              0x01000000
 838 #define TLBnPS_32G              0x02000000
 839 #define TLBnPS_64G              0x04000000
 840 #define TLBnPS_128G             0x08000000
 841 #define TLBnPS_256G             0x10000000
 842
 843 /* tlbilx action encoding */
 844 #define TLBILX_T_ALL                    0
 845 #define TLBILX_T_TID                    1
 846 #define TLBILX_T_FULLMATCH              3
 847 #define TLBILX_T_CLASS0                 4
 848 #define TLBILX_T_CLASS1                 5
 849 #define TLBILX_T_CLASS2                 6
 850 #define TLBILX_T_CLASS3                 7
 851
 852 /* BookE 2.06 helper defines */
 853
 854 #define BOOKE206_FLUSH_TLB0    (1 << 0)
 855 #define BOOKE206_FLUSH_TLB1    (1 << 1)
 856 #define BOOKE206_FLUSH_TLB2    (1 << 2)
 857 #define BOOKE206_FLUSH_TLB3    (1 << 3)
 858
 859 /* number of possible TLBs */
 860 #define BOOKE206_MAX_TLBN      4
 861
 862 /*****************************************************************************/
 863 /* Embedded.Processor Control */
 864
 865 #define DBELL_TYPE_SHIFT               27
 866 #define DBELL_TYPE_MASK                (0x1f << DBELL_TYPE_SHIFT)
 867 #define DBELL_TYPE_DBELL               (0x00 << DBELL_TYPE_SHIFT)
 868 #define DBELL_TYPE_DBELL_CRIT          (0x01 << DBELL_TYPE_SHIFT)
 869 #define DBELL_TYPE_G_DBELL             (0x02 << DBELL_TYPE_SHIFT)
 870 #define DBELL_TYPE_G_DBELL_CRIT        (0x03 << DBELL_TYPE_SHIFT)
 871 #define DBELL_TYPE_G_DBELL_MC          (0x04 << DBELL_TYPE_SHIFT)
 872
 873 #define DBELL_BRDCAST                  (1 << 26)
 874 #define DBELL_LPIDTAG_SHIFT            14
 875 #define DBELL_LPIDTAG_MASK             (0xfff << DBELL_LPIDTAG_SHIFT)
 876 #define DBELL_PIRTAG_MASK              0x3fff
 877
 878 /*****************************************************************************/
 879 /* Segment page size information, used by recent hash MMUs
 880  * The format of this structure mirrors kvm_ppc_smmu_info
 881  */
 882
 883 #define PPC_PAGE_SIZES_MAX_SZ   8
 884
 885 struct ppc_one_page_size {
 886     uint32_t page_shift;  /* Page shift (or 0) */
 887     uint32_t pte_enc;     /* Encoding in the HPTE (>>12) */
 888 };
 889
 890 struct ppc_one_seg_page_size {
 891     uint32_t page_shift;  /* Base page shift of segment (or 0) */
 892     uint32_t slb_enc;     /* SLB encoding for BookS */
 893     struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
 894 };
 895
 896 struct ppc_segment_page_sizes {
 897     struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
 898 };
 899
 900
 901 /*****************************************************************************/
 902 /* The whole PowerPC CPU context */
 903 #define NB_MMU_MODES 3
 904
 905 struct ppc_def_t {
 906     const char *name;
 907     uint32_t pvr;
 908     uint32_t svr;
 909     uint64_t insns_flags;
 910     uint64_t insns_flags2;
 911     uint64_t msr_mask;
 912     powerpc_mmu_t   mmu_model;
 913     powerpc_excp_t  excp_model;
 914     powerpc_input_t bus_model;
 915     uint32_t flags;
 916     int bfd_mach;
 917 #if defined(TARGET_PPC64)
 918     const struct ppc_segment_page_sizes *sps;
 919 #endif
 920     void (*init_proc)(CPUPPCState *env);
 921     int  (*check_pow)(CPUPPCState *env);
 922 };
 923
 924 struct CPUPPCState {
 925     /* First are the most commonly used resources
 926      * during translated code execution
 927      */
 928     /* general purpose registers */
 929     target_ulong gpr[32];
 930 #if !defined(TARGET_PPC64)
 931     /* Storage for GPR MSB, used by the SPE extension */
 932     target_ulong gprh[32];
 933 #endif
 934     /* LR */
 935     target_ulong lr;
 936     /* CTR */
 937     target_ulong ctr;
 938     /* condition register */
 939     uint32_t crf[8];
 940 #if defined(TARGET_PPC64)
 941     /* CFAR */
 942     target_ulong cfar;
 943 #endif
 944     /* XER */
 945     target_ulong xer;
 946     /* Reservation address */
 947     target_ulong reserve_addr;
 948     /* Reservation value */
 949     target_ulong reserve_val;
 950     /* Reservation store address */
 951     target_ulong reserve_ea;
 952     /* Reserved store source register and size */
 953     target_ulong reserve_info;
 954
 955     /* Those ones are used in supervisor mode only */
 956     /* machine state register */
 957     target_ulong msr;
 958     /* temporary general purpose registers */
 959     target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
 960
 961     /* Floating point execution context */
 962     float_status fp_status;
 963     /* floating point registers */
 964     float64 fpr[32];
 965     /* floating point status and control register */
 966     target_ulong fpscr;
 967
 968     /* Next instruction pointer */
 969     target_ulong nip;
 970
 971     int access_type; /* when a memory exception occurs, the access
 972                         type is stored here */
 973
 974     CPU_COMMON
 975
 976     /* MMU context - only relevant for full system emulation */
 977 #if !defined(CONFIG_USER_ONLY)
 978 #if defined(TARGET_PPC64)
 979     /* Address space register */
 980     target_ulong asr;
 981     /* PowerPC 64 SLB area */
 982     ppc_slb_t slb[64];
 983     int slb_nr;
 984 #endif
 985     /* segment registers */
 986     hwaddr htab_base;
 987     hwaddr htab_mask;
 988     target_ulong sr[32];
 989     /* externally stored hash table */
 990     uint8_t *external_htab;
 991     /* BATs */
 992     int nb_BATs;
 993     target_ulong DBAT[2][8];
 994     target_ulong IBAT[2][8];
 995     /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
 996     int nb_tlb;      /* Total number of TLB                                  */
 997     int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
 998     int nb_ways;     /* Number of ways in the TLB set                        */
 999     int last_way;    /* Last used way used to allocate TLB in a LRU way      */
1000     int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */
1001     int nb_pids;     /* Number of available PID registers                    */
1002     int tlb_type;    /* Type of TLB we're dealing with                       */
1003     ppc_tlb_t tlb;   /* TLB is optional. Allocate them only if needed        */
1004     /* 403 dedicated access protection registers */
1005     target_ulong pb[4];
1006     bool tlb_dirty;   /* Set to non-zero when modifying TLB                  */
1007     bool kvm_sw_tlb;  /* non-zero if KVM SW TLB API is active                */
1008 #endif
1009
1010     /* Other registers */
1011     /* Special purpose registers */
1012     target_ulong spr[1024];
1013     ppc_spr_t spr_cb[1024];
1014     /* Altivec registers */
1015     ppc_avr_t avr[32];
1016     uint32_t vscr;
1017     /* VSX registers */
1018     uint64_t vsr[32];
1019     /* SPE registers */
1020     uint64_t spe_acc;
1021     uint32_t spe_fscr;
1022     /* SPE and Altivec can share a status since they will never be used
1023      * simultaneously */
1024     float_status vec_status;
1025
1026     /* Internal devices resources */
1027     /* Time base and decrementer */
1028     ppc_tb_t *tb_env;
1029     /* Device control registers */
1030     ppc_dcr_t *dcr_env;
1031
1032     int dcache_line_size;
1033     int icache_line_size;
1034
1035     /* Those resources are used during exception processing */
1036     /* CPU model definition */
1037     target_ulong msr_mask;
1038     powerpc_mmu_t mmu_model;
1039     powerpc_excp_t excp_model;
1040     powerpc_input_t bus_model;
1041     int bfd_mach;
1042     uint32_t flags;
1043     uint64_t insns_flags;
1044     uint64_t insns_flags2;
1045 #if defined(TARGET_PPC64)
1046     struct ppc_segment_page_sizes sps;
1047 #endif
1048
1049 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1050     uint64_t vpa_addr;
1051     uint64_t slb_shadow_addr, slb_shadow_size;
1052     uint64_t dtl_addr, dtl_size;
1053 #endif /* TARGET_PPC64 */
1054
1055     int error_code;
1056     uint32_t pending_interrupts;
1057 #if !defined(CONFIG_USER_ONLY)
1058     /* This is the IRQ controller, which is implementation dependent
1059      * and only relevant when emulating a complete machine.
1060      */
1061     uint32_t irq_input_state;
1062     void **irq_inputs;
1063     /* Exception vectors */
1064     target_ulong excp_vectors[POWERPC_EXCP_NB];
1065     target_ulong excp_prefix;
1066     target_ulong hreset_excp_prefix;
1067     target_ulong ivor_mask;
1068     target_ulong ivpr_mask;
1069     target_ulong hreset_vector;
1070     hwaddr mpic_cpu_base;
1071 #endif
1072
1073     /* Those resources are used only during code translation */
1074     /* opcode handlers */
1075     opc_handler_t *opcodes[0x40];
1076
1077     /* Those resources are used only in QEMU core */
1078     target_ulong hflags;      /* hflags is a MSR & HFLAGS_MASK         */
1079     target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
1080     int mmu_idx;         /* precomputed MMU index to speed up mem accesses */
1081
1082     /* Power management */
1083     int (*check_pow)(CPUPPCState *env);
1084
1085 #if !defined(CONFIG_USER_ONLY)
1086     void *load_info;    /* Holds boot loading state.  */
1087 #endif
1088
1089     /* booke timers */
1090
1091     /* Specifies bit locations of the Time Base used to signal a fixed timer
1092      * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1093      *
1094      * 0 selects the least significant bit.
1095      * 63 selects the most significant bit.
1096      */
1097     uint8_t fit_period[4];
1098     uint8_t wdt_period[4];
1099 };
1100
1101 #define SET_FIT_PERIOD(a_, b_, c_, d_)          \
1102 do {                                            \
1103     env->fit_period[0] = (a_);                  \
1104     env->fit_period[1] = (b_);                  \
1105     env->fit_period[2] = (c_);                  \
1106     env->fit_period[3] = (d_);                  \
1107  } while (0)
1108
1109 #define SET_WDT_PERIOD(a_, b_, c_, d_)          \
1110 do {                                            \
1111     env->wdt_period[0] = (a_);                  \
1112     env->wdt_period[1] = (b_);                  \
1113     env->wdt_period[2] = (c_);                  \
1114     env->wdt_period[3] = (d_);                  \
1115  } while (0)
1116
1117 #if !defined(CONFIG_USER_ONLY)
1118 /* Context used internally during MMU translations */
1119 typedef struct mmu_ctx_t mmu_ctx_t;
1120 struct mmu_ctx_t {
1121     hwaddr raddr;      /* Real address              */
1122     hwaddr eaddr;      /* Effective address         */
1123     int prot;                      /* Protection bits           */
1124     hwaddr hash[2];    /* Pagetable hash values     */
1125     target_ulong ptem;             /* Virtual segment ID | API  */
1126     int key;                       /* Access key                */
1127     int nx;                        /* Non-execute area          */
1128 };
1129 #endif
1130
1131 #include "cpu-qom.h"
1132
1133 /*****************************************************************************/
1134 PowerPCCPU *cpu_ppc_init(const char *cpu_model);
1135 void ppc_translate_init(void);
1136 int cpu_ppc_exec (CPUPPCState *s);
1137 /* you can call this signal handler from your SIGBUS and SIGSEGV
1138    signal handlers to inform the virtual CPU of exceptions. non zero
1139    is returned if the signal was handled by the virtual CPU.  */
1140 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1141                             void *puc);
1142 int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
1143                               int mmu_idx);
1144 #define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault
1145 void do_interrupt (CPUPPCState *env);
1146 void ppc_hw_interrupt (CPUPPCState *env);
1147
1148 #if !defined(CONFIG_USER_ONLY)
1149 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
1150 #if defined(TARGET_PPC64)
1151 void ppc_store_asr (CPUPPCState *env, target_ulong value);
1152 int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
1153 #endif /* defined(TARGET_PPC64) */
1154 #endif /* !defined(CONFIG_USER_ONLY) */
1155 void ppc_store_msr (CPUPPCState *env, target_ulong value);
1156
1157 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
1158
1159 const ppc_def_t *ppc_find_by_pvr(uint32_t pvr);
1160 const ppc_def_t *cpu_ppc_find_by_name (const char *name);
1161 int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def);
1162
1163 /* Time-base and decrementer management */
1164 #ifndef NO_CPU_IO_DEFS
1165 uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
1166 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1167 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1168 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
1169 uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
1170 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1171 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1172 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
1173 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1174 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
1175 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1176 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1177 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
1178 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1179 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1180 #if !defined(CONFIG_USER_ONLY)
1181 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1182 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1183 target_ulong load_40x_pit (CPUPPCState *env);
1184 void store_40x_pit (CPUPPCState *env, target_ulong val);
1185 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
1186 void store_40x_sler (CPUPPCState *env, uint32_t val);
1187 void store_booke_tcr (CPUPPCState *env, target_ulong val);
1188 void store_booke_tsr (CPUPPCState *env, target_ulong val);
1189 int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb,
1190                      hwaddr *raddrp, target_ulong address,
1191                      uint32_t pid);
1192 void ppc_tlb_invalidate_all (CPUPPCState *env);
1193 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
1194 #endif
1195 #endif
1196
1197 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1198 {
1199     uint64_t gprv;
1200
1201     gprv = env->gpr[gprn];
1202 #if !defined(TARGET_PPC64)
1203     if (env->flags & POWERPC_FLAG_SPE) {
1204         /* If the CPU implements the SPE extension, we have to get the
1205          * high bits of the GPR from the gprh storage area
1206          */
1207         gprv &= 0xFFFFFFFFULL;
1208         gprv |= (uint64_t)env->gprh[gprn] << 32;
1209     }
1210 #endif
1211
1212     return gprv;
1213 }
1214
1215 /* Device control registers */
1216 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1217 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1218
1219 static inline CPUPPCState *cpu_init(const char *cpu_model)
1220 {
1221     PowerPCCPU *cpu = cpu_ppc_init(cpu_model);
1222     if (cpu == NULL) {
1223         return NULL;
1224     }
1225     return &cpu->env;
1226 }
1227
1228 #define cpu_exec cpu_ppc_exec
1229 #define cpu_gen_code cpu_ppc_gen_code
1230 #define cpu_signal_handler cpu_ppc_signal_handler
1231 #define cpu_list ppc_cpu_list
1232
1233 #define CPU_SAVE_VERSION 4
1234
1235 /* MMU modes definitions */
1236 #define MMU_MODE0_SUFFIX _user
1237 #define MMU_MODE1_SUFFIX _kernel
1238 #define MMU_MODE2_SUFFIX _hypv
1239 #define MMU_USER_IDX 0
1240 static inline int cpu_mmu_index (CPUPPCState *env)
1241 {
1242     return env->mmu_idx;
1243 }
1244
1245 #if defined(CONFIG_USER_ONLY)
1246 static inline void cpu_clone_regs(CPUPPCState *env, target_ulong newsp)
1247 {
1248     if (newsp)
1249         env->gpr[1] = newsp;
1250     env->gpr[3] = 0;
1251 }
1252 #endif
1253
1254 #include "cpu-all.h"
1255
1256 /*****************************************************************************/
1257 /* CRF definitions */
1258 #define CRF_LT        3
1259 #define CRF_GT        2
1260 #define CRF_EQ        1
1261 #define CRF_SO        0
1262 #define CRF_CH        (1 << CRF_LT)
1263 #define CRF_CL        (1 << CRF_GT)
1264 #define CRF_CH_OR_CL  (1 << CRF_EQ)
1265 #define CRF_CH_AND_CL (1 << CRF_SO)
1266
1267 /* XER definitions */
1268 #define XER_SO  31
1269 #define XER_OV  30
1270 #define XER_CA  29
1271 #define XER_CMP  8
1272 #define XER_BC   0
1273 #define xer_so  ((env->xer >> XER_SO)  &    1)
1274 #define xer_ov  ((env->xer >> XER_OV)  &    1)
1275 #define xer_ca  ((env->xer >> XER_CA)  &    1)
1276 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1277 #define xer_bc  ((env->xer >> XER_BC)  & 0x7F)
1278
1279 /* SPR definitions */
1280 #define SPR_MQ                (0x000)
1281 #define SPR_XER               (0x001)
1282 #define SPR_601_VRTCU         (0x004)
1283 #define SPR_601_VRTCL         (0x005)
1284 #define SPR_601_UDECR         (0x006)
1285 #define SPR_LR                (0x008)
1286 #define SPR_CTR               (0x009)
1287 #define SPR_DSCR              (0x011)
1288 #define SPR_DSISR             (0x012)
1289 #define SPR_DAR               (0x013) /* DAE for PowerPC 601 */
1290 #define SPR_601_RTCU          (0x014)
1291 #define SPR_601_RTCL          (0x015)
1292 #define SPR_DECR              (0x016)
1293 #define SPR_SDR1              (0x019)
1294 #define SPR_SRR0              (0x01A)
1295 #define SPR_SRR1              (0x01B)
1296 #define SPR_CFAR              (0x01C)
1297 #define SPR_AMR               (0x01D)
1298 #define SPR_BOOKE_PID         (0x030)
1299 #define SPR_BOOKE_DECAR       (0x036)
1300 #define SPR_BOOKE_CSRR0       (0x03A)
1301 #define SPR_BOOKE_CSRR1       (0x03B)
1302 #define SPR_BOOKE_DEAR        (0x03D)
1303 #define SPR_BOOKE_ESR         (0x03E)
1304 #define SPR_BOOKE_IVPR        (0x03F)
1305 #define SPR_MPC_EIE           (0x050)
1306 #define SPR_MPC_EID           (0x051)
1307 #define SPR_MPC_NRI           (0x052)
1308 #define SPR_CTRL              (0x088)
1309 #define SPR_MPC_CMPA          (0x090)
1310 #define SPR_MPC_CMPB          (0x091)
1311 #define SPR_MPC_CMPC          (0x092)
1312 #define SPR_MPC_CMPD          (0x093)
1313 #define SPR_MPC_ECR           (0x094)
1314 #define SPR_MPC_DER           (0x095)
1315 #define SPR_MPC_COUNTA        (0x096)
1316 #define SPR_MPC_COUNTB        (0x097)
1317 #define SPR_UCTRL             (0x098)
1318 #define SPR_MPC_CMPE          (0x098)
1319 #define SPR_MPC_CMPF          (0x099)
1320 #define SPR_MPC_CMPG          (0x09A)
1321 #define SPR_MPC_CMPH          (0x09B)
1322 #define SPR_MPC_LCTRL1        (0x09C)
1323 #define SPR_MPC_LCTRL2        (0x09D)
1324 #define SPR_MPC_ICTRL         (0x09E)
1325 #define SPR_MPC_BAR           (0x09F)
1326 #define SPR_VRSAVE            (0x100)
1327 #define SPR_USPRG0            (0x100)
1328 #define SPR_USPRG1            (0x101)
1329 #define SPR_USPRG2            (0x102)
1330 #define SPR_USPRG3            (0x103)
1331 #define SPR_USPRG4            (0x104)
1332 #define SPR_USPRG5            (0x105)
1333 #define SPR_USPRG6            (0x106)
1334 #define SPR_USPRG7            (0x107)
1335 #define SPR_VTBL              (0x10C)
1336 #define SPR_VTBU              (0x10D)
1337 #define SPR_SPRG0             (0x110)
1338 #define SPR_SPRG1             (0x111)
1339 #define SPR_SPRG2             (0x112)
1340 #define SPR_SPRG3             (0x113)
1341 #define SPR_SPRG4             (0x114)
1342 #define SPR_SCOMC             (0x114)
1343 #define SPR_SPRG5             (0x115)
1344 #define SPR_SCOMD             (0x115)
1345 #define SPR_SPRG6             (0x116)
1346 #define SPR_SPRG7             (0x117)
1347 #define SPR_ASR               (0x118)
1348 #define SPR_EAR               (0x11A)
1349 #define SPR_TBL               (0x11C)
1350 #define SPR_TBU               (0x11D)
1351 #define SPR_TBU40             (0x11E)
1352 #define SPR_SVR               (0x11E)
1353 #define SPR_BOOKE_PIR         (0x11E)
1354 #define SPR_PVR               (0x11F)
1355 #define SPR_HSPRG0            (0x130)
1356 #define SPR_BOOKE_DBSR        (0x130)
1357 #define SPR_HSPRG1            (0x131)
1358 #define SPR_HDSISR            (0x132)
1359 #define SPR_HDAR              (0x133)
1360 #define SPR_BOOKE_EPCR        (0x133)
1361 #define SPR_SPURR             (0x134)
1362 #define SPR_BOOKE_DBCR0       (0x134)
1363 #define SPR_IBCR              (0x135)
1364 #define SPR_PURR              (0x135)
1365 #define SPR_BOOKE_DBCR1       (0x135)
1366 #define SPR_DBCR              (0x136)
1367 #define SPR_HDEC              (0x136)
1368 #define SPR_BOOKE_DBCR2       (0x136)
1369 #define SPR_HIOR              (0x137)
1370 #define SPR_MBAR              (0x137)
1371 #define SPR_RMOR              (0x138)
1372 #define SPR_BOOKE_IAC1        (0x138)
1373 #define SPR_HRMOR             (0x139)
1374 #define SPR_BOOKE_IAC2        (0x139)
1375 #define SPR_HSRR0             (0x13A)
1376 #define SPR_BOOKE_IAC3        (0x13A)
1377 #define SPR_HSRR1             (0x13B)
1378 #define SPR_BOOKE_IAC4        (0x13B)
1379 #define SPR_LPCR              (0x13C)
1380 #define SPR_BOOKE_DAC1        (0x13C)
1381 #define SPR_LPIDR             (0x13D)
1382 #define SPR_DABR2             (0x13D)
1383 #define SPR_BOOKE_DAC2        (0x13D)
1384 #define SPR_BOOKE_DVC1        (0x13E)
1385 #define SPR_BOOKE_DVC2        (0x13F)
1386 #define SPR_BOOKE_TSR         (0x150)
1387 #define SPR_BOOKE_TCR         (0x154)
1388 #define SPR_BOOKE_TLB0PS      (0x158)
1389 #define SPR_BOOKE_TLB1PS      (0x159)
1390 #define SPR_BOOKE_TLB2PS      (0x15A)
1391 #define SPR_BOOKE_TLB3PS      (0x15B)
1392 #define SPR_BOOKE_MAS7_MAS3   (0x174)
1393 #define SPR_BOOKE_IVOR0       (0x190)
1394 #define SPR_BOOKE_IVOR1       (0x191)
1395 #define SPR_BOOKE_IVOR2       (0x192)
1396 #define SPR_BOOKE_IVOR3       (0x193)
1397 #define SPR_BOOKE_IVOR4       (0x194)
1398 #define SPR_BOOKE_IVOR5       (0x195)
1399 #define SPR_BOOKE_IVOR6       (0x196)
1400 #define SPR_BOOKE_IVOR7       (0x197)
1401 #define SPR_BOOKE_IVOR8       (0x198)
1402 #define SPR_BOOKE_IVOR9       (0x199)
1403 #define SPR_BOOKE_IVOR10      (0x19A)
1404 #define SPR_BOOKE_IVOR11      (0x19B)
1405 #define SPR_BOOKE_IVOR12      (0x19C)
1406 #define SPR_BOOKE_IVOR13      (0x19D)
1407 #define SPR_BOOKE_IVOR14      (0x19E)
1408 #define SPR_BOOKE_IVOR15      (0x19F)
1409 #define SPR_BOOKE_IVOR38      (0x1B0)
1410 #define SPR_BOOKE_IVOR39      (0x1B1)
1411 #define SPR_BOOKE_IVOR40      (0x1B2)
1412 #define SPR_BOOKE_IVOR41      (0x1B3)
1413 #define SPR_BOOKE_IVOR42      (0x1B4)
1414 #define SPR_BOOKE_SPEFSCR     (0x200)
1415 #define SPR_Exxx_BBEAR        (0x201)
1416 #define SPR_Exxx_BBTAR        (0x202)
1417 #define SPR_Exxx_L1CFG0       (0x203)
1418 #define SPR_Exxx_NPIDR        (0x205)
1419 #define SPR_ATBL              (0x20E)
1420 #define SPR_ATBU              (0x20F)
1421 #define SPR_IBAT0U            (0x210)
1422 #define SPR_BOOKE_IVOR32      (0x210)
1423 #define SPR_RCPU_MI_GRA       (0x210)
1424 #define SPR_IBAT0L            (0x211)
1425 #define SPR_BOOKE_IVOR33      (0x211)
1426 #define SPR_IBAT1U            (0x212)
1427 #define SPR_BOOKE_IVOR34      (0x212)
1428 #define SPR_IBAT1L            (0x213)
1429 #define SPR_BOOKE_IVOR35      (0x213)
1430 #define SPR_IBAT2U            (0x214)
1431 #define SPR_BOOKE_IVOR36      (0x214)
1432 #define SPR_IBAT2L            (0x215)
1433 #define SPR_BOOKE_IVOR37      (0x215)
1434 #define SPR_IBAT3U            (0x216)
1435 #define SPR_IBAT3L            (0x217)
1436 #define SPR_DBAT0U            (0x218)
1437 #define SPR_RCPU_L2U_GRA      (0x218)
1438 #define SPR_DBAT0L            (0x219)
1439 #define SPR_DBAT1U            (0x21A)
1440 #define SPR_DBAT1L            (0x21B)
1441 #define SPR_DBAT2U            (0x21C)
1442 #define SPR_DBAT2L            (0x21D)
1443 #define SPR_DBAT3U            (0x21E)
1444 #define SPR_DBAT3L            (0x21F)
1445 #define SPR_IBAT4U            (0x230)
1446 #define SPR_RPCU_BBCMCR       (0x230)
1447 #define SPR_MPC_IC_CST        (0x230)
1448 #define SPR_Exxx_CTXCR        (0x230)
1449 #define SPR_IBAT4L            (0x231)
1450 #define SPR_MPC_IC_ADR        (0x231)
1451 #define SPR_Exxx_DBCR3        (0x231)
1452 #define SPR_IBAT5U            (0x232)
1453 #define SPR_MPC_IC_DAT        (0x232)
1454 #define SPR_Exxx_DBCNT        (0x232)
1455 #define SPR_IBAT5L            (0x233)
1456 #define SPR_IBAT6U            (0x234)
1457 #define SPR_IBAT6L            (0x235)
1458 #define SPR_IBAT7U            (0x236)
1459 #define SPR_IBAT7L            (0x237)
1460 #define SPR_DBAT4U            (0x238)
1461 #define SPR_RCPU_L2U_MCR      (0x238)
1462 #define SPR_MPC_DC_CST        (0x238)
1463 #define SPR_Exxx_ALTCTXCR     (0x238)
1464 #define SPR_DBAT4L            (0x239)
1465 #define SPR_MPC_DC_ADR        (0x239)
1466 #define SPR_DBAT5U            (0x23A)
1467 #define SPR_BOOKE_MCSRR0      (0x23A)
1468 #define SPR_MPC_DC_DAT        (0x23A)
1469 #define SPR_DBAT5L            (0x23B)
1470 #define SPR_BOOKE_MCSRR1      (0x23B)
1471 #define SPR_DBAT6U            (0x23C)
1472 #define SPR_BOOKE_MCSR        (0x23C)
1473 #define SPR_DBAT6L            (0x23D)
1474 #define SPR_Exxx_MCAR         (0x23D)
1475 #define SPR_DBAT7U            (0x23E)
1476 #define SPR_BOOKE_DSRR0       (0x23E)
1477 #define SPR_DBAT7L            (0x23F)
1478 #define SPR_BOOKE_DSRR1       (0x23F)
1479 #define SPR_BOOKE_SPRG8       (0x25C)
1480 #define SPR_BOOKE_SPRG9       (0x25D)
1481 #define SPR_BOOKE_MAS0        (0x270)
1482 #define SPR_BOOKE_MAS1        (0x271)
1483 #define SPR_BOOKE_MAS2        (0x272)
1484 #define SPR_BOOKE_MAS3        (0x273)
1485 #define SPR_BOOKE_MAS4        (0x274)
1486 #define SPR_BOOKE_MAS5        (0x275)
1487 #define SPR_BOOKE_MAS6        (0x276)
1488 #define SPR_BOOKE_PID1        (0x279)
1489 #define SPR_BOOKE_PID2        (0x27A)
1490 #define SPR_MPC_DPDR          (0x280)
1491 #define SPR_MPC_IMMR          (0x288)
1492 #define SPR_BOOKE_TLB0CFG     (0x2B0)
1493 #define SPR_BOOKE_TLB1CFG     (0x2B1)
1494 #define SPR_BOOKE_TLB2CFG     (0x2B2)
1495 #define SPR_BOOKE_TLB3CFG     (0x2B3)
1496 #define SPR_BOOKE_EPR         (0x2BE)
1497 #define SPR_PERF0             (0x300)
1498 #define SPR_RCPU_MI_RBA0      (0x300)
1499 #define SPR_MPC_MI_CTR        (0x300)
1500 #define SPR_PERF1             (0x301)
1501 #define SPR_RCPU_MI_RBA1      (0x301)
1502 #define SPR_PERF2             (0x302)
1503 #define SPR_RCPU_MI_RBA2      (0x302)
1504 #define SPR_MPC_MI_AP         (0x302)
1505 #define SPR_PERF3             (0x303)
1506 #define SPR_620_PMC1R         (0x303)
1507 #define SPR_RCPU_MI_RBA3      (0x303)
1508 #define SPR_MPC_MI_EPN        (0x303)
1509 #define SPR_PERF4             (0x304)
1510 #define SPR_620_PMC2R         (0x304)
1511 #define SPR_PERF5             (0x305)
1512 #define SPR_MPC_MI_TWC        (0x305)
1513 #define SPR_PERF6             (0x306)
1514 #define SPR_MPC_MI_RPN        (0x306)
1515 #define SPR_PERF7             (0x307)
1516 #define SPR_PERF8             (0x308)
1517 #define SPR_RCPU_L2U_RBA0     (0x308)
1518 #define SPR_MPC_MD_CTR        (0x308)
1519 #define SPR_PERF9             (0x309)
1520 #define SPR_RCPU_L2U_RBA1     (0x309)
1521 #define SPR_MPC_MD_CASID      (0x309)
1522 #define SPR_PERFA             (0x30A)
1523 #define SPR_RCPU_L2U_RBA2     (0x30A)
1524 #define SPR_MPC_MD_AP         (0x30A)
1525 #define SPR_PERFB             (0x30B)
1526 #define SPR_620_MMCR0R        (0x30B)
1527 #define SPR_RCPU_L2U_RBA3     (0x30B)
1528 #define SPR_MPC_MD_EPN        (0x30B)
1529 #define SPR_PERFC             (0x30C)
1530 #define SPR_MPC_MD_TWB        (0x30C)
1531 #define SPR_PERFD             (0x30D)
1532 #define SPR_MPC_MD_TWC        (0x30D)
1533 #define SPR_PERFE             (0x30E)
1534 #define SPR_MPC_MD_RPN        (0x30E)
1535 #define SPR_PERFF             (0x30F)
1536 #define SPR_MPC_MD_TW         (0x30F)
1537 #define SPR_UPERF0            (0x310)
1538 #define SPR_UPERF1            (0x311)
1539 #define SPR_UPERF2            (0x312)
1540 #define SPR_UPERF3            (0x313)
1541 #define SPR_620_PMC1W         (0x313)
1542 #define SPR_UPERF4            (0x314)
1543 #define SPR_620_PMC2W         (0x314)
1544 #define SPR_UPERF5            (0x315)
1545 #define SPR_UPERF6            (0x316)
1546 #define SPR_UPERF7            (0x317)
1547 #define SPR_UPERF8            (0x318)
1548 #define SPR_UPERF9            (0x319)
1549 #define SPR_UPERFA            (0x31A)
1550 #define SPR_UPERFB            (0x31B)
1551 #define SPR_620_MMCR0W        (0x31B)
1552 #define SPR_UPERFC            (0x31C)
1553 #define SPR_UPERFD            (0x31D)
1554 #define SPR_UPERFE            (0x31E)
1555 #define SPR_UPERFF            (0x31F)
1556 #define SPR_RCPU_MI_RA0       (0x320)
1557 #define SPR_MPC_MI_DBCAM      (0x320)
1558 #define SPR_RCPU_MI_RA1       (0x321)
1559 #define SPR_MPC_MI_DBRAM0     (0x321)
1560 #define SPR_RCPU_MI_RA2       (0x322)
1561 #define SPR_MPC_MI_DBRAM1     (0x322)
1562 #define SPR_RCPU_MI_RA3       (0x323)
1563 #define SPR_RCPU_L2U_RA0      (0x328)
1564 #define SPR_MPC_MD_DBCAM      (0x328)
1565 #define SPR_RCPU_L2U_RA1      (0x329)
1566 #define SPR_MPC_MD_DBRAM0     (0x329)
1567 #define SPR_RCPU_L2U_RA2      (0x32A)
1568 #define SPR_MPC_MD_DBRAM1     (0x32A)
1569 #define SPR_RCPU_L2U_RA3      (0x32B)
1570 #define SPR_440_INV0          (0x370)
1571 #define SPR_440_INV1          (0x371)
1572 #define SPR_440_INV2          (0x372)
1573 #define SPR_440_INV3          (0x373)
1574 #define SPR_440_ITV0          (0x374)
1575 #define SPR_440_ITV1          (0x375)
1576 #define SPR_440_ITV2          (0x376)
1577 #define SPR_440_ITV3          (0x377)
1578 #define SPR_440_CCR1          (0x378)
1579 #define SPR_DCRIPR            (0x37B)
1580 #define SPR_PPR               (0x380)
1581 #define SPR_750_GQR0          (0x390)
1582 #define SPR_440_DNV0          (0x390)
1583 #define SPR_750_GQR1          (0x391)
1584 #define SPR_440_DNV1          (0x391)
1585 #define SPR_750_GQR2          (0x392)
1586 #define SPR_440_DNV2          (0x392)
1587 #define SPR_750_GQR3          (0x393)
1588 #define SPR_440_DNV3          (0x393)
1589 #define SPR_750_GQR4          (0x394)
1590 #define SPR_440_DTV0          (0x394)
1591 #define SPR_750_GQR5          (0x395)
1592 #define SPR_440_DTV1          (0x395)
1593 #define SPR_750_GQR6          (0x396)
1594 #define SPR_440_DTV2          (0x396)
1595 #define SPR_750_GQR7          (0x397)
1596 #define SPR_440_DTV3          (0x397)
1597 #define SPR_750_THRM4         (0x398)
1598 #define SPR_750CL_HID2        (0x398)
1599 #define SPR_440_DVLIM         (0x398)
1600 #define SPR_750_WPAR          (0x399)
1601 #define SPR_440_IVLIM         (0x399)
1602 #define SPR_750_DMAU          (0x39A)
1603 #define SPR_750_DMAL          (0x39B)
1604 #define SPR_440_RSTCFG        (0x39B)
1605 #define SPR_BOOKE_DCDBTRL     (0x39C)
1606 #define SPR_BOOKE_DCDBTRH     (0x39D)
1607 #define SPR_BOOKE_ICDBTRL     (0x39E)
1608 #define SPR_BOOKE_ICDBTRH     (0x39F)
1609 #define SPR_UMMCR2            (0x3A0)
1610 #define SPR_UPMC5             (0x3A1)
1611 #define SPR_UPMC6             (0x3A2)
1612 #define SPR_UBAMR             (0x3A7)
1613 #define SPR_UMMCR0            (0x3A8)
1614 #define SPR_UPMC1             (0x3A9)
1615 #define SPR_UPMC2             (0x3AA)
1616 #define SPR_USIAR             (0x3AB)
1617 #define SPR_UMMCR1            (0x3AC)
1618 #define SPR_UPMC3             (0x3AD)
1619 #define SPR_UPMC4             (0x3AE)
1620 #define SPR_USDA              (0x3AF)
1621 #define SPR_40x_ZPR           (0x3B0)
1622 #define SPR_BOOKE_MAS7        (0x3B0)
1623 #define SPR_620_PMR0          (0x3B0)
1624 #define SPR_MMCR2             (0x3B0)
1625 #define SPR_PMC5              (0x3B1)
1626 #define SPR_40x_PID           (0x3B1)
1627 #define SPR_620_PMR1          (0x3B1)
1628 #define SPR_PMC6              (0x3B2)
1629 #define SPR_440_MMUCR         (0x3B2)
1630 #define SPR_620_PMR2          (0x3B2)
1631 #define SPR_4xx_CCR0          (0x3B3)
1632 #define SPR_BOOKE_EPLC        (0x3B3)
1633 #define SPR_620_PMR3          (0x3B3)
1634 #define SPR_405_IAC3          (0x3B4)
1635 #define SPR_BOOKE_EPSC        (0x3B4)
1636 #define SPR_620_PMR4          (0x3B4)
1637 #define SPR_405_IAC4          (0x3B5)
1638 #define SPR_620_PMR5          (0x3B5)
1639 #define SPR_405_DVC1          (0x3B6)
1640 #define SPR_620_PMR6          (0x3B6)
1641 #define SPR_405_DVC2          (0x3B7)
1642 #define SPR_620_PMR7          (0x3B7)
1643 #define SPR_BAMR              (0x3B7)
1644 #define SPR_MMCR0             (0x3B8)
1645 #define SPR_620_PMR8          (0x3B8)
1646 #define SPR_PMC1              (0x3B9)
1647 #define SPR_40x_SGR           (0x3B9)
1648 #define SPR_620_PMR9          (0x3B9)
1649 #define SPR_PMC2              (0x3BA)
1650 #define SPR_40x_DCWR          (0x3BA)
1651 #define SPR_620_PMRA          (0x3BA)
1652 #define SPR_SIAR              (0x3BB)
1653 #define SPR_405_SLER          (0x3BB)
1654 #define SPR_620_PMRB          (0x3BB)
1655 #define SPR_MMCR1             (0x3BC)
1656 #define SPR_405_SU0R          (0x3BC)
1657 #define SPR_620_PMRC          (0x3BC)
1658 #define SPR_401_SKR           (0x3BC)
1659 #define SPR_PMC3              (0x3BD)
1660 #define SPR_405_DBCR1         (0x3BD)
1661 #define SPR_620_PMRD          (0x3BD)
1662 #define SPR_PMC4              (0x3BE)
1663 #define SPR_620_PMRE          (0x3BE)
1664 #define SPR_SDA               (0x3BF)
1665 #define SPR_620_PMRF          (0x3BF)
1666 #define SPR_403_VTBL          (0x3CC)
1667 #define SPR_403_VTBU          (0x3CD)
1668 #define SPR_DMISS             (0x3D0)
1669 #define SPR_DCMP              (0x3D1)
1670 #define SPR_HASH1             (0x3D2)
1671 #define SPR_HASH2             (0x3D3)
1672 #define SPR_BOOKE_ICDBDR      (0x3D3)
1673 #define SPR_TLBMISS           (0x3D4)
1674 #define SPR_IMISS             (0x3D4)
1675 #define SPR_40x_ESR           (0x3D4)
1676 #define SPR_PTEHI             (0x3D5)
1677 #define SPR_ICMP              (0x3D5)
1678 #define SPR_40x_DEAR          (0x3D5)
1679 #define SPR_PTELO             (0x3D6)
1680 #define SPR_RPA               (0x3D6)
1681 #define SPR_40x_EVPR          (0x3D6)
1682 #define SPR_L3PM              (0x3D7)
1683 #define SPR_403_CDBCR         (0x3D7)
1684 #define SPR_L3ITCR0           (0x3D8)
1685 #define SPR_TCR               (0x3D8)
1686 #define SPR_40x_TSR           (0x3D8)
1687 #define SPR_IBR               (0x3DA)
1688 #define SPR_40x_TCR           (0x3DA)
1689 #define SPR_ESASRR            (0x3DB)
1690 #define SPR_40x_PIT           (0x3DB)
1691 #define SPR_403_TBL           (0x3DC)
1692 #define SPR_403_TBU           (0x3DD)
1693 #define SPR_SEBR              (0x3DE)
1694 #define SPR_40x_SRR2          (0x3DE)
1695 #define SPR_SER               (0x3DF)
1696 #define SPR_40x_SRR3          (0x3DF)
1697 #define SPR_L3OHCR            (0x3E8)
1698 #define SPR_L3ITCR1           (0x3E9)
1699 #define SPR_L3ITCR2           (0x3EA)
1700 #define SPR_L3ITCR3           (0x3EB)
1701 #define SPR_HID0              (0x3F0)
1702 #define SPR_40x_DBSR          (0x3F0)
1703 #define SPR_HID1              (0x3F1)
1704 #define SPR_IABR              (0x3F2)
1705 #define SPR_40x_DBCR0         (0x3F2)
1706 #define SPR_601_HID2          (0x3F2)
1707 #define SPR_Exxx_L1CSR0       (0x3F2)
1708 #define SPR_ICTRL             (0x3F3)
1709 #define SPR_HID2              (0x3F3)
1710 #define SPR_750CL_HID4        (0x3F3)
1711 #define SPR_Exxx_L1CSR1       (0x3F3)
1712 #define SPR_440_DBDR          (0x3F3)
1713 #define SPR_LDSTDB            (0x3F4)
1714 #define SPR_750_TDCL          (0x3F4)
1715 #define SPR_40x_IAC1          (0x3F4)
1716 #define SPR_MMUCSR0           (0x3F4)
1717 #define SPR_DABR              (0x3F5)
1718 #define DABR_MASK (~(target_ulong)0x7)
1719 #define SPR_Exxx_BUCSR        (0x3F5)
1720 #define SPR_40x_IAC2          (0x3F5)
1721 #define SPR_601_HID5          (0x3F5)
1722 #define SPR_40x_DAC1          (0x3F6)
1723 #define SPR_MSSCR0            (0x3F6)
1724 #define SPR_970_HID5          (0x3F6)
1725 #define SPR_MSSSR0            (0x3F7)
1726 #define SPR_MSSCR1            (0x3F7)
1727 #define SPR_DABRX             (0x3F7)
1728 #define SPR_40x_DAC2          (0x3F7)
1729 #define SPR_MMUCFG            (0x3F7)
1730 #define SPR_LDSTCR            (0x3F8)
1731 #define SPR_L2PMCR            (0x3F8)
1732 #define SPR_750FX_HID2        (0x3F8)
1733 #define SPR_620_BUSCSR        (0x3F8)
1734 #define SPR_Exxx_L1FINV0      (0x3F8)
1735 #define SPR_L2CR              (0x3F9)
1736 #define SPR_620_L2CR          (0x3F9)
1737 #define SPR_L3CR              (0x3FA)
1738 #define SPR_750_TDCH          (0x3FA)
1739 #define SPR_IABR2             (0x3FA)
1740 #define SPR_40x_DCCR          (0x3FA)
1741 #define SPR_620_L2SR          (0x3FA)
1742 #define SPR_ICTC              (0x3FB)
1743 #define SPR_40x_ICCR          (0x3FB)
1744 #define SPR_THRM1             (0x3FC)
1745 #define SPR_403_PBL1          (0x3FC)
1746 #define SPR_SP                (0x3FD)
1747 #define SPR_THRM2             (0x3FD)
1748 #define SPR_403_PBU1          (0x3FD)
1749 #define SPR_604_HID13         (0x3FD)
1750 #define SPR_LT                (0x3FE)
1751 #define SPR_THRM3             (0x3FE)
1752 #define SPR_RCPU_FPECR        (0x3FE)
1753 #define SPR_403_PBL2          (0x3FE)
1754 #define SPR_PIR               (0x3FF)
1755 #define SPR_403_PBU2          (0x3FF)
1756 #define SPR_601_HID15         (0x3FF)
1757 #define SPR_604_HID15         (0x3FF)
1758 #define SPR_E500_SVR          (0x3FF)
1759
1760 /* Disable MAS Interrupt Updates for Hypervisor */
1761 #define EPCR_DMIUH            (1 << 22)
1762 /* Disable Guest TLB Management Instructions */
1763 #define EPCR_DGTMI            (1 << 23)
1764 /* Guest Interrupt Computation Mode */
1765 #define EPCR_GICM             (1 << 24)
1766 /* Interrupt Computation Mode */
1767 #define EPCR_ICM              (1 << 25)
1768 /* Disable Embedded Hypervisor Debug */
1769 #define EPCR_DUVD             (1 << 26)
1770 /* Instruction Storage Interrupt Directed to Guest State */
1771 #define EPCR_ISIGS            (1 << 27)
1772 /* Data Storage Interrupt Directed to Guest State */
1773 #define EPCR_DSIGS            (1 << 28)
1774 /* Instruction TLB Error Interrupt Directed to Guest State */
1775 #define EPCR_ITLBGS           (1 << 29)
1776 /* Data TLB Error Interrupt Directed to Guest State */
1777 #define EPCR_DTLBGS           (1 << 30)
1778 /* External Input Interrupt Directed to Guest State */
1779 #define EPCR_EXTGS            (1 << 31)
1780
1781 /*****************************************************************************/
1782 /* PowerPC Instructions types definitions                                    */
1783 enum {
1784     PPC_NONE           = 0x0000000000000000ULL,
1785     /* PowerPC base instructions set                                         */
1786     PPC_INSNS_BASE     = 0x0000000000000001ULL,
1787     /*   integer operations instructions                                     */
1788 #define PPC_INTEGER PPC_INSNS_BASE
1789     /*   flow control instructions                                           */
1790 #define PPC_FLOW    PPC_INSNS_BASE
1791     /*   virtual memory instructions                                         */
1792 #define PPC_MEM     PPC_INSNS_BASE
1793     /*   ld/st with reservation instructions                                 */
1794 #define PPC_RES     PPC_INSNS_BASE
1795     /*   spr/msr access instructions                                         */
1796 #define PPC_MISC    PPC_INSNS_BASE
1797     /* Deprecated instruction sets                                           */
1798     /*   Original POWER instruction set                                      */
1799     PPC_POWER          = 0x0000000000000002ULL,
1800     /*   POWER2 instruction set extension                                    */
1801     PPC_POWER2         = 0x0000000000000004ULL,
1802     /*   Power RTC support                                                   */
1803     PPC_POWER_RTC      = 0x0000000000000008ULL,
1804     /*   Power-to-PowerPC bridge (601)                                       */
1805     PPC_POWER_BR       = 0x0000000000000010ULL,
1806     /* 64 bits PowerPC instruction set                                       */
1807     PPC_64B            = 0x0000000000000020ULL,
1808     /*   New 64 bits extensions (PowerPC 2.0x)                               */
1809     PPC_64BX           = 0x0000000000000040ULL,
1810     /*   64 bits hypervisor extensions                                       */
1811     PPC_64H            = 0x0000000000000080ULL,
1812     /*   New wait instruction (PowerPC 2.0x)                                 */
1813     PPC_WAIT           = 0x0000000000000100ULL,
1814     /*   Time base mftb instruction                                          */
1815     PPC_MFTB           = 0x0000000000000200ULL,
1816
1817     /* Fixed-point unit extensions                                           */
1818     /*   PowerPC 602 specific                                                */
1819     PPC_602_SPEC       = 0x0000000000000400ULL,
1820     /*   isel instruction                                                    */
1821     PPC_ISEL           = 0x0000000000000800ULL,
1822     /*   popcntb instruction                                                 */
1823     PPC_POPCNTB        = 0x0000000000001000ULL,
1824     /*   string load / store                                                 */
1825     PPC_STRING         = 0x0000000000002000ULL,
1826
1827     /* Floating-point unit extensions                                        */
1828     /*   Optional floating point instructions                                */
1829     PPC_FLOAT          = 0x0000000000010000ULL,
1830     /* New floating-point extensions (PowerPC 2.0x)                          */
1831     PPC_FLOAT_EXT      = 0x0000000000020000ULL,
1832     PPC_FLOAT_FSQRT    = 0x0000000000040000ULL,
1833     PPC_FLOAT_FRES     = 0x0000000000080000ULL,
1834     PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,
1835     PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1836     PPC_FLOAT_FSEL     = 0x0000000000400000ULL,
1837     PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,
1838
1839     /* Vector/SIMD extensions                                                */
1840     /*   Altivec support                                                     */
1841     PPC_ALTIVEC        = 0x0000000001000000ULL,
1842     /*   PowerPC 2.03 SPE extension                                          */
1843     PPC_SPE            = 0x0000000002000000ULL,
1844     /*   PowerPC 2.03 SPE single-precision floating-point extension          */
1845     PPC_SPE_SINGLE     = 0x0000000004000000ULL,
1846     /*   PowerPC 2.03 SPE double-precision floating-point extension          */
1847     PPC_SPE_DOUBLE     = 0x0000000008000000ULL,
1848
1849     /* Optional memory control instructions                                  */
1850     PPC_MEM_TLBIA      = 0x0000000010000000ULL,
1851     PPC_MEM_TLBIE      = 0x0000000020000000ULL,
1852     PPC_MEM_TLBSYNC    = 0x0000000040000000ULL,
1853     /*   sync instruction                                                    */
1854     PPC_MEM_SYNC       = 0x0000000080000000ULL,
1855     /*   eieio instruction                                                   */
1856     PPC_MEM_EIEIO      = 0x0000000100000000ULL,
1857
1858     /* Cache control instructions                                            */
1859     PPC_CACHE          = 0x0000000200000000ULL,
1860     /*   icbi instruction                                                    */
1861     PPC_CACHE_ICBI     = 0x0000000400000000ULL,
1862     /*   dcbz instruction with fixed cache line size                         */
1863     PPC_CACHE_DCBZ     = 0x0000000800000000ULL,
1864     /*   dcbz instruction with tunable cache line size                       */
1865     PPC_CACHE_DCBZT    = 0x0000001000000000ULL,
1866     /*   dcba instruction                                                    */
1867     PPC_CACHE_DCBA     = 0x0000002000000000ULL,
1868     /*   Freescale cache locking instructions                                */
1869     PPC_CACHE_LOCK     = 0x0000004000000000ULL,
1870
1871     /* MMU related extensions                                                */
1872     /*   external control instructions                                       */
1873     PPC_EXTERN         = 0x0000010000000000ULL,
1874     /*   segment register access instructions                                */
1875     PPC_SEGMENT        = 0x0000020000000000ULL,
1876     /*   PowerPC 6xx TLB management instructions                             */
1877     PPC_6xx_TLB        = 0x0000040000000000ULL,
1878     /* PowerPC 74xx TLB management instructions                              */
1879     PPC_74xx_TLB       = 0x0000080000000000ULL,
1880     /*   PowerPC 40x TLB management instructions                             */
1881     PPC_40x_TLB        = 0x0000100000000000ULL,
1882     /*   segment register access instructions for PowerPC 64 "bridge"        */
1883     PPC_SEGMENT_64B    = 0x0000200000000000ULL,
1884     /*   SLB management                                                      */
1885     PPC_SLBI           = 0x0000400000000000ULL,
1886
1887     /* Embedded PowerPC dedicated instructions                               */
1888     PPC_WRTEE          = 0x0001000000000000ULL,
1889     /* PowerPC 40x exception model                                           */
1890     PPC_40x_EXCP       = 0x0002000000000000ULL,
1891     /* PowerPC 405 Mac instructions                                          */
1892     PPC_405_MAC        = 0x0004000000000000ULL,
1893     /* PowerPC 440 specific instructions                                     */
1894     PPC_440_SPEC       = 0x0008000000000000ULL,
1895     /* BookE (embedded) PowerPC specification                                */
1896     PPC_BOOKE          = 0x0010000000000000ULL,
1897     /* mfapidi instruction                                                   */
1898     PPC_MFAPIDI        = 0x0020000000000000ULL,
1899     /* tlbiva instruction                                                    */
1900     PPC_TLBIVA         = 0x0040000000000000ULL,
1901     /* tlbivax instruction                                                   */
1902     PPC_TLBIVAX        = 0x0080000000000000ULL,
1903     /* PowerPC 4xx dedicated instructions                                    */
1904     PPC_4xx_COMMON     = 0x0100000000000000ULL,
1905     /* PowerPC 40x ibct instructions                                         */
1906     PPC_40x_ICBT       = 0x0200000000000000ULL,
1907     /* rfmci is not implemented in all BookE PowerPC                         */
1908     PPC_RFMCI          = 0x0400000000000000ULL,
1909     /* rfdi instruction                                                      */
1910     PPC_RFDI           = 0x0800000000000000ULL,
1911     /* DCR accesses                                                          */
1912     PPC_DCR            = 0x1000000000000000ULL,
1913     /* DCR extended accesse                                                  */
1914     PPC_DCRX           = 0x2000000000000000ULL,
1915     /* user-mode DCR access, implemented in PowerPC 460                      */
1916     PPC_DCRUX          = 0x4000000000000000ULL,
1917     /* popcntw and popcntd instructions                                      */
1918     PPC_POPCNTWD       = 0x8000000000000000ULL,
1919
1920 #define PPC_TCG_INSNS  (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
1921                         | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
1922                         | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
1923                         | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
1924                         | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
1925                         | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
1926                         | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
1927                         | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
1928                         | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
1929                         | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
1930                         | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
1931                         | PPC_MEM_SYNC | PPC_MEM_EIEIO \
1932                         | PPC_CACHE | PPC_CACHE_ICBI \
1933                         | PPC_CACHE_DCBZ | PPC_CACHE_DCBZT \
1934                         | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
1935                         | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
1936                         | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
1937                         | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
1938                         | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
1939                         | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
1940                         | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
1941                         | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
1942                         | PPC_POPCNTWD)
1943
1944     /* extended type values */
1945
1946     /* BookE 2.06 PowerPC specification                                      */
1947     PPC2_BOOKE206      = 0x0000000000000001ULL,
1948     /* VSX (extensions to Altivec / VMX)                                     */
1949     PPC2_VSX           = 0x0000000000000002ULL,
1950     /* Decimal Floating Point (DFP)                                          */
1951     PPC2_DFP           = 0x0000000000000004ULL,
1952     /* Embedded.Processor Control                                            */
1953     PPC2_PRCNTL        = 0x0000000000000008ULL,
1954     /* Byte-reversed, indexed, double-word load and store                    */
1955     PPC2_DBRX          = 0x0000000000000010ULL,
1956
1957 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_DBRX)
1958 };
1959
1960 /*****************************************************************************/
1961 /* Memory access type :
1962  * may be needed for precise access rights control and precise exceptions.
1963  */
1964 enum {
1965     /* 1 bit to define user level / supervisor access */
1966     ACCESS_USER  = 0x00,
1967     ACCESS_SUPER = 0x01,
1968     /* Type of instruction that generated the access */
1969     ACCESS_CODE  = 0x10, /* Code fetch access                */
1970     ACCESS_INT   = 0x20, /* Integer load/store access        */
1971     ACCESS_FLOAT = 0x30, /* floating point load/store access */
1972     ACCESS_RES   = 0x40, /* load/store with reservation      */
1973     ACCESS_EXT   = 0x50, /* external access                  */
1974     ACCESS_CACHE = 0x60, /* Cache manipulation               */
1975 };
1976
1977 /* Hardware interruption sources:
1978  * all those exception can be raised simulteaneously
1979  */
1980 /* Input pins definitions */
1981 enum {
1982     /* 6xx bus input pins */
1983     PPC6xx_INPUT_HRESET     = 0,
1984     PPC6xx_INPUT_SRESET     = 1,
1985     PPC6xx_INPUT_CKSTP_IN   = 2,
1986     PPC6xx_INPUT_MCP        = 3,
1987     PPC6xx_INPUT_SMI        = 4,
1988     PPC6xx_INPUT_INT        = 5,
1989     PPC6xx_INPUT_TBEN       = 6,
1990     PPC6xx_INPUT_WAKEUP     = 7,
1991     PPC6xx_INPUT_NB,
1992 };
1993
1994 enum {
1995     /* Embedded PowerPC input pins */
1996     PPCBookE_INPUT_HRESET     = 0,
1997     PPCBookE_INPUT_SRESET     = 1,
1998     PPCBookE_INPUT_CKSTP_IN   = 2,
1999     PPCBookE_INPUT_MCP        = 3,
2000     PPCBookE_INPUT_SMI        = 4,
2001     PPCBookE_INPUT_INT        = 5,
2002     PPCBookE_INPUT_CINT       = 6,
2003     PPCBookE_INPUT_NB,
2004 };
2005
2006 enum {
2007     /* PowerPC E500 input pins */
2008     PPCE500_INPUT_RESET_CORE = 0,
2009     PPCE500_INPUT_MCK        = 1,
2010     PPCE500_INPUT_CINT       = 3,
2011     PPCE500_INPUT_INT        = 4,
2012     PPCE500_INPUT_DEBUG      = 6,
2013     PPCE500_INPUT_NB,
2014 };
2015
2016 enum {
2017     /* PowerPC 40x input pins */
2018     PPC40x_INPUT_RESET_CORE = 0,
2019     PPC40x_INPUT_RESET_CHIP = 1,
2020     PPC40x_INPUT_RESET_SYS  = 2,
2021     PPC40x_INPUT_CINT       = 3,
2022     PPC40x_INPUT_INT        = 4,
2023     PPC40x_INPUT_HALT       = 5,
2024     PPC40x_INPUT_DEBUG      = 6,
2025     PPC40x_INPUT_NB,
2026 };
2027
2028 enum {
2029     /* RCPU input pins */
2030     PPCRCPU_INPUT_PORESET   = 0,
2031     PPCRCPU_INPUT_HRESET    = 1,
2032     PPCRCPU_INPUT_SRESET    = 2,
2033     PPCRCPU_INPUT_IRQ0      = 3,
2034     PPCRCPU_INPUT_IRQ1      = 4,
2035     PPCRCPU_INPUT_IRQ2      = 5,
2036     PPCRCPU_INPUT_IRQ3      = 6,
2037     PPCRCPU_INPUT_IRQ4      = 7,
2038     PPCRCPU_INPUT_IRQ5      = 8,
2039     PPCRCPU_INPUT_IRQ6      = 9,
2040     PPCRCPU_INPUT_IRQ7      = 10,
2041     PPCRCPU_INPUT_NB,
2042 };
2043
2044 #if defined(TARGET_PPC64)
2045 enum {
2046     /* PowerPC 970 input pins */
2047     PPC970_INPUT_HRESET     = 0,
2048     PPC970_INPUT_SRESET     = 1,
2049     PPC970_INPUT_CKSTP      = 2,
2050     PPC970_INPUT_TBEN       = 3,
2051     PPC970_INPUT_MCP        = 4,
2052     PPC970_INPUT_INT        = 5,
2053     PPC970_INPUT_THINT      = 6,
2054     PPC970_INPUT_NB,
2055 };
2056
2057 enum {
2058     /* POWER7 input pins */
2059     POWER7_INPUT_INT        = 0,
2060     /* POWER7 probably has other inputs, but we don't care about them
2061      * for any existing machine.  We can wire these up when we need
2062      * them */
2063     POWER7_INPUT_NB,
2064 };
2065 #endif
2066
2067 /* Hardware exceptions definitions */
2068 enum {
2069     /* External hardware exception sources */
2070     PPC_INTERRUPT_RESET     = 0,  /* Reset exception                      */
2071     PPC_INTERRUPT_WAKEUP,         /* Wakeup exception                     */
2072     PPC_INTERRUPT_MCK,            /* Machine check exception              */
2073     PPC_INTERRUPT_EXT,            /* External interrupt                   */
2074     PPC_INTERRUPT_SMI,            /* System management interrupt          */
2075     PPC_INTERRUPT_CEXT,           /* Critical external interrupt          */
2076     PPC_INTERRUPT_DEBUG,          /* External debug exception             */
2077     PPC_INTERRUPT_THERM,          /* Thermal exception                    */
2078     /* Internal hardware exception sources */
2079     PPC_INTERRUPT_DECR,           /* Decrementer exception                */
2080     PPC_INTERRUPT_HDECR,          /* Hypervisor decrementer exception     */
2081     PPC_INTERRUPT_PIT,            /* Programmable inteval timer interrupt */
2082     PPC_INTERRUPT_FIT,            /* Fixed interval timer interrupt       */
2083     PPC_INTERRUPT_WDT,            /* Watchdog timer interrupt             */
2084     PPC_INTERRUPT_CDOORBELL,      /* Critical doorbell interrupt          */
2085     PPC_INTERRUPT_DOORBELL,       /* Doorbell interrupt                   */
2086     PPC_INTERRUPT_PERFM,          /* Performance monitor interrupt        */
2087 };
2088
2089 /* CPU should be reset next, restart from scratch afterwards */
2090 #define CPU_INTERRUPT_RESET       CPU_INTERRUPT_TGT_INT_0
2091
2092 /*****************************************************************************/
2093
2094 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2095                                         target_ulong *cs_base, int *flags)
2096 {
2097     *pc = env->nip;
2098     *cs_base = 0;
2099     *flags = env->hflags;
2100 }
2101
2102 static inline void cpu_set_tls(CPUPPCState *env, target_ulong newtls)
2103 {
2104 #if defined(TARGET_PPC64)
2105     /* The kernel checks TIF_32BIT here; we don't support loading 32-bit
2106        binaries on PPC64 yet. */
2107     env->gpr[13] = newtls;
2108 #else
2109     env->gpr[2] = newtls;
2110 #endif
2111 }
2112
2113 #if !defined(CONFIG_USER_ONLY)
2114 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2115 {
2116     uintptr_t tlbml = (uintptr_t)tlbm;
2117     uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2118
2119     return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2120 }
2121
2122 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2123 {
2124     uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2125     int r = tlbncfg & TLBnCFG_N_ENTRY;
2126     return r;
2127 }
2128
2129 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2130 {
2131     uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2132     int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2133     return r;
2134 }
2135
2136 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2137 {
2138     int id = booke206_tlbm_id(env, tlbm);
2139     int end = 0;
2140     int i;
2141
2142     for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2143         end += booke206_tlb_size(env, i);
2144         if (id < end) {
2145             return i;
2146         }
2147     }
2148
2149     cpu_abort(env, "Unknown TLBe: %d\n", id);
2150     return 0;
2151 }
2152
2153 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2154 {
2155     int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2156     int tlbid = booke206_tlbm_id(env, tlb);
2157     return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2158 }
2159
2160 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2161                                               target_ulong ea, int way)
2162 {
2163     int r;
2164     uint32_t ways = booke206_tlb_ways(env, tlbn);
2165     int ways_bits = ffs(ways) - 1;
2166     int tlb_bits = ffs(booke206_tlb_size(env, tlbn)) - 1;
2167     int i;
2168
2169     way &= ways - 1;
2170     ea >>= MAS2_EPN_SHIFT;
2171     ea &= (1 << (tlb_bits - ways_bits)) - 1;
2172     r = (ea << ways_bits) | way;
2173
2174     if (r >= booke206_tlb_size(env, tlbn)) {
2175         return NULL;
2176     }
2177
2178     /* bump up to tlbn index */
2179     for (i = 0; i < tlbn; i++) {
2180         r += booke206_tlb_size(env, i);
2181     }
2182
2183     return &env->tlb.tlbm[r];
2184 }
2185
2186 /* returns bitmap of supported page sizes for a given TLB */
2187 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2188 {
2189     bool mav2 = false;
2190     uint32_t ret = 0;
2191
2192     if (mav2) {
2193         ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2194     } else {
2195         uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2196         uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2197         uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2198         int i;
2199         for (i = min; i <= max; i++) {
2200             ret |= (1 << (i << 1));
2201         }
2202     }
2203
2204     return ret;
2205 }
2206
2207 #endif
2208
2209 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2210 {
2211     if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2212         return msr & (1ULL << MSR_CM);
2213     }
2214
2215     return msr & (1ULL << MSR_SF);
2216 }
2217
2218 extern void (*cpu_ppc_hypercall)(PowerPCCPU *);
2219
2220 static inline bool cpu_has_work(CPUState *cpu)
2221 {
2222     CPUPPCState *env = &POWERPC_CPU(cpu)->env;
2223
2224     return msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD);
2225 }
2226
2227 #include "exec-all.h"
2228
2229 static inline void cpu_pc_from_tb(CPUPPCState *env, TranslationBlock *tb)
2230 {
2231     env->nip = tb->pc;
2232 }
2233
2234 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
2235
2236 #endif /* !defined (__CPU_PPC_H__) */