2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 #include "qemu-common.h"
26 /* Target word size (must be identical to pointer size). */
27 #if UINTPTR_MAX == UINT32_MAX
28 # define TCG_TARGET_REG_BITS 32
29 #elif UINTPTR_MAX == UINT64_MAX
30 # define TCG_TARGET_REG_BITS 64
32 # error Unknown pointer size for tcg target
35 #if TCG_TARGET_REG_BITS == 32
36 typedef int32_t tcg_target_long
;
37 typedef uint32_t tcg_target_ulong
;
38 #define TCG_PRIlx PRIx32
39 #define TCG_PRIld PRId32
40 #elif TCG_TARGET_REG_BITS == 64
41 typedef int64_t tcg_target_long
;
42 typedef uint64_t tcg_target_ulong
;
43 #define TCG_PRIlx PRIx64
44 #define TCG_PRIld PRId64
49 #include "tcg-target.h"
50 #include "tcg-runtime.h"
52 #if TCG_TARGET_NB_REGS <= 32
53 typedef uint32_t TCGRegSet
;
54 #elif TCG_TARGET_NB_REGS <= 64
55 typedef uint64_t TCGRegSet
;
60 /* Turn some undef macros into false macros. */
61 #if TCG_TARGET_REG_BITS == 32
62 #define TCG_TARGET_HAS_div_i64 0
63 #define TCG_TARGET_HAS_div2_i64 0
64 #define TCG_TARGET_HAS_rot_i64 0
65 #define TCG_TARGET_HAS_ext8s_i64 0
66 #define TCG_TARGET_HAS_ext16s_i64 0
67 #define TCG_TARGET_HAS_ext32s_i64 0
68 #define TCG_TARGET_HAS_ext8u_i64 0
69 #define TCG_TARGET_HAS_ext16u_i64 0
70 #define TCG_TARGET_HAS_ext32u_i64 0
71 #define TCG_TARGET_HAS_bswap16_i64 0
72 #define TCG_TARGET_HAS_bswap32_i64 0
73 #define TCG_TARGET_HAS_bswap64_i64 0
74 #define TCG_TARGET_HAS_neg_i64 0
75 #define TCG_TARGET_HAS_not_i64 0
76 #define TCG_TARGET_HAS_andc_i64 0
77 #define TCG_TARGET_HAS_orc_i64 0
78 #define TCG_TARGET_HAS_eqv_i64 0
79 #define TCG_TARGET_HAS_nand_i64 0
80 #define TCG_TARGET_HAS_nor_i64 0
81 #define TCG_TARGET_HAS_deposit_i64 0
82 #define TCG_TARGET_HAS_movcond_i64 0
85 #ifndef TCG_TARGET_deposit_i32_valid
86 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1
88 #ifndef TCG_TARGET_deposit_i64_valid
89 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1
92 /* Only one of DIV or DIV2 should be defined. */
93 #if defined(TCG_TARGET_HAS_div_i32)
94 #define TCG_TARGET_HAS_div2_i32 0
95 #elif defined(TCG_TARGET_HAS_div2_i32)
96 #define TCG_TARGET_HAS_div_i32 0
98 #if defined(TCG_TARGET_HAS_div_i64)
99 #define TCG_TARGET_HAS_div2_i64 0
100 #elif defined(TCG_TARGET_HAS_div2_i64)
101 #define TCG_TARGET_HAS_div_i64 0
104 typedef enum TCGOpcode
{
105 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name,
111 #define tcg_regset_clear(d) (d) = 0
112 #define tcg_regset_set(d, s) (d) = (s)
113 #define tcg_regset_set32(d, reg, val32) (d) |= (val32) << (reg)
114 #define tcg_regset_set_reg(d, r) (d) |= 1L << (r)
115 #define tcg_regset_reset_reg(d, r) (d) &= ~(1L << (r))
116 #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1)
117 #define tcg_regset_or(d, a, b) (d) = (a) | (b)
118 #define tcg_regset_and(d, a, b) (d) = (a) & (b)
119 #define tcg_regset_andnot(d, a, b) (d) = (a) & ~(b)
120 #define tcg_regset_not(d, a) (d) = ~(a)
122 typedef struct TCGRelocation
{
123 struct TCGRelocation
*next
;
126 tcg_target_long addend
;
129 typedef struct TCGLabel
{
132 tcg_target_ulong value
;
133 TCGRelocation
*first_reloc
;
137 typedef struct TCGPool
{
138 struct TCGPool
*next
;
140 uint8_t data
[0] __attribute__ ((aligned
));
143 #define TCG_POOL_CHUNK_SIZE 32768
145 #define TCG_MAX_LABELS 512
147 #define TCG_MAX_TEMPS 512
149 /* when the size of the arguments of a called function is smaller than
150 this value, they are statically allocated in the TB stack frame */
151 #define TCG_STATIC_CALL_ARGS_SIZE 128
153 typedef enum TCGType
{
156 TCG_TYPE_COUNT
, /* number of different types */
158 /* An alias for the size of the host register. */
159 #if TCG_TARGET_REG_BITS == 32
160 TCG_TYPE_REG
= TCG_TYPE_I32
,
162 TCG_TYPE_REG
= TCG_TYPE_I64
,
165 /* An alias for the size of the native pointer. We don't currently
166 support any hosts with 64-bit registers and 32-bit pointers. */
167 TCG_TYPE_PTR
= TCG_TYPE_REG
,
169 /* An alias for the size of the target "long", aka register. */
170 #if TARGET_LONG_BITS == 64
171 TCG_TYPE_TL
= TCG_TYPE_I64
,
173 TCG_TYPE_TL
= TCG_TYPE_I32
,
177 typedef tcg_target_ulong TCGArg
;
179 /* Define a type and accessor macros for variables. Using a struct is
180 nice because it gives some level of type safely. Ideally the compiler
181 be able to see through all this. However in practice this is not true,
182 especially on targets with braindamaged ABIs (e.g. i386).
183 We use plain int by default to avoid this runtime overhead.
184 Users of tcg_gen_* don't need to know about any of this, and should
185 treat TCGv as an opaque type.
186 In addition we do typechecking for different types of variables. TCGv_i32
187 and TCGv_i64 are 32/64-bit variables respectively. TCGv and TCGv_ptr
188 are aliases for target_ulong and host pointer sized values respectively.
191 #if defined(CONFIG_QEMU_LDST_OPTIMIZATION) && defined(CONFIG_SOFTMMU)
192 /* Macros/structures for qemu_ld/st IR code optimization:
193 TCG_MAX_HELPER_LABELS is defined as same as OPC_BUF_SIZE in exec-all.h. */
194 #define TCG_MAX_QEMU_LDST 640
196 typedef struct TCGLabelQemuLdst
{
197 int is_ld
:1; /* qemu_ld: 1, qemu_st: 0 */
199 int addrlo_reg
; /* reg index for low word of guest virtual addr */
200 int addrhi_reg
; /* reg index for high word of guest virtual addr */
201 int datalo_reg
; /* reg index for low word to be loaded or stored */
202 int datahi_reg
; /* reg index for high word to be loaded or stored */
203 int mem_index
; /* soft MMU memory index */
204 uint8_t *raddr
; /* gen code addr of the next IR of qemu_ld/st IR */
205 uint8_t *label_ptr
[2]; /* label pointers to be updated */
209 #ifdef CONFIG_DEBUG_TCG
229 #define MAKE_TCGV_I32(i) __extension__ \
230 ({ TCGv_i32 make_tcgv_tmp = {i}; make_tcgv_tmp;})
231 #define MAKE_TCGV_I64(i) __extension__ \
232 ({ TCGv_i64 make_tcgv_tmp = {i}; make_tcgv_tmp;})
233 #define MAKE_TCGV_PTR(i) __extension__ \
234 ({ TCGv_ptr make_tcgv_tmp = {i}; make_tcgv_tmp; })
235 #define GET_TCGV_I32(t) ((t).i32)
236 #define GET_TCGV_I64(t) ((t).i64)
237 #define GET_TCGV_PTR(t) ((t).iptr)
238 #if TCG_TARGET_REG_BITS == 32
239 #define TCGV_LOW(t) MAKE_TCGV_I32(GET_TCGV_I64(t))
240 #define TCGV_HIGH(t) MAKE_TCGV_I32(GET_TCGV_I64(t) + 1)
243 #else /* !DEBUG_TCGV */
245 typedef int TCGv_i32
;
246 typedef int TCGv_i64
;
247 #if TCG_TARGET_REG_BITS == 32
248 #define TCGv_ptr TCGv_i32
250 #define TCGv_ptr TCGv_i64
252 #define MAKE_TCGV_I32(x) (x)
253 #define MAKE_TCGV_I64(x) (x)
254 #define MAKE_TCGV_PTR(x) (x)
255 #define GET_TCGV_I32(t) (t)
256 #define GET_TCGV_I64(t) (t)
257 #define GET_TCGV_PTR(t) (t)
259 #if TCG_TARGET_REG_BITS == 32
260 #define TCGV_LOW(t) (t)
261 #define TCGV_HIGH(t) ((t) + 1)
264 #endif /* DEBUG_TCGV */
266 #define TCGV_EQUAL_I32(a, b) (GET_TCGV_I32(a) == GET_TCGV_I32(b))
267 #define TCGV_EQUAL_I64(a, b) (GET_TCGV_I64(a) == GET_TCGV_I64(b))
269 /* Dummy definition to avoid compiler warnings. */
270 #define TCGV_UNUSED_I32(x) x = MAKE_TCGV_I32(-1)
271 #define TCGV_UNUSED_I64(x) x = MAKE_TCGV_I64(-1)
274 /* Helper does not read globals (either directly or through an exception). It
275 implies TCG_CALL_NO_WRITE_GLOBALS. */
276 #define TCG_CALL_NO_READ_GLOBALS 0x0010
277 /* Helper does not write globals */
278 #define TCG_CALL_NO_WRITE_GLOBALS 0x0020
279 /* Helper can be safely suppressed if the return value is not used. */
280 #define TCG_CALL_NO_SIDE_EFFECTS 0x0040
282 /* convenience version of most used call flags */
283 #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS
284 #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS
285 #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS
286 #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE)
287 #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE)
289 /* used to align parameters */
290 #define TCG_CALL_DUMMY_TCGV MAKE_TCGV_I32(-1)
291 #define TCG_CALL_DUMMY_ARG ((TCGArg)(-1))
293 /* Conditions. Note that these are laid out for easy manipulation by
295 bit 0 is used for inverting;
298 bit 3 is used with bit 0 for swapping signed/unsigned. */
301 TCG_COND_NEVER
= 0 | 0 | 0 | 0,
302 TCG_COND_ALWAYS
= 0 | 0 | 0 | 1,
303 TCG_COND_EQ
= 8 | 0 | 0 | 0,
304 TCG_COND_NE
= 8 | 0 | 0 | 1,
306 TCG_COND_LT
= 0 | 0 | 2 | 0,
307 TCG_COND_GE
= 0 | 0 | 2 | 1,
308 TCG_COND_LE
= 8 | 0 | 2 | 0,
309 TCG_COND_GT
= 8 | 0 | 2 | 1,
311 TCG_COND_LTU
= 0 | 4 | 0 | 0,
312 TCG_COND_GEU
= 0 | 4 | 0 | 1,
313 TCG_COND_LEU
= 8 | 4 | 0 | 0,
314 TCG_COND_GTU
= 8 | 4 | 0 | 1,
317 /* Invert the sense of the comparison. */
318 static inline TCGCond
tcg_invert_cond(TCGCond c
)
320 return (TCGCond
)(c
^ 1);
323 /* Swap the operands in a comparison. */
324 static inline TCGCond
tcg_swap_cond(TCGCond c
)
326 return c
& 6 ? (TCGCond
)(c
^ 9) : c
;
329 /* Create an "unsigned" version of a "signed" comparison. */
330 static inline TCGCond
tcg_unsigned_cond(TCGCond c
)
332 return c
& 2 ? (TCGCond
)(c
^ 6) : c
;
335 /* Must a comparison be considered unsigned? */
336 static inline bool is_unsigned_cond(TCGCond c
)
341 /* Create a "high" version of a double-word comparison.
342 This removes equality from a LTE or GTE comparison. */
343 static inline TCGCond
tcg_high_cond(TCGCond c
)
350 return (TCGCond
)(c
^ 8);
356 #define TEMP_VAL_DEAD 0
357 #define TEMP_VAL_REG 1
358 #define TEMP_VAL_MEM 2
359 #define TEMP_VAL_CONST 3
361 /* XXX: optimize memory layout */
362 typedef struct TCGTemp
{
369 tcg_target_long mem_offset
;
370 unsigned int fixed_reg
:1;
371 unsigned int mem_coherent
:1;
372 unsigned int mem_allocated
:1;
373 unsigned int temp_local
:1; /* If true, the temp is saved across
374 basic blocks. Otherwise, it is not
375 preserved across basic blocks. */
376 unsigned int temp_allocated
:1; /* never used for code gen */
377 /* index of next free temp of same base type, -1 if end */
382 typedef struct TCGHelperInfo
{
383 tcg_target_ulong func
;
387 typedef struct TCGContext TCGContext
;
390 uint8_t *pool_cur
, *pool_end
;
391 TCGPool
*pool_first
, *pool_current
, *pool_first_large
;
396 /* index of free temps, -1 if none */
397 int first_free_temp
[TCG_TYPE_COUNT
* 2];
399 /* goto_tb support */
402 uint16_t *tb_next_offset
;
403 uint16_t *tb_jmp_offset
; /* != NULL if USE_DIRECT_JUMP */
405 /* liveness analysis */
406 uint16_t *op_dead_args
; /* for each operation, each bit tells if the
407 corresponding argument is dead */
408 uint8_t *op_sync_args
; /* for each operation, each bit tells if the
409 corresponding output argument needs to be
412 /* tells in which temporary a given register is. It does not take
413 into account fixed registers */
414 int reg_to_temp
[TCG_TARGET_NB_REGS
];
415 TCGRegSet reserved_regs
;
416 tcg_target_long current_frame_offset
;
417 tcg_target_long frame_start
;
418 tcg_target_long frame_end
;
422 TCGTemp temps
[TCG_MAX_TEMPS
]; /* globals first, temps after */
424 TCGHelperInfo
*helpers
;
426 int allocated_helpers
;
429 #ifdef CONFIG_PROFILER
433 int64_t op_count
; /* total insn count */
434 int op_count_max
; /* max insn per TB */
437 int64_t del_op_count
;
439 int64_t code_out_len
;
444 int64_t restore_count
;
445 int64_t restore_time
;
448 #ifdef CONFIG_DEBUG_TCG
450 int goto_tb_issue_mask
;
453 uint16_t gen_opc_buf
[OPC_BUF_SIZE
];
454 TCGArg gen_opparam_buf
[OPPARAM_BUF_SIZE
];
456 uint16_t *gen_opc_ptr
;
457 TCGArg
*gen_opparam_ptr
;
458 target_ulong gen_opc_pc
[OPC_BUF_SIZE
];
459 uint16_t gen_opc_icount
[OPC_BUF_SIZE
];
460 uint8_t gen_opc_instr_start
[OPC_BUF_SIZE
];
462 #if defined(CONFIG_QEMU_LDST_OPTIMIZATION) && defined(CONFIG_SOFTMMU)
463 /* labels info for qemu_ld/st IRs
464 The labels help to generate TLB miss case codes at the end of TB */
465 TCGLabelQemuLdst
*qemu_ldst_labels
;
466 int nb_qemu_ldst_labels
;
470 extern TCGContext tcg_ctx
;
472 /* pool based memory allocation */
474 void *tcg_malloc_internal(TCGContext
*s
, int size
);
475 void tcg_pool_reset(TCGContext
*s
);
476 void tcg_pool_delete(TCGContext
*s
);
478 static inline void *tcg_malloc(int size
)
480 TCGContext
*s
= &tcg_ctx
;
481 uint8_t *ptr
, *ptr_end
;
482 size
= (size
+ sizeof(long) - 1) & ~(sizeof(long) - 1);
484 ptr_end
= ptr
+ size
;
485 if (unlikely(ptr_end
> s
->pool_end
)) {
486 return tcg_malloc_internal(&tcg_ctx
, size
);
488 s
->pool_cur
= ptr_end
;
493 void tcg_context_init(TCGContext
*s
);
494 void tcg_prologue_init(TCGContext
*s
);
495 void tcg_func_start(TCGContext
*s
);
497 int tcg_gen_code(TCGContext
*s
, uint8_t *gen_code_buf
);
498 int tcg_gen_code_search_pc(TCGContext
*s
, uint8_t *gen_code_buf
, long offset
);
500 void tcg_set_frame(TCGContext
*s
, int reg
,
501 tcg_target_long start
, tcg_target_long size
);
503 TCGv_i32
tcg_global_reg_new_i32(int reg
, const char *name
);
504 TCGv_i32
tcg_global_mem_new_i32(int reg
, tcg_target_long offset
,
506 TCGv_i32
tcg_temp_new_internal_i32(int temp_local
);
507 static inline TCGv_i32
tcg_temp_new_i32(void)
509 return tcg_temp_new_internal_i32(0);
511 static inline TCGv_i32
tcg_temp_local_new_i32(void)
513 return tcg_temp_new_internal_i32(1);
515 void tcg_temp_free_i32(TCGv_i32 arg
);
516 char *tcg_get_arg_str_i32(TCGContext
*s
, char *buf
, int buf_size
, TCGv_i32 arg
);
518 TCGv_i64
tcg_global_reg_new_i64(int reg
, const char *name
);
519 TCGv_i64
tcg_global_mem_new_i64(int reg
, tcg_target_long offset
,
521 TCGv_i64
tcg_temp_new_internal_i64(int temp_local
);
522 static inline TCGv_i64
tcg_temp_new_i64(void)
524 return tcg_temp_new_internal_i64(0);
526 static inline TCGv_i64
tcg_temp_local_new_i64(void)
528 return tcg_temp_new_internal_i64(1);
530 void tcg_temp_free_i64(TCGv_i64 arg
);
531 char *tcg_get_arg_str_i64(TCGContext
*s
, char *buf
, int buf_size
, TCGv_i64 arg
);
533 #if defined(CONFIG_DEBUG_TCG)
534 /* If you call tcg_clear_temp_count() at the start of a section of
535 * code which is not supposed to leak any TCG temporaries, then
536 * calling tcg_check_temp_count() at the end of the section will
537 * return 1 if the section did in fact leak a temporary.
539 void tcg_clear_temp_count(void);
540 int tcg_check_temp_count(void);
542 #define tcg_clear_temp_count() do { } while (0)
543 #define tcg_check_temp_count() 0
546 void tcg_dump_info(FILE *f
, fprintf_function cpu_fprintf
);
548 #define TCG_CT_ALIAS 0x80
549 #define TCG_CT_IALIAS 0x40
550 #define TCG_CT_REG 0x01
551 #define TCG_CT_CONST 0x02 /* any constant of register size */
553 typedef struct TCGArgConstraint
{
561 #define TCG_MAX_OP_ARGS 16
563 /* Bits for TCGOpDef->flags, 8 bits available. */
565 /* Instruction defines the end of a basic block. */
566 TCG_OPF_BB_END
= 0x01,
567 /* Instruction clobbers call registers and potentially update globals. */
568 TCG_OPF_CALL_CLOBBER
= 0x02,
569 /* Instruction has side effects: it cannot be removed if its outputs
570 are not used, and might trigger exceptions. */
571 TCG_OPF_SIDE_EFFECTS
= 0x04,
572 /* Instruction operands are 64-bits (otherwise 32-bits). */
573 TCG_OPF_64BIT
= 0x08,
574 /* Instruction is optional and not implemented by the host. */
575 TCG_OPF_NOT_PRESENT
= 0x10,
578 typedef struct TCGOpDef
{
580 uint8_t nb_oargs
, nb_iargs
, nb_cargs
, nb_args
;
582 TCGArgConstraint
*args_ct
;
584 #if defined(CONFIG_DEBUG_TCG)
589 extern TCGOpDef tcg_op_defs
[];
590 extern const size_t tcg_op_defs_max
;
592 typedef struct TCGTargetOpDef
{
594 const char *args_ct_str
[TCG_MAX_OP_ARGS
];
597 #define tcg_abort() \
599 fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\
603 #ifdef CONFIG_DEBUG_TCG
604 # define tcg_debug_assert(X) do { assert(X); } while (0)
605 #elif QEMU_GNUC_PREREQ(4, 5)
606 # define tcg_debug_assert(X) \
607 do { if (!(X)) { __builtin_unreachable(); } } while (0)
609 # define tcg_debug_assert(X) do { (void)(X); } while (0)
612 void tcg_add_target_add_op_defs(const TCGTargetOpDef
*tdefs
);
614 #if TCG_TARGET_REG_BITS == 32
615 #define TCGV_NAT_TO_PTR(n) MAKE_TCGV_PTR(GET_TCGV_I32(n))
616 #define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I32(GET_TCGV_PTR(n))
618 #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i32((tcg_target_long)(V)))
619 #define tcg_global_reg_new_ptr(R, N) \
620 TCGV_NAT_TO_PTR(tcg_global_reg_new_i32((R), (N)))
621 #define tcg_global_mem_new_ptr(R, O, N) \
622 TCGV_NAT_TO_PTR(tcg_global_mem_new_i32((R), (O), (N)))
623 #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i32())
624 #define tcg_temp_free_ptr(T) tcg_temp_free_i32(TCGV_PTR_TO_NAT(T))
626 #define TCGV_NAT_TO_PTR(n) MAKE_TCGV_PTR(GET_TCGV_I64(n))
627 #define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I64(GET_TCGV_PTR(n))
629 #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i64((tcg_target_long)(V)))
630 #define tcg_global_reg_new_ptr(R, N) \
631 TCGV_NAT_TO_PTR(tcg_global_reg_new_i64((R), (N)))
632 #define tcg_global_mem_new_ptr(R, O, N) \
633 TCGV_NAT_TO_PTR(tcg_global_mem_new_i64((R), (O), (N)))
634 #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i64())
635 #define tcg_temp_free_ptr(T) tcg_temp_free_i64(TCGV_PTR_TO_NAT(T))
638 void tcg_gen_callN(TCGContext
*s
, TCGv_ptr func
, unsigned int flags
,
639 int sizemask
, TCGArg ret
, int nargs
, TCGArg
*args
);
641 void tcg_gen_shifti_i64(TCGv_i64 ret
, TCGv_i64 arg1
,
642 int c
, int right
, int arith
);
644 TCGArg
*tcg_optimize(TCGContext
*s
, uint16_t *tcg_opc_ptr
, TCGArg
*args
,
645 TCGOpDef
*tcg_op_def
);
647 /* only used for debugging purposes */
648 void tcg_register_helper(void *func
, const char *name
);
649 const char *tcg_helper_get_name(TCGContext
*s
, void *func
);
650 void tcg_dump_ops(TCGContext
*s
);
652 void dump_ops(const uint16_t *opc_buf
, const TCGArg
*opparam_buf
);
653 TCGv_i32
tcg_const_i32(int32_t val
);
654 TCGv_i64
tcg_const_i64(int64_t val
);
655 TCGv_i32
tcg_const_local_i32(int32_t val
);
656 TCGv_i64
tcg_const_local_i64(int64_t val
);
658 extern uint8_t *code_gen_prologue
;
660 /* TCG targets may use a different definition of tcg_qemu_tb_exec. */
661 #if !defined(tcg_qemu_tb_exec)
662 # define tcg_qemu_tb_exec(env, tb_ptr) \
663 ((tcg_target_ulong (*)(void *, void *))code_gen_prologue)(env, tb_ptr)
666 void tcg_register_jit(void *buf
, size_t buf_size
);
668 #if defined(CONFIG_QEMU_LDST_OPTIMIZATION) && defined(CONFIG_SOFTMMU)
669 /* Generate TB finalization at the end of block */
670 void tcg_out_tb_finalize(TCGContext
*s
);