hw/versatilepb.c

   1 /*
   2  * ARM Versatile Platform/Application Baseboard System emulation.
   3  *
   4  * Copyright (c) 2005-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "sysbus.h"
  11 #include "arm-misc.h"
  12 #include "devices.h"
  13 #include "net.h"
  14 #include "sysemu.h"
  15 #include "pci.h"
  16 #include "boards.h"
  17 #include "blockdev.h"
  18 #include "exec-memory.h"
  19
  20 /* Primary interrupt controller.  */
  21
  22 typedef struct vpb_sic_state
  23 {
  24   SysBusDevice busdev;
  25   MemoryRegion iomem;
  26   uint32_t level;
  27   uint32_t mask;
  28   uint32_t pic_enable;
  29   qemu_irq parent[32];
  30   int irq;
  31 } vpb_sic_state;
  32
  33 static const VMStateDescription vmstate_vpb_sic = {
  34     .name = "versatilepb_sic",
  35     .version_id = 1,
  36     .minimum_version_id = 1,
  37     .fields = (VMStateField[]) {
  38         VMSTATE_UINT32(level, vpb_sic_state),
  39         VMSTATE_UINT32(mask, vpb_sic_state),
  40         VMSTATE_UINT32(pic_enable, vpb_sic_state),
  41         VMSTATE_END_OF_LIST()
  42     }
  43 };
  44
  45 static void vpb_sic_update(vpb_sic_state *s)
  46 {
  47     uint32_t flags;
  48
  49     flags = s->level & s->mask;
  50     qemu_set_irq(s->parent[s->irq], flags != 0);
  51 }
  52
  53 static void vpb_sic_update_pic(vpb_sic_state *s)
  54 {
  55     int i;
  56     uint32_t mask;
  57
  58     for (i = 21; i <= 30; i++) {
  59         mask = 1u << i;
  60         if (!(s->pic_enable & mask))
  61             continue;
  62         qemu_set_irq(s->parent[i], (s->level & mask) != 0);
  63     }
  64 }
  65
  66 static void vpb_sic_set_irq(void *opaque, int irq, int level)
  67 {
  68     vpb_sic_state *s = (vpb_sic_state *)opaque;
  69     if (level)
  70         s->level |= 1u << irq;
  71     else
  72         s->level &= ~(1u << irq);
  73     if (s->pic_enable & (1u << irq))
  74         qemu_set_irq(s->parent[irq], level);
  75     vpb_sic_update(s);
  76 }
  77
  78 static uint64_t vpb_sic_read(void *opaque, target_phys_addr_t offset,
  79                              unsigned size)
  80 {
  81     vpb_sic_state *s = (vpb_sic_state *)opaque;
  82
  83     switch (offset >> 2) {
  84     case 0: /* STATUS */
  85         return s->level & s->mask;
  86     case 1: /* RAWSTAT */
  87         return s->level;
  88     case 2: /* ENABLE */
  89         return s->mask;
  90     case 4: /* SOFTINT */
  91         return s->level & 1;
  92     case 8: /* PICENABLE */
  93         return s->pic_enable;
  94     default:
  95         printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset);
  96         return 0;
  97     }
  98 }
  99
 100 static void vpb_sic_write(void *opaque, target_phys_addr_t offset,
 101                           uint64_t value, unsigned size)
 102 {
 103     vpb_sic_state *s = (vpb_sic_state *)opaque;
 104
 105     switch (offset >> 2) {
 106     case 2: /* ENSET */
 107         s->mask |= value;
 108         break;
 109     case 3: /* ENCLR */
 110         s->mask &= ~value;
 111         break;
 112     case 4: /* SOFTINTSET */
 113         if (value)
 114             s->mask |= 1;
 115         break;
 116     case 5: /* SOFTINTCLR */
 117         if (value)
 118             s->mask &= ~1u;
 119         break;
 120     case 8: /* PICENSET */
 121         s->pic_enable |= (value & 0x7fe00000);
 122         vpb_sic_update_pic(s);
 123         break;
 124     case 9: /* PICENCLR */
 125         s->pic_enable &= ~value;
 126         vpb_sic_update_pic(s);
 127         break;
 128     default:
 129         printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset);
 130         return;
 131     }
 132     vpb_sic_update(s);
 133 }
 134
 135 static const MemoryRegionOps vpb_sic_ops = {
 136     .read = vpb_sic_read,
 137     .write = vpb_sic_write,
 138     .endianness = DEVICE_NATIVE_ENDIAN,
 139 };
 140
 141 static int vpb_sic_init(SysBusDevice *dev)
 142 {
 143     vpb_sic_state *s = FROM_SYSBUS(vpb_sic_state, dev);
 144     int i;
 145
 146     qdev_init_gpio_in(&dev->qdev, vpb_sic_set_irq, 32);
 147     for (i = 0; i < 32; i++) {
 148         sysbus_init_irq(dev, &s->parent[i]);
 149     }
 150     s->irq = 31;
 151     memory_region_init_io(&s->iomem, &vpb_sic_ops, s, "vpb-sic", 0x1000);
 152     sysbus_init_mmio(dev, &s->iomem);
 153     return 0;
 154 }
 155
 156 /* Board init.  */
 157
 158 /* The AB and PB boards both use the same core, just with different
 159    peripherans and expansion busses.  For now we emulate a subset of the
 160    PB peripherals and just change the board ID.  */
 161
 162 static struct arm_boot_info versatile_binfo;
 163
 164 static void versatile_init(ram_addr_t ram_size,
 165                      const char *boot_device,
 166                      const char *kernel_filename, const char *kernel_cmdline,
 167                      const char *initrd_filename, const char *cpu_model,
 168                      int board_id)
 169 {
 170     CPUState *env;
 171     MemoryRegion *sysmem = get_system_memory();
 172     MemoryRegion *ram = g_new(MemoryRegion, 1);
 173     qemu_irq *cpu_pic;
 174     qemu_irq pic[32];
 175     qemu_irq sic[32];
 176     DeviceState *dev, *sysctl;
 177     SysBusDevice *busdev;
 178     DeviceState *pl041;
 179     PCIBus *pci_bus;
 180     NICInfo *nd;
 181     int n;
 182     int done_smc = 0;
 183
 184     if (!cpu_model)
 185         cpu_model = "arm926";
 186     env = cpu_init(cpu_model);
 187     if (!env) {
 188         fprintf(stderr, "Unable to find CPU definition\n");
 189         exit(1);
 190     }
 191     memory_region_init_ram(ram, "versatile.ram", ram_size);
 192     vmstate_register_ram_global(ram);
 193     /* ??? RAM should repeat to fill physical memory space.  */
 194     /* SDRAM at address zero.  */
 195     memory_region_add_subregion(sysmem, 0, ram);
 196
 197     sysctl = qdev_create(NULL, "realview_sysctl");
 198     qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004);
 199     qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000);
 200     qdev_init_nofail(sysctl);
 201     sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000);
 202
 203     cpu_pic = arm_pic_init_cpu(env);
 204     dev = sysbus_create_varargs("pl190", 0x10140000,
 205                                 cpu_pic[0], cpu_pic[1], NULL);
 206     for (n = 0; n < 32; n++) {
 207         pic[n] = qdev_get_gpio_in(dev, n);
 208     }
 209     dev = sysbus_create_simple("versatilepb_sic", 0x10003000, NULL);
 210     for (n = 0; n < 32; n++) {
 211         sysbus_connect_irq(sysbus_from_qdev(dev), n, pic[n]);
 212         sic[n] = qdev_get_gpio_in(dev, n);
 213     }
 214
 215     sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]);
 216     sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]);
 217
 218     dev = qdev_create(NULL, "versatile_pci");
 219     busdev = sysbus_from_qdev(dev);
 220     qdev_init_nofail(dev);
 221     sysbus_mmio_map(busdev, 0, 0x41000000); /* PCI self-config */
 222     sysbus_mmio_map(busdev, 1, 0x42000000); /* PCI config */
 223     sysbus_connect_irq(busdev, 0, sic[27]);
 224     sysbus_connect_irq(busdev, 1, sic[28]);
 225     sysbus_connect_irq(busdev, 2, sic[29]);
 226     sysbus_connect_irq(busdev, 3, sic[30]);
 227     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
 228
 229     /* The Versatile PCI bridge does not provide access to PCI IO space,
 230        so many of the qemu PCI devices are not useable.  */
 231     for(n = 0; n < nb_nics; n++) {
 232         nd = &nd_table[n];
 233
 234         if (!done_smc && (!nd->model || strcmp(nd->model, "smc91c111") == 0)) {
 235             smc91c111_init(nd, 0x10010000, sic[25]);
 236             done_smc = 1;
 237         } else {
 238             pci_nic_init_nofail(nd, "rtl8139", NULL);
 239         }
 240     }
 241     if (usb_enabled) {
 242         pci_create_simple(pci_bus, -1, "pci-ohci");
 243     }
 244     n = drive_get_max_bus(IF_SCSI);
 245     while (n >= 0) {
 246         pci_create_simple(pci_bus, -1, "lsi53c895a");
 247         n--;
 248     }
 249
 250     sysbus_create_simple("pl011", 0x101f1000, pic[12]);
 251     sysbus_create_simple("pl011", 0x101f2000, pic[13]);
 252     sysbus_create_simple("pl011", 0x101f3000, pic[14]);
 253     sysbus_create_simple("pl011", 0x10009000, sic[6]);
 254
 255     sysbus_create_simple("pl080", 0x10130000, pic[17]);
 256     sysbus_create_simple("sp804", 0x101e2000, pic[4]);
 257     sysbus_create_simple("sp804", 0x101e3000, pic[5]);
 258
 259     /* The versatile/PB actually has a modified Color LCD controller
 260        that includes hardware cursor support from the PL111.  */
 261     dev = sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]);
 262     /* Wire up the mux control signals from the SYS_CLCD register */
 263     qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0));
 264
 265     sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL);
 266     sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL);
 267
 268     /* Add PL031 Real Time Clock. */
 269     sysbus_create_simple("pl031", 0x101e8000, pic[10]);
 270
 271     /* Add PL041 AACI Interface to the LM4549 codec */
 272     pl041 = qdev_create(NULL, "pl041");
 273     qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
 274     qdev_init_nofail(pl041);
 275     sysbus_mmio_map(sysbus_from_qdev(pl041), 0, 0x10004000);
 276     sysbus_connect_irq(sysbus_from_qdev(pl041), 0, sic[24]);
 277
 278     /* Memory map for Versatile/PB:  */
 279     /* 0x10000000 System registers.  */
 280     /* 0x10001000 PCI controller config registers.  */
 281     /* 0x10002000 Serial bus interface.  */
 282     /*  0x10003000 Secondary interrupt controller.  */
 283     /* 0x10004000 AACI (audio).  */
 284     /*  0x10005000 MMCI0.  */
 285     /*  0x10006000 KMI0 (keyboard).  */
 286     /*  0x10007000 KMI1 (mouse).  */
 287     /* 0x10008000 Character LCD Interface.  */
 288     /*  0x10009000 UART3.  */
 289     /* 0x1000a000 Smart card 1.  */
 290     /*  0x1000b000 MMCI1.  */
 291     /*  0x10010000 Ethernet.  */
 292     /* 0x10020000 USB.  */
 293     /* 0x10100000 SSMC.  */
 294     /* 0x10110000 MPMC.  */
 295     /*  0x10120000 CLCD Controller.  */
 296     /*  0x10130000 DMA Controller.  */
 297     /*  0x10140000 Vectored interrupt controller.  */
 298     /* 0x101d0000 AHB Monitor Interface.  */
 299     /* 0x101e0000 System Controller.  */
 300     /* 0x101e1000 Watchdog Interface.  */
 301     /* 0x101e2000 Timer 0/1.  */
 302     /* 0x101e3000 Timer 2/3.  */
 303     /* 0x101e4000 GPIO port 0.  */
 304     /* 0x101e5000 GPIO port 1.  */
 305     /* 0x101e6000 GPIO port 2.  */
 306     /* 0x101e7000 GPIO port 3.  */
 307     /* 0x101e8000 RTC.  */
 308     /* 0x101f0000 Smart card 0.  */
 309     /*  0x101f1000 UART0.  */
 310     /*  0x101f2000 UART1.  */
 311     /*  0x101f3000 UART2.  */
 312     /* 0x101f4000 SSPI.  */
 313
 314     versatile_binfo.ram_size = ram_size;
 315     versatile_binfo.kernel_filename = kernel_filename;
 316     versatile_binfo.kernel_cmdline = kernel_cmdline;
 317     versatile_binfo.initrd_filename = initrd_filename;
 318     versatile_binfo.board_id = board_id;
 319     arm_load_kernel(env, &versatile_binfo);
 320 }
 321
 322 static void vpb_init(ram_addr_t ram_size,
 323                      const char *boot_device,
 324                      const char *kernel_filename, const char *kernel_cmdline,
 325                      const char *initrd_filename, const char *cpu_model)
 326 {
 327     versatile_init(ram_size,
 328                    boot_device,
 329                    kernel_filename, kernel_cmdline,
 330                    initrd_filename, cpu_model, 0x183);
 331 }
 332
 333 static void vab_init(ram_addr_t ram_size,
 334                      const char *boot_device,
 335                      const char *kernel_filename, const char *kernel_cmdline,
 336                      const char *initrd_filename, const char *cpu_model)
 337 {
 338     versatile_init(ram_size,
 339                    boot_device,
 340                    kernel_filename, kernel_cmdline,
 341                    initrd_filename, cpu_model, 0x25e);
 342 }
 343
 344 static QEMUMachine versatilepb_machine = {
 345     .name = "versatilepb",
 346     .desc = "ARM Versatile/PB (ARM926EJ-S)",
 347     .init = vpb_init,
 348     .use_scsi = 1,
 349 };
 350
 351 static QEMUMachine versatileab_machine = {
 352     .name = "versatileab",
 353     .desc = "ARM Versatile/AB (ARM926EJ-S)",
 354     .init = vab_init,
 355     .use_scsi = 1,
 356 };
 357
 358 static void versatile_machine_init(void)
 359 {
 360     qemu_register_machine(&versatilepb_machine);
 361     qemu_register_machine(&versatileab_machine);
 362 }
 363
 364 machine_init(versatile_machine_init);
 365
 366 static void vpb_sic_class_init(ObjectClass *klass, void *data)
 367 {
 368     DeviceClass *dc = DEVICE_CLASS(klass);
 369     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 370
 371     k->init = vpb_sic_init;
 372     dc->no_user = 1;
 373     dc->vmsd = &vmstate_vpb_sic;
 374 }
 375
 376 static TypeInfo vpb_sic_info = {
 377     .name          = "versatilepb_sic",
 378     .parent        = TYPE_SYS_BUS_DEVICE,
 379     .instance_size = sizeof(vpb_sic_state),
 380     .class_init    = vpb_sic_class_init,
 381 };
 382
 383 static void versatilepb_register_types(void)
 384 {
 385     type_register_static(&vpb_sic_info);
 386 }
 387
 388 type_init(versatilepb_register_types)