hw/arm_mptimer.c

   1 /*
   2  * Private peripheral timer/watchdog blocks for ARM 11MPCore and A9MP
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Copyright (c) 2011 Linaro Limited
   6  * Written by Paul Brook, Peter Maydell
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version
  11  * 2 of the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "sysbus.h"
  23 #include "qemu/timer.h"
  24
  25 /* This device implements the per-cpu private timer and watchdog block
  26  * which is used in both the ARM11MPCore and Cortex-A9MP.
  27  */
  28
  29 #define MAX_CPUS 4
  30
  31 /* State of a single timer or watchdog block */
  32 typedef struct {
  33     uint32_t count;
  34     uint32_t load;
  35     uint32_t control;
  36     uint32_t status;
  37     int64_t tick;
  38     QEMUTimer *timer;
  39     qemu_irq irq;
  40     MemoryRegion iomem;
  41 } timerblock;
  42
  43 typedef struct {
  44     SysBusDevice busdev;
  45     uint32_t num_cpu;
  46     timerblock timerblock[MAX_CPUS * 2];
  47     MemoryRegion iomem[2];
  48 } arm_mptimer_state;
  49
  50 static inline int get_current_cpu(arm_mptimer_state *s)
  51 {
  52     CPUState *cpu_single_cpu = ENV_GET_CPU(cpu_single_env);
  53
  54     if (cpu_single_cpu->cpu_index >= s->num_cpu) {
  55         hw_error("arm_mptimer: num-cpu %d but this cpu is %d!\n",
  56                  s->num_cpu, cpu_single_cpu->cpu_index);
  57     }
  58     return cpu_single_cpu->cpu_index;
  59 }
  60
  61 static inline void timerblock_update_irq(timerblock *tb)
  62 {
  63     qemu_set_irq(tb->irq, tb->status);
  64 }
  65
  66 /* Return conversion factor from mpcore timer ticks to qemu timer ticks.  */
  67 static inline uint32_t timerblock_scale(timerblock *tb)
  68 {
  69     return (((tb->control >> 8) & 0xff) + 1) * 10;
  70 }
  71
  72 static void timerblock_reload(timerblock *tb, int restart)
  73 {
  74     if (tb->count == 0) {
  75         return;
  76     }
  77     if (restart) {
  78         tb->tick = qemu_get_clock_ns(vm_clock);
  79     }
  80     tb->tick += (int64_t)tb->count * timerblock_scale(tb);
  81     qemu_mod_timer(tb->timer, tb->tick);
  82 }
  83
  84 static void timerblock_tick(void *opaque)
  85 {
  86     timerblock *tb = (timerblock *)opaque;
  87     tb->status = 1;
  88     if (tb->control & 2) {
  89         tb->count = tb->load;
  90         timerblock_reload(tb, 0);
  91     } else {
  92         tb->count = 0;
  93     }
  94     timerblock_update_irq(tb);
  95 }
  96
  97 static uint64_t timerblock_read(void *opaque, hwaddr addr,
  98                                 unsigned size)
  99 {
 100     timerblock *tb = (timerblock *)opaque;
 101     int64_t val;
 102     switch (addr) {
 103     case 0: /* Load */
 104         return tb->load;
 105     case 4: /* Counter.  */
 106         if (((tb->control & 1) == 0) || (tb->count == 0)) {
 107             return 0;
 108         }
 109         /* Slow and ugly, but hopefully won't happen too often.  */
 110         val = tb->tick - qemu_get_clock_ns(vm_clock);
 111         val /= timerblock_scale(tb);
 112         if (val < 0) {
 113             val = 0;
 114         }
 115         return val;
 116     case 8: /* Control.  */
 117         return tb->control;
 118     case 12: /* Interrupt status.  */
 119         return tb->status;
 120     default:
 121         return 0;
 122     }
 123 }
 124
 125 static void timerblock_write(void *opaque, hwaddr addr,
 126                              uint64_t value, unsigned size)
 127 {
 128     timerblock *tb = (timerblock *)opaque;
 129     int64_t old;
 130     switch (addr) {
 131     case 0: /* Load */
 132         tb->load = value;
 133         /* Fall through.  */
 134     case 4: /* Counter.  */
 135         if ((tb->control & 1) && tb->count) {
 136             /* Cancel the previous timer.  */
 137             qemu_del_timer(tb->timer);
 138         }
 139         tb->count = value;
 140         if (tb->control & 1) {
 141             timerblock_reload(tb, 1);
 142         }
 143         break;
 144     case 8: /* Control.  */
 145         old = tb->control;
 146         tb->control = value;
 147         if (((old & 1) == 0) && (value & 1)) {
 148             if (tb->count == 0 && (tb->control & 2)) {
 149                 tb->count = tb->load;
 150             }
 151             timerblock_reload(tb, 1);
 152         }
 153         break;
 154     case 12: /* Interrupt status.  */
 155         tb->status &= ~value;
 156         timerblock_update_irq(tb);
 157         break;
 158     }
 159 }
 160
 161 /* Wrapper functions to implement the "read timer/watchdog for
 162  * the current CPU" memory regions.
 163  */
 164 static uint64_t arm_thistimer_read(void *opaque, hwaddr addr,
 165                                    unsigned size)
 166 {
 167     arm_mptimer_state *s = (arm_mptimer_state *)opaque;
 168     int id = get_current_cpu(s);
 169     return timerblock_read(&s->timerblock[id * 2], addr, size);
 170 }
 171
 172 static void arm_thistimer_write(void *opaque, hwaddr addr,
 173                                 uint64_t value, unsigned size)
 174 {
 175     arm_mptimer_state *s = (arm_mptimer_state *)opaque;
 176     int id = get_current_cpu(s);
 177     timerblock_write(&s->timerblock[id * 2], addr, value, size);
 178 }
 179
 180 static uint64_t arm_thiswdog_read(void *opaque, hwaddr addr,
 181                                   unsigned size)
 182 {
 183     arm_mptimer_state *s = (arm_mptimer_state *)opaque;
 184     int id = get_current_cpu(s);
 185     return timerblock_read(&s->timerblock[id * 2 + 1], addr, size);
 186 }
 187
 188 static void arm_thiswdog_write(void *opaque, hwaddr addr,
 189                                uint64_t value, unsigned size)
 190 {
 191     arm_mptimer_state *s = (arm_mptimer_state *)opaque;
 192     int id = get_current_cpu(s);
 193     timerblock_write(&s->timerblock[id * 2 + 1], addr, value, size);
 194 }
 195
 196 static const MemoryRegionOps arm_thistimer_ops = {
 197     .read = arm_thistimer_read,
 198     .write = arm_thistimer_write,
 199     .valid = {
 200         .min_access_size = 4,
 201         .max_access_size = 4,
 202     },
 203     .endianness = DEVICE_NATIVE_ENDIAN,
 204 };
 205
 206 static const MemoryRegionOps arm_thiswdog_ops = {
 207     .read = arm_thiswdog_read,
 208     .write = arm_thiswdog_write,
 209     .valid = {
 210         .min_access_size = 4,
 211         .max_access_size = 4,
 212     },
 213     .endianness = DEVICE_NATIVE_ENDIAN,
 214 };
 215
 216 static const MemoryRegionOps timerblock_ops = {
 217     .read = timerblock_read,
 218     .write = timerblock_write,
 219     .valid = {
 220         .min_access_size = 4,
 221         .max_access_size = 4,
 222     },
 223     .endianness = DEVICE_NATIVE_ENDIAN,
 224 };
 225
 226 static void timerblock_reset(timerblock *tb)
 227 {
 228     tb->count = 0;
 229     tb->load = 0;
 230     tb->control = 0;
 231     tb->status = 0;
 232     tb->tick = 0;
 233     if (tb->timer) {
 234         qemu_del_timer(tb->timer);
 235     }
 236 }
 237
 238 static void arm_mptimer_reset(DeviceState *dev)
 239 {
 240     arm_mptimer_state *s =
 241         FROM_SYSBUS(arm_mptimer_state, sysbus_from_qdev(dev));
 242     int i;
 243     /* We reset every timer in the array, not just the ones we're using,
 244      * because vmsave will look at every array element.
 245      */
 246     for (i = 0; i < ARRAY_SIZE(s->timerblock); i++) {
 247         timerblock_reset(&s->timerblock[i]);
 248     }
 249 }
 250
 251 static int arm_mptimer_init(SysBusDevice *dev)
 252 {
 253     arm_mptimer_state *s = FROM_SYSBUS(arm_mptimer_state, dev);
 254     int i;
 255     if (s->num_cpu < 1 || s->num_cpu > MAX_CPUS) {
 256         hw_error("%s: num-cpu must be between 1 and %d\n", __func__, MAX_CPUS);
 257     }
 258     /* We implement one timer and one watchdog block per CPU, and
 259      * expose multiple MMIO regions:
 260      *  * region 0 is "timer for this core"
 261      *  * region 1 is "watchdog for this core"
 262      *  * region 2 is "timer for core 0"
 263      *  * region 3 is "watchdog for core 0"
 264      *  * region 4 is "timer for core 1"
 265      *  * region 5 is "watchdog for core 1"
 266      * and so on.
 267      * The outgoing interrupt lines are
 268      *  * timer for core 0
 269      *  * watchdog for core 0
 270      *  * timer for core 1
 271      *  * watchdog for core 1
 272      * and so on.
 273      */
 274     memory_region_init_io(&s->iomem[0], &arm_thistimer_ops, s,
 275                           "arm_mptimer_timer", 0x20);
 276     sysbus_init_mmio(dev, &s->iomem[0]);
 277     memory_region_init_io(&s->iomem[1], &arm_thiswdog_ops, s,
 278                           "arm_mptimer_wdog", 0x20);
 279     sysbus_init_mmio(dev, &s->iomem[1]);
 280     for (i = 0; i < (s->num_cpu * 2); i++) {
 281         timerblock *tb = &s->timerblock[i];
 282         tb->timer = qemu_new_timer_ns(vm_clock, timerblock_tick, tb);
 283         sysbus_init_irq(dev, &tb->irq);
 284         memory_region_init_io(&tb->iomem, &timerblock_ops, tb,
 285                               "arm_mptimer_timerblock", 0x20);
 286         sysbus_init_mmio(dev, &tb->iomem);
 287     }
 288
 289     return 0;
 290 }
 291
 292 static const VMStateDescription vmstate_timerblock = {
 293     .name = "arm_mptimer_timerblock",
 294     .version_id = 1,
 295     .minimum_version_id = 1,
 296     .fields = (VMStateField[]) {
 297         VMSTATE_UINT32(count, timerblock),
 298         VMSTATE_UINT32(load, timerblock),
 299         VMSTATE_UINT32(control, timerblock),
 300         VMSTATE_UINT32(status, timerblock),
 301         VMSTATE_INT64(tick, timerblock),
 302         VMSTATE_END_OF_LIST()
 303     }
 304 };
 305
 306 static const VMStateDescription vmstate_arm_mptimer = {
 307     .name = "arm_mptimer",
 308     .version_id = 1,
 309     .minimum_version_id = 1,
 310     .fields = (VMStateField[]) {
 311         VMSTATE_STRUCT_ARRAY(timerblock, arm_mptimer_state, (MAX_CPUS * 2),
 312                              1, vmstate_timerblock, timerblock),
 313         VMSTATE_END_OF_LIST()
 314     }
 315 };
 316
 317 static Property arm_mptimer_properties[] = {
 318     DEFINE_PROP_UINT32("num-cpu", arm_mptimer_state, num_cpu, 0),
 319     DEFINE_PROP_END_OF_LIST()
 320 };
 321
 322 static void arm_mptimer_class_init(ObjectClass *klass, void *data)
 323 {
 324     DeviceClass *dc = DEVICE_CLASS(klass);
 325     SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
 326
 327     sbc->init = arm_mptimer_init;
 328     dc->vmsd = &vmstate_arm_mptimer;
 329     dc->reset = arm_mptimer_reset;
 330     dc->no_user = 1;
 331     dc->props = arm_mptimer_properties;
 332 }
 333
 334 static const TypeInfo arm_mptimer_info = {
 335     .name          = "arm_mptimer",
 336     .parent        = TYPE_SYS_BUS_DEVICE,
 337     .instance_size = sizeof(arm_mptimer_state),
 338     .class_init    = arm_mptimer_class_init,
 339 };
 340
 341 static void arm_mptimer_register_types(void)
 342 {
 343     type_register_static(&arm_mptimer_info);
 344 }
 345
 346 type_init(arm_mptimer_register_types)