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ppc: Pass PowerPCCPU to [h]decr callbacks
[qemu/opensuse.git] / target-sparc / ldst_helper.c
blob8d815e503899a3190fd71730502dffe62295be1d
1 /*
2 * Helpers for loads and stores
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "cpu.h"
21 #include "helper.h"
22
23 //#define DEBUG_MMU
24 //#define DEBUG_MXCC
25 //#define DEBUG_UNALIGNED
26 //#define DEBUG_UNASSIGNED
27 //#define DEBUG_ASI
28 //#define DEBUG_CACHE_CONTROL
29
30 #ifdef DEBUG_MMU
31 #define DPRINTF_MMU(fmt, ...) \
32 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
33 #else
34 #define DPRINTF_MMU(fmt, ...) do {} while (0)
35 #endif
36
37 #ifdef DEBUG_MXCC
38 #define DPRINTF_MXCC(fmt, ...) \
39 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
40 #else
41 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
42 #endif
43
44 #ifdef DEBUG_ASI
45 #define DPRINTF_ASI(fmt, ...) \
46 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
47 #endif
48
49 #ifdef DEBUG_CACHE_CONTROL
50 #define DPRINTF_CACHE_CONTROL(fmt, ...) \
51 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
52 #else
53 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
54 #endif
55
56 #ifdef TARGET_SPARC64
57 #ifndef TARGET_ABI32
58 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
59 #else
60 #define AM_CHECK(env1) (1)
61 #endif
62 #endif
63
64 #define QT0 (env->qt0)
65 #define QT1 (env->qt1)
66
67 #if !defined(CONFIG_USER_ONLY)
68 static void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env,
69 target_ulong addr, int is_write,
70 int is_user, uintptr_t retaddr);
71 #include "softmmu_exec.h"
72 #define MMUSUFFIX _mmu
73 #define ALIGNED_ONLY
74
75 #define SHIFT 0
76 #include "softmmu_template.h"
77
78 #define SHIFT 1
79 #include "softmmu_template.h"
80
81 #define SHIFT 2
82 #include "softmmu_template.h"
83
84 #define SHIFT 3
85 #include "softmmu_template.h"
86 #endif
87
88 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
89 /* Calculates TSB pointer value for fault page size 8k or 64k */
90 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
91 uint64_t tag_access_register,
92 int page_size)
93 {
94 uint64_t tsb_base = tsb_register & ~0x1fffULL;
95 int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0;
96 int tsb_size = tsb_register & 0xf;
97
98 /* discard lower 13 bits which hold tag access context */
99 uint64_t tag_access_va = tag_access_register & ~0x1fffULL;
100
101 /* now reorder bits */
102 uint64_t tsb_base_mask = ~0x1fffULL;
103 uint64_t va = tag_access_va;
104
105 /* move va bits to correct position */
106 if (page_size == 8*1024) {
107 va >>= 9;
108 } else if (page_size == 64*1024) {
109 va >>= 12;
110 }
111
112 if (tsb_size) {
113 tsb_base_mask <<= tsb_size;
114 }
115
116 /* calculate tsb_base mask and adjust va if split is in use */
117 if (tsb_split) {
118 if (page_size == 8*1024) {
119 va &= ~(1ULL << (13 + tsb_size));
120 } else if (page_size == 64*1024) {
121 va |= (1ULL << (13 + tsb_size));
122 }
123 tsb_base_mask <<= 1;
124 }
125
126 return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;
127 }
128
129 /* Calculates tag target register value by reordering bits
130 in tag access register */
131 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
132 {
133 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22);
134 }
135
136 static void replace_tlb_entry(SparcTLBEntry *tlb,
137 uint64_t tlb_tag, uint64_t tlb_tte,
138 CPUSPARCState *env1)
139 {
140 target_ulong mask, size, va, offset;
141
142 /* flush page range if translation is valid */
143 if (TTE_IS_VALID(tlb->tte)) {
144
145 mask = 0xffffffffffffe000ULL;
146 mask <<= 3 * ((tlb->tte >> 61) & 3);
147 size = ~mask + 1;
148
149 va = tlb->tag & mask;
150
151 for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) {
152 tlb_flush_page(env1, va + offset);
153 }
154 }
155
156 tlb->tag = tlb_tag;
157 tlb->tte = tlb_tte;
158 }
159
160 static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,
161 const char *strmmu, CPUSPARCState *env1)
162 {
163 unsigned int i;
164 target_ulong mask;
165 uint64_t context;
166
167 int is_demap_context = (demap_addr >> 6) & 1;
168
169 /* demap context */
170 switch ((demap_addr >> 4) & 3) {
171 case 0: /* primary */
172 context = env1->dmmu.mmu_primary_context;
173 break;
174 case 1: /* secondary */
175 context = env1->dmmu.mmu_secondary_context;
176 break;
177 case 2: /* nucleus */
178 context = 0;
179 break;
180 case 3: /* reserved */
181 default:
182 return;
183 }
184
185 for (i = 0; i < 64; i++) {
186 if (TTE_IS_VALID(tlb[i].tte)) {
187
188 if (is_demap_context) {
189 /* will remove non-global entries matching context value */
190 if (TTE_IS_GLOBAL(tlb[i].tte) ||
191 !tlb_compare_context(&tlb[i], context)) {
192 continue;
193 }
194 } else {
195 /* demap page
196 will remove any entry matching VA */
197 mask = 0xffffffffffffe000ULL;
198 mask <<= 3 * ((tlb[i].tte >> 61) & 3);
199
200 if (!compare_masked(demap_addr, tlb[i].tag, mask)) {
201 continue;
202 }
203
204 /* entry should be global or matching context value */
205 if (!TTE_IS_GLOBAL(tlb[i].tte) &&
206 !tlb_compare_context(&tlb[i], context)) {
207 continue;
208 }
209 }
210
211 replace_tlb_entry(&tlb[i], 0, 0, env1);
212 #ifdef DEBUG_MMU
213 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
214 dump_mmu(stdout, fprintf, env1);
215 #endif
216 }
217 }
218 }
219
220 static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
221 uint64_t tlb_tag, uint64_t tlb_tte,
222 const char *strmmu, CPUSPARCState *env1)
223 {
224 unsigned int i, replace_used;
225
226 /* Try replacing invalid entry */
227 for (i = 0; i < 64; i++) {
228 if (!TTE_IS_VALID(tlb[i].tte)) {
229 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
230 #ifdef DEBUG_MMU
231 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);
232 dump_mmu(stdout, fprintf, env1);
233 #endif
234 return;
235 }
236 }
237
238 /* All entries are valid, try replacing unlocked entry */
239
240 for (replace_used = 0; replace_used < 2; ++replace_used) {
241
242 /* Used entries are not replaced on first pass */
243
244 for (i = 0; i < 64; i++) {
245 if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) {
246
247 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
248 #ifdef DEBUG_MMU
249 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
250 strmmu, (replace_used ? "used" : "unused"), i);
251 dump_mmu(stdout, fprintf, env1);
252 #endif
253 return;
254 }
255 }
256
257 /* Now reset used bit and search for unused entries again */
258
259 for (i = 0; i < 64; i++) {
260 TTE_SET_UNUSED(tlb[i].tte);
261 }
262 }
263
264 #ifdef DEBUG_MMU
265 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu);
266 #endif
267 /* error state? */
268 }
269
270 #endif
271
272 static inline target_ulong address_mask(CPUSPARCState *env1, target_ulong addr)
273 {
274 #ifdef TARGET_SPARC64
275 if (AM_CHECK(env1)) {
276 addr &= 0xffffffffULL;
277 }
278 #endif
279 return addr;
280 }
281
282 /* returns true if access using this ASI is to have address translated by MMU
283 otherwise access is to raw physical address */
284 static inline int is_translating_asi(int asi)
285 {
286 #ifdef TARGET_SPARC64
287 /* Ultrasparc IIi translating asi
288 - note this list is defined by cpu implementation
289 */
290 switch (asi) {
291 case 0x04 ... 0x11:
292 case 0x16 ... 0x19:
293 case 0x1E ... 0x1F:
294 case 0x24 ... 0x2C:
295 case 0x70 ... 0x73:
296 case 0x78 ... 0x79:
297 case 0x80 ... 0xFF:
298 return 1;
299
300 default:
301 return 0;
302 }
303 #else
304 /* TODO: check sparc32 bits */
305 return 0;
306 #endif
307 }
308
309 static inline target_ulong asi_address_mask(CPUSPARCState *env,
310 int asi, target_ulong addr)
311 {
312 if (is_translating_asi(asi)) {
313 return address_mask(env, addr);
314 } else {
315 return addr;
316 }
317 }
318
319 void helper_check_align(CPUSPARCState *env, target_ulong addr, uint32_t align)
320 {
321 if (addr & align) {
322 #ifdef DEBUG_UNALIGNED
323 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
324 "\n", addr, env->pc);
325 #endif
326 helper_raise_exception(env, TT_UNALIGNED);
327 }
328 }
329
330 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
331 defined(DEBUG_MXCC)
332 static void dump_mxcc(CPUSPARCState *env)
333 {
334 printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
335 "\n",
336 env->mxccdata[0], env->mxccdata[1],
337 env->mxccdata[2], env->mxccdata[3]);
338 printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
339 "\n"
340 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
341 "\n",
342 env->mxccregs[0], env->mxccregs[1],
343 env->mxccregs[2], env->mxccregs[3],
344 env->mxccregs[4], env->mxccregs[5],
345 env->mxccregs[6], env->mxccregs[7]);
346 }
347 #endif
348
349 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
350 && defined(DEBUG_ASI)
351 static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
352 uint64_t r1)
353 {
354 switch (size) {
355 case 1:
356 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
357 addr, asi, r1 & 0xff);
358 break;
359 case 2:
360 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
361 addr, asi, r1 & 0xffff);
362 break;
363 case 4:
364 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
365 addr, asi, r1 & 0xffffffff);
366 break;
367 case 8:
368 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
369 addr, asi, r1);
370 break;
371 }
372 }
373 #endif
374
375 #ifndef TARGET_SPARC64
376 #ifndef CONFIG_USER_ONLY
377
378
379 /* Leon3 cache control */
380
381 static void leon3_cache_control_st(CPUSPARCState *env, target_ulong addr,
382 uint64_t val, int size)
383 {
384 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n",
385 addr, val, size);
386
387 if (size != 4) {
388 DPRINTF_CACHE_CONTROL("32bits only\n");
389 return;
390 }
391
392 switch (addr) {
393 case 0x00: /* Cache control */
394
395 /* These values must always be read as zeros */
396 val &= ~CACHE_CTRL_FD;
397 val &= ~CACHE_CTRL_FI;
398 val &= ~CACHE_CTRL_IB;
399 val &= ~CACHE_CTRL_IP;
400 val &= ~CACHE_CTRL_DP;
401
402 env->cache_control = val;
403 break;
404 case 0x04: /* Instruction cache configuration */
405 case 0x08: /* Data cache configuration */
406 /* Read Only */
407 break;
408 default:
409 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr);
410 break;
411 };
412 }
413
414 static uint64_t leon3_cache_control_ld(CPUSPARCState *env, target_ulong addr,
415 int size)
416 {
417 uint64_t ret = 0;
418
419 if (size != 4) {
420 DPRINTF_CACHE_CONTROL("32bits only\n");
421 return 0;
422 }
423
424 switch (addr) {
425 case 0x00: /* Cache control */
426 ret = env->cache_control;
427 break;
428
429 /* Configuration registers are read and only always keep those
430 predefined values */
431
432 case 0x04: /* Instruction cache configuration */
433 ret = 0x10220000;
434 break;
435 case 0x08: /* Data cache configuration */
436 ret = 0x18220000;
437 break;
438 default:
439 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr);
440 break;
441 };
442 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n",
443 addr, ret, size);
444 return ret;
445 }
446
447 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
448 int sign)
449 {
450 uint64_t ret = 0;
451 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
452 uint32_t last_addr = addr;
453 #endif
454
455 helper_check_align(env, addr, size - 1);
456 switch (asi) {
457 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
458 switch (addr) {
459 case 0x00: /* Leon3 Cache Control */
460 case 0x08: /* Leon3 Instruction Cache config */
461 case 0x0C: /* Leon3 Date Cache config */
462 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
463 ret = leon3_cache_control_ld(env, addr, size);
464 }
465 break;
466 case 0x01c00a00: /* MXCC control register */
467 if (size == 8) {
468 ret = env->mxccregs[3];
469 } else {
470 qemu_log_mask(LOG_UNIMP,
471 "%08x: unimplemented access size: %d\n", addr,
472 size);
473 }
474 break;
475 case 0x01c00a04: /* MXCC control register */
476 if (size == 4) {
477 ret = env->mxccregs[3];
478 } else {
479 qemu_log_mask(LOG_UNIMP,
480 "%08x: unimplemented access size: %d\n", addr,
481 size);
482 }
483 break;
484 case 0x01c00c00: /* Module reset register */
485 if (size == 8) {
486 ret = env->mxccregs[5];
487 /* should we do something here? */
488 } else {
489 qemu_log_mask(LOG_UNIMP,
490 "%08x: unimplemented access size: %d\n", addr,
491 size);
492 }
493 break;
494 case 0x01c00f00: /* MBus port address register */
495 if (size == 8) {
496 ret = env->mxccregs[7];
497 } else {
498 qemu_log_mask(LOG_UNIMP,
499 "%08x: unimplemented access size: %d\n", addr,
500 size);
501 }
502 break;
503 default:
504 qemu_log_mask(LOG_UNIMP,
505 "%08x: unimplemented address, size: %d\n", addr,
506 size);
507 break;
508 }
509 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
510 "addr = %08x -> ret = %" PRIx64 ","
511 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
512 #ifdef DEBUG_MXCC
513 dump_mxcc(env);
514 #endif
515 break;
516 case 3: /* MMU probe */
517 {
518 int mmulev;
519
520 mmulev = (addr >> 8) & 15;
521 if (mmulev > 4) {
522 ret = 0;
523 } else {
524 ret = mmu_probe(env, addr, mmulev);
525 }
526 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
527 addr, mmulev, ret);
528 }
529 break;
530 case 4: /* read MMU regs */
531 {
532 int reg = (addr >> 8) & 0x1f;
533
534 ret = env->mmuregs[reg];
535 if (reg == 3) { /* Fault status cleared on read */
536 env->mmuregs[3] = 0;
537 } else if (reg == 0x13) { /* Fault status read */
538 ret = env->mmuregs[3];
539 } else if (reg == 0x14) { /* Fault address read */
540 ret = env->mmuregs[4];
541 }
542 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
543 }
544 break;
545 case 5: /* Turbosparc ITLB Diagnostic */
546 case 6: /* Turbosparc DTLB Diagnostic */
547 case 7: /* Turbosparc IOTLB Diagnostic */
548 break;
549 case 9: /* Supervisor code access */
550 switch (size) {
551 case 1:
552 ret = cpu_ldub_code(env, addr);
553 break;
554 case 2:
555 ret = cpu_lduw_code(env, addr);
556 break;
557 default:
558 case 4:
559 ret = cpu_ldl_code(env, addr);
560 break;
561 case 8:
562 ret = cpu_ldq_code(env, addr);
563 break;
564 }
565 break;
566 case 0xa: /* User data access */
567 switch (size) {
568 case 1:
569 ret = cpu_ldub_user(env, addr);
570 break;
571 case 2:
572 ret = cpu_lduw_user(env, addr);
573 break;
574 default:
575 case 4:
576 ret = cpu_ldl_user(env, addr);
577 break;
578 case 8:
579 ret = cpu_ldq_user(env, addr);
580 break;
581 }
582 break;
583 case 0xb: /* Supervisor data access */
584 switch (size) {
585 case 1:
586 ret = cpu_ldub_kernel(env, addr);
587 break;
588 case 2:
589 ret = cpu_lduw_kernel(env, addr);
590 break;
591 default:
592 case 4:
593 ret = cpu_ldl_kernel(env, addr);
594 break;
595 case 8:
596 ret = cpu_ldq_kernel(env, addr);
597 break;
598 }
599 break;
600 case 0xc: /* I-cache tag */
601 case 0xd: /* I-cache data */
602 case 0xe: /* D-cache tag */
603 case 0xf: /* D-cache data */
604 break;
605 case 0x20: /* MMU passthrough */
606 switch (size) {
607 case 1:
608 ret = ldub_phys(addr);
609 break;
610 case 2:
611 ret = lduw_phys(addr);
612 break;
613 default:
614 case 4:
615 ret = ldl_phys(addr);
616 break;
617 case 8:
618 ret = ldq_phys(addr);
619 break;
620 }
621 break;
622 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
623 switch (size) {
624 case 1:
625 ret = ldub_phys((hwaddr)addr
626 | ((hwaddr)(asi & 0xf) << 32));
627 break;
628 case 2:
629 ret = lduw_phys((hwaddr)addr
630 | ((hwaddr)(asi & 0xf) << 32));
631 break;
632 default:
633 case 4:
634 ret = ldl_phys((hwaddr)addr
635 | ((hwaddr)(asi & 0xf) << 32));
636 break;
637 case 8:
638 ret = ldq_phys((hwaddr)addr
639 | ((hwaddr)(asi & 0xf) << 32));
640 break;
641 }
642 break;
643 case 0x30: /* Turbosparc secondary cache diagnostic */
644 case 0x31: /* Turbosparc RAM snoop */
645 case 0x32: /* Turbosparc page table descriptor diagnostic */
646 case 0x39: /* data cache diagnostic register */
647 ret = 0;
648 break;
649 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
650 {
651 int reg = (addr >> 8) & 3;
652
653 switch (reg) {
654 case 0: /* Breakpoint Value (Addr) */
655 ret = env->mmubpregs[reg];
656 break;
657 case 1: /* Breakpoint Mask */
658 ret = env->mmubpregs[reg];
659 break;
660 case 2: /* Breakpoint Control */
661 ret = env->mmubpregs[reg];
662 break;
663 case 3: /* Breakpoint Status */
664 ret = env->mmubpregs[reg];
665 env->mmubpregs[reg] = 0ULL;
666 break;
667 }
668 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg,
669 ret);
670 }
671 break;
672 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
673 ret = env->mmubpctrv;
674 break;
675 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
676 ret = env->mmubpctrc;
677 break;
678 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
679 ret = env->mmubpctrs;
680 break;
681 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
682 ret = env->mmubpaction;
683 break;
684 case 8: /* User code access, XXX */
685 default:
686 cpu_unassigned_access(env, addr, 0, 0, asi, size);
687 ret = 0;
688 break;
689 }
690 if (sign) {
691 switch (size) {
692 case 1:
693 ret = (int8_t) ret;
694 break;
695 case 2:
696 ret = (int16_t) ret;
697 break;
698 case 4:
699 ret = (int32_t) ret;
700 break;
701 default:
702 break;
703 }
704 }
705 #ifdef DEBUG_ASI
706 dump_asi("read ", last_addr, asi, size, ret);
707 #endif
708 return ret;
709 }
710
711 void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
712 int size)
713 {
714 helper_check_align(env, addr, size - 1);
715 switch (asi) {
716 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
717 switch (addr) {
718 case 0x00: /* Leon3 Cache Control */
719 case 0x08: /* Leon3 Instruction Cache config */
720 case 0x0C: /* Leon3 Date Cache config */
721 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
722 leon3_cache_control_st(env, addr, val, size);
723 }
724 break;
725
726 case 0x01c00000: /* MXCC stream data register 0 */
727 if (size == 8) {
728 env->mxccdata[0] = val;
729 } else {
730 qemu_log_mask(LOG_UNIMP,
731 "%08x: unimplemented access size: %d\n", addr,
732 size);
733 }
734 break;
735 case 0x01c00008: /* MXCC stream data register 1 */
736 if (size == 8) {
737 env->mxccdata[1] = val;
738 } else {
739 qemu_log_mask(LOG_UNIMP,
740 "%08x: unimplemented access size: %d\n", addr,
741 size);
742 }
743 break;
744 case 0x01c00010: /* MXCC stream data register 2 */
745 if (size == 8) {
746 env->mxccdata[2] = val;
747 } else {
748 qemu_log_mask(LOG_UNIMP,
749 "%08x: unimplemented access size: %d\n", addr,
750 size);
751 }
752 break;
753 case 0x01c00018: /* MXCC stream data register 3 */
754 if (size == 8) {
755 env->mxccdata[3] = val;
756 } else {
757 qemu_log_mask(LOG_UNIMP,
758 "%08x: unimplemented access size: %d\n", addr,
759 size);
760 }
761 break;
762 case 0x01c00100: /* MXCC stream source */
763 if (size == 8) {
764 env->mxccregs[0] = val;
765 } else {
766 qemu_log_mask(LOG_UNIMP,
767 "%08x: unimplemented access size: %d\n", addr,
768 size);
769 }
770 env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
771 0);
772 env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
773 8);
774 env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
775 16);
776 env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
777 24);
778 break;
779 case 0x01c00200: /* MXCC stream destination */
780 if (size == 8) {
781 env->mxccregs[1] = val;
782 } else {
783 qemu_log_mask(LOG_UNIMP,
784 "%08x: unimplemented access size: %d\n", addr,
785 size);
786 }
787 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0,
788 env->mxccdata[0]);
789 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8,
790 env->mxccdata[1]);
791 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16,
792 env->mxccdata[2]);
793 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24,
794 env->mxccdata[3]);
795 break;
796 case 0x01c00a00: /* MXCC control register */
797 if (size == 8) {
798 env->mxccregs[3] = val;
799 } else {
800 qemu_log_mask(LOG_UNIMP,
801 "%08x: unimplemented access size: %d\n", addr,
802 size);
803 }
804 break;
805 case 0x01c00a04: /* MXCC control register */
806 if (size == 4) {
807 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)
808 | val;
809 } else {
810 qemu_log_mask(LOG_UNIMP,
811 "%08x: unimplemented access size: %d\n", addr,
812 size);
813 }
814 break;
815 case 0x01c00e00: /* MXCC error register */
816 /* writing a 1 bit clears the error */
817 if (size == 8) {
818 env->mxccregs[6] &= ~val;
819 } else {
820 qemu_log_mask(LOG_UNIMP,
821 "%08x: unimplemented access size: %d\n", addr,
822 size);
823 }
824 break;
825 case 0x01c00f00: /* MBus port address register */
826 if (size == 8) {
827 env->mxccregs[7] = val;
828 } else {
829 qemu_log_mask(LOG_UNIMP,
830 "%08x: unimplemented access size: %d\n", addr,
831 size);
832 }
833 break;
834 default:
835 qemu_log_mask(LOG_UNIMP,
836 "%08x: unimplemented address, size: %d\n", addr,
837 size);
838 break;
839 }
840 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",
841 asi, size, addr, val);
842 #ifdef DEBUG_MXCC
843 dump_mxcc(env);
844 #endif
845 break;
846 case 3: /* MMU flush */
847 {
848 int mmulev;
849
850 mmulev = (addr >> 8) & 15;
851 DPRINTF_MMU("mmu flush level %d\n", mmulev);
852 switch (mmulev) {
853 case 0: /* flush page */
854 tlb_flush_page(env, addr & 0xfffff000);
855 break;
856 case 1: /* flush segment (256k) */
857 case 2: /* flush region (16M) */
858 case 3: /* flush context (4G) */
859 case 4: /* flush entire */
860 tlb_flush(env, 1);
861 break;
862 default:
863 break;
864 }
865 #ifdef DEBUG_MMU
866 dump_mmu(stdout, fprintf, env);
867 #endif
868 }
869 break;
870 case 4: /* write MMU regs */
871 {
872 int reg = (addr >> 8) & 0x1f;
873 uint32_t oldreg;
874
875 oldreg = env->mmuregs[reg];
876 switch (reg) {
877 case 0: /* Control Register */
878 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
879 (val & 0x00ffffff);
880 /* Mappings generated during no-fault mode or MMU
881 disabled mode are invalid in normal mode */
882 if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
883 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm))) {
884 tlb_flush(env, 1);
885 }
886 break;
887 case 1: /* Context Table Pointer Register */
888 env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
889 break;
890 case 2: /* Context Register */
891 env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
892 if (oldreg != env->mmuregs[reg]) {
893 /* we flush when the MMU context changes because
894 QEMU has no MMU context support */
895 tlb_flush(env, 1);
896 }
897 break;
898 case 3: /* Synchronous Fault Status Register with Clear */
899 case 4: /* Synchronous Fault Address Register */
900 break;
901 case 0x10: /* TLB Replacement Control Register */
902 env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
903 break;
904 case 0x13: /* Synchronous Fault Status Register with Read
905 and Clear */
906 env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
907 break;
908 case 0x14: /* Synchronous Fault Address Register */
909 env->mmuregs[4] = val;
910 break;
911 default:
912 env->mmuregs[reg] = val;
913 break;
914 }
915 if (oldreg != env->mmuregs[reg]) {
916 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
917 reg, oldreg, env->mmuregs[reg]);
918 }
919 #ifdef DEBUG_MMU
920 dump_mmu(stdout, fprintf, env);
921 #endif
922 }
923 break;
924 case 5: /* Turbosparc ITLB Diagnostic */
925 case 6: /* Turbosparc DTLB Diagnostic */
926 case 7: /* Turbosparc IOTLB Diagnostic */
927 break;
928 case 0xa: /* User data access */
929 switch (size) {
930 case 1:
931 cpu_stb_user(env, addr, val);
932 break;
933 case 2:
934 cpu_stw_user(env, addr, val);
935 break;
936 default:
937 case 4:
938 cpu_stl_user(env, addr, val);
939 break;
940 case 8:
941 cpu_stq_user(env, addr, val);
942 break;
943 }
944 break;
945 case 0xb: /* Supervisor data access */
946 switch (size) {
947 case 1:
948 cpu_stb_kernel(env, addr, val);
949 break;
950 case 2:
951 cpu_stw_kernel(env, addr, val);
952 break;
953 default:
954 case 4:
955 cpu_stl_kernel(env, addr, val);
956 break;
957 case 8:
958 cpu_stq_kernel(env, addr, val);
959 break;
960 }
961 break;
962 case 0xc: /* I-cache tag */
963 case 0xd: /* I-cache data */
964 case 0xe: /* D-cache tag */
965 case 0xf: /* D-cache data */
966 case 0x10: /* I/D-cache flush page */
967 case 0x11: /* I/D-cache flush segment */
968 case 0x12: /* I/D-cache flush region */
969 case 0x13: /* I/D-cache flush context */
970 case 0x14: /* I/D-cache flush user */
971 break;
972 case 0x17: /* Block copy, sta access */
973 {
974 /* val = src
975 addr = dst
976 copy 32 bytes */
977 unsigned int i;
978 uint32_t src = val & ~3, dst = addr & ~3, temp;
979
980 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
981 temp = cpu_ldl_kernel(env, src);
982 cpu_stl_kernel(env, dst, temp);
983 }
984 }
985 break;
986 case 0x1f: /* Block fill, stda access */
987 {
988 /* addr = dst
989 fill 32 bytes with val */
990 unsigned int i;
991 uint32_t dst = addr & 7;
992
993 for (i = 0; i < 32; i += 8, dst += 8) {
994 cpu_stq_kernel(env, dst, val);
995 }
996 }
997 break;
998 case 0x20: /* MMU passthrough */
999 {
1000 switch (size) {
1001 case 1:
1002 stb_phys(addr, val);
1003 break;
1004 case 2:
1005 stw_phys(addr, val);
1006 break;
1007 case 4:
1008 default:
1009 stl_phys(addr, val);
1010 break;
1011 case 8:
1012 stq_phys(addr, val);
1013 break;
1014 }
1015 }
1016 break;
1017 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1018 {
1019 switch (size) {
1020 case 1:
1021 stb_phys((hwaddr)addr
1022 | ((hwaddr)(asi & 0xf) << 32), val);
1023 break;
1024 case 2:
1025 stw_phys((hwaddr)addr
1026 | ((hwaddr)(asi & 0xf) << 32), val);
1027 break;
1028 case 4:
1029 default:
1030 stl_phys((hwaddr)addr
1031 | ((hwaddr)(asi & 0xf) << 32), val);
1032 break;
1033 case 8:
1034 stq_phys((hwaddr)addr
1035 | ((hwaddr)(asi & 0xf) << 32), val);
1036 break;
1037 }
1038 }
1039 break;
1040 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */
1041 case 0x31: /* store buffer data, Ross RT620 I-cache flush or
1042 Turbosparc snoop RAM */
1043 case 0x32: /* store buffer control or Turbosparc page table
1044 descriptor diagnostic */
1045 case 0x36: /* I-cache flash clear */
1046 case 0x37: /* D-cache flash clear */
1047 break;
1048 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1049 {
1050 int reg = (addr >> 8) & 3;
1051
1052 switch (reg) {
1053 case 0: /* Breakpoint Value (Addr) */
1054 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1055 break;
1056 case 1: /* Breakpoint Mask */
1057 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1058 break;
1059 case 2: /* Breakpoint Control */
1060 env->mmubpregs[reg] = (val & 0x7fULL);
1061 break;
1062 case 3: /* Breakpoint Status */
1063 env->mmubpregs[reg] = (val & 0xfULL);
1064 break;
1065 }
1066 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg,
1067 env->mmuregs[reg]);
1068 }
1069 break;
1070 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
1071 env->mmubpctrv = val & 0xffffffff;
1072 break;
1073 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
1074 env->mmubpctrc = val & 0x3;
1075 break;
1076 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
1077 env->mmubpctrs = val & 0x3;
1078 break;
1079 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
1080 env->mmubpaction = val & 0x1fff;
1081 break;
1082 case 8: /* User code access, XXX */
1083 case 9: /* Supervisor code access, XXX */
1084 default:
1085 cpu_unassigned_access(env, addr, 1, 0, asi, size);
1086 break;
1087 }
1088 #ifdef DEBUG_ASI
1089 dump_asi("write", addr, asi, size, val);
1090 #endif
1091 }
1092
1093 #endif /* CONFIG_USER_ONLY */
1094 #else /* TARGET_SPARC64 */
1095
1096 #ifdef CONFIG_USER_ONLY
1097 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
1098 int sign)
1099 {
1100 uint64_t ret = 0;
1101 #if defined(DEBUG_ASI)
1102 target_ulong last_addr = addr;
1103 #endif
1104
1105 if (asi < 0x80) {
1106 helper_raise_exception(env, TT_PRIV_ACT);
1107 }
1108
1109 helper_check_align(env, addr, size - 1);
1110 addr = asi_address_mask(env, asi, addr);
1111
1112 switch (asi) {
1113 case 0x82: /* Primary no-fault */
1114 case 0x8a: /* Primary no-fault LE */
1115 if (page_check_range(addr, size, PAGE_READ) == -1) {
1116 #ifdef DEBUG_ASI
1117 dump_asi("read ", last_addr, asi, size, ret);
1118 #endif
1119 return 0;
1120 }
1121 /* Fall through */
1122 case 0x80: /* Primary */
1123 case 0x88: /* Primary LE */
1124 {
1125 switch (size) {
1126 case 1:
1127 ret = ldub_raw(addr);
1128 break;
1129 case 2:
1130 ret = lduw_raw(addr);
1131 break;
1132 case 4:
1133 ret = ldl_raw(addr);
1134 break;
1135 default:
1136 case 8:
1137 ret = ldq_raw(addr);
1138 break;
1139 }
1140 }
1141 break;
1142 case 0x83: /* Secondary no-fault */
1143 case 0x8b: /* Secondary no-fault LE */
1144 if (page_check_range(addr, size, PAGE_READ) == -1) {
1145 #ifdef DEBUG_ASI
1146 dump_asi("read ", last_addr, asi, size, ret);
1147 #endif
1148 return 0;
1149 }
1150 /* Fall through */
1151 case 0x81: /* Secondary */
1152 case 0x89: /* Secondary LE */
1153 /* XXX */
1154 break;
1155 default:
1156 break;
1157 }
1158
1159 /* Convert from little endian */
1160 switch (asi) {
1161 case 0x88: /* Primary LE */
1162 case 0x89: /* Secondary LE */
1163 case 0x8a: /* Primary no-fault LE */
1164 case 0x8b: /* Secondary no-fault LE */
1165 switch (size) {
1166 case 2:
1167 ret = bswap16(ret);
1168 break;
1169 case 4:
1170 ret = bswap32(ret);
1171 break;
1172 case 8:
1173 ret = bswap64(ret);
1174 break;
1175 default:
1176 break;
1177 }
1178 default:
1179 break;
1180 }
1181
1182 /* Convert to signed number */
1183 if (sign) {
1184 switch (size) {
1185 case 1:
1186 ret = (int8_t) ret;
1187 break;
1188 case 2:
1189 ret = (int16_t) ret;
1190 break;
1191 case 4:
1192 ret = (int32_t) ret;
1193 break;
1194 default:
1195 break;
1196 }
1197 }
1198 #ifdef DEBUG_ASI
1199 dump_asi("read ", last_addr, asi, size, ret);
1200 #endif
1201 return ret;
1202 }
1203
1204 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1205 int asi, int size)
1206 {
1207 #ifdef DEBUG_ASI
1208 dump_asi("write", addr, asi, size, val);
1209 #endif
1210 if (asi < 0x80) {
1211 helper_raise_exception(env, TT_PRIV_ACT);
1212 }
1213
1214 helper_check_align(env, addr, size - 1);
1215 addr = asi_address_mask(env, asi, addr);
1216
1217 /* Convert to little endian */
1218 switch (asi) {
1219 case 0x88: /* Primary LE */
1220 case 0x89: /* Secondary LE */
1221 switch (size) {
1222 case 2:
1223 val = bswap16(val);
1224 break;
1225 case 4:
1226 val = bswap32(val);
1227 break;
1228 case 8:
1229 val = bswap64(val);
1230 break;
1231 default:
1232 break;
1233 }
1234 default:
1235 break;
1236 }
1237
1238 switch (asi) {
1239 case 0x80: /* Primary */
1240 case 0x88: /* Primary LE */
1241 {
1242 switch (size) {
1243 case 1:
1244 stb_raw(addr, val);
1245 break;
1246 case 2:
1247 stw_raw(addr, val);
1248 break;
1249 case 4:
1250 stl_raw(addr, val);
1251 break;
1252 case 8:
1253 default:
1254 stq_raw(addr, val);
1255 break;
1256 }
1257 }
1258 break;
1259 case 0x81: /* Secondary */
1260 case 0x89: /* Secondary LE */
1261 /* XXX */
1262 return;
1263
1264 case 0x82: /* Primary no-fault, RO */
1265 case 0x83: /* Secondary no-fault, RO */
1266 case 0x8a: /* Primary no-fault LE, RO */
1267 case 0x8b: /* Secondary no-fault LE, RO */
1268 default:
1269 helper_raise_exception(env, TT_DATA_ACCESS);
1270 return;
1271 }
1272 }
1273
1274 #else /* CONFIG_USER_ONLY */
1275
1276 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
1277 int sign)
1278 {
1279 uint64_t ret = 0;
1280 #if defined(DEBUG_ASI)
1281 target_ulong last_addr = addr;
1282 #endif
1283
1284 asi &= 0xff;
1285
1286 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1287 || (cpu_has_hypervisor(env)
1288 && asi >= 0x30 && asi < 0x80
1289 && !(env->hpstate & HS_PRIV))) {
1290 helper_raise_exception(env, TT_PRIV_ACT);
1291 }
1292
1293 helper_check_align(env, addr, size - 1);
1294 addr = asi_address_mask(env, asi, addr);
1295
1296 /* process nonfaulting loads first */
1297 if ((asi & 0xf6) == 0x82) {
1298 int mmu_idx;
1299
1300 /* secondary space access has lowest asi bit equal to 1 */
1301 if (env->pstate & PS_PRIV) {
1302 mmu_idx = (asi & 1) ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX;
1303 } else {
1304 mmu_idx = (asi & 1) ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX;
1305 }
1306
1307 if (cpu_get_phys_page_nofault(env, addr, mmu_idx) == -1ULL) {
1308 #ifdef DEBUG_ASI
1309 dump_asi("read ", last_addr, asi, size, ret);
1310 #endif
1311 /* env->exception_index is set in get_physical_address_data(). */
1312 helper_raise_exception(env, env->exception_index);
1313 }
1314
1315 /* convert nonfaulting load ASIs to normal load ASIs */
1316 asi &= ~0x02;
1317 }
1318
1319 switch (asi) {
1320 case 0x10: /* As if user primary */
1321 case 0x11: /* As if user secondary */
1322 case 0x18: /* As if user primary LE */
1323 case 0x19: /* As if user secondary LE */
1324 case 0x80: /* Primary */
1325 case 0x81: /* Secondary */
1326 case 0x88: /* Primary LE */
1327 case 0x89: /* Secondary LE */
1328 case 0xe2: /* UA2007 Primary block init */
1329 case 0xe3: /* UA2007 Secondary block init */
1330 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1331 if (cpu_hypervisor_mode(env)) {
1332 switch (size) {
1333 case 1:
1334 ret = cpu_ldub_hypv(env, addr);
1335 break;
1336 case 2:
1337 ret = cpu_lduw_hypv(env, addr);
1338 break;
1339 case 4:
1340 ret = cpu_ldl_hypv(env, addr);
1341 break;
1342 default:
1343 case 8:
1344 ret = cpu_ldq_hypv(env, addr);
1345 break;
1346 }
1347 } else {
1348 /* secondary space access has lowest asi bit equal to 1 */
1349 if (asi & 1) {
1350 switch (size) {
1351 case 1:
1352 ret = cpu_ldub_kernel_secondary(env, addr);
1353 break;
1354 case 2:
1355 ret = cpu_lduw_kernel_secondary(env, addr);
1356 break;
1357 case 4:
1358 ret = cpu_ldl_kernel_secondary(env, addr);
1359 break;
1360 default:
1361 case 8:
1362 ret = cpu_ldq_kernel_secondary(env, addr);
1363 break;
1364 }
1365 } else {
1366 switch (size) {
1367 case 1:
1368 ret = cpu_ldub_kernel(env, addr);
1369 break;
1370 case 2:
1371 ret = cpu_lduw_kernel(env, addr);
1372 break;
1373 case 4:
1374 ret = cpu_ldl_kernel(env, addr);
1375 break;
1376 default:
1377 case 8:
1378 ret = cpu_ldq_kernel(env, addr);
1379 break;
1380 }
1381 }
1382 }
1383 } else {
1384 /* secondary space access has lowest asi bit equal to 1 */
1385 if (asi & 1) {
1386 switch (size) {
1387 case 1:
1388 ret = cpu_ldub_user_secondary(env, addr);
1389 break;
1390 case 2:
1391 ret = cpu_lduw_user_secondary(env, addr);
1392 break;
1393 case 4:
1394 ret = cpu_ldl_user_secondary(env, addr);
1395 break;
1396 default:
1397 case 8:
1398 ret = cpu_ldq_user_secondary(env, addr);
1399 break;
1400 }
1401 } else {
1402 switch (size) {
1403 case 1:
1404 ret = cpu_ldub_user(env, addr);
1405 break;
1406 case 2:
1407 ret = cpu_lduw_user(env, addr);
1408 break;
1409 case 4:
1410 ret = cpu_ldl_user(env, addr);
1411 break;
1412 default:
1413 case 8:
1414 ret = cpu_ldq_user(env, addr);
1415 break;
1416 }
1417 }
1418 }
1419 break;
1420 case 0x14: /* Bypass */
1421 case 0x15: /* Bypass, non-cacheable */
1422 case 0x1c: /* Bypass LE */
1423 case 0x1d: /* Bypass, non-cacheable LE */
1424 {
1425 switch (size) {
1426 case 1:
1427 ret = ldub_phys(addr);
1428 break;
1429 case 2:
1430 ret = lduw_phys(addr);
1431 break;
1432 case 4:
1433 ret = ldl_phys(addr);
1434 break;
1435 default:
1436 case 8:
1437 ret = ldq_phys(addr);
1438 break;
1439 }
1440 break;
1441 }
1442 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1443 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1444 Only ldda allowed */
1445 helper_raise_exception(env, TT_ILL_INSN);
1446 return 0;
1447 case 0x04: /* Nucleus */
1448 case 0x0c: /* Nucleus Little Endian (LE) */
1449 {
1450 switch (size) {
1451 case 1:
1452 ret = cpu_ldub_nucleus(env, addr);
1453 break;
1454 case 2:
1455 ret = cpu_lduw_nucleus(env, addr);
1456 break;
1457 case 4:
1458 ret = cpu_ldl_nucleus(env, addr);
1459 break;
1460 default:
1461 case 8:
1462 ret = cpu_ldq_nucleus(env, addr);
1463 break;
1464 }
1465 break;
1466 }
1467 case 0x4a: /* UPA config */
1468 /* XXX */
1469 break;
1470 case 0x45: /* LSU */
1471 ret = env->lsu;
1472 break;
1473 case 0x50: /* I-MMU regs */
1474 {
1475 int reg = (addr >> 3) & 0xf;
1476
1477 if (reg == 0) {
1478 /* I-TSB Tag Target register */
1479 ret = ultrasparc_tag_target(env->immu.tag_access);
1480 } else {
1481 ret = env->immuregs[reg];
1482 }
1483
1484 break;
1485 }
1486 case 0x51: /* I-MMU 8k TSB pointer */
1487 {
1488 /* env->immuregs[5] holds I-MMU TSB register value
1489 env->immuregs[6] holds I-MMU Tag Access register value */
1490 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
1491 8*1024);
1492 break;
1493 }
1494 case 0x52: /* I-MMU 64k TSB pointer */
1495 {
1496 /* env->immuregs[5] holds I-MMU TSB register value
1497 env->immuregs[6] holds I-MMU Tag Access register value */
1498 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
1499 64*1024);
1500 break;
1501 }
1502 case 0x55: /* I-MMU data access */
1503 {
1504 int reg = (addr >> 3) & 0x3f;
1505
1506 ret = env->itlb[reg].tte;
1507 break;
1508 }
1509 case 0x56: /* I-MMU tag read */
1510 {
1511 int reg = (addr >> 3) & 0x3f;
1512
1513 ret = env->itlb[reg].tag;
1514 break;
1515 }
1516 case 0x58: /* D-MMU regs */
1517 {
1518 int reg = (addr >> 3) & 0xf;
1519
1520 if (reg == 0) {
1521 /* D-TSB Tag Target register */
1522 ret = ultrasparc_tag_target(env->dmmu.tag_access);
1523 } else {
1524 ret = env->dmmuregs[reg];
1525 }
1526 break;
1527 }
1528 case 0x59: /* D-MMU 8k TSB pointer */
1529 {
1530 /* env->dmmuregs[5] holds D-MMU TSB register value
1531 env->dmmuregs[6] holds D-MMU Tag Access register value */
1532 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
1533 8*1024);
1534 break;
1535 }
1536 case 0x5a: /* D-MMU 64k TSB pointer */
1537 {
1538 /* env->dmmuregs[5] holds D-MMU TSB register value
1539 env->dmmuregs[6] holds D-MMU Tag Access register value */
1540 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
1541 64*1024);
1542 break;
1543 }
1544 case 0x5d: /* D-MMU data access */
1545 {
1546 int reg = (addr >> 3) & 0x3f;
1547
1548 ret = env->dtlb[reg].tte;
1549 break;
1550 }
1551 case 0x5e: /* D-MMU tag read */
1552 {
1553 int reg = (addr >> 3) & 0x3f;
1554
1555 ret = env->dtlb[reg].tag;
1556 break;
1557 }
1558 case 0x48: /* Interrupt dispatch, RO */
1559 break;
1560 case 0x49: /* Interrupt data receive */
1561 ret = env->ivec_status;
1562 break;
1563 case 0x7f: /* Incoming interrupt vector, RO */
1564 {
1565 int reg = (addr >> 4) & 0x3;
1566 if (reg < 3) {
1567 ret = env->ivec_data[reg];
1568 }
1569 break;
1570 }
1571 case 0x46: /* D-cache data */
1572 case 0x47: /* D-cache tag access */
1573 case 0x4b: /* E-cache error enable */
1574 case 0x4c: /* E-cache asynchronous fault status */
1575 case 0x4d: /* E-cache asynchronous fault address */
1576 case 0x4e: /* E-cache tag data */
1577 case 0x66: /* I-cache instruction access */
1578 case 0x67: /* I-cache tag access */
1579 case 0x6e: /* I-cache predecode */
1580 case 0x6f: /* I-cache LRU etc. */
1581 case 0x76: /* E-cache tag */
1582 case 0x7e: /* E-cache tag */
1583 break;
1584 case 0x5b: /* D-MMU data pointer */
1585 case 0x54: /* I-MMU data in, WO */
1586 case 0x57: /* I-MMU demap, WO */
1587 case 0x5c: /* D-MMU data in, WO */
1588 case 0x5f: /* D-MMU demap, WO */
1589 case 0x77: /* Interrupt vector, WO */
1590 default:
1591 cpu_unassigned_access(env, addr, 0, 0, 1, size);
1592 ret = 0;
1593 break;
1594 }
1595
1596 /* Convert from little endian */
1597 switch (asi) {
1598 case 0x0c: /* Nucleus Little Endian (LE) */
1599 case 0x18: /* As if user primary LE */
1600 case 0x19: /* As if user secondary LE */
1601 case 0x1c: /* Bypass LE */
1602 case 0x1d: /* Bypass, non-cacheable LE */
1603 case 0x88: /* Primary LE */
1604 case 0x89: /* Secondary LE */
1605 switch(size) {
1606 case 2:
1607 ret = bswap16(ret);
1608 break;
1609 case 4:
1610 ret = bswap32(ret);
1611 break;
1612 case 8:
1613 ret = bswap64(ret);
1614 break;
1615 default:
1616 break;
1617 }
1618 default:
1619 break;
1620 }
1621
1622 /* Convert to signed number */
1623 if (sign) {
1624 switch (size) {
1625 case 1:
1626 ret = (int8_t) ret;
1627 break;
1628 case 2:
1629 ret = (int16_t) ret;
1630 break;
1631 case 4:
1632 ret = (int32_t) ret;
1633 break;
1634 default:
1635 break;
1636 }
1637 }
1638 #ifdef DEBUG_ASI
1639 dump_asi("read ", last_addr, asi, size, ret);
1640 #endif
1641 return ret;
1642 }
1643
1644 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1645 int asi, int size)
1646 {
1647 #ifdef DEBUG_ASI
1648 dump_asi("write", addr, asi, size, val);
1649 #endif
1650
1651 asi &= 0xff;
1652
1653 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1654 || (cpu_has_hypervisor(env)
1655 && asi >= 0x30 && asi < 0x80
1656 && !(env->hpstate & HS_PRIV))) {
1657 helper_raise_exception(env, TT_PRIV_ACT);
1658 }
1659
1660 helper_check_align(env, addr, size - 1);
1661 addr = asi_address_mask(env, asi, addr);
1662
1663 /* Convert to little endian */
1664 switch (asi) {
1665 case 0x0c: /* Nucleus Little Endian (LE) */
1666 case 0x18: /* As if user primary LE */
1667 case 0x19: /* As if user secondary LE */
1668 case 0x1c: /* Bypass LE */
1669 case 0x1d: /* Bypass, non-cacheable LE */
1670 case 0x88: /* Primary LE */
1671 case 0x89: /* Secondary LE */
1672 switch (size) {
1673 case 2:
1674 val = bswap16(val);
1675 break;
1676 case 4:
1677 val = bswap32(val);
1678 break;
1679 case 8:
1680 val = bswap64(val);
1681 break;
1682 default:
1683 break;
1684 }
1685 default:
1686 break;
1687 }
1688
1689 switch (asi) {
1690 case 0x10: /* As if user primary */
1691 case 0x11: /* As if user secondary */
1692 case 0x18: /* As if user primary LE */
1693 case 0x19: /* As if user secondary LE */
1694 case 0x80: /* Primary */
1695 case 0x81: /* Secondary */
1696 case 0x88: /* Primary LE */
1697 case 0x89: /* Secondary LE */
1698 case 0xe2: /* UA2007 Primary block init */
1699 case 0xe3: /* UA2007 Secondary block init */
1700 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1701 if (cpu_hypervisor_mode(env)) {
1702 switch (size) {
1703 case 1:
1704 cpu_stb_hypv(env, addr, val);
1705 break;
1706 case 2:
1707 cpu_stw_hypv(env, addr, val);
1708 break;
1709 case 4:
1710 cpu_stl_hypv(env, addr, val);
1711 break;
1712 case 8:
1713 default:
1714 cpu_stq_hypv(env, addr, val);
1715 break;
1716 }
1717 } else {
1718 /* secondary space access has lowest asi bit equal to 1 */
1719 if (asi & 1) {
1720 switch (size) {
1721 case 1:
1722 cpu_stb_kernel_secondary(env, addr, val);
1723 break;
1724 case 2:
1725 cpu_stw_kernel_secondary(env, addr, val);
1726 break;
1727 case 4:
1728 cpu_stl_kernel_secondary(env, addr, val);
1729 break;
1730 case 8:
1731 default:
1732 cpu_stq_kernel_secondary(env, addr, val);
1733 break;
1734 }
1735 } else {
1736 switch (size) {
1737 case 1:
1738 cpu_stb_kernel(env, addr, val);
1739 break;
1740 case 2:
1741 cpu_stw_kernel(env, addr, val);
1742 break;
1743 case 4:
1744 cpu_stl_kernel(env, addr, val);
1745 break;
1746 case 8:
1747 default:
1748 cpu_stq_kernel(env, addr, val);
1749 break;
1750 }
1751 }
1752 }
1753 } else {
1754 /* secondary space access has lowest asi bit equal to 1 */
1755 if (asi & 1) {
1756 switch (size) {
1757 case 1:
1758 cpu_stb_user_secondary(env, addr, val);
1759 break;
1760 case 2:
1761 cpu_stw_user_secondary(env, addr, val);
1762 break;
1763 case 4:
1764 cpu_stl_user_secondary(env, addr, val);
1765 break;
1766 case 8:
1767 default:
1768 cpu_stq_user_secondary(env, addr, val);
1769 break;
1770 }
1771 } else {
1772 switch (size) {
1773 case 1:
1774 cpu_stb_user(env, addr, val);
1775 break;
1776 case 2:
1777 cpu_stw_user(env, addr, val);
1778 break;
1779 case 4:
1780 cpu_stl_user(env, addr, val);
1781 break;
1782 case 8:
1783 default:
1784 cpu_stq_user(env, addr, val);
1785 break;
1786 }
1787 }
1788 }
1789 break;
1790 case 0x14: /* Bypass */
1791 case 0x15: /* Bypass, non-cacheable */
1792 case 0x1c: /* Bypass LE */
1793 case 0x1d: /* Bypass, non-cacheable LE */
1794 {
1795 switch (size) {
1796 case 1:
1797 stb_phys(addr, val);
1798 break;
1799 case 2:
1800 stw_phys(addr, val);
1801 break;
1802 case 4:
1803 stl_phys(addr, val);
1804 break;
1805 case 8:
1806 default:
1807 stq_phys(addr, val);
1808 break;
1809 }
1810 }
1811 return;
1812 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1813 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1814 Only ldda allowed */
1815 helper_raise_exception(env, TT_ILL_INSN);
1816 return;
1817 case 0x04: /* Nucleus */
1818 case 0x0c: /* Nucleus Little Endian (LE) */
1819 {
1820 switch (size) {
1821 case 1:
1822 cpu_stb_nucleus(env, addr, val);
1823 break;
1824 case 2:
1825 cpu_stw_nucleus(env, addr, val);
1826 break;
1827 case 4:
1828 cpu_stl_nucleus(env, addr, val);
1829 break;
1830 default:
1831 case 8:
1832 cpu_stq_nucleus(env, addr, val);
1833 break;
1834 }
1835 break;
1836 }
1837
1838 case 0x4a: /* UPA config */
1839 /* XXX */
1840 return;
1841 case 0x45: /* LSU */
1842 {
1843 uint64_t oldreg;
1844
1845 oldreg = env->lsu;
1846 env->lsu = val & (DMMU_E | IMMU_E);
1847 /* Mappings generated during D/I MMU disabled mode are
1848 invalid in normal mode */
1849 if (oldreg != env->lsu) {
1850 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
1851 oldreg, env->lsu);
1852 #ifdef DEBUG_MMU
1853 dump_mmu(stdout, fprintf, env1);
1854 #endif
1855 tlb_flush(env, 1);
1856 }
1857 return;
1858 }
1859 case 0x50: /* I-MMU regs */
1860 {
1861 int reg = (addr >> 3) & 0xf;
1862 uint64_t oldreg;
1863
1864 oldreg = env->immuregs[reg];
1865 switch (reg) {
1866 case 0: /* RO */
1867 return;
1868 case 1: /* Not in I-MMU */
1869 case 2:
1870 return;
1871 case 3: /* SFSR */
1872 if ((val & 1) == 0) {
1873 val = 0; /* Clear SFSR */
1874 }
1875 env->immu.sfsr = val;
1876 break;
1877 case 4: /* RO */
1878 return;
1879 case 5: /* TSB access */
1880 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016"
1881 PRIx64 "\n", env->immu.tsb, val);
1882 env->immu.tsb = val;
1883 break;
1884 case 6: /* Tag access */
1885 env->immu.tag_access = val;
1886 break;
1887 case 7:
1888 case 8:
1889 return;
1890 default:
1891 break;
1892 }
1893
1894 if (oldreg != env->immuregs[reg]) {
1895 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1896 PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
1897 }
1898 #ifdef DEBUG_MMU
1899 dump_mmu(stdout, fprintf, env);
1900 #endif
1901 return;
1902 }
1903 case 0x54: /* I-MMU data in */
1904 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, val, "immu", env);
1905 return;
1906 case 0x55: /* I-MMU data access */
1907 {
1908 /* TODO: auto demap */
1909
1910 unsigned int i = (addr >> 3) & 0x3f;
1911
1912 replace_tlb_entry(&env->itlb[i], env->immu.tag_access, val, env);
1913
1914 #ifdef DEBUG_MMU
1915 DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
1916 dump_mmu(stdout, fprintf, env);
1917 #endif
1918 return;
1919 }
1920 case 0x57: /* I-MMU demap */
1921 demap_tlb(env->itlb, addr, "immu", env);
1922 return;
1923 case 0x58: /* D-MMU regs */
1924 {
1925 int reg = (addr >> 3) & 0xf;
1926 uint64_t oldreg;
1927
1928 oldreg = env->dmmuregs[reg];
1929 switch (reg) {
1930 case 0: /* RO */
1931 case 4:
1932 return;
1933 case 3: /* SFSR */
1934 if ((val & 1) == 0) {
1935 val = 0; /* Clear SFSR, Fault address */
1936 env->dmmu.sfar = 0;
1937 }
1938 env->dmmu.sfsr = val;
1939 break;
1940 case 1: /* Primary context */
1941 env->dmmu.mmu_primary_context = val;
1942 /* can be optimized to only flush MMU_USER_IDX
1943 and MMU_KERNEL_IDX entries */
1944 tlb_flush(env, 1);
1945 break;
1946 case 2: /* Secondary context */
1947 env->dmmu.mmu_secondary_context = val;
1948 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
1949 and MMU_KERNEL_SECONDARY_IDX entries */
1950 tlb_flush(env, 1);
1951 break;
1952 case 5: /* TSB access */
1953 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
1954 PRIx64 "\n", env->dmmu.tsb, val);
1955 env->dmmu.tsb = val;
1956 break;
1957 case 6: /* Tag access */
1958 env->dmmu.tag_access = val;
1959 break;
1960 case 7: /* Virtual Watchpoint */
1961 case 8: /* Physical Watchpoint */
1962 default:
1963 env->dmmuregs[reg] = val;
1964 break;
1965 }
1966
1967 if (oldreg != env->dmmuregs[reg]) {
1968 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1969 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
1970 }
1971 #ifdef DEBUG_MMU
1972 dump_mmu(stdout, fprintf, env);
1973 #endif
1974 return;
1975 }
1976 case 0x5c: /* D-MMU data in */
1977 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, val, "dmmu", env);
1978 return;
1979 case 0x5d: /* D-MMU data access */
1980 {
1981 unsigned int i = (addr >> 3) & 0x3f;
1982
1983 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, val, env);
1984
1985 #ifdef DEBUG_MMU
1986 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
1987 dump_mmu(stdout, fprintf, env);
1988 #endif
1989 return;
1990 }
1991 case 0x5f: /* D-MMU demap */
1992 demap_tlb(env->dtlb, addr, "dmmu", env);
1993 return;
1994 case 0x49: /* Interrupt data receive */
1995 env->ivec_status = val & 0x20;
1996 return;
1997 case 0x46: /* D-cache data */
1998 case 0x47: /* D-cache tag access */
1999 case 0x4b: /* E-cache error enable */
2000 case 0x4c: /* E-cache asynchronous fault status */
2001 case 0x4d: /* E-cache asynchronous fault address */
2002 case 0x4e: /* E-cache tag data */
2003 case 0x66: /* I-cache instruction access */
2004 case 0x67: /* I-cache tag access */
2005 case 0x6e: /* I-cache predecode */
2006 case 0x6f: /* I-cache LRU etc. */
2007 case 0x76: /* E-cache tag */
2008 case 0x7e: /* E-cache tag */
2009 return;
2010 case 0x51: /* I-MMU 8k TSB pointer, RO */
2011 case 0x52: /* I-MMU 64k TSB pointer, RO */
2012 case 0x56: /* I-MMU tag read, RO */
2013 case 0x59: /* D-MMU 8k TSB pointer, RO */
2014 case 0x5a: /* D-MMU 64k TSB pointer, RO */
2015 case 0x5b: /* D-MMU data pointer, RO */
2016 case 0x5e: /* D-MMU tag read, RO */
2017 case 0x48: /* Interrupt dispatch, RO */
2018 case 0x7f: /* Incoming interrupt vector, RO */
2019 case 0x82: /* Primary no-fault, RO */
2020 case 0x83: /* Secondary no-fault, RO */
2021 case 0x8a: /* Primary no-fault LE, RO */
2022 case 0x8b: /* Secondary no-fault LE, RO */
2023 default:
2024 cpu_unassigned_access(env, addr, 1, 0, 1, size);
2025 return;
2026 }
2027 }
2028 #endif /* CONFIG_USER_ONLY */
2029
2030 void helper_ldda_asi(CPUSPARCState *env, target_ulong addr, int asi, int rd)
2031 {
2032 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2033 || (cpu_has_hypervisor(env)
2034 && asi >= 0x30 && asi < 0x80
2035 && !(env->hpstate & HS_PRIV))) {
2036 helper_raise_exception(env, TT_PRIV_ACT);
2037 }
2038
2039 addr = asi_address_mask(env, asi, addr);
2040
2041 switch (asi) {
2042 #if !defined(CONFIG_USER_ONLY)
2043 case 0x24: /* Nucleus quad LDD 128 bit atomic */
2044 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE */
2045 helper_check_align(env, addr, 0xf);
2046 if (rd == 0) {
2047 env->gregs[1] = cpu_ldq_nucleus(env, addr + 8);
2048 if (asi == 0x2c) {
2049 bswap64s(&env->gregs[1]);
2050 }
2051 } else if (rd < 8) {
2052 env->gregs[rd] = cpu_ldq_nucleus(env, addr);
2053 env->gregs[rd + 1] = cpu_ldq_nucleus(env, addr + 8);
2054 if (asi == 0x2c) {
2055 bswap64s(&env->gregs[rd]);
2056 bswap64s(&env->gregs[rd + 1]);
2057 }
2058 } else {
2059 env->regwptr[rd] = cpu_ldq_nucleus(env, addr);
2060 env->regwptr[rd + 1] = cpu_ldq_nucleus(env, addr + 8);
2061 if (asi == 0x2c) {
2062 bswap64s(&env->regwptr[rd]);
2063 bswap64s(&env->regwptr[rd + 1]);
2064 }
2065 }
2066 break;
2067 #endif
2068 default:
2069 helper_check_align(env, addr, 0x3);
2070 if (rd == 0) {
2071 env->gregs[1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
2072 } else if (rd < 8) {
2073 env->gregs[rd] = helper_ld_asi(env, addr, asi, 4, 0);
2074 env->gregs[rd + 1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
2075 } else {
2076 env->regwptr[rd] = helper_ld_asi(env, addr, asi, 4, 0);
2077 env->regwptr[rd + 1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
2078 }
2079 break;
2080 }
2081 }
2082
2083 void helper_ldf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
2084 int rd)
2085 {
2086 unsigned int i;
2087 target_ulong val;
2088
2089 helper_check_align(env, addr, 3);
2090 addr = asi_address_mask(env, asi, addr);
2091
2092 switch (asi) {
2093 case 0xf0: /* UA2007/JPS1 Block load primary */
2094 case 0xf1: /* UA2007/JPS1 Block load secondary */
2095 case 0xf8: /* UA2007/JPS1 Block load primary LE */
2096 case 0xf9: /* UA2007/JPS1 Block load secondary LE */
2097 if (rd & 7) {
2098 helper_raise_exception(env, TT_ILL_INSN);
2099 return;
2100 }
2101 helper_check_align(env, addr, 0x3f);
2102 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2103 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x8f, 8, 0);
2104 }
2105 return;
2106
2107 case 0x16: /* UA2007 Block load primary, user privilege */
2108 case 0x17: /* UA2007 Block load secondary, user privilege */
2109 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2110 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2111 case 0x70: /* JPS1 Block load primary, user privilege */
2112 case 0x71: /* JPS1 Block load secondary, user privilege */
2113 case 0x78: /* JPS1 Block load primary LE, user privilege */
2114 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2115 if (rd & 7) {
2116 helper_raise_exception(env, TT_ILL_INSN);
2117 return;
2118 }
2119 helper_check_align(env, addr, 0x3f);
2120 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2121 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x19, 8, 0);
2122 }
2123 return;
2124
2125 default:
2126 break;
2127 }
2128
2129 switch (size) {
2130 default:
2131 case 4:
2132 val = helper_ld_asi(env, addr, asi, size, 0);
2133 if (rd & 1) {
2134 env->fpr[rd / 2].l.lower = val;
2135 } else {
2136 env->fpr[rd / 2].l.upper = val;
2137 }
2138 break;
2139 case 8:
2140 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, size, 0);
2141 break;
2142 case 16:
2143 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, 8, 0);
2144 env->fpr[rd / 2 + 1].ll = helper_ld_asi(env, addr + 8, asi, 8, 0);
2145 break;
2146 }
2147 }
2148
2149 void helper_stf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
2150 int rd)
2151 {
2152 unsigned int i;
2153 target_ulong val;
2154
2155 helper_check_align(env, addr, 3);
2156 addr = asi_address_mask(env, asi, addr);
2157
2158 switch (asi) {
2159 case 0xe0: /* UA2007/JPS1 Block commit store primary (cache flush) */
2160 case 0xe1: /* UA2007/JPS1 Block commit store secondary (cache flush) */
2161 case 0xf0: /* UA2007/JPS1 Block store primary */
2162 case 0xf1: /* UA2007/JPS1 Block store secondary */
2163 case 0xf8: /* UA2007/JPS1 Block store primary LE */
2164 case 0xf9: /* UA2007/JPS1 Block store secondary LE */
2165 if (rd & 7) {
2166 helper_raise_exception(env, TT_ILL_INSN);
2167 return;
2168 }
2169 helper_check_align(env, addr, 0x3f);
2170 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2171 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x8f, 8);
2172 }
2173
2174 return;
2175 case 0x16: /* UA2007 Block load primary, user privilege */
2176 case 0x17: /* UA2007 Block load secondary, user privilege */
2177 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2178 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2179 case 0x70: /* JPS1 Block store primary, user privilege */
2180 case 0x71: /* JPS1 Block store secondary, user privilege */
2181 case 0x78: /* JPS1 Block load primary LE, user privilege */
2182 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2183 if (rd & 7) {
2184 helper_raise_exception(env, TT_ILL_INSN);
2185 return;
2186 }
2187 helper_check_align(env, addr, 0x3f);
2188 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2189 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x19, 8);
2190 }
2191
2192 return;
2193 default:
2194 break;
2195 }
2196
2197 switch (size) {
2198 default:
2199 case 4:
2200 if (rd & 1) {
2201 val = env->fpr[rd / 2].l.lower;
2202 } else {
2203 val = env->fpr[rd / 2].l.upper;
2204 }
2205 helper_st_asi(env, addr, val, asi, size);
2206 break;
2207 case 8:
2208 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, size);
2209 break;
2210 case 16:
2211 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, 8);
2212 helper_st_asi(env, addr + 8, env->fpr[rd / 2 + 1].ll, asi, 8);
2213 break;
2214 }
2215 }
2216
2217 target_ulong helper_cas_asi(CPUSPARCState *env, target_ulong addr,
2218 target_ulong val1, target_ulong val2, uint32_t asi)
2219 {
2220 target_ulong ret;
2221
2222 val2 &= 0xffffffffUL;
2223 ret = helper_ld_asi(env, addr, asi, 4, 0);
2224 ret &= 0xffffffffUL;
2225 if (val2 == ret) {
2226 helper_st_asi(env, addr, val1 & 0xffffffffUL, asi, 4);
2227 }
2228 return ret;
2229 }
2230
2231 target_ulong helper_casx_asi(CPUSPARCState *env, target_ulong addr,
2232 target_ulong val1, target_ulong val2,
2233 uint32_t asi)
2234 {
2235 target_ulong ret;
2236
2237 ret = helper_ld_asi(env, addr, asi, 8, 0);
2238 if (val2 == ret) {
2239 helper_st_asi(env, addr, val1, asi, 8);
2240 }
2241 return ret;
2242 }
2243 #endif /* TARGET_SPARC64 */
2244
2245 void helper_ldqf(CPUSPARCState *env, target_ulong addr, int mem_idx)
2246 {
2247 /* XXX add 128 bit load */
2248 CPU_QuadU u;
2249
2250 helper_check_align(env, addr, 7);
2251 #if !defined(CONFIG_USER_ONLY)
2252 switch (mem_idx) {
2253 case MMU_USER_IDX:
2254 u.ll.upper = cpu_ldq_user(env, addr);
2255 u.ll.lower = cpu_ldq_user(env, addr + 8);
2256 QT0 = u.q;
2257 break;
2258 case MMU_KERNEL_IDX:
2259 u.ll.upper = cpu_ldq_kernel(env, addr);
2260 u.ll.lower = cpu_ldq_kernel(env, addr + 8);
2261 QT0 = u.q;
2262 break;
2263 #ifdef TARGET_SPARC64
2264 case MMU_HYPV_IDX:
2265 u.ll.upper = cpu_ldq_hypv(env, addr);
2266 u.ll.lower = cpu_ldq_hypv(env, addr + 8);
2267 QT0 = u.q;
2268 break;
2269 #endif
2270 default:
2271 DPRINTF_MMU("helper_ldqf: need to check MMU idx %d\n", mem_idx);
2272 break;
2273 }
2274 #else
2275 u.ll.upper = ldq_raw(address_mask(env, addr));
2276 u.ll.lower = ldq_raw(address_mask(env, addr + 8));
2277 QT0 = u.q;
2278 #endif
2279 }
2280
2281 void helper_stqf(CPUSPARCState *env, target_ulong addr, int mem_idx)
2282 {
2283 /* XXX add 128 bit store */
2284 CPU_QuadU u;
2285
2286 helper_check_align(env, addr, 7);
2287 #if !defined(CONFIG_USER_ONLY)
2288 switch (mem_idx) {
2289 case MMU_USER_IDX:
2290 u.q = QT0;
2291 cpu_stq_user(env, addr, u.ll.upper);
2292 cpu_stq_user(env, addr + 8, u.ll.lower);
2293 break;
2294 case MMU_KERNEL_IDX:
2295 u.q = QT0;
2296 cpu_stq_kernel(env, addr, u.ll.upper);
2297 cpu_stq_kernel(env, addr + 8, u.ll.lower);
2298 break;
2299 #ifdef TARGET_SPARC64
2300 case MMU_HYPV_IDX:
2301 u.q = QT0;
2302 cpu_stq_hypv(env, addr, u.ll.upper);
2303 cpu_stq_hypv(env, addr + 8, u.ll.lower);
2304 break;
2305 #endif
2306 default:
2307 DPRINTF_MMU("helper_stqf: need to check MMU idx %d\n", mem_idx);
2308 break;
2309 }
2310 #else
2311 u.q = QT0;
2312 stq_raw(address_mask(env, addr), u.ll.upper);
2313 stq_raw(address_mask(env, addr + 8), u.ll.lower);
2314 #endif
2315 }
2316
2317 #if !defined(CONFIG_USER_ONLY)
2318 #ifndef TARGET_SPARC64
2319 void cpu_unassigned_access(CPUSPARCState *env, hwaddr addr,
2320 int is_write, int is_exec, int is_asi, int size)
2321 {
2322 int fault_type;
2323
2324 #ifdef DEBUG_UNASSIGNED
2325 if (is_asi) {
2326 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2327 " asi 0x%02x from " TARGET_FMT_lx "\n",
2328 is_exec ? "exec" : is_write ? "write" : "read", size,
2329 size == 1 ? "" : "s", addr, is_asi, env->pc);
2330 } else {
2331 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2332 " from " TARGET_FMT_lx "\n",
2333 is_exec ? "exec" : is_write ? "write" : "read", size,
2334 size == 1 ? "" : "s", addr, env->pc);
2335 }
2336 #endif
2337 /* Don't overwrite translation and access faults */
2338 fault_type = (env->mmuregs[3] & 0x1c) >> 2;
2339 if ((fault_type > 4) || (fault_type == 0)) {
2340 env->mmuregs[3] = 0; /* Fault status register */
2341 if (is_asi) {
2342 env->mmuregs[3] |= 1 << 16;
2343 }
2344 if (env->psrs) {
2345 env->mmuregs[3] |= 1 << 5;
2346 }
2347 if (is_exec) {
2348 env->mmuregs[3] |= 1 << 6;
2349 }
2350 if (is_write) {
2351 env->mmuregs[3] |= 1 << 7;
2352 }
2353 env->mmuregs[3] |= (5 << 2) | 2;
2354 /* SuperSPARC will never place instruction fault addresses in the FAR */
2355 if (!is_exec) {
2356 env->mmuregs[4] = addr; /* Fault address register */
2357 }
2358 }
2359 /* overflow (same type fault was not read before another fault) */
2360 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) {
2361 env->mmuregs[3] |= 1;
2362 }
2363
2364 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
2365 if (is_exec) {
2366 helper_raise_exception(env, TT_CODE_ACCESS);
2367 } else {
2368 helper_raise_exception(env, TT_DATA_ACCESS);
2369 }
2370 }
2371
2372 /* flush neverland mappings created during no-fault mode,
2373 so the sequential MMU faults report proper fault types */
2374 if (env->mmuregs[0] & MMU_NF) {
2375 tlb_flush(env, 1);
2376 }
2377 }
2378 #else
2379 void cpu_unassigned_access(CPUSPARCState *env, hwaddr addr,
2380 int is_write, int is_exec, int is_asi, int size)
2381 {
2382 #ifdef DEBUG_UNASSIGNED
2383 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
2384 "\n", addr, env->pc);
2385 #endif
2386
2387 if (is_exec) {
2388 helper_raise_exception(env, TT_CODE_ACCESS);
2389 } else {
2390 helper_raise_exception(env, TT_DATA_ACCESS);
2391 }
2392 }
2393 #endif
2394 #endif
2395
2396 #if !defined(CONFIG_USER_ONLY)
2397 static void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env,
2398 target_ulong addr, int is_write,
2399 int is_user, uintptr_t retaddr)
2400 {
2401 #ifdef DEBUG_UNALIGNED
2402 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
2403 "\n", addr, env->pc);
2404 #endif
2405 if (retaddr) {
2406 cpu_restore_state(env, retaddr);
2407 }
2408 helper_raise_exception(env, TT_UNALIGNED);
2409 }
2410
2411 /* try to fill the TLB and return an exception if error. If retaddr is
2412 NULL, it means that the function was called in C code (i.e. not
2413 from generated code or from helper.c) */
2414 /* XXX: fix it to restore all registers */
2415 void tlb_fill(CPUSPARCState *env, target_ulong addr, int is_write, int mmu_idx,
2416 uintptr_t retaddr)
2417 {
2418 int ret;
2419
2420 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx);
2421 if (ret) {
2422 if (retaddr) {
2423 cpu_restore_state(env, retaddr);
2424 }
2425 cpu_loop_exit(env);
2426 }
2427 }
2428 #endif
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