target-sparc/mmu_helper.c

   1 /*
   2  *  Sparc MMU helpers
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21 #include "trace.h"
  22 #include "exec-memory.h"
  23
  24 /* Sparc MMU emulation */
  25
  26 #if defined(CONFIG_USER_ONLY)
  27
  28 int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong address, int rw,
  29                                int mmu_idx)
  30 {
  31     if (rw & 2) {
  32         env1->exception_index = TT_TFAULT;
  33     } else {
  34         env1->exception_index = TT_DFAULT;
  35     }
  36     return 1;
  37 }
  38
  39 #else
  40
  41 #ifndef TARGET_SPARC64
  42 /*
  43  * Sparc V8 Reference MMU (SRMMU)
  44  */
  45 static const int access_table[8][8] = {
  46     { 0, 0, 0, 0, 8, 0, 12, 12 },
  47     { 0, 0, 0, 0, 8, 0, 0, 0 },
  48     { 8, 8, 0, 0, 0, 8, 12, 12 },
  49     { 8, 8, 0, 0, 0, 8, 0, 0 },
  50     { 8, 0, 8, 0, 8, 8, 12, 12 },
  51     { 8, 0, 8, 0, 8, 0, 8, 0 },
  52     { 8, 8, 8, 0, 8, 8, 12, 12 },
  53     { 8, 8, 8, 0, 8, 8, 8, 0 }
  54 };
  55
  56 static const int perm_table[2][8] = {
  57     {
  58         PAGE_READ,
  59         PAGE_READ | PAGE_WRITE,
  60         PAGE_READ | PAGE_EXEC,
  61         PAGE_READ | PAGE_WRITE | PAGE_EXEC,
  62         PAGE_EXEC,
  63         PAGE_READ | PAGE_WRITE,
  64         PAGE_READ | PAGE_EXEC,
  65         PAGE_READ | PAGE_WRITE | PAGE_EXEC
  66     },
  67     {
  68         PAGE_READ,
  69         PAGE_READ | PAGE_WRITE,
  70         PAGE_READ | PAGE_EXEC,
  71         PAGE_READ | PAGE_WRITE | PAGE_EXEC,
  72         PAGE_EXEC,
  73         PAGE_READ,
  74         0,
  75         0,
  76     }
  77 };
  78
  79 static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
  80                                 int *prot, int *access_index,
  81                                 target_ulong address, int rw, int mmu_idx,
  82                                 target_ulong *page_size)
  83 {
  84     int access_perms = 0;
  85     target_phys_addr_t pde_ptr;
  86     uint32_t pde;
  87     int error_code = 0, is_dirty, is_user;
  88     unsigned long page_offset;
  89
  90     is_user = mmu_idx == MMU_USER_IDX;
  91
  92     if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
  93         *page_size = TARGET_PAGE_SIZE;
  94         /* Boot mode: instruction fetches are taken from PROM */
  95         if (rw == 2 && (env->mmuregs[0] & env->def->mmu_bm)) {
  96             *physical = env->prom_addr | (address & 0x7ffffULL);
  97             *prot = PAGE_READ | PAGE_EXEC;
  98             return 0;
  99         }
 100         *physical = address;
 101         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 102         return 0;
 103     }
 104
 105     *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user ? 0 : 1);
 106     *physical = 0xffffffffffff0000ULL;
 107
 108     /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
 109     /* Context base + context number */
 110     pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
 111     pde = ldl_phys(pde_ptr);
 112
 113     /* Ctx pde */
 114     switch (pde & PTE_ENTRYTYPE_MASK) {
 115     default:
 116     case 0: /* Invalid */
 117         return 1 << 2;
 118     case 2: /* L0 PTE, maybe should not happen? */
 119     case 3: /* Reserved */
 120         return 4 << 2;
 121     case 1: /* L0 PDE */
 122         pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
 123         pde = ldl_phys(pde_ptr);
 124
 125         switch (pde & PTE_ENTRYTYPE_MASK) {
 126         default:
 127         case 0: /* Invalid */
 128             return (1 << 8) | (1 << 2);
 129         case 3: /* Reserved */
 130             return (1 << 8) | (4 << 2);
 131         case 1: /* L1 PDE */
 132             pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
 133             pde = ldl_phys(pde_ptr);
 134
 135             switch (pde & PTE_ENTRYTYPE_MASK) {
 136             default:
 137             case 0: /* Invalid */
 138                 return (2 << 8) | (1 << 2);
 139             case 3: /* Reserved */
 140                 return (2 << 8) | (4 << 2);
 141             case 1: /* L2 PDE */
 142                 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
 143                 pde = ldl_phys(pde_ptr);
 144
 145                 switch (pde & PTE_ENTRYTYPE_MASK) {
 146                 default:
 147                 case 0: /* Invalid */
 148                     return (3 << 8) | (1 << 2);
 149                 case 1: /* PDE, should not happen */
 150                 case 3: /* Reserved */
 151                     return (3 << 8) | (4 << 2);
 152                 case 2: /* L3 PTE */
 153                     page_offset = (address & TARGET_PAGE_MASK) &
 154                         (TARGET_PAGE_SIZE - 1);
 155                 }
 156                 *page_size = TARGET_PAGE_SIZE;
 157                 break;
 158             case 2: /* L2 PTE */
 159                 page_offset = address & 0x3ffff;
 160                 *page_size = 0x40000;
 161             }
 162             break;
 163         case 2: /* L1 PTE */
 164             page_offset = address & 0xffffff;
 165             *page_size = 0x1000000;
 166         }
 167     }
 168
 169     /* check access */
 170     access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
 171     error_code = access_table[*access_index][access_perms];
 172     if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user)) {
 173         return error_code;
 174     }
 175
 176     /* update page modified and dirty bits */
 177     is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
 178     if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
 179         pde |= PG_ACCESSED_MASK;
 180         if (is_dirty) {
 181             pde |= PG_MODIFIED_MASK;
 182         }
 183         stl_phys_notdirty(pde_ptr, pde);
 184     }
 185
 186     /* the page can be put in the TLB */
 187     *prot = perm_table[is_user][access_perms];
 188     if (!(pde & PG_MODIFIED_MASK)) {
 189         /* only set write access if already dirty... otherwise wait
 190            for dirty access */
 191         *prot &= ~PAGE_WRITE;
 192     }
 193
 194     /* Even if large ptes, we map only one 4KB page in the cache to
 195        avoid filling it too fast */
 196     *physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
 197     return error_code;
 198 }
 199
 200 /* Perform address translation */
 201 int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
 202                                int mmu_idx)
 203 {
 204     target_phys_addr_t paddr;
 205     target_ulong vaddr;
 206     target_ulong page_size;
 207     int error_code = 0, prot, access_index;
 208
 209     error_code = get_physical_address(env, &paddr, &prot, &access_index,
 210                                       address, rw, mmu_idx, &page_size);
 211     if (error_code == 0) {
 212         vaddr = address & TARGET_PAGE_MASK;
 213         paddr &= TARGET_PAGE_MASK;
 214 #ifdef DEBUG_MMU
 215         printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
 216                TARGET_FMT_lx "\n", address, paddr, vaddr);
 217 #endif
 218         tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size);
 219         return 0;
 220     }
 221
 222     if (env->mmuregs[3]) { /* Fault status register */
 223         env->mmuregs[3] = 1; /* overflow (not read before another fault) */
 224     }
 225     env->mmuregs[3] |= (access_index << 5) | error_code | 2;
 226     env->mmuregs[4] = address; /* Fault address register */
 227
 228     if ((env->mmuregs[0] & MMU_NF) || env->psret == 0)  {
 229         /* No fault mode: if a mapping is available, just override
 230            permissions. If no mapping is available, redirect accesses to
 231            neverland. Fake/overridden mappings will be flushed when
 232            switching to normal mode. */
 233         vaddr = address & TARGET_PAGE_MASK;
 234         prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 235         tlb_set_page(env, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE);
 236         return 0;
 237     } else {
 238         if (rw & 2) {
 239             env->exception_index = TT_TFAULT;
 240         } else {
 241             env->exception_index = TT_DFAULT;
 242         }
 243         return 1;
 244     }
 245 }
 246
 247 target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
 248 {
 249     target_phys_addr_t pde_ptr;
 250     uint32_t pde;
 251
 252     /* Context base + context number */
 253     pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) +
 254         (env->mmuregs[2] << 2);
 255     pde = ldl_phys(pde_ptr);
 256
 257     switch (pde & PTE_ENTRYTYPE_MASK) {
 258     default:
 259     case 0: /* Invalid */
 260     case 2: /* PTE, maybe should not happen? */
 261     case 3: /* Reserved */
 262         return 0;
 263     case 1: /* L1 PDE */
 264         if (mmulev == 3) {
 265             return pde;
 266         }
 267         pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
 268         pde = ldl_phys(pde_ptr);
 269
 270         switch (pde & PTE_ENTRYTYPE_MASK) {
 271         default:
 272         case 0: /* Invalid */
 273         case 3: /* Reserved */
 274             return 0;
 275         case 2: /* L1 PTE */
 276             return pde;
 277         case 1: /* L2 PDE */
 278             if (mmulev == 2) {
 279                 return pde;
 280             }
 281             pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
 282             pde = ldl_phys(pde_ptr);
 283
 284             switch (pde & PTE_ENTRYTYPE_MASK) {
 285             default:
 286             case 0: /* Invalid */
 287             case 3: /* Reserved */
 288                 return 0;
 289             case 2: /* L2 PTE */
 290                 return pde;
 291             case 1: /* L3 PDE */
 292                 if (mmulev == 1) {
 293                     return pde;
 294                 }
 295                 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
 296                 pde = ldl_phys(pde_ptr);
 297
 298                 switch (pde & PTE_ENTRYTYPE_MASK) {
 299                 default:
 300                 case 0: /* Invalid */
 301                 case 1: /* PDE, should not happen */
 302                 case 3: /* Reserved */
 303                     return 0;
 304                 case 2: /* L3 PTE */
 305                     return pde;
 306                 }
 307             }
 308         }
 309     }
 310     return 0;
 311 }
 312
 313 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
 314 {
 315     target_ulong va, va1, va2;
 316     unsigned int n, m, o;
 317     target_phys_addr_t pde_ptr, pa;
 318     uint32_t pde;
 319
 320     pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
 321     pde = ldl_phys(pde_ptr);
 322     (*cpu_fprintf)(f, "Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
 323                    (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]);
 324     for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
 325         pde = mmu_probe(env, va, 2);
 326         if (pde) {
 327             pa = cpu_get_phys_page_debug(env, va);
 328             (*cpu_fprintf)(f, "VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
 329                            " PDE: " TARGET_FMT_lx "\n", va, pa, pde);
 330             for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
 331                 pde = mmu_probe(env, va1, 1);
 332                 if (pde) {
 333                     pa = cpu_get_phys_page_debug(env, va1);
 334                     (*cpu_fprintf)(f, " VA: " TARGET_FMT_lx ", PA: "
 335                                    TARGET_FMT_plx " PDE: " TARGET_FMT_lx "\n",
 336                                    va1, pa, pde);
 337                     for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
 338                         pde = mmu_probe(env, va2, 0);
 339                         if (pde) {
 340                             pa = cpu_get_phys_page_debug(env, va2);
 341                             (*cpu_fprintf)(f, "  VA: " TARGET_FMT_lx ", PA: "
 342                                            TARGET_FMT_plx " PTE: "
 343                                            TARGET_FMT_lx "\n",
 344                                            va2, pa, pde);
 345                         }
 346                     }
 347                 }
 348             }
 349         }
 350     }
 351 }
 352
 353 /* Gdb expects all registers windows to be flushed in ram. This function handles
 354  * reads (and only reads) in stack frames as if windows were flushed. We assume
 355  * that the sparc ABI is followed.
 356  */
 357 int target_memory_rw_debug(CPUState *env, target_ulong addr,
 358                            uint8_t *buf, int len, int is_write)
 359 {
 360     int i;
 361     int len1;
 362     int cwp = env->cwp;
 363
 364     if (!is_write) {
 365         for (i = 0; i < env->nwindows; i++) {
 366             int off;
 367             target_ulong fp = env->regbase[cwp * 16 + 22];
 368
 369             /* Assume fp == 0 means end of frame.  */
 370             if (fp == 0) {
 371                 break;
 372             }
 373
 374             cwp = cpu_cwp_inc(env, cwp + 1);
 375
 376             /* Invalid window ? */
 377             if (env->wim & (1 << cwp)) {
 378                 break;
 379             }
 380
 381             /* According to the ABI, the stack is growing downward.  */
 382             if (addr + len < fp) {
 383                 break;
 384             }
 385
 386             /* Not in this frame.  */
 387             if (addr > fp + 64) {
 388                 continue;
 389             }
 390
 391             /* Handle access before this window.  */
 392             if (addr < fp) {
 393                 len1 = fp - addr;
 394                 if (cpu_memory_rw_debug(env, addr, buf, len1, is_write) != 0) {
 395                     return -1;
 396                 }
 397                 addr += len1;
 398                 len -= len1;
 399                 buf += len1;
 400             }
 401
 402             /* Access byte per byte to registers. Not very efficient but speed
 403              * is not critical.
 404              */
 405             off = addr - fp;
 406             len1 = 64 - off;
 407
 408             if (len1 > len) {
 409                 len1 = len;
 410             }
 411
 412             for (; len1; len1--) {
 413                 int reg = cwp * 16 + 8 + (off >> 2);
 414                 union {
 415                     uint32_t v;
 416                     uint8_t c[4];
 417                 } u;
 418                 u.v = cpu_to_be32(env->regbase[reg]);
 419                 *buf++ = u.c[off & 3];
 420                 addr++;
 421                 len--;
 422                 off++;
 423             }
 424
 425             if (len == 0) {
 426                 return 0;
 427             }
 428         }
 429     }
 430     return cpu_memory_rw_debug(env, addr, buf, len, is_write);
 431 }
 432
 433 #else /* !TARGET_SPARC64 */
 434
 435 /* 41 bit physical address space */
 436 static inline target_phys_addr_t ultrasparc_truncate_physical(uint64_t x)
 437 {
 438     return x & 0x1ffffffffffULL;
 439 }
 440
 441 /*
 442  * UltraSparc IIi I/DMMUs
 443  */
 444
 445 /* Returns true if TTE tag is valid and matches virtual address value
 446    in context requires virtual address mask value calculated from TTE
 447    entry size */
 448 static inline int ultrasparc_tag_match(SparcTLBEntry *tlb,
 449                                        uint64_t address, uint64_t context,
 450                                        target_phys_addr_t *physical)
 451 {
 452     uint64_t mask;
 453
 454     switch (TTE_PGSIZE(tlb->tte)) {
 455     default:
 456     case 0x0: /* 8k */
 457         mask = 0xffffffffffffe000ULL;
 458         break;
 459     case 0x1: /* 64k */
 460         mask = 0xffffffffffff0000ULL;
 461         break;
 462     case 0x2: /* 512k */
 463         mask = 0xfffffffffff80000ULL;
 464         break;
 465     case 0x3: /* 4M */
 466         mask = 0xffffffffffc00000ULL;
 467         break;
 468     }
 469
 470     /* valid, context match, virtual address match? */
 471     if (TTE_IS_VALID(tlb->tte) &&
 472         (TTE_IS_GLOBAL(tlb->tte) || tlb_compare_context(tlb, context))
 473         && compare_masked(address, tlb->tag, mask)) {
 474         /* decode physical address */
 475         *physical = ((tlb->tte & mask) | (address & ~mask)) & 0x1ffffffe000ULL;
 476         return 1;
 477     }
 478
 479     return 0;
 480 }
 481
 482 static int get_physical_address_data(CPUState *env,
 483                                      target_phys_addr_t *physical, int *prot,
 484                                      target_ulong address, int rw, int mmu_idx)
 485 {
 486     unsigned int i;
 487     uint64_t context;
 488     uint64_t sfsr = 0;
 489
 490     int is_user = (mmu_idx == MMU_USER_IDX ||
 491                    mmu_idx == MMU_USER_SECONDARY_IDX);
 492
 493     if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
 494         *physical = ultrasparc_truncate_physical(address);
 495         *prot = PAGE_READ | PAGE_WRITE;
 496         return 0;
 497     }
 498
 499     switch (mmu_idx) {
 500     case MMU_USER_IDX:
 501     case MMU_KERNEL_IDX:
 502         context = env->dmmu.mmu_primary_context & 0x1fff;
 503         sfsr |= SFSR_CT_PRIMARY;
 504         break;
 505     case MMU_USER_SECONDARY_IDX:
 506     case MMU_KERNEL_SECONDARY_IDX:
 507         context = env->dmmu.mmu_secondary_context & 0x1fff;
 508         sfsr |= SFSR_CT_SECONDARY;
 509         break;
 510     case MMU_NUCLEUS_IDX:
 511         sfsr |= SFSR_CT_NUCLEUS;
 512         /* FALLTHRU */
 513     default:
 514         context = 0;
 515         break;
 516     }
 517
 518     if (rw == 1) {
 519         sfsr |= SFSR_WRITE_BIT;
 520     } else if (rw == 4) {
 521         sfsr |= SFSR_NF_BIT;
 522     }
 523
 524     for (i = 0; i < 64; i++) {
 525         /* ctx match, vaddr match, valid? */
 526         if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical)) {
 527             int do_fault = 0;
 528
 529             /* access ok? */
 530             /* multiple bits in SFSR.FT may be set on TT_DFAULT */
 531             if (TTE_IS_PRIV(env->dtlb[i].tte) && is_user) {
 532                 do_fault = 1;
 533                 sfsr |= SFSR_FT_PRIV_BIT; /* privilege violation */
 534                 trace_mmu_helper_dfault(address, context, mmu_idx, env->tl);
 535             }
 536             if (rw == 4) {
 537                 if (TTE_IS_SIDEEFFECT(env->dtlb[i].tte)) {
 538                     do_fault = 1;
 539                     sfsr |= SFSR_FT_NF_E_BIT;
 540                 }
 541             } else {
 542                 if (TTE_IS_NFO(env->dtlb[i].tte)) {
 543                     do_fault = 1;
 544                     sfsr |= SFSR_FT_NFO_BIT;
 545                 }
 546             }
 547
 548             if (do_fault) {
 549                 /* faults above are reported with TT_DFAULT. */
 550                 env->exception_index = TT_DFAULT;
 551             } else if (!TTE_IS_W_OK(env->dtlb[i].tte) && (rw == 1)) {
 552                 do_fault = 1;
 553                 env->exception_index = TT_DPROT;
 554
 555                 trace_mmu_helper_dprot(address, context, mmu_idx, env->tl);
 556             }
 557
 558             if (!do_fault) {
 559                 *prot = PAGE_READ;
 560                 if (TTE_IS_W_OK(env->dtlb[i].tte)) {
 561                     *prot |= PAGE_WRITE;
 562                 }
 563
 564                 TTE_SET_USED(env->dtlb[i].tte);
 565
 566                 return 0;
 567             }
 568
 569             if (env->dmmu.sfsr & SFSR_VALID_BIT) { /* Fault status register */
 570                 sfsr |= SFSR_OW_BIT; /* overflow (not read before
 571                                         another fault) */
 572             }
 573
 574             if (env->pstate & PS_PRIV) {
 575                 sfsr |= SFSR_PR_BIT;
 576             }
 577
 578             /* FIXME: ASI field in SFSR must be set */
 579             env->dmmu.sfsr = sfsr | SFSR_VALID_BIT;
 580
 581             env->dmmu.sfar = address; /* Fault address register */
 582
 583             env->dmmu.tag_access = (address & ~0x1fffULL) | context;
 584
 585             return 1;
 586         }
 587     }
 588
 589     trace_mmu_helper_dmiss(address, context);
 590
 591     /*
 592      * On MMU misses:
 593      * - UltraSPARC IIi: SFSR and SFAR unmodified
 594      * - JPS1: SFAR updated and some fields of SFSR updated
 595      */
 596     env->dmmu.tag_access = (address & ~0x1fffULL) | context;
 597     env->exception_index = TT_DMISS;
 598     return 1;
 599 }
 600
 601 static int get_physical_address_code(CPUState *env,
 602                                      target_phys_addr_t *physical, int *prot,
 603                                      target_ulong address, int mmu_idx)
 604 {
 605     unsigned int i;
 606     uint64_t context;
 607
 608     int is_user = (mmu_idx == MMU_USER_IDX ||
 609                    mmu_idx == MMU_USER_SECONDARY_IDX);
 610
 611     if ((env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0) {
 612         /* IMMU disabled */
 613         *physical = ultrasparc_truncate_physical(address);
 614         *prot = PAGE_EXEC;
 615         return 0;
 616     }
 617
 618     if (env->tl == 0) {
 619         /* PRIMARY context */
 620         context = env->dmmu.mmu_primary_context & 0x1fff;
 621     } else {
 622         /* NUCLEUS context */
 623         context = 0;
 624     }
 625
 626     for (i = 0; i < 64; i++) {
 627         /* ctx match, vaddr match, valid? */
 628         if (ultrasparc_tag_match(&env->itlb[i],
 629                                  address, context, physical)) {
 630             /* access ok? */
 631             if (TTE_IS_PRIV(env->itlb[i].tte) && is_user) {
 632                 /* Fault status register */
 633                 if (env->immu.sfsr & SFSR_VALID_BIT) {
 634                     env->immu.sfsr = SFSR_OW_BIT; /* overflow (not read before
 635                                                      another fault) */
 636                 } else {
 637                     env->immu.sfsr = 0;
 638                 }
 639                 if (env->pstate & PS_PRIV) {
 640                     env->immu.sfsr |= SFSR_PR_BIT;
 641                 }
 642                 if (env->tl > 0) {
 643                     env->immu.sfsr |= SFSR_CT_NUCLEUS;
 644                 }
 645
 646                 /* FIXME: ASI field in SFSR must be set */
 647                 env->immu.sfsr |= SFSR_FT_PRIV_BIT | SFSR_VALID_BIT;
 648                 env->exception_index = TT_TFAULT;
 649
 650                 env->immu.tag_access = (address & ~0x1fffULL) | context;
 651
 652                 trace_mmu_helper_tfault(address, context);
 653
 654                 return 1;
 655             }
 656             *prot = PAGE_EXEC;
 657             TTE_SET_USED(env->itlb[i].tte);
 658             return 0;
 659         }
 660     }
 661
 662     trace_mmu_helper_tmiss(address, context);
 663
 664     /* Context is stored in DMMU (dmmuregs[1]) also for IMMU */
 665     env->immu.tag_access = (address & ~0x1fffULL) | context;
 666     env->exception_index = TT_TMISS;
 667     return 1;
 668 }
 669
 670 static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
 671                                 int *prot, int *access_index,
 672                                 target_ulong address, int rw, int mmu_idx,
 673                                 target_ulong *page_size)
 674 {
 675     /* ??? We treat everything as a small page, then explicitly flush
 676        everything when an entry is evicted.  */
 677     *page_size = TARGET_PAGE_SIZE;
 678
 679     /* safety net to catch wrong softmmu index use from dynamic code */
 680     if (env->tl > 0 && mmu_idx != MMU_NUCLEUS_IDX) {
 681         if (rw == 2) {
 682             trace_mmu_helper_get_phys_addr_code(env->tl, mmu_idx,
 683                                                 env->dmmu.mmu_primary_context,
 684                                                 env->dmmu.mmu_secondary_context,
 685                                                 address);
 686         } else {
 687             trace_mmu_helper_get_phys_addr_data(env->tl, mmu_idx,
 688                                                 env->dmmu.mmu_primary_context,
 689                                                 env->dmmu.mmu_secondary_context,
 690                                                 address);
 691         }
 692     }
 693
 694     if (rw == 2) {
 695         return get_physical_address_code(env, physical, prot, address,
 696                                          mmu_idx);
 697     } else {
 698         return get_physical_address_data(env, physical, prot, address, rw,
 699                                          mmu_idx);
 700     }
 701 }
 702
 703 /* Perform address translation */
 704 int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
 705                                int mmu_idx)
 706 {
 707     target_ulong virt_addr, vaddr;
 708     target_phys_addr_t paddr;
 709     target_ulong page_size;
 710     int error_code = 0, prot, access_index;
 711
 712     error_code = get_physical_address(env, &paddr, &prot, &access_index,
 713                                       address, rw, mmu_idx, &page_size);
 714     if (error_code == 0) {
 715         virt_addr = address & TARGET_PAGE_MASK;
 716         vaddr = virt_addr + ((address & TARGET_PAGE_MASK) &
 717                              (TARGET_PAGE_SIZE - 1));
 718
 719         trace_mmu_helper_mmu_fault(address, paddr, mmu_idx, env->tl,
 720                                    env->dmmu.mmu_primary_context,
 721                                    env->dmmu.mmu_secondary_context);
 722
 723         tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size);
 724         return 0;
 725     }
 726     /* XXX */
 727     return 1;
 728 }
 729
 730 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
 731 {
 732     unsigned int i;
 733     const char *mask;
 734
 735     (*cpu_fprintf)(f, "MMU contexts: Primary: %" PRId64 ", Secondary: %"
 736                    PRId64 "\n",
 737                    env->dmmu.mmu_primary_context,
 738                    env->dmmu.mmu_secondary_context);
 739     if ((env->lsu & DMMU_E) == 0) {
 740         (*cpu_fprintf)(f, "DMMU disabled\n");
 741     } else {
 742         (*cpu_fprintf)(f, "DMMU dump\n");
 743         for (i = 0; i < 64; i++) {
 744             switch (TTE_PGSIZE(env->dtlb[i].tte)) {
 745             default:
 746             case 0x0:
 747                 mask = "  8k";
 748                 break;
 749             case 0x1:
 750                 mask = " 64k";
 751                 break;
 752             case 0x2:
 753                 mask = "512k";
 754                 break;
 755             case 0x3:
 756                 mask = "  4M";
 757                 break;
 758             }
 759             if (TTE_IS_VALID(env->dtlb[i].tte)) {
 760                 (*cpu_fprintf)(f, "[%02u] VA: %" PRIx64 ", PA: %llx"
 761                                ", %s, %s, %s, %s, ctx %" PRId64 " %s\n",
 762                                i,
 763                                env->dtlb[i].tag & (uint64_t)~0x1fffULL,
 764                                TTE_PA(env->dtlb[i].tte),
 765                                mask,
 766                                TTE_IS_PRIV(env->dtlb[i].tte) ? "priv" : "user",
 767                                TTE_IS_W_OK(env->dtlb[i].tte) ? "RW" : "RO",
 768                                TTE_IS_LOCKED(env->dtlb[i].tte) ?
 769                                "locked" : "unlocked",
 770                                env->dtlb[i].tag & (uint64_t)0x1fffULL,
 771                                TTE_IS_GLOBAL(env->dtlb[i].tte) ?
 772                                "global" : "local");
 773             }
 774         }
 775     }
 776     if ((env->lsu & IMMU_E) == 0) {
 777         (*cpu_fprintf)(f, "IMMU disabled\n");
 778     } else {
 779         (*cpu_fprintf)(f, "IMMU dump\n");
 780         for (i = 0; i < 64; i++) {
 781             switch (TTE_PGSIZE(env->itlb[i].tte)) {
 782             default:
 783             case 0x0:
 784                 mask = "  8k";
 785                 break;
 786             case 0x1:
 787                 mask = " 64k";
 788                 break;
 789             case 0x2:
 790                 mask = "512k";
 791                 break;
 792             case 0x3:
 793                 mask = "  4M";
 794                 break;
 795             }
 796             if (TTE_IS_VALID(env->itlb[i].tte)) {
 797                 (*cpu_fprintf)(f, "[%02u] VA: %" PRIx64 ", PA: %llx"
 798                                ", %s, %s, %s, ctx %" PRId64 " %s\n",
 799                                i,
 800                                env->itlb[i].tag & (uint64_t)~0x1fffULL,
 801                                TTE_PA(env->itlb[i].tte),
 802                                mask,
 803                                TTE_IS_PRIV(env->itlb[i].tte) ? "priv" : "user",
 804                                TTE_IS_LOCKED(env->itlb[i].tte) ?
 805                                "locked" : "unlocked",
 806                                env->itlb[i].tag & (uint64_t)0x1fffULL,
 807                                TTE_IS_GLOBAL(env->itlb[i].tte) ?
 808                                "global" : "local");
 809             }
 810         }
 811     }
 812 }
 813
 814 #endif /* TARGET_SPARC64 */
 815
 816 static int cpu_sparc_get_phys_page(CPUState *env, target_phys_addr_t *phys,
 817                                    target_ulong addr, int rw, int mmu_idx)
 818 {
 819     target_ulong page_size;
 820     int prot, access_index;
 821
 822     return get_physical_address(env, phys, &prot, &access_index, addr, rw,
 823                                 mmu_idx, &page_size);
 824 }
 825
 826 #if defined(TARGET_SPARC64)
 827 target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env, target_ulong addr,
 828                                            int mmu_idx)
 829 {
 830     target_phys_addr_t phys_addr;
 831
 832     if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 4, mmu_idx) != 0) {
 833         return -1;
 834     }
 835     return phys_addr;
 836 }
 837 #endif
 838
 839 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
 840 {
 841     target_phys_addr_t phys_addr;
 842     int mmu_idx = cpu_mmu_index(env);
 843     MemoryRegionSection section;
 844
 845     if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 2, mmu_idx) != 0) {
 846         if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 0, mmu_idx) != 0) {
 847             return -1;
 848         }
 849     }
 850     section = memory_region_find(get_system_memory(), phys_addr, 1);
 851     if (!section.size) {
 852         return -1;
 853     }
 854     return phys_addr;
 855 }
 856 #endif