hw/mips_jazz.c

   1 /*
   2  * QEMU MIPS Jazz support
   3  *
   4  * Copyright (c) 2007-2008 Hervé Poussineau
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "mips.h"
  27 #include "mips_cpudevs.h"
  28 #include "pc.h"
  29 #include "isa.h"
  30 #include "fdc.h"
  31 #include "sysemu.h"
  32 #include "arch_init.h"
  33 #include "boards.h"
  34 #include "net.h"
  35 #include "esp.h"
  36 #include "mips-bios.h"
  37 #include "loader.h"
  38 #include "mc146818rtc.h"
  39 #include "i8254.h"
  40 #include "pcspk.h"
  41 #include "blockdev.h"
  42 #include "sysbus.h"
  43 #include "exec-memory.h"
  44
  45 enum jazz_model_e
  46 {
  47     JAZZ_MAGNUM,
  48     JAZZ_PICA61,
  49 };
  50
  51 static void main_cpu_reset(void *opaque)
  52 {
  53     MIPSCPU *cpu = opaque;
  54
  55     cpu_reset(CPU(cpu));
  56 }
  57
  58 static uint64_t rtc_read(void *opaque, target_phys_addr_t addr, unsigned size)
  59 {
  60     return cpu_inw(0x71);
  61 }
  62
  63 static void rtc_write(void *opaque, target_phys_addr_t addr,
  64                       uint64_t val, unsigned size)
  65 {
  66     cpu_outw(0x71, val & 0xff);
  67 }
  68
  69 static const MemoryRegionOps rtc_ops = {
  70     .read = rtc_read,
  71     .write = rtc_write,
  72     .endianness = DEVICE_NATIVE_ENDIAN,
  73 };
  74
  75 static uint64_t dma_dummy_read(void *opaque, target_phys_addr_t addr,
  76                                unsigned size)
  77 {
  78     /* Nothing to do. That is only to ensure that
  79      * the current DMA acknowledge cycle is completed. */
  80     return 0xff;
  81 }
  82
  83 static void dma_dummy_write(void *opaque, target_phys_addr_t addr,
  84                             uint64_t val, unsigned size)
  85 {
  86     /* Nothing to do. That is only to ensure that
  87      * the current DMA acknowledge cycle is completed. */
  88 }
  89
  90 static const MemoryRegionOps dma_dummy_ops = {
  91     .read = dma_dummy_read,
  92     .write = dma_dummy_write,
  93     .endianness = DEVICE_NATIVE_ENDIAN,
  94 };
  95
  96 #define MAGNUM_BIOS_SIZE_MAX 0x7e000
  97 #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
  98
  99 static void cpu_request_exit(void *opaque, int irq, int level)
 100 {
 101     CPUMIPSState *env = cpu_single_env;
 102
 103     if (env && level) {
 104         cpu_exit(env);
 105     }
 106 }
 107
 108 static void mips_jazz_init(MemoryRegion *address_space,
 109                            MemoryRegion *address_space_io,
 110                            ram_addr_t ram_size,
 111                            const char *cpu_model,
 112                            enum jazz_model_e jazz_model)
 113 {
 114     char *filename;
 115     int bios_size, n;
 116     MIPSCPU *cpu;
 117     CPUMIPSState *env;
 118     qemu_irq *rc4030, *i8259;
 119     rc4030_dma *dmas;
 120     void* rc4030_opaque;
 121     MemoryRegion *rtc = g_new(MemoryRegion, 1);
 122     MemoryRegion *i8042 = g_new(MemoryRegion, 1);
 123     MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
 124     NICInfo *nd;
 125     DeviceState *dev;
 126     SysBusDevice *sysbus;
 127     ISABus *isa_bus;
 128     ISADevice *pit;
 129     DriveInfo *fds[MAX_FD];
 130     qemu_irq esp_reset, dma_enable;
 131     qemu_irq *cpu_exit_irq;
 132     MemoryRegion *ram = g_new(MemoryRegion, 1);
 133     MemoryRegion *bios = g_new(MemoryRegion, 1);
 134     MemoryRegion *bios2 = g_new(MemoryRegion, 1);
 135
 136     /* init CPUs */
 137     if (cpu_model == NULL) {
 138 #ifdef TARGET_MIPS64
 139         cpu_model = "R4000";
 140 #else
 141         /* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
 142         cpu_model = "24Kf";
 143 #endif
 144     }
 145     cpu = cpu_mips_init(cpu_model);
 146     if (cpu == NULL) {
 147         fprintf(stderr, "Unable to find CPU definition\n");
 148         exit(1);
 149     }
 150     env = &cpu->env;
 151     qemu_register_reset(main_cpu_reset, cpu);
 152
 153     /* allocate RAM */
 154     memory_region_init_ram(ram, "mips_jazz.ram", ram_size);
 155     vmstate_register_ram_global(ram);
 156     memory_region_add_subregion(address_space, 0, ram);
 157
 158     memory_region_init_ram(bios, "mips_jazz.bios", MAGNUM_BIOS_SIZE);
 159     vmstate_register_ram_global(bios);
 160     memory_region_set_readonly(bios, true);
 161     memory_region_init_alias(bios2, "mips_jazz.bios", bios,
 162                              0, MAGNUM_BIOS_SIZE);
 163     memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
 164     memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
 165
 166     /* load the BIOS image. */
 167     if (bios_name == NULL)
 168         bios_name = BIOS_FILENAME;
 169     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 170     if (filename) {
 171         bios_size = load_image_targphys(filename, 0xfff00000LL,
 172                                         MAGNUM_BIOS_SIZE);
 173         g_free(filename);
 174     } else {
 175         bios_size = -1;
 176     }
 177     if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) {
 178         fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
 179                 bios_name);
 180         exit(1);
 181     }
 182
 183     /* Init CPU internal devices */
 184     cpu_mips_irq_init_cpu(env);
 185     cpu_mips_clock_init(env);
 186
 187     /* Chipset */
 188     rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas,
 189                                 address_space);
 190     memory_region_init_io(dma_dummy, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
 191     memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
 192
 193     /* ISA devices */
 194     isa_bus = isa_bus_new(NULL, address_space_io);
 195     i8259 = i8259_init(isa_bus, env->irq[4]);
 196     isa_bus_irqs(isa_bus, i8259);
 197     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
 198     DMA_init(0, cpu_exit_irq);
 199     pit = pit_init(isa_bus, 0x40, 0, NULL);
 200     pcspk_init(isa_bus, pit);
 201
 202     /* ISA IO space at 0x90000000 */
 203     isa_mmio_init(0x90000000, 0x01000000);
 204     isa_mem_base = 0x11000000;
 205
 206     /* Video card */
 207     switch (jazz_model) {
 208     case JAZZ_MAGNUM:
 209         dev = qdev_create(NULL, "sysbus-g364");
 210         qdev_init_nofail(dev);
 211         sysbus = sysbus_from_qdev(dev);
 212         sysbus_mmio_map(sysbus, 0, 0x60080000);
 213         sysbus_mmio_map(sysbus, 1, 0x40000000);
 214         sysbus_connect_irq(sysbus, 0, rc4030[3]);
 215         {
 216             /* Simple ROM, so user doesn't have to provide one */
 217             MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
 218             memory_region_init_ram(rom_mr, "g364fb.rom", 0x80000);
 219             vmstate_register_ram_global(rom_mr);
 220             memory_region_set_readonly(rom_mr, true);
 221             uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
 222             memory_region_add_subregion(address_space, 0x60000000, rom_mr);
 223             rom[0] = 0x10; /* Mips G364 */
 224         }
 225         break;
 226     case JAZZ_PICA61:
 227         isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
 228         break;
 229     default:
 230         break;
 231     }
 232
 233     /* Network controller */
 234     for (n = 0; n < nb_nics; n++) {
 235         nd = &nd_table[n];
 236         if (!nd->model)
 237             nd->model = g_strdup("dp83932");
 238         if (strcmp(nd->model, "dp83932") == 0) {
 239             dp83932_init(nd, 0x80001000, 2, get_system_memory(), rc4030[4],
 240                          rc4030_opaque, rc4030_dma_memory_rw);
 241             break;
 242         } else if (strcmp(nd->model, "?") == 0) {
 243             fprintf(stderr, "qemu: Supported NICs: dp83932\n");
 244             exit(1);
 245         } else {
 246             fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
 247             exit(1);
 248         }
 249     }
 250
 251     /* SCSI adapter */
 252     esp_init(0x80002000, 0,
 253              rc4030_dma_read, rc4030_dma_write, dmas[0],
 254              rc4030[5], &esp_reset, &dma_enable);
 255
 256     /* Floppy */
 257     if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
 258         fprintf(stderr, "qemu: too many floppy drives\n");
 259         exit(1);
 260     }
 261     for (n = 0; n < MAX_FD; n++) {
 262         fds[n] = drive_get(IF_FLOPPY, 0, n);
 263     }
 264     fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds);
 265
 266     /* Real time clock */
 267     rtc_init(isa_bus, 1980, NULL);
 268     memory_region_init_io(rtc, &rtc_ops, NULL, "rtc", 0x1000);
 269     memory_region_add_subregion(address_space, 0x80004000, rtc);
 270
 271     /* Keyboard (i8042) */
 272     i8042_mm_init(rc4030[6], rc4030[7], i8042, 0x1000, 0x1);
 273     memory_region_add_subregion(address_space, 0x80005000, i8042);
 274
 275     /* Serial ports */
 276     if (serial_hds[0]) {
 277         serial_mm_init(address_space, 0x80006000, 0, rc4030[8], 8000000/16,
 278                        serial_hds[0], DEVICE_NATIVE_ENDIAN);
 279     }
 280     if (serial_hds[1]) {
 281         serial_mm_init(address_space, 0x80007000, 0, rc4030[9], 8000000/16,
 282                        serial_hds[1], DEVICE_NATIVE_ENDIAN);
 283     }
 284
 285     /* Parallel port */
 286     if (parallel_hds[0])
 287         parallel_mm_init(address_space, 0x80008000, 0, rc4030[0],
 288                          parallel_hds[0]);
 289
 290     /* Sound card */
 291     /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
 292     audio_init(isa_bus, NULL);
 293
 294     /* NVRAM */
 295     dev = qdev_create(NULL, "ds1225y");
 296     qdev_init_nofail(dev);
 297     sysbus = sysbus_from_qdev(dev);
 298     sysbus_mmio_map(sysbus, 0, 0x80009000);
 299
 300     /* LED indicator */
 301     sysbus_create_simple("jazz-led", 0x8000f000, NULL);
 302 }
 303
 304 static
 305 void mips_magnum_init (ram_addr_t ram_size,
 306                        const char *boot_device,
 307                        const char *kernel_filename, const char *kernel_cmdline,
 308                        const char *initrd_filename, const char *cpu_model)
 309 {
 310         mips_jazz_init(get_system_memory(), get_system_io(),
 311                        ram_size, cpu_model, JAZZ_MAGNUM);
 312 }
 313
 314 static
 315 void mips_pica61_init (ram_addr_t ram_size,
 316                        const char *boot_device,
 317                        const char *kernel_filename, const char *kernel_cmdline,
 318                        const char *initrd_filename, const char *cpu_model)
 319 {
 320     mips_jazz_init(get_system_memory(), get_system_io(),
 321                    ram_size, cpu_model, JAZZ_PICA61);
 322 }
 323
 324 static QEMUMachine mips_magnum_machine = {
 325     .name = "magnum",
 326     .desc = "MIPS Magnum",
 327     .init = mips_magnum_init,
 328     .use_scsi = 1,
 329 };
 330
 331 static QEMUMachine mips_pica61_machine = {
 332     .name = "pica61",
 333     .desc = "Acer Pica 61",
 334     .init = mips_pica61_init,
 335     .use_scsi = 1,
 336 };
 337
 338 static void mips_jazz_machine_init(void)
 339 {
 340     qemu_register_machine(&mips_magnum_machine);
 341     qemu_register_machine(&mips_pica61_machine);
 342 }
 343
 344 machine_init(mips_jazz_machine_init);